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db8500-regs.h

db8500-regs.h 5.1 KB
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  1. /*
    2. 

  2.  * Copyright (C) ST-Ericsson SA 2010
    3. 

  3.  *
    4. 

  4.  * License terms: GNU General Public License (GPL) version 2
    5. 

  5.  */
    6. 

  6. 

  7. #ifndef __MACH_DB8500_REGS_H
    8. 

  8. #define __MACH_DB8500_REGS_H
    9. 

  9. 

  10. #define U8500_PER3_BASE		0x80000000
    11. 

  11. #define U8500_STM_BASE		0x80100000
    12. 

  12. #define U8500_STM_REG_BASE	(U8500_STM_BASE + 0xF000)
    13. 

  13. #define U8500_PER2_BASE		0x80110000
    14. 

  14. #define U8500_PER1_BASE		0x80120000
    15. 

  15. #define U8500_B2R2_BASE		0x80130000
    16. 

  16. #define U8500_HSEM_BASE		0x80140000
    17. 

  17. #define U8500_PER4_BASE		0x80150000
    18. 

  18. #define U8500_ICN_BASE		0x81000000
    19. 

  19. 

  20. #define U8500_BOOT_ROM_BASE	0x90000000
    21. 

  21. /* ASIC ID is at 0xff4 offset within this region */
    22. 

  22. #define U8500_ASIC_ID_BASE	0x9001F000
    23. 

  23. 

  24. #define U8500_PER6_BASE		0xa03c0000
    25. 

  25. #define U8500_PER5_BASE		0xa03e0000
    26. 

  26. #define U8500_PER7_BASE_ED	0xa03d0000
    27. 

  27. 

  28. #define U8500_SVA_BASE		0xa0100000
    29. 

  29. #define U8500_SIA_BASE		0xa0200000
    30. 

  30. 

  31. #define U8500_SGA_BASE		0xa0300000
    32. 

  32. #define U8500_MCDE_BASE		0xa0350000
    33. 

  33. #define U8500_DMA_BASE_ED	0xa0362000
    34. 

  34. #define U8500_DMA_BASE		0x801C0000	/* v1 */
    35. 

  35. 

  36. #define U8500_SBAG_BASE		0xa0390000
    37. 

  37. 

  38. #define U8500_SCU_BASE		0xa0410000
    39. 

  39. #define U8500_GIC_CPU_BASE	0xa0410100
    40. 

  40. #define U8500_TWD_BASE		0xa0410600
    41. 

  41. #define U8500_GIC_DIST_BASE	0xa0411000
    42. 

  42. #define U8500_L2CC_BASE		0xa0412000
    43. 

  43. 

  44. #define U8500_MODEM_I2C		0xb7e02000
    45. 

  45. 

  46. #define U8500_GPIO0_BASE	(U8500_PER1_BASE + 0xE000)
    47. 

  47. #define U8500_GPIO1_BASE	(U8500_PER3_BASE + 0xE000)
    48. 

  48. #define U8500_GPIO2_BASE	(U8500_PER2_BASE + 0xE000)
    49. 

  49. #define U8500_GPIO3_BASE	(U8500_PER5_BASE + 0x1E000)
    50. 

  50. 

  51. /* per7 base addressess */
    52. 

  52. #define U8500_CR_BASE_ED	(U8500_PER7_BASE_ED + 0x8000)
    53. 

  53. #define U8500_MTU0_BASE_ED	(U8500_PER7_BASE_ED + 0xa000)
    54. 

  54. #define U8500_MTU1_BASE_ED	(U8500_PER7_BASE_ED + 0xb000)
    55. 

  55. #define U8500_TZPC0_BASE_ED	(U8500_PER7_BASE_ED + 0xc000)
    56. 

  56. #define U8500_CLKRST7_BASE_ED	(U8500_PER7_BASE_ED + 0xf000)
    57. 

  57. 

  58. #define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
    59. 

  59. #define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)
    60. 

  60. 

  61. /* per6 base addressess */
    62. 

  62. #define U8500_RNG_BASE		(U8500_PER6_BASE + 0x0000)
    63. 

  63. #define U8500_PKA_BASE		(U8500_PER6_BASE + 0x1000)
    64. 

  64. #define U8500_PKAM_BASE		(U8500_PER6_BASE + 0x2000)
    65. 

  65. #define U8500_MTU0_BASE		(U8500_PER6_BASE + 0x6000) /* v1 */
    66. 

  66. #define U8500_MTU1_BASE		(U8500_PER6_BASE + 0x7000) /* v1 */
    67. 

  67. #define U8500_CR_BASE		(U8500_PER6_BASE + 0x8000) /* v1 */
    68. 

  68. #define U8500_CRYPTO0_BASE	(U8500_PER6_BASE + 0xa000)
    69. 

  69. #define U8500_CRYPTO1_BASE	(U8500_PER6_BASE + 0xb000)
    70. 

  70. #define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)
    71. 

  71. 

  72. /* per5 base addressess */
    73. 

  73. #define U8500_USBOTG_BASE	(U8500_PER5_BASE + 0x00000)
    74. 

  74. #define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)
    75. 

  75. 

  76. /* per4 base addressess */
    77. 

  77. #define U8500_BACKUPRAM0_BASE	(U8500_PER4_BASE + 0x00000)
    78. 

  78. #define U8500_BACKUPRAM1_BASE	(U8500_PER4_BASE + 0x01000)
    79. 

  79. #define U8500_RTT0_BASE		(U8500_PER4_BASE + 0x02000)
    80. 

  80. #define U8500_RTT1_BASE		(U8500_PER4_BASE + 0x03000)
    81. 

  81. #define U8500_RTC_BASE		(U8500_PER4_BASE + 0x04000)
    82. 

  82. #define U8500_SCR_BASE		(U8500_PER4_BASE + 0x05000)
    83. 

  83. #define U8500_DMC_BASE		(U8500_PER4_BASE + 0x06000)
    84. 

  84. #define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x07000)
    85. 

  85. #define U8500_PRCMU_TCDM_BASE	(U8500_PER4_BASE + 0x0f000)
    86. 

  86. 

  87. /* per3 base addresses */
    88. 

  88. #define U8500_FSMC_BASE		(U8500_PER3_BASE + 0x0000)
    89. 

  89. #define U8500_SSP0_BASE		(U8500_PER3_BASE + 0x2000)
    90. 

  90. #define U8500_SSP1_BASE		(U8500_PER3_BASE + 0x3000)
    91. 

  91. #define U8500_I2C0_BASE		(U8500_PER3_BASE + 0x4000)
    92. 

  92. #define U8500_SDI2_BASE		(U8500_PER3_BASE + 0x5000)
    93. 

  93. #define U8500_SKE_BASE		(U8500_PER3_BASE + 0x6000)
    94. 

  94. #define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
    95. 

  95. #define U8500_SDI5_BASE		(U8500_PER3_BASE + 0x8000)
    96. 

  96. #define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)
    97. 

  97. 

  98. /* per2 base addressess */
    99. 

  99. #define U8500_I2C3_BASE		(U8500_PER2_BASE + 0x0000)
    100. 

  100. #define U8500_SPI2_BASE		(U8500_PER2_BASE + 0x1000)
    101. 

  101. #define U8500_SPI1_BASE		(U8500_PER2_BASE + 0x2000)
    102. 

  102. #define U8500_PWL_BASE		(U8500_PER2_BASE + 0x3000)
    103. 

  103. #define U8500_SDI4_BASE		(U8500_PER2_BASE + 0x4000)
    104. 

  104. #define U8500_MSP2_BASE		(U8500_PER2_BASE + 0x7000)
    105. 

  105. #define U8500_SDI1_BASE		(U8500_PER2_BASE + 0x8000)
    106. 

  106. #define U8500_SDI3_BASE		(U8500_PER2_BASE + 0x9000)
    107. 

  107. #define U8500_SPI0_BASE		(U8500_PER2_BASE + 0xa000)
    108. 

  108. #define U8500_HSIR_BASE		(U8500_PER2_BASE + 0xb000)
    109. 

  109. #define U8500_HSIT_BASE		(U8500_PER2_BASE + 0xc000)
    110. 

  110. #define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)
    111. 

  111. 

  112. /* per1 base addresses */
    113. 

  113. #define U8500_I2C1_BASE		(U8500_PER1_BASE + 0x2000)
    114. 

  114. #define U8500_MSP0_BASE		(U8500_PER1_BASE + 0x3000)
    115. 

  115. #define U8500_MSP1_BASE		(U8500_PER1_BASE + 0x4000)
    116. 

  116. #define U8500_SDI0_BASE		(U8500_PER1_BASE + 0x6000)
    117. 

  117. #define U8500_I2C2_BASE		(U8500_PER1_BASE + 0x8000)
    118. 

  118. #define U8500_SPI3_BASE		(U8500_PER1_BASE + 0x9000)
    119. 

  119. #define U8500_I2C4_BASE		(U8500_PER1_BASE + 0xa000)
    120. 

  120. #define U8500_SLIM0_BASE	(U8500_PER1_BASE + 0xb000)
    121. 

  121. #define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)
    122. 

  122. 

  123. #define U8500_SHRM_GOP_INTERRUPT_BASE	0xB7C00040
    124. 

  124. 

  125. #define U8500_GPIOBANK0_BASE	U8500_GPIO0_BASE
    126. 

  126. #define U8500_GPIOBANK1_BASE	(U8500_GPIO0_BASE + 0x80)
    127. 

  127. #define U8500_GPIOBANK2_BASE	U8500_GPIO1_BASE
    128. 

  128. #define U8500_GPIOBANK3_BASE	(U8500_GPIO1_BASE + 0x80)
    129. 

  129. #define U8500_GPIOBANK4_BASE	(U8500_GPIO1_BASE + 0x100)
    130. 

  130. #define U8500_GPIOBANK5_BASE	(U8500_GPIO1_BASE + 0x180)
    131. 

  131. #define U8500_GPIOBANK6_BASE	U8500_GPIO2_BASE
    132. 

  132. #define U8500_GPIOBANK7_BASE	(U8500_GPIO2_BASE + 0x80)
    133. 

  133. #define U8500_GPIOBANK8_BASE	U8500_GPIO3_BASE
    134. 

  134. 

  135. #endif
    136.