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linux-vybrid_pu...
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arch
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arm
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mach-s5pc100
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include
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mach
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map.h

map.h 4.8 KB
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  1. /* linux/arch/arm/mach-s5pc100/include/mach/map.h
    2. 

  2.  *
    3. 

  3.  * Copyright 2009 Samsung Electronics Co.
    4. 

  4.  *	Byungho Min <bhmin@samsung.com>
    5. 

  5.  *
    6. 

  6.  * Based on mach-s3c6400/include/mach/map.h
    7. 

  7.  *
    8. 

  8.  * S5PC1XX - Memory map definitions
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute it and/or modify
    11. 

  11.  * it under the terms of the GNU General Public License version 2 as
    12. 

  12.  * published by the Free Software Foundation.
    13. 

  13. */
    14. 

  14. 

  15. #ifndef __ASM_ARCH_MAP_H
    16. 

  16. #define __ASM_ARCH_MAP_H __FILE__
    17. 

  17. 

  18. #include <plat/map-base.h>
    19. 

  19. 

  20. /*
    21. 

  21.  * map-base.h has already defined virtual memory address
    22. 

  22.  * S3C_VA_IRQ		S3C_ADDR(0x00000000)	irq controller(s)
    23. 

  23.  * S3C_VA_SYS		S3C_ADDR(0x00100000)	system control
    24. 

  24.  * S3C_VA_MEM		S3C_ADDR(0x00200000)	system control (not used)
    25. 

  25.  * S3C_VA_TIMER		S3C_ADDR(0x00300000)	timer block
    26. 

  26.  * S3C_VA_WATCHDOG	S3C_ADDR(0x00400000)	watchdog
    27. 

  27.  * S3C_VA_UART		S3C_ADDR(0x01000000)	UART
    28. 

  28.  *
    29. 

  29.  * S5PC100 specific virtual memory address can be defined here
    30. 

  30.  * S5PC1XX_VA_GPIO	S3C_ADDR(0x00500000)	GPIO
    31. 

  31.  *
    32. 

  32.  */
    33. 

  33. 

  34. #define S5PC100_PA_ONENAND_BUF	(0xB0000000)
    35. 

  35. #define S5PC100_SZ_ONENAND_BUF	(SZ_256M - SZ_32M)
    36. 

  36. 

  37. /* Chip ID */
    38. 

  38. #define S5PC100_PA_CHIPID	(0xE0000000)
    39. 

  39. #define S5PC1XX_PA_CHIPID	S5PC100_PA_CHIPID
    40. 

  40. #define S5PC1XX_VA_CHIPID	S3C_VA_SYS
    41. 

  41. 

  42. /* System */
    43. 

  43. #define S5PC100_PA_CLK		(0xE0100000)
    44. 

  44. #define S5PC100_PA_CLK_OTHER	(0xE0200000)
    45. 

  45. #define S5PC100_PA_PWR		(0xE0108000)
    46. 

  46. #define S5PC1XX_PA_CLK		S5PC100_PA_CLK
    47. 

  47. #define S5PC1XX_PA_PWR		S5PC100_PA_PWR
    48. 

  48. #define S5PC1XX_PA_CLK_OTHER	S5PC100_PA_CLK_OTHER
    49. 

  49. #define S5PC1XX_VA_CLK		(S3C_VA_SYS + 0x10000)
    50. 

  50. #define S5PC1XX_VA_PWR		(S3C_VA_SYS + 0x20000)
    51. 

  51. #define S5PC1XX_VA_CLK_OTHER	(S3C_VA_SYS + 0x30000)
    52. 

  52. 

  53. /* GPIO */
    54. 

  54. #define S5PC100_PA_GPIO		(0xE0300000)
    55. 

  55. #define S5PC1XX_PA_GPIO		S5PC100_PA_GPIO
    56. 

  56. #define S5PC1XX_VA_GPIO		S3C_ADDR(0x00500000)
    57. 

  57. 

  58. /* Interrupt */
    59. 

  59. #define S5PC100_PA_VIC		(0xE4000000)
    60. 

  60. #define S5PC100_VA_VIC		S3C_VA_IRQ
    61. 

  61. #define S5PC100_PA_VIC_OFFSET	0x100000
    62. 

  62. #define S5PC100_VA_VIC_OFFSET	0x10000
    63. 

  63. #define S5PC1XX_PA_VIC(x)	(S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
    64. 

  64. #define S5PC1XX_VA_VIC(x)	(S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
    65. 

  65. 

  66. #define S5PC100_PA_ONENAND	(0xE7100000)
    67. 

  67. 

  68. /* DMA */
    69. 

  69. #define S5PC100_PA_MDMA		(0xE8100000)
    70. 

  70. #define S5PC100_PA_PDMA0	(0xE9000000)
    71. 

  71. #define S5PC100_PA_PDMA1	(0xE9200000)
    72. 

  72. 

  73. /* Timer */
    74. 

  74. #define S5PC100_PA_TIMER	(0xEA000000)
    75. 

  75. #define S5PC1XX_PA_TIMER	S5PC100_PA_TIMER
    76. 

  76. #define S5PC1XX_VA_TIMER	S3C_VA_TIMER
    77. 

  77. 

  78. /* RTC */
    79. 

  79. #define S5PC100_PA_RTC		(0xEA300000)
    80. 

  80. 

  81. /* UART */
    82. 

  82. #define S5PC100_PA_UART		(0xEC000000)
    83. 

  83. #define S5PC1XX_PA_UART		S5PC100_PA_UART
    84. 

  84. #define S5PC1XX_VA_UART		S3C_VA_UART
    85. 

  85. 

  86. /* I2C */
    87. 

  87. #define S5PC100_PA_I2C		(0xEC100000)
    88. 

  88. #define S5PC100_PA_I2C1		(0xEC200000)
    89. 

  89. 

  90. /* USB HS OTG */
    91. 

  91. #define S5PC100_PA_USB_HSOTG	(0xED200000)
    92. 

  92. #define S5PC100_PA_USB_HSPHY	(0xED300000)
    93. 

  93. 

  94. /* SD/MMC */
    95. 

  95. #define S5PC100_PA_HSMMC(x)	(0xED800000 + ((x) * 0x100000))
    96. 

  96. #define S5PC100_PA_HSMMC0	S5PC100_PA_HSMMC(0)
    97. 

  97. #define S5PC100_PA_HSMMC1	S5PC100_PA_HSMMC(1)
    98. 

  98. #define S5PC100_PA_HSMMC2	S5PC100_PA_HSMMC(2)
    99. 

  99. 

  100. /* LCD */
    101. 

  101. #define S5PC100_PA_FB		(0xEE000000)
    102. 

  102. 

  103. /* Multimedia */
    104. 

  104. #define S5PC100_PA_G2D		(0xEE800000)
    105. 

  105. #define S5PC100_PA_JPEG		(0xEE500000)
    106. 

  106. #define S5PC100_PA_ROTATOR	(0xEE100000)
    107. 

  107. #define S5PC100_PA_G3D		(0xEF000000)
    108. 

  108. 

  109. /* I2S */
    110. 

  110. #define S5PC100_PA_I2S0		(0xF2000000)
    111. 

  111. #define S5PC100_PA_I2S1		(0xF2100000)
    112. 

  112. #define S5PC100_PA_I2S2		(0xF2200000)
    113. 

  113. 

  114. /* KEYPAD */
    115. 

  115. #define S5PC100_PA_KEYPAD	(0xF3100000)
    116. 

  116. 

  117. /* ADC & TouchScreen */
    118. 

  118. #define S5PC100_PA_TSADC	(0xF3000000)
    119. 

  119. 

  120. /* ETC */
    121. 

  121. #define S5PC100_PA_SDRAM	(0x20000000)
    122. 

  122. #define S5PC1XX_PA_SDRAM	S5PC100_PA_SDRAM
    123. 

  123. 

  124. /* compatibility defines. */
    125. 

  125. #define S3C_PA_RTC		S5PC100_PA_RTC
    126. 

  126. #define S3C_PA_UART		S5PC100_PA_UART
    127. 

  127. #define S3C_PA_UART0		(S5PC100_PA_UART + 0x0)
    128. 

  128. #define S3C_PA_UART1		(S5PC100_PA_UART + 0x400)
    129. 

  129. #define S3C_PA_UART2		(S5PC100_PA_UART + 0x800)
    130. 

  130. #define S3C_PA_UART3		(S5PC100_PA_UART + 0xC00)
    131. 

  131. #define S3C_VA_UART0		(S3C_VA_UART + 0x0)
    132. 

  132. #define S3C_VA_UART1		(S3C_VA_UART + 0x400)
    133. 

  133. #define S3C_VA_UART2		(S3C_VA_UART + 0x800)
    134. 

  134. #define S3C_VA_UART3		(S3C_VA_UART + 0xC00)
    135. 

  135. #define S3C_UART_OFFSET		0x400
    136. 

  136. #define S3C_VA_UARTx(x)		(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
    137. 

  137. #define S3C_PA_FB		S5PC100_PA_FB
    138. 

  138. #define S3C_PA_G2D		S5PC100_PA_G2D
    139. 

  139. #define S3C_PA_G3D		S5PC100_PA_G3D
    140. 

  140. #define S3C_PA_JPEG		S5PC100_PA_JPEG
    141. 

  141. #define S3C_PA_ROTATOR		S5PC100_PA_ROTATOR
    142. 

  142. #define S3C_VA_VIC0		(S3C_VA_IRQ + 0x0)
    143. 

  143. #define S3C_VA_VIC1		(S3C_VA_IRQ + 0x10000)
    144. 

  144. #define S3C_VA_VIC2		(S3C_VA_IRQ + 0x20000)
    145. 

  145. #define S3C_PA_IIC		S5PC100_PA_I2C
    146. 

  146. #define S3C_PA_IIC1		S5PC100_PA_I2C1
    147. 

  147. #define S3C_PA_USB_HSOTG	S5PC100_PA_USB_HSOTG
    148. 

  148. #define S3C_PA_USB_HSPHY	S5PC100_PA_USB_HSPHY
    149. 

  149. #define S3C_PA_HSMMC0		S5PC100_PA_HSMMC0
    150. 

  150. #define S3C_PA_HSMMC1		S5PC100_PA_HSMMC1
    151. 

  151. #define S3C_PA_HSMMC2		S5PC100_PA_HSMMC2
    152. 

  152. #define S3C_PA_KEYPAD		S5PC100_PA_KEYPAD
    153. 

  153. #define S3C_PA_TSADC		S5PC100_PA_TSADC
    154. 

  154. #define S3C_PA_ONENAND		S5PC100_PA_ONENAND
    155. 

  155. #define S3C_PA_ONENAND_BUF	S5PC100_PA_ONENAND_BUF
    156. 

  156. #define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF
    157. 

  157. 

  158. #endif /* __ASM_ARCH_C100_MAP_H */
    159.