em28xx-core.c 31 KB

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  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/slab.h>
  23. #include <linux/usb.h>
  24. #include <linux/vmalloc.h>
  25. #include <media/v4l2-common.h>
  26. #include "em28xx.h"
  27. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  28. static unsigned int core_debug;
  29. module_param(core_debug, int, 0644);
  30. MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
  31. #define em28xx_coredbg(fmt, arg...) do {\
  32. if (core_debug) \
  33. printk(KERN_INFO "%s %s :"fmt, \
  34. dev->name, __func__ , ##arg); } while (0)
  35. static unsigned int reg_debug;
  36. module_param(reg_debug, int, 0644);
  37. MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
  38. #define em28xx_regdbg(fmt, arg...) do {\
  39. if (reg_debug) \
  40. printk(KERN_INFO "%s %s :"fmt, \
  41. dev->name, __func__ , ##arg); } while (0)
  42. static int alt;
  43. module_param(alt, int, 0644);
  44. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  45. static unsigned int disable_vbi;
  46. module_param(disable_vbi, int, 0644);
  47. MODULE_PARM_DESC(disable_vbi, "disable vbi support");
  48. /* FIXME */
  49. #define em28xx_isocdbg(fmt, arg...) do {\
  50. if (core_debug) \
  51. printk(KERN_INFO "%s %s :"fmt, \
  52. dev->name, __func__ , ##arg); } while (0)
  53. /*
  54. * em28xx_read_reg_req()
  55. * reads data from the usb device specifying bRequest
  56. */
  57. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  58. char *buf, int len)
  59. {
  60. int ret;
  61. int pipe = usb_rcvctrlpipe(dev->udev, 0);
  62. if (dev->state & DEV_DISCONNECTED)
  63. return -ENODEV;
  64. if (len > URB_MAX_CTRL_SIZE)
  65. return -EINVAL;
  66. if (reg_debug) {
  67. printk(KERN_DEBUG "(pipe 0x%08x): "
  68. "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
  69. pipe,
  70. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  71. req, 0, 0,
  72. reg & 0xff, reg >> 8,
  73. len & 0xff, len >> 8);
  74. }
  75. mutex_lock(&dev->ctrl_urb_lock);
  76. ret = usb_control_msg(dev->udev, pipe, req,
  77. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  78. 0x0000, reg, dev->urb_buf, len, HZ);
  79. if (ret < 0) {
  80. if (reg_debug)
  81. printk(" failed!\n");
  82. mutex_unlock(&dev->ctrl_urb_lock);
  83. return ret;
  84. }
  85. if (len)
  86. memcpy(buf, dev->urb_buf, len);
  87. mutex_unlock(&dev->ctrl_urb_lock);
  88. if (reg_debug) {
  89. int byte;
  90. printk("<<<");
  91. for (byte = 0; byte < len; byte++)
  92. printk(" %02x", (unsigned char)buf[byte]);
  93. printk("\n");
  94. }
  95. return ret;
  96. }
  97. /*
  98. * em28xx_read_reg_req()
  99. * reads data from the usb device specifying bRequest
  100. */
  101. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  102. {
  103. int ret;
  104. u8 val;
  105. ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
  106. if (ret < 0)
  107. return ret;
  108. return val;
  109. }
  110. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  111. {
  112. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  113. }
  114. /*
  115. * em28xx_write_regs_req()
  116. * sends data to the usb device, specifying bRequest
  117. */
  118. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  119. int len)
  120. {
  121. int ret;
  122. int pipe = usb_sndctrlpipe(dev->udev, 0);
  123. if (dev->state & DEV_DISCONNECTED)
  124. return -ENODEV;
  125. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  126. return -EINVAL;
  127. if (reg_debug) {
  128. int byte;
  129. printk(KERN_DEBUG "(pipe 0x%08x): "
  130. "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
  131. pipe,
  132. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  133. req, 0, 0,
  134. reg & 0xff, reg >> 8,
  135. len & 0xff, len >> 8);
  136. for (byte = 0; byte < len; byte++)
  137. printk(" %02x", (unsigned char)buf[byte]);
  138. printk("\n");
  139. }
  140. mutex_lock(&dev->ctrl_urb_lock);
  141. memcpy(dev->urb_buf, buf, len);
  142. ret = usb_control_msg(dev->udev, pipe, req,
  143. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  144. 0x0000, reg, dev->urb_buf, len, HZ);
  145. mutex_unlock(&dev->ctrl_urb_lock);
  146. if (dev->wait_after_write)
  147. msleep(dev->wait_after_write);
  148. return ret;
  149. }
  150. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  151. {
  152. int rc;
  153. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  154. /* Stores GPO/GPIO values at the cache, if changed
  155. Only write values should be stored, since input on a GPIO
  156. register will return the input bits.
  157. Not sure what happens on reading GPO register.
  158. */
  159. if (rc >= 0) {
  160. if (reg == dev->reg_gpo_num)
  161. dev->reg_gpo = buf[0];
  162. else if (reg == dev->reg_gpio_num)
  163. dev->reg_gpio = buf[0];
  164. }
  165. return rc;
  166. }
  167. /* Write a single register */
  168. int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
  169. {
  170. return em28xx_write_regs(dev, reg, &val, 1);
  171. }
  172. /*
  173. * em28xx_write_reg_bits()
  174. * sets only some bits (specified by bitmask) of a register, by first reading
  175. * the actual value
  176. */
  177. int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  178. u8 bitmask)
  179. {
  180. int oldval;
  181. u8 newval;
  182. /* Uses cache for gpo/gpio registers */
  183. if (reg == dev->reg_gpo_num)
  184. oldval = dev->reg_gpo;
  185. else if (reg == dev->reg_gpio_num)
  186. oldval = dev->reg_gpio;
  187. else
  188. oldval = em28xx_read_reg(dev, reg);
  189. if (oldval < 0)
  190. return oldval;
  191. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  192. return em28xx_write_regs(dev, reg, &newval, 1);
  193. }
  194. /*
  195. * em28xx_is_ac97_ready()
  196. * Checks if ac97 is ready
  197. */
  198. static int em28xx_is_ac97_ready(struct em28xx *dev)
  199. {
  200. int ret, i;
  201. /* Wait up to 50 ms for AC97 command to complete */
  202. for (i = 0; i < 10; i++, msleep(5)) {
  203. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  204. if (ret < 0)
  205. return ret;
  206. if (!(ret & 0x01))
  207. return 0;
  208. }
  209. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  210. return -EBUSY;
  211. }
  212. /*
  213. * em28xx_read_ac97()
  214. * write a 16 bit value to the specified AC97 address (LSB first!)
  215. */
  216. int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  217. {
  218. int ret;
  219. u8 addr = (reg & 0x7f) | 0x80;
  220. u16 val;
  221. ret = em28xx_is_ac97_ready(dev);
  222. if (ret < 0)
  223. return ret;
  224. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  225. if (ret < 0)
  226. return ret;
  227. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  228. (u8 *)&val, sizeof(val));
  229. if (ret < 0)
  230. return ret;
  231. return le16_to_cpu(val);
  232. }
  233. /*
  234. * em28xx_write_ac97()
  235. * write a 16 bit value to the specified AC97 address (LSB first!)
  236. */
  237. int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  238. {
  239. int ret;
  240. u8 addr = reg & 0x7f;
  241. __le16 value;
  242. value = cpu_to_le16(val);
  243. ret = em28xx_is_ac97_ready(dev);
  244. if (ret < 0)
  245. return ret;
  246. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
  247. if (ret < 0)
  248. return ret;
  249. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  250. if (ret < 0)
  251. return ret;
  252. return 0;
  253. }
  254. struct em28xx_vol_table {
  255. enum em28xx_amux mux;
  256. u8 reg;
  257. };
  258. static struct em28xx_vol_table inputs[] = {
  259. { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
  260. { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
  261. { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
  262. { EM28XX_AMUX_MIC, AC97_MIC_VOL },
  263. { EM28XX_AMUX_CD, AC97_CD_VOL },
  264. { EM28XX_AMUX_AUX, AC97_AUX_VOL },
  265. { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
  266. };
  267. static int set_ac97_input(struct em28xx *dev)
  268. {
  269. int ret, i;
  270. enum em28xx_amux amux = dev->ctl_ainput;
  271. /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  272. em28xx should point to LINE IN, while AC97 should use VIDEO
  273. */
  274. if (amux == EM28XX_AMUX_VIDEO2)
  275. amux = EM28XX_AMUX_VIDEO;
  276. /* Mute all entres but the one that were selected */
  277. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  278. if (amux == inputs[i].mux)
  279. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  280. else
  281. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  282. if (ret < 0)
  283. em28xx_warn("couldn't setup AC97 register %d\n",
  284. inputs[i].reg);
  285. }
  286. return 0;
  287. }
  288. static int em28xx_set_audio_source(struct em28xx *dev)
  289. {
  290. int ret;
  291. u8 input;
  292. if (dev->board.is_em2800) {
  293. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  294. input = EM2800_AUDIO_SRC_TUNER;
  295. else
  296. input = EM2800_AUDIO_SRC_LINE;
  297. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  298. if (ret < 0)
  299. return ret;
  300. }
  301. if (dev->board.has_msp34xx)
  302. input = EM28XX_AUDIO_SRC_TUNER;
  303. else {
  304. switch (dev->ctl_ainput) {
  305. case EM28XX_AMUX_VIDEO:
  306. input = EM28XX_AUDIO_SRC_TUNER;
  307. break;
  308. default:
  309. input = EM28XX_AUDIO_SRC_LINE;
  310. break;
  311. }
  312. }
  313. if (dev->board.mute_gpio && dev->mute)
  314. em28xx_gpio_set(dev, dev->board.mute_gpio);
  315. else
  316. em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  317. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  318. if (ret < 0)
  319. return ret;
  320. msleep(5);
  321. switch (dev->audio_mode.ac97) {
  322. case EM28XX_NO_AC97:
  323. break;
  324. default:
  325. ret = set_ac97_input(dev);
  326. }
  327. return ret;
  328. }
  329. static const struct em28xx_vol_table outputs[] = {
  330. { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
  331. { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
  332. { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
  333. { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
  334. { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
  335. };
  336. int em28xx_audio_analog_set(struct em28xx *dev)
  337. {
  338. int ret, i;
  339. u8 xclk;
  340. if (!dev->audio_mode.has_audio)
  341. return 0;
  342. /* It is assumed that all devices use master volume for output.
  343. It would be possible to use also line output.
  344. */
  345. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  346. /* Mute all outputs */
  347. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  348. ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
  349. if (ret < 0)
  350. em28xx_warn("couldn't setup AC97 register %d\n",
  351. outputs[i].reg);
  352. }
  353. }
  354. xclk = dev->board.xclk & 0x7f;
  355. if (!dev->mute)
  356. xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
  357. ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
  358. if (ret < 0)
  359. return ret;
  360. msleep(10);
  361. /* Selects the proper audio input */
  362. ret = em28xx_set_audio_source(dev);
  363. /* Sets volume */
  364. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  365. int vol;
  366. em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
  367. em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
  368. em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
  369. /* LSB: left channel - both channels with the same level */
  370. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  371. /* Mute device, if needed */
  372. if (dev->mute)
  373. vol |= 0x8000;
  374. /* Sets volume */
  375. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  376. if (dev->ctl_aoutput & outputs[i].mux)
  377. ret = em28xx_write_ac97(dev, outputs[i].reg,
  378. vol);
  379. if (ret < 0)
  380. em28xx_warn("couldn't setup AC97 register %d\n",
  381. outputs[i].reg);
  382. }
  383. if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
  384. int sel = ac97_return_record_select(dev->ctl_aoutput);
  385. /* Use the same input for both left and right
  386. channels */
  387. sel |= (sel << 8);
  388. em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
  389. }
  390. }
  391. return ret;
  392. }
  393. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  394. int em28xx_audio_setup(struct em28xx *dev)
  395. {
  396. int vid1, vid2, feat, cfg;
  397. u32 vid;
  398. if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
  399. /* Digital only device - don't load any alsa module */
  400. dev->audio_mode.has_audio = 0;
  401. dev->has_audio_class = 0;
  402. dev->has_alsa_audio = 0;
  403. return 0;
  404. }
  405. /* If device doesn't support Usb Audio Class, use vendor class */
  406. if (!dev->has_audio_class)
  407. dev->has_alsa_audio = 1;
  408. dev->audio_mode.has_audio = 1;
  409. /* See how this device is configured */
  410. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  411. em28xx_info("Config register raw data: 0x%02x\n", cfg);
  412. if (cfg < 0) {
  413. /* Register read error? */
  414. cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
  415. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
  416. /* The device doesn't have vendor audio at all */
  417. dev->has_alsa_audio = 0;
  418. dev->audio_mode.has_audio = 0;
  419. return 0;
  420. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  421. EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
  422. em28xx_info("I2S Audio (3 sample rates)\n");
  423. dev->audio_mode.i2s_3rates = 1;
  424. } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  425. EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
  426. em28xx_info("I2S Audio (5 sample rates)\n");
  427. dev->audio_mode.i2s_5rates = 1;
  428. }
  429. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
  430. /* Skip the code that does AC97 vendor detection */
  431. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  432. goto init_audio;
  433. }
  434. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  435. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  436. if (vid1 < 0) {
  437. /*
  438. * Device likely doesn't support AC97
  439. * Note: (some) em2800 devices without eeprom reports 0x91 on
  440. * CHIPCFG register, even not having an AC97 chip
  441. */
  442. em28xx_warn("AC97 chip type couldn't be determined\n");
  443. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  444. dev->has_alsa_audio = 0;
  445. dev->audio_mode.has_audio = 0;
  446. goto init_audio;
  447. }
  448. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  449. if (vid2 < 0)
  450. goto init_audio;
  451. vid = vid1 << 16 | vid2;
  452. dev->audio_mode.ac97_vendor_id = vid;
  453. em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
  454. feat = em28xx_read_ac97(dev, AC97_RESET);
  455. if (feat < 0)
  456. goto init_audio;
  457. dev->audio_mode.ac97_feat = feat;
  458. em28xx_warn("AC97 features = 0x%04x\n", feat);
  459. /* Try to identify what audio processor we have */
  460. if ((vid == 0xffffffff) && (feat == 0x6a90))
  461. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  462. else if ((vid >> 8) == 0x838476)
  463. dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
  464. init_audio:
  465. /* Reports detected AC97 processor */
  466. switch (dev->audio_mode.ac97) {
  467. case EM28XX_NO_AC97:
  468. em28xx_info("No AC97 audio processor\n");
  469. break;
  470. case EM28XX_AC97_EM202:
  471. em28xx_info("Empia 202 AC97 audio processor detected\n");
  472. break;
  473. case EM28XX_AC97_SIGMATEL:
  474. em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
  475. dev->audio_mode.ac97_vendor_id & 0xff);
  476. break;
  477. case EM28XX_AC97_OTHER:
  478. em28xx_warn("Unknown AC97 audio processor detected!\n");
  479. break;
  480. default:
  481. break;
  482. }
  483. return em28xx_audio_analog_set(dev);
  484. }
  485. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  486. int em28xx_colorlevels_set_default(struct em28xx *dev)
  487. {
  488. em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
  489. em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
  490. em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
  491. em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
  492. em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
  493. em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
  494. em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
  495. em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
  496. em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
  497. em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
  498. em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
  499. em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
  500. return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
  501. }
  502. int em28xx_capture_start(struct em28xx *dev, int start)
  503. {
  504. int rc;
  505. if (dev->chip_id == CHIP_ID_EM2874) {
  506. /* The Transport Stream Enable Register moved in em2874 */
  507. if (!start) {
  508. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  509. 0x00,
  510. EM2874_TS1_CAPTURE_ENABLE);
  511. return rc;
  512. }
  513. /* Enable Transport Stream */
  514. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  515. EM2874_TS1_CAPTURE_ENABLE,
  516. EM2874_TS1_CAPTURE_ENABLE);
  517. return rc;
  518. }
  519. /* FIXME: which is the best order? */
  520. /* video registers are sampled by VREF */
  521. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  522. start ? 0x10 : 0x00, 0x10);
  523. if (rc < 0)
  524. return rc;
  525. if (!start) {
  526. /* disable video capture */
  527. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
  528. return rc;
  529. }
  530. if (dev->board.is_webcam)
  531. rc = em28xx_write_reg(dev, 0x13, 0x0c);
  532. /* enable video capture */
  533. rc = em28xx_write_reg(dev, 0x48, 0x00);
  534. if (dev->mode == EM28XX_ANALOG_MODE)
  535. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  536. else
  537. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  538. msleep(6);
  539. return rc;
  540. }
  541. int em28xx_vbi_supported(struct em28xx *dev)
  542. {
  543. /* Modprobe option to manually disable */
  544. if (disable_vbi == 1)
  545. return 0;
  546. if (dev->chip_id == CHIP_ID_EM2860 ||
  547. dev->chip_id == CHIP_ID_EM2883)
  548. return 1;
  549. /* Version of em28xx that does not support VBI */
  550. return 0;
  551. }
  552. int em28xx_set_outfmt(struct em28xx *dev)
  553. {
  554. int ret;
  555. u8 vinctrl;
  556. ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
  557. dev->format->reg | 0x20, 0xff);
  558. if (ret < 0)
  559. return ret;
  560. ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
  561. if (ret < 0)
  562. return ret;
  563. vinctrl = dev->vinctl;
  564. if (em28xx_vbi_supported(dev) == 1) {
  565. vinctrl |= EM28XX_VINCTRL_VBI_RAW;
  566. em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
  567. em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
  568. em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
  569. if (dev->norm & V4L2_STD_525_60) {
  570. /* NTSC */
  571. em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
  572. } else if (dev->norm & V4L2_STD_625_50) {
  573. /* PAL */
  574. em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
  575. }
  576. }
  577. return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
  578. }
  579. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  580. u8 ymin, u8 ymax)
  581. {
  582. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  583. xmin, ymin, xmax, ymax);
  584. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  585. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  586. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  587. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  588. }
  589. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  590. u16 width, u16 height)
  591. {
  592. u8 cwidth = width;
  593. u8 cheight = height;
  594. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  595. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  596. (width | (overflow & 2) << 7),
  597. (height | (overflow & 1) << 8));
  598. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  599. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  600. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  601. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  602. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  603. }
  604. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  605. {
  606. u8 mode;
  607. /* the em2800 scaler only supports scaling down to 50% */
  608. if (dev->board.is_em2800) {
  609. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  610. } else {
  611. u8 buf[2];
  612. buf[0] = h;
  613. buf[1] = h >> 8;
  614. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  615. buf[0] = v;
  616. buf[1] = v >> 8;
  617. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  618. /* it seems that both H and V scalers must be active
  619. to work correctly */
  620. mode = (h || v) ? 0x30 : 0x00;
  621. }
  622. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  623. }
  624. /* FIXME: this only function read values from dev */
  625. int em28xx_resolution_set(struct em28xx *dev)
  626. {
  627. int width, height;
  628. width = norm_maxw(dev);
  629. height = norm_maxh(dev);
  630. /* Properly setup VBI */
  631. dev->vbi_width = 720;
  632. if (dev->norm & V4L2_STD_525_60)
  633. dev->vbi_height = 12;
  634. else
  635. dev->vbi_height = 18;
  636. if (!dev->progressive)
  637. height >>= norm_maxh(dev);
  638. em28xx_set_outfmt(dev);
  639. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  640. /* If we don't set the start position to 4 in VBI mode, we end up
  641. with line 21 being YUYV encoded instead of being in 8-bit
  642. greyscale */
  643. if (em28xx_vbi_supported(dev) == 1)
  644. em28xx_capture_area_set(dev, 0, 4, width >> 2, height >> 2);
  645. else
  646. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  647. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  648. }
  649. int em28xx_set_alternate(struct em28xx *dev)
  650. {
  651. int errCode, prev_alt = dev->alt;
  652. int i;
  653. unsigned int min_pkt_size = dev->width * 2 + 4;
  654. /*
  655. * alt = 0 is used only for control messages, so, only values
  656. * greater than 0 can be used for streaming.
  657. */
  658. if (alt && alt < dev->num_alt) {
  659. em28xx_coredbg("alternate forced to %d\n", dev->alt);
  660. dev->alt = alt;
  661. goto set_alt;
  662. }
  663. /* When image size is bigger than a certain value,
  664. the frame size should be increased, otherwise, only
  665. green screen will be received.
  666. */
  667. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  668. min_pkt_size *= 2;
  669. for (i = 0; i < dev->num_alt; i++) {
  670. /* stop when the selected alt setting offers enough bandwidth */
  671. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  672. dev->alt = i;
  673. break;
  674. /* otherwise make sure that we end up with the maximum bandwidth
  675. because the min_pkt_size equation might be wrong...
  676. */
  677. } else if (dev->alt_max_pkt_size[i] >
  678. dev->alt_max_pkt_size[dev->alt])
  679. dev->alt = i;
  680. }
  681. set_alt:
  682. if (dev->alt != prev_alt) {
  683. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  684. min_pkt_size, dev->alt);
  685. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  686. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  687. dev->alt, dev->max_pkt_size);
  688. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  689. if (errCode < 0) {
  690. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  691. dev->alt, errCode);
  692. return errCode;
  693. }
  694. }
  695. return 0;
  696. }
  697. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  698. {
  699. int rc = 0;
  700. if (!gpio)
  701. return rc;
  702. if (dev->mode != EM28XX_SUSPEND) {
  703. em28xx_write_reg(dev, 0x48, 0x00);
  704. if (dev->mode == EM28XX_ANALOG_MODE)
  705. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  706. else
  707. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  708. msleep(6);
  709. }
  710. /* Send GPIO reset sequences specified at board entry */
  711. while (gpio->sleep >= 0) {
  712. if (gpio->reg >= 0) {
  713. rc = em28xx_write_reg_bits(dev,
  714. gpio->reg,
  715. gpio->val,
  716. gpio->mask);
  717. if (rc < 0)
  718. return rc;
  719. }
  720. if (gpio->sleep > 0)
  721. msleep(gpio->sleep);
  722. gpio++;
  723. }
  724. return rc;
  725. }
  726. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  727. {
  728. if (dev->mode == set_mode)
  729. return 0;
  730. if (set_mode == EM28XX_SUSPEND) {
  731. dev->mode = set_mode;
  732. /* FIXME: add suspend support for ac97 */
  733. return em28xx_gpio_set(dev, dev->board.suspend_gpio);
  734. }
  735. dev->mode = set_mode;
  736. if (dev->mode == EM28XX_DIGITAL_MODE)
  737. return em28xx_gpio_set(dev, dev->board.dvb_gpio);
  738. else
  739. return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  740. }
  741. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  742. /* ------------------------------------------------------------------
  743. URB control
  744. ------------------------------------------------------------------*/
  745. /*
  746. * IRQ callback, called by URB callback
  747. */
  748. static void em28xx_irq_callback(struct urb *urb)
  749. {
  750. struct em28xx *dev = urb->context;
  751. int rc, i;
  752. switch (urb->status) {
  753. case 0: /* success */
  754. case -ETIMEDOUT: /* NAK */
  755. break;
  756. case -ECONNRESET: /* kill */
  757. case -ENOENT:
  758. case -ESHUTDOWN:
  759. return;
  760. default: /* error */
  761. em28xx_isocdbg("urb completition error %d.\n", urb->status);
  762. break;
  763. }
  764. /* Copy data from URB */
  765. spin_lock(&dev->slock);
  766. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  767. spin_unlock(&dev->slock);
  768. /* Reset urb buffers */
  769. for (i = 0; i < urb->number_of_packets; i++) {
  770. urb->iso_frame_desc[i].status = 0;
  771. urb->iso_frame_desc[i].actual_length = 0;
  772. }
  773. urb->status = 0;
  774. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  775. if (urb->status) {
  776. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  777. urb->status);
  778. }
  779. }
  780. /*
  781. * Stop and Deallocate URBs
  782. */
  783. void em28xx_uninit_isoc(struct em28xx *dev)
  784. {
  785. struct urb *urb;
  786. int i;
  787. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  788. dev->isoc_ctl.nfields = -1;
  789. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  790. urb = dev->isoc_ctl.urb[i];
  791. if (urb) {
  792. if (!irqs_disabled())
  793. usb_kill_urb(urb);
  794. else
  795. usb_unlink_urb(urb);
  796. if (dev->isoc_ctl.transfer_buffer[i]) {
  797. usb_free_coherent(dev->udev,
  798. urb->transfer_buffer_length,
  799. dev->isoc_ctl.transfer_buffer[i],
  800. urb->transfer_dma);
  801. }
  802. usb_free_urb(urb);
  803. dev->isoc_ctl.urb[i] = NULL;
  804. }
  805. dev->isoc_ctl.transfer_buffer[i] = NULL;
  806. }
  807. kfree(dev->isoc_ctl.urb);
  808. kfree(dev->isoc_ctl.transfer_buffer);
  809. dev->isoc_ctl.urb = NULL;
  810. dev->isoc_ctl.transfer_buffer = NULL;
  811. dev->isoc_ctl.num_bufs = 0;
  812. em28xx_capture_start(dev, 0);
  813. }
  814. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  815. /*
  816. * Allocate URBs and start IRQ
  817. */
  818. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  819. int num_bufs, int max_pkt_size,
  820. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  821. {
  822. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  823. struct em28xx_dmaqueue *vbi_dma_q = &dev->vbiq;
  824. int i;
  825. int sb_size, pipe;
  826. struct urb *urb;
  827. int j, k;
  828. int rc;
  829. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  830. /* De-allocates all pending stuff */
  831. em28xx_uninit_isoc(dev);
  832. dev->isoc_ctl.isoc_copy = isoc_copy;
  833. dev->isoc_ctl.num_bufs = num_bufs;
  834. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  835. if (!dev->isoc_ctl.urb) {
  836. em28xx_errdev("cannot alloc memory for usb buffers\n");
  837. return -ENOMEM;
  838. }
  839. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  840. GFP_KERNEL);
  841. if (!dev->isoc_ctl.transfer_buffer) {
  842. em28xx_errdev("cannot allocate memory for usb transfer\n");
  843. kfree(dev->isoc_ctl.urb);
  844. return -ENOMEM;
  845. }
  846. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  847. dev->isoc_ctl.vid_buf = NULL;
  848. dev->isoc_ctl.vbi_buf = NULL;
  849. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  850. /* allocate urbs and transfer buffers */
  851. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  852. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  853. if (!urb) {
  854. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  855. em28xx_uninit_isoc(dev);
  856. return -ENOMEM;
  857. }
  858. dev->isoc_ctl.urb[i] = urb;
  859. dev->isoc_ctl.transfer_buffer[i] = usb_alloc_coherent(dev->udev,
  860. sb_size, GFP_KERNEL, &urb->transfer_dma);
  861. if (!dev->isoc_ctl.transfer_buffer[i]) {
  862. em28xx_err("unable to allocate %i bytes for transfer"
  863. " buffer %i%s\n",
  864. sb_size, i,
  865. in_interrupt() ? " while in int" : "");
  866. em28xx_uninit_isoc(dev);
  867. return -ENOMEM;
  868. }
  869. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  870. /* FIXME: this is a hack - should be
  871. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  872. should also be using 'desc.bInterval'
  873. */
  874. pipe = usb_rcvisocpipe(dev->udev,
  875. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  876. usb_fill_int_urb(urb, dev->udev, pipe,
  877. dev->isoc_ctl.transfer_buffer[i], sb_size,
  878. em28xx_irq_callback, dev, 1);
  879. urb->number_of_packets = max_packets;
  880. urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
  881. k = 0;
  882. for (j = 0; j < max_packets; j++) {
  883. urb->iso_frame_desc[j].offset = k;
  884. urb->iso_frame_desc[j].length =
  885. dev->isoc_ctl.max_pkt_size;
  886. k += dev->isoc_ctl.max_pkt_size;
  887. }
  888. }
  889. init_waitqueue_head(&dma_q->wq);
  890. init_waitqueue_head(&vbi_dma_q->wq);
  891. em28xx_capture_start(dev, 1);
  892. /* submit urbs and enables IRQ */
  893. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  894. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  895. if (rc) {
  896. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  897. rc);
  898. em28xx_uninit_isoc(dev);
  899. return rc;
  900. }
  901. }
  902. return 0;
  903. }
  904. EXPORT_SYMBOL_GPL(em28xx_init_isoc);
  905. /* Determine the packet size for the DVB stream for the given device
  906. (underlying value programmed into the eeprom) */
  907. int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
  908. {
  909. unsigned int chip_cfg2;
  910. unsigned int packet_size = 564;
  911. if (dev->chip_id == CHIP_ID_EM2874) {
  912. /* FIXME - for now assume 564 like it was before, but the
  913. em2874 code should be added to return the proper value... */
  914. packet_size = 564;
  915. } else {
  916. /* TS max packet size stored in bits 1-0 of R01 */
  917. chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
  918. switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
  919. case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
  920. packet_size = 188;
  921. break;
  922. case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
  923. packet_size = 376;
  924. break;
  925. case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
  926. packet_size = 564;
  927. break;
  928. case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
  929. packet_size = 752;
  930. break;
  931. }
  932. }
  933. em28xx_coredbg("dvb max packet size=%d\n", packet_size);
  934. return packet_size;
  935. }
  936. EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
  937. /*
  938. * em28xx_wake_i2c()
  939. * configure i2c attached devices
  940. */
  941. void em28xx_wake_i2c(struct em28xx *dev)
  942. {
  943. v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
  944. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
  945. INPUT(dev->ctl_input)->vmux, 0, 0);
  946. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
  947. }
  948. /*
  949. * Device control list
  950. */
  951. static LIST_HEAD(em28xx_devlist);
  952. static DEFINE_MUTEX(em28xx_devlist_mutex);
  953. /*
  954. * em28xx_realease_resources()
  955. * unregisters the v4l2,i2c and usb devices
  956. * called when the device gets disconected or at module unload
  957. */
  958. void em28xx_remove_from_devlist(struct em28xx *dev)
  959. {
  960. mutex_lock(&em28xx_devlist_mutex);
  961. list_del(&dev->devlist);
  962. mutex_unlock(&em28xx_devlist_mutex);
  963. };
  964. void em28xx_add_into_devlist(struct em28xx *dev)
  965. {
  966. mutex_lock(&em28xx_devlist_mutex);
  967. list_add_tail(&dev->devlist, &em28xx_devlist);
  968. mutex_unlock(&em28xx_devlist_mutex);
  969. };
  970. /*
  971. * Extension interface
  972. */
  973. static LIST_HEAD(em28xx_extension_devlist);
  974. static DEFINE_MUTEX(em28xx_extension_devlist_lock);
  975. int em28xx_register_extension(struct em28xx_ops *ops)
  976. {
  977. struct em28xx *dev = NULL;
  978. mutex_lock(&em28xx_devlist_mutex);
  979. mutex_lock(&em28xx_extension_devlist_lock);
  980. list_add_tail(&ops->next, &em28xx_extension_devlist);
  981. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  982. if (dev)
  983. ops->init(dev);
  984. }
  985. printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
  986. mutex_unlock(&em28xx_extension_devlist_lock);
  987. mutex_unlock(&em28xx_devlist_mutex);
  988. return 0;
  989. }
  990. EXPORT_SYMBOL(em28xx_register_extension);
  991. void em28xx_unregister_extension(struct em28xx_ops *ops)
  992. {
  993. struct em28xx *dev = NULL;
  994. mutex_lock(&em28xx_devlist_mutex);
  995. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  996. if (dev)
  997. ops->fini(dev);
  998. }
  999. mutex_lock(&em28xx_extension_devlist_lock);
  1000. printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
  1001. list_del(&ops->next);
  1002. mutex_unlock(&em28xx_extension_devlist_lock);
  1003. mutex_unlock(&em28xx_devlist_mutex);
  1004. }
  1005. EXPORT_SYMBOL(em28xx_unregister_extension);
  1006. void em28xx_init_extension(struct em28xx *dev)
  1007. {
  1008. struct em28xx_ops *ops = NULL;
  1009. mutex_lock(&em28xx_extension_devlist_lock);
  1010. if (!list_empty(&em28xx_extension_devlist)) {
  1011. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  1012. if (ops->init)
  1013. ops->init(dev);
  1014. }
  1015. }
  1016. mutex_unlock(&em28xx_extension_devlist_lock);
  1017. }
  1018. void em28xx_close_extension(struct em28xx *dev)
  1019. {
  1020. struct em28xx_ops *ops = NULL;
  1021. mutex_lock(&em28xx_extension_devlist_lock);
  1022. if (!list_empty(&em28xx_extension_devlist)) {
  1023. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  1024. if (ops->fini)
  1025. ops->fini(dev);
  1026. }
  1027. }
  1028. mutex_unlock(&em28xx_extension_devlist_lock);
  1029. }