intel_display.c 262 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include <drm/drmP.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include <drm/drm_dp_helper.h>
  40. #include <drm/drm_crtc_helper.h>
  41. #include <linux/dma_remapping.h>
  42. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  43. static void intel_increase_pllclock(struct drm_crtc *crtc);
  44. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  45. typedef struct {
  46. int min, max;
  47. } intel_range_t;
  48. typedef struct {
  49. int dot_limit;
  50. int p2_slow, p2_fast;
  51. } intel_p2_t;
  52. #define INTEL_P2_NUM 2
  53. typedef struct intel_limit intel_limit_t;
  54. struct intel_limit {
  55. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  56. intel_p2_t p2;
  57. /**
  58. * find_pll() - Find the best values for the PLL
  59. * @limit: limits for the PLL
  60. * @crtc: current CRTC
  61. * @target: target frequency in kHz
  62. * @refclk: reference clock frequency in kHz
  63. * @match_clock: if provided, @best_clock P divider must
  64. * match the P divider from @match_clock
  65. * used for LVDS downclocking
  66. * @best_clock: best PLL values found
  67. *
  68. * Returns true on success, false on failure.
  69. */
  70. bool (*find_pll)(const intel_limit_t *limit,
  71. struct drm_crtc *crtc,
  72. int target, int refclk,
  73. intel_clock_t *match_clock,
  74. intel_clock_t *best_clock);
  75. };
  76. /* FDI */
  77. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  78. int
  79. intel_pch_rawclk(struct drm_device *dev)
  80. {
  81. struct drm_i915_private *dev_priv = dev->dev_private;
  82. WARN_ON(!HAS_PCH_SPLIT(dev));
  83. return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  84. }
  85. static bool
  86. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  87. int target, int refclk, intel_clock_t *match_clock,
  88. intel_clock_t *best_clock);
  89. static bool
  90. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  91. int target, int refclk, intel_clock_t *match_clock,
  92. intel_clock_t *best_clock);
  93. static bool
  94. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  95. int target, int refclk, intel_clock_t *match_clock,
  96. intel_clock_t *best_clock);
  97. static bool
  98. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  99. int target, int refclk, intel_clock_t *match_clock,
  100. intel_clock_t *best_clock);
  101. static bool
  102. intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  103. int target, int refclk, intel_clock_t *match_clock,
  104. intel_clock_t *best_clock);
  105. static inline u32 /* units of 100MHz */
  106. intel_fdi_link_freq(struct drm_device *dev)
  107. {
  108. if (IS_GEN5(dev)) {
  109. struct drm_i915_private *dev_priv = dev->dev_private;
  110. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  111. } else
  112. return 27;
  113. }
  114. static const intel_limit_t intel_limits_i8xx_dvo = {
  115. .dot = { .min = 25000, .max = 350000 },
  116. .vco = { .min = 930000, .max = 1400000 },
  117. .n = { .min = 3, .max = 16 },
  118. .m = { .min = 96, .max = 140 },
  119. .m1 = { .min = 18, .max = 26 },
  120. .m2 = { .min = 6, .max = 16 },
  121. .p = { .min = 4, .max = 128 },
  122. .p1 = { .min = 2, .max = 33 },
  123. .p2 = { .dot_limit = 165000,
  124. .p2_slow = 4, .p2_fast = 2 },
  125. .find_pll = intel_find_best_PLL,
  126. };
  127. static const intel_limit_t intel_limits_i8xx_lvds = {
  128. .dot = { .min = 25000, .max = 350000 },
  129. .vco = { .min = 930000, .max = 1400000 },
  130. .n = { .min = 3, .max = 16 },
  131. .m = { .min = 96, .max = 140 },
  132. .m1 = { .min = 18, .max = 26 },
  133. .m2 = { .min = 6, .max = 16 },
  134. .p = { .min = 4, .max = 128 },
  135. .p1 = { .min = 1, .max = 6 },
  136. .p2 = { .dot_limit = 165000,
  137. .p2_slow = 14, .p2_fast = 7 },
  138. .find_pll = intel_find_best_PLL,
  139. };
  140. static const intel_limit_t intel_limits_i9xx_sdvo = {
  141. .dot = { .min = 20000, .max = 400000 },
  142. .vco = { .min = 1400000, .max = 2800000 },
  143. .n = { .min = 1, .max = 6 },
  144. .m = { .min = 70, .max = 120 },
  145. .m1 = { .min = 8, .max = 18 },
  146. .m2 = { .min = 3, .max = 7 },
  147. .p = { .min = 5, .max = 80 },
  148. .p1 = { .min = 1, .max = 8 },
  149. .p2 = { .dot_limit = 200000,
  150. .p2_slow = 10, .p2_fast = 5 },
  151. .find_pll = intel_find_best_PLL,
  152. };
  153. static const intel_limit_t intel_limits_i9xx_lvds = {
  154. .dot = { .min = 20000, .max = 400000 },
  155. .vco = { .min = 1400000, .max = 2800000 },
  156. .n = { .min = 1, .max = 6 },
  157. .m = { .min = 70, .max = 120 },
  158. .m1 = { .min = 8, .max = 18 },
  159. .m2 = { .min = 3, .max = 7 },
  160. .p = { .min = 7, .max = 98 },
  161. .p1 = { .min = 1, .max = 8 },
  162. .p2 = { .dot_limit = 112000,
  163. .p2_slow = 14, .p2_fast = 7 },
  164. .find_pll = intel_find_best_PLL,
  165. };
  166. static const intel_limit_t intel_limits_g4x_sdvo = {
  167. .dot = { .min = 25000, .max = 270000 },
  168. .vco = { .min = 1750000, .max = 3500000},
  169. .n = { .min = 1, .max = 4 },
  170. .m = { .min = 104, .max = 138 },
  171. .m1 = { .min = 17, .max = 23 },
  172. .m2 = { .min = 5, .max = 11 },
  173. .p = { .min = 10, .max = 30 },
  174. .p1 = { .min = 1, .max = 3},
  175. .p2 = { .dot_limit = 270000,
  176. .p2_slow = 10,
  177. .p2_fast = 10
  178. },
  179. .find_pll = intel_g4x_find_best_PLL,
  180. };
  181. static const intel_limit_t intel_limits_g4x_hdmi = {
  182. .dot = { .min = 22000, .max = 400000 },
  183. .vco = { .min = 1750000, .max = 3500000},
  184. .n = { .min = 1, .max = 4 },
  185. .m = { .min = 104, .max = 138 },
  186. .m1 = { .min = 16, .max = 23 },
  187. .m2 = { .min = 5, .max = 11 },
  188. .p = { .min = 5, .max = 80 },
  189. .p1 = { .min = 1, .max = 8},
  190. .p2 = { .dot_limit = 165000,
  191. .p2_slow = 10, .p2_fast = 5 },
  192. .find_pll = intel_g4x_find_best_PLL,
  193. };
  194. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  195. .dot = { .min = 20000, .max = 115000 },
  196. .vco = { .min = 1750000, .max = 3500000 },
  197. .n = { .min = 1, .max = 3 },
  198. .m = { .min = 104, .max = 138 },
  199. .m1 = { .min = 17, .max = 23 },
  200. .m2 = { .min = 5, .max = 11 },
  201. .p = { .min = 28, .max = 112 },
  202. .p1 = { .min = 2, .max = 8 },
  203. .p2 = { .dot_limit = 0,
  204. .p2_slow = 14, .p2_fast = 14
  205. },
  206. .find_pll = intel_g4x_find_best_PLL,
  207. };
  208. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  209. .dot = { .min = 80000, .max = 224000 },
  210. .vco = { .min = 1750000, .max = 3500000 },
  211. .n = { .min = 1, .max = 3 },
  212. .m = { .min = 104, .max = 138 },
  213. .m1 = { .min = 17, .max = 23 },
  214. .m2 = { .min = 5, .max = 11 },
  215. .p = { .min = 14, .max = 42 },
  216. .p1 = { .min = 2, .max = 6 },
  217. .p2 = { .dot_limit = 0,
  218. .p2_slow = 7, .p2_fast = 7
  219. },
  220. .find_pll = intel_g4x_find_best_PLL,
  221. };
  222. static const intel_limit_t intel_limits_g4x_display_port = {
  223. .dot = { .min = 161670, .max = 227000 },
  224. .vco = { .min = 1750000, .max = 3500000},
  225. .n = { .min = 1, .max = 2 },
  226. .m = { .min = 97, .max = 108 },
  227. .m1 = { .min = 0x10, .max = 0x12 },
  228. .m2 = { .min = 0x05, .max = 0x06 },
  229. .p = { .min = 10, .max = 20 },
  230. .p1 = { .min = 1, .max = 2},
  231. .p2 = { .dot_limit = 0,
  232. .p2_slow = 10, .p2_fast = 10 },
  233. .find_pll = intel_find_pll_g4x_dp,
  234. };
  235. static const intel_limit_t intel_limits_pineview_sdvo = {
  236. .dot = { .min = 20000, .max = 400000},
  237. .vco = { .min = 1700000, .max = 3500000 },
  238. /* Pineview's Ncounter is a ring counter */
  239. .n = { .min = 3, .max = 6 },
  240. .m = { .min = 2, .max = 256 },
  241. /* Pineview only has one combined m divider, which we treat as m2. */
  242. .m1 = { .min = 0, .max = 0 },
  243. .m2 = { .min = 0, .max = 254 },
  244. .p = { .min = 5, .max = 80 },
  245. .p1 = { .min = 1, .max = 8 },
  246. .p2 = { .dot_limit = 200000,
  247. .p2_slow = 10, .p2_fast = 5 },
  248. .find_pll = intel_find_best_PLL,
  249. };
  250. static const intel_limit_t intel_limits_pineview_lvds = {
  251. .dot = { .min = 20000, .max = 400000 },
  252. .vco = { .min = 1700000, .max = 3500000 },
  253. .n = { .min = 3, .max = 6 },
  254. .m = { .min = 2, .max = 256 },
  255. .m1 = { .min = 0, .max = 0 },
  256. .m2 = { .min = 0, .max = 254 },
  257. .p = { .min = 7, .max = 112 },
  258. .p1 = { .min = 1, .max = 8 },
  259. .p2 = { .dot_limit = 112000,
  260. .p2_slow = 14, .p2_fast = 14 },
  261. .find_pll = intel_find_best_PLL,
  262. };
  263. /* Ironlake / Sandybridge
  264. *
  265. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  266. * the range value for them is (actual_value - 2).
  267. */
  268. static const intel_limit_t intel_limits_ironlake_dac = {
  269. .dot = { .min = 25000, .max = 350000 },
  270. .vco = { .min = 1760000, .max = 3510000 },
  271. .n = { .min = 1, .max = 5 },
  272. .m = { .min = 79, .max = 127 },
  273. .m1 = { .min = 12, .max = 22 },
  274. .m2 = { .min = 5, .max = 9 },
  275. .p = { .min = 5, .max = 80 },
  276. .p1 = { .min = 1, .max = 8 },
  277. .p2 = { .dot_limit = 225000,
  278. .p2_slow = 10, .p2_fast = 5 },
  279. .find_pll = intel_g4x_find_best_PLL,
  280. };
  281. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  282. .dot = { .min = 25000, .max = 350000 },
  283. .vco = { .min = 1760000, .max = 3510000 },
  284. .n = { .min = 1, .max = 3 },
  285. .m = { .min = 79, .max = 118 },
  286. .m1 = { .min = 12, .max = 22 },
  287. .m2 = { .min = 5, .max = 9 },
  288. .p = { .min = 28, .max = 112 },
  289. .p1 = { .min = 2, .max = 8 },
  290. .p2 = { .dot_limit = 225000,
  291. .p2_slow = 14, .p2_fast = 14 },
  292. .find_pll = intel_g4x_find_best_PLL,
  293. };
  294. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  295. .dot = { .min = 25000, .max = 350000 },
  296. .vco = { .min = 1760000, .max = 3510000 },
  297. .n = { .min = 1, .max = 3 },
  298. .m = { .min = 79, .max = 127 },
  299. .m1 = { .min = 12, .max = 22 },
  300. .m2 = { .min = 5, .max = 9 },
  301. .p = { .min = 14, .max = 56 },
  302. .p1 = { .min = 2, .max = 8 },
  303. .p2 = { .dot_limit = 225000,
  304. .p2_slow = 7, .p2_fast = 7 },
  305. .find_pll = intel_g4x_find_best_PLL,
  306. };
  307. /* LVDS 100mhz refclk limits. */
  308. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  309. .dot = { .min = 25000, .max = 350000 },
  310. .vco = { .min = 1760000, .max = 3510000 },
  311. .n = { .min = 1, .max = 2 },
  312. .m = { .min = 79, .max = 126 },
  313. .m1 = { .min = 12, .max = 22 },
  314. .m2 = { .min = 5, .max = 9 },
  315. .p = { .min = 28, .max = 112 },
  316. .p1 = { .min = 2, .max = 8 },
  317. .p2 = { .dot_limit = 225000,
  318. .p2_slow = 14, .p2_fast = 14 },
  319. .find_pll = intel_g4x_find_best_PLL,
  320. };
  321. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  322. .dot = { .min = 25000, .max = 350000 },
  323. .vco = { .min = 1760000, .max = 3510000 },
  324. .n = { .min = 1, .max = 3 },
  325. .m = { .min = 79, .max = 126 },
  326. .m1 = { .min = 12, .max = 22 },
  327. .m2 = { .min = 5, .max = 9 },
  328. .p = { .min = 14, .max = 42 },
  329. .p1 = { .min = 2, .max = 6 },
  330. .p2 = { .dot_limit = 225000,
  331. .p2_slow = 7, .p2_fast = 7 },
  332. .find_pll = intel_g4x_find_best_PLL,
  333. };
  334. static const intel_limit_t intel_limits_ironlake_display_port = {
  335. .dot = { .min = 25000, .max = 350000 },
  336. .vco = { .min = 1760000, .max = 3510000},
  337. .n = { .min = 1, .max = 2 },
  338. .m = { .min = 81, .max = 90 },
  339. .m1 = { .min = 12, .max = 22 },
  340. .m2 = { .min = 5, .max = 9 },
  341. .p = { .min = 10, .max = 20 },
  342. .p1 = { .min = 1, .max = 2},
  343. .p2 = { .dot_limit = 0,
  344. .p2_slow = 10, .p2_fast = 10 },
  345. .find_pll = intel_find_pll_ironlake_dp,
  346. };
  347. static const intel_limit_t intel_limits_vlv_dac = {
  348. .dot = { .min = 25000, .max = 270000 },
  349. .vco = { .min = 4000000, .max = 6000000 },
  350. .n = { .min = 1, .max = 7 },
  351. .m = { .min = 22, .max = 450 }, /* guess */
  352. .m1 = { .min = 2, .max = 3 },
  353. .m2 = { .min = 11, .max = 156 },
  354. .p = { .min = 10, .max = 30 },
  355. .p1 = { .min = 1, .max = 3 },
  356. .p2 = { .dot_limit = 270000,
  357. .p2_slow = 2, .p2_fast = 20 },
  358. .find_pll = intel_vlv_find_best_pll,
  359. };
  360. static const intel_limit_t intel_limits_vlv_hdmi = {
  361. .dot = { .min = 25000, .max = 270000 },
  362. .vco = { .min = 4000000, .max = 6000000 },
  363. .n = { .min = 1, .max = 7 },
  364. .m = { .min = 60, .max = 300 }, /* guess */
  365. .m1 = { .min = 2, .max = 3 },
  366. .m2 = { .min = 11, .max = 156 },
  367. .p = { .min = 10, .max = 30 },
  368. .p1 = { .min = 2, .max = 3 },
  369. .p2 = { .dot_limit = 270000,
  370. .p2_slow = 2, .p2_fast = 20 },
  371. .find_pll = intel_vlv_find_best_pll,
  372. };
  373. static const intel_limit_t intel_limits_vlv_dp = {
  374. .dot = { .min = 25000, .max = 270000 },
  375. .vco = { .min = 4000000, .max = 6000000 },
  376. .n = { .min = 1, .max = 7 },
  377. .m = { .min = 22, .max = 450 },
  378. .m1 = { .min = 2, .max = 3 },
  379. .m2 = { .min = 11, .max = 156 },
  380. .p = { .min = 10, .max = 30 },
  381. .p1 = { .min = 1, .max = 3 },
  382. .p2 = { .dot_limit = 270000,
  383. .p2_slow = 2, .p2_fast = 20 },
  384. .find_pll = intel_vlv_find_best_pll,
  385. };
  386. u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
  387. {
  388. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  389. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  390. DRM_ERROR("DPIO idle wait timed out\n");
  391. return 0;
  392. }
  393. I915_WRITE(DPIO_REG, reg);
  394. I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
  395. DPIO_BYTE);
  396. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  397. DRM_ERROR("DPIO read wait timed out\n");
  398. return 0;
  399. }
  400. return I915_READ(DPIO_DATA);
  401. }
  402. void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
  403. {
  404. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  405. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  406. DRM_ERROR("DPIO idle wait timed out\n");
  407. return;
  408. }
  409. I915_WRITE(DPIO_DATA, val);
  410. I915_WRITE(DPIO_REG, reg);
  411. I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
  412. DPIO_BYTE);
  413. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
  414. DRM_ERROR("DPIO write wait timed out\n");
  415. }
  416. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  417. int refclk)
  418. {
  419. struct drm_device *dev = crtc->dev;
  420. const intel_limit_t *limit;
  421. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  422. if (intel_is_dual_link_lvds(dev)) {
  423. if (refclk == 100000)
  424. limit = &intel_limits_ironlake_dual_lvds_100m;
  425. else
  426. limit = &intel_limits_ironlake_dual_lvds;
  427. } else {
  428. if (refclk == 100000)
  429. limit = &intel_limits_ironlake_single_lvds_100m;
  430. else
  431. limit = &intel_limits_ironlake_single_lvds;
  432. }
  433. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  434. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  435. limit = &intel_limits_ironlake_display_port;
  436. else
  437. limit = &intel_limits_ironlake_dac;
  438. return limit;
  439. }
  440. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  441. {
  442. struct drm_device *dev = crtc->dev;
  443. const intel_limit_t *limit;
  444. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  445. if (intel_is_dual_link_lvds(dev))
  446. limit = &intel_limits_g4x_dual_channel_lvds;
  447. else
  448. limit = &intel_limits_g4x_single_channel_lvds;
  449. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  450. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  451. limit = &intel_limits_g4x_hdmi;
  452. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  453. limit = &intel_limits_g4x_sdvo;
  454. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  455. limit = &intel_limits_g4x_display_port;
  456. } else /* The option is for other outputs */
  457. limit = &intel_limits_i9xx_sdvo;
  458. return limit;
  459. }
  460. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  461. {
  462. struct drm_device *dev = crtc->dev;
  463. const intel_limit_t *limit;
  464. if (HAS_PCH_SPLIT(dev))
  465. limit = intel_ironlake_limit(crtc, refclk);
  466. else if (IS_G4X(dev)) {
  467. limit = intel_g4x_limit(crtc);
  468. } else if (IS_PINEVIEW(dev)) {
  469. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  470. limit = &intel_limits_pineview_lvds;
  471. else
  472. limit = &intel_limits_pineview_sdvo;
  473. } else if (IS_VALLEYVIEW(dev)) {
  474. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  475. limit = &intel_limits_vlv_dac;
  476. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  477. limit = &intel_limits_vlv_hdmi;
  478. else
  479. limit = &intel_limits_vlv_dp;
  480. } else if (!IS_GEN2(dev)) {
  481. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  482. limit = &intel_limits_i9xx_lvds;
  483. else
  484. limit = &intel_limits_i9xx_sdvo;
  485. } else {
  486. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  487. limit = &intel_limits_i8xx_lvds;
  488. else
  489. limit = &intel_limits_i8xx_dvo;
  490. }
  491. return limit;
  492. }
  493. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  494. static void pineview_clock(int refclk, intel_clock_t *clock)
  495. {
  496. clock->m = clock->m2 + 2;
  497. clock->p = clock->p1 * clock->p2;
  498. clock->vco = refclk * clock->m / clock->n;
  499. clock->dot = clock->vco / clock->p;
  500. }
  501. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  502. {
  503. if (IS_PINEVIEW(dev)) {
  504. pineview_clock(refclk, clock);
  505. return;
  506. }
  507. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  508. clock->p = clock->p1 * clock->p2;
  509. clock->vco = refclk * clock->m / (clock->n + 2);
  510. clock->dot = clock->vco / clock->p;
  511. }
  512. /**
  513. * Returns whether any output on the specified pipe is of the specified type
  514. */
  515. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  516. {
  517. struct drm_device *dev = crtc->dev;
  518. struct intel_encoder *encoder;
  519. for_each_encoder_on_crtc(dev, crtc, encoder)
  520. if (encoder->type == type)
  521. return true;
  522. return false;
  523. }
  524. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  525. /**
  526. * Returns whether the given set of divisors are valid for a given refclk with
  527. * the given connectors.
  528. */
  529. static bool intel_PLL_is_valid(struct drm_device *dev,
  530. const intel_limit_t *limit,
  531. const intel_clock_t *clock)
  532. {
  533. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  534. INTELPllInvalid("p1 out of range\n");
  535. if (clock->p < limit->p.min || limit->p.max < clock->p)
  536. INTELPllInvalid("p out of range\n");
  537. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  538. INTELPllInvalid("m2 out of range\n");
  539. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  540. INTELPllInvalid("m1 out of range\n");
  541. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  542. INTELPllInvalid("m1 <= m2\n");
  543. if (clock->m < limit->m.min || limit->m.max < clock->m)
  544. INTELPllInvalid("m out of range\n");
  545. if (clock->n < limit->n.min || limit->n.max < clock->n)
  546. INTELPllInvalid("n out of range\n");
  547. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  548. INTELPllInvalid("vco out of range\n");
  549. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  550. * connector, etc., rather than just a single range.
  551. */
  552. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  553. INTELPllInvalid("dot out of range\n");
  554. return true;
  555. }
  556. static bool
  557. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  558. int target, int refclk, intel_clock_t *match_clock,
  559. intel_clock_t *best_clock)
  560. {
  561. struct drm_device *dev = crtc->dev;
  562. intel_clock_t clock;
  563. int err = target;
  564. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  565. /*
  566. * For LVDS just rely on its current settings for dual-channel.
  567. * We haven't figured out how to reliably set up different
  568. * single/dual channel state, if we even can.
  569. */
  570. if (intel_is_dual_link_lvds(dev))
  571. clock.p2 = limit->p2.p2_fast;
  572. else
  573. clock.p2 = limit->p2.p2_slow;
  574. } else {
  575. if (target < limit->p2.dot_limit)
  576. clock.p2 = limit->p2.p2_slow;
  577. else
  578. clock.p2 = limit->p2.p2_fast;
  579. }
  580. memset(best_clock, 0, sizeof(*best_clock));
  581. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  582. clock.m1++) {
  583. for (clock.m2 = limit->m2.min;
  584. clock.m2 <= limit->m2.max; clock.m2++) {
  585. /* m1 is always 0 in Pineview */
  586. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  587. break;
  588. for (clock.n = limit->n.min;
  589. clock.n <= limit->n.max; clock.n++) {
  590. for (clock.p1 = limit->p1.min;
  591. clock.p1 <= limit->p1.max; clock.p1++) {
  592. int this_err;
  593. intel_clock(dev, refclk, &clock);
  594. if (!intel_PLL_is_valid(dev, limit,
  595. &clock))
  596. continue;
  597. if (match_clock &&
  598. clock.p != match_clock->p)
  599. continue;
  600. this_err = abs(clock.dot - target);
  601. if (this_err < err) {
  602. *best_clock = clock;
  603. err = this_err;
  604. }
  605. }
  606. }
  607. }
  608. }
  609. return (err != target);
  610. }
  611. static bool
  612. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  613. int target, int refclk, intel_clock_t *match_clock,
  614. intel_clock_t *best_clock)
  615. {
  616. struct drm_device *dev = crtc->dev;
  617. intel_clock_t clock;
  618. int max_n;
  619. bool found;
  620. /* approximately equals target * 0.00585 */
  621. int err_most = (target >> 8) + (target >> 9);
  622. found = false;
  623. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  624. int lvds_reg;
  625. if (HAS_PCH_SPLIT(dev))
  626. lvds_reg = PCH_LVDS;
  627. else
  628. lvds_reg = LVDS;
  629. if (intel_is_dual_link_lvds(dev))
  630. clock.p2 = limit->p2.p2_fast;
  631. else
  632. clock.p2 = limit->p2.p2_slow;
  633. } else {
  634. if (target < limit->p2.dot_limit)
  635. clock.p2 = limit->p2.p2_slow;
  636. else
  637. clock.p2 = limit->p2.p2_fast;
  638. }
  639. memset(best_clock, 0, sizeof(*best_clock));
  640. max_n = limit->n.max;
  641. /* based on hardware requirement, prefer smaller n to precision */
  642. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  643. /* based on hardware requirement, prefere larger m1,m2 */
  644. for (clock.m1 = limit->m1.max;
  645. clock.m1 >= limit->m1.min; clock.m1--) {
  646. for (clock.m2 = limit->m2.max;
  647. clock.m2 >= limit->m2.min; clock.m2--) {
  648. for (clock.p1 = limit->p1.max;
  649. clock.p1 >= limit->p1.min; clock.p1--) {
  650. int this_err;
  651. intel_clock(dev, refclk, &clock);
  652. if (!intel_PLL_is_valid(dev, limit,
  653. &clock))
  654. continue;
  655. if (match_clock &&
  656. clock.p != match_clock->p)
  657. continue;
  658. this_err = abs(clock.dot - target);
  659. if (this_err < err_most) {
  660. *best_clock = clock;
  661. err_most = this_err;
  662. max_n = clock.n;
  663. found = true;
  664. }
  665. }
  666. }
  667. }
  668. }
  669. return found;
  670. }
  671. static bool
  672. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  673. int target, int refclk, intel_clock_t *match_clock,
  674. intel_clock_t *best_clock)
  675. {
  676. struct drm_device *dev = crtc->dev;
  677. intel_clock_t clock;
  678. if (target < 200000) {
  679. clock.n = 1;
  680. clock.p1 = 2;
  681. clock.p2 = 10;
  682. clock.m1 = 12;
  683. clock.m2 = 9;
  684. } else {
  685. clock.n = 2;
  686. clock.p1 = 1;
  687. clock.p2 = 10;
  688. clock.m1 = 14;
  689. clock.m2 = 8;
  690. }
  691. intel_clock(dev, refclk, &clock);
  692. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  693. return true;
  694. }
  695. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  696. static bool
  697. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  698. int target, int refclk, intel_clock_t *match_clock,
  699. intel_clock_t *best_clock)
  700. {
  701. intel_clock_t clock;
  702. if (target < 200000) {
  703. clock.p1 = 2;
  704. clock.p2 = 10;
  705. clock.n = 2;
  706. clock.m1 = 23;
  707. clock.m2 = 8;
  708. } else {
  709. clock.p1 = 1;
  710. clock.p2 = 10;
  711. clock.n = 1;
  712. clock.m1 = 14;
  713. clock.m2 = 2;
  714. }
  715. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  716. clock.p = (clock.p1 * clock.p2);
  717. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  718. clock.vco = 0;
  719. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  720. return true;
  721. }
  722. static bool
  723. intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  724. int target, int refclk, intel_clock_t *match_clock,
  725. intel_clock_t *best_clock)
  726. {
  727. u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  728. u32 m, n, fastclk;
  729. u32 updrate, minupdate, fracbits, p;
  730. unsigned long bestppm, ppm, absppm;
  731. int dotclk, flag;
  732. flag = 0;
  733. dotclk = target * 1000;
  734. bestppm = 1000000;
  735. ppm = absppm = 0;
  736. fastclk = dotclk / (2*100);
  737. updrate = 0;
  738. minupdate = 19200;
  739. fracbits = 1;
  740. n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  741. bestm1 = bestm2 = bestp1 = bestp2 = 0;
  742. /* based on hardware requirement, prefer smaller n to precision */
  743. for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  744. updrate = refclk / n;
  745. for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  746. for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  747. if (p2 > 10)
  748. p2 = p2 - 1;
  749. p = p1 * p2;
  750. /* based on hardware requirement, prefer bigger m1,m2 values */
  751. for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  752. m2 = (((2*(fastclk * p * n / m1 )) +
  753. refclk) / (2*refclk));
  754. m = m1 * m2;
  755. vco = updrate * m;
  756. if (vco >= limit->vco.min && vco < limit->vco.max) {
  757. ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  758. absppm = (ppm > 0) ? ppm : (-ppm);
  759. if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  760. bestppm = 0;
  761. flag = 1;
  762. }
  763. if (absppm < bestppm - 10) {
  764. bestppm = absppm;
  765. flag = 1;
  766. }
  767. if (flag) {
  768. bestn = n;
  769. bestm1 = m1;
  770. bestm2 = m2;
  771. bestp1 = p1;
  772. bestp2 = p2;
  773. flag = 0;
  774. }
  775. }
  776. }
  777. }
  778. }
  779. }
  780. best_clock->n = bestn;
  781. best_clock->m1 = bestm1;
  782. best_clock->m2 = bestm2;
  783. best_clock->p1 = bestp1;
  784. best_clock->p2 = bestp2;
  785. return true;
  786. }
  787. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  788. enum pipe pipe)
  789. {
  790. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  791. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  792. return intel_crtc->config.cpu_transcoder;
  793. }
  794. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  795. {
  796. struct drm_i915_private *dev_priv = dev->dev_private;
  797. u32 frame, frame_reg = PIPEFRAME(pipe);
  798. frame = I915_READ(frame_reg);
  799. if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  800. DRM_DEBUG_KMS("vblank wait timed out\n");
  801. }
  802. /**
  803. * intel_wait_for_vblank - wait for vblank on a given pipe
  804. * @dev: drm device
  805. * @pipe: pipe to wait for
  806. *
  807. * Wait for vblank to occur on a given pipe. Needed for various bits of
  808. * mode setting code.
  809. */
  810. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  811. {
  812. struct drm_i915_private *dev_priv = dev->dev_private;
  813. int pipestat_reg = PIPESTAT(pipe);
  814. if (INTEL_INFO(dev)->gen >= 5) {
  815. ironlake_wait_for_vblank(dev, pipe);
  816. return;
  817. }
  818. /* Clear existing vblank status. Note this will clear any other
  819. * sticky status fields as well.
  820. *
  821. * This races with i915_driver_irq_handler() with the result
  822. * that either function could miss a vblank event. Here it is not
  823. * fatal, as we will either wait upon the next vblank interrupt or
  824. * timeout. Generally speaking intel_wait_for_vblank() is only
  825. * called during modeset at which time the GPU should be idle and
  826. * should *not* be performing page flips and thus not waiting on
  827. * vblanks...
  828. * Currently, the result of us stealing a vblank from the irq
  829. * handler is that a single frame will be skipped during swapbuffers.
  830. */
  831. I915_WRITE(pipestat_reg,
  832. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  833. /* Wait for vblank interrupt bit to set */
  834. if (wait_for(I915_READ(pipestat_reg) &
  835. PIPE_VBLANK_INTERRUPT_STATUS,
  836. 50))
  837. DRM_DEBUG_KMS("vblank wait timed out\n");
  838. }
  839. /*
  840. * intel_wait_for_pipe_off - wait for pipe to turn off
  841. * @dev: drm device
  842. * @pipe: pipe to wait for
  843. *
  844. * After disabling a pipe, we can't wait for vblank in the usual way,
  845. * spinning on the vblank interrupt status bit, since we won't actually
  846. * see an interrupt when the pipe is disabled.
  847. *
  848. * On Gen4 and above:
  849. * wait for the pipe register state bit to turn off
  850. *
  851. * Otherwise:
  852. * wait for the display line value to settle (it usually
  853. * ends up stopping at the start of the next frame).
  854. *
  855. */
  856. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  857. {
  858. struct drm_i915_private *dev_priv = dev->dev_private;
  859. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  860. pipe);
  861. if (INTEL_INFO(dev)->gen >= 4) {
  862. int reg = PIPECONF(cpu_transcoder);
  863. /* Wait for the Pipe State to go off */
  864. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  865. 100))
  866. WARN(1, "pipe_off wait timed out\n");
  867. } else {
  868. u32 last_line, line_mask;
  869. int reg = PIPEDSL(pipe);
  870. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  871. if (IS_GEN2(dev))
  872. line_mask = DSL_LINEMASK_GEN2;
  873. else
  874. line_mask = DSL_LINEMASK_GEN3;
  875. /* Wait for the display line to settle */
  876. do {
  877. last_line = I915_READ(reg) & line_mask;
  878. mdelay(5);
  879. } while (((I915_READ(reg) & line_mask) != last_line) &&
  880. time_after(timeout, jiffies));
  881. if (time_after(jiffies, timeout))
  882. WARN(1, "pipe_off wait timed out\n");
  883. }
  884. }
  885. /*
  886. * ibx_digital_port_connected - is the specified port connected?
  887. * @dev_priv: i915 private structure
  888. * @port: the port to test
  889. *
  890. * Returns true if @port is connected, false otherwise.
  891. */
  892. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  893. struct intel_digital_port *port)
  894. {
  895. u32 bit;
  896. if (HAS_PCH_IBX(dev_priv->dev)) {
  897. switch(port->port) {
  898. case PORT_B:
  899. bit = SDE_PORTB_HOTPLUG;
  900. break;
  901. case PORT_C:
  902. bit = SDE_PORTC_HOTPLUG;
  903. break;
  904. case PORT_D:
  905. bit = SDE_PORTD_HOTPLUG;
  906. break;
  907. default:
  908. return true;
  909. }
  910. } else {
  911. switch(port->port) {
  912. case PORT_B:
  913. bit = SDE_PORTB_HOTPLUG_CPT;
  914. break;
  915. case PORT_C:
  916. bit = SDE_PORTC_HOTPLUG_CPT;
  917. break;
  918. case PORT_D:
  919. bit = SDE_PORTD_HOTPLUG_CPT;
  920. break;
  921. default:
  922. return true;
  923. }
  924. }
  925. return I915_READ(SDEISR) & bit;
  926. }
  927. static const char *state_string(bool enabled)
  928. {
  929. return enabled ? "on" : "off";
  930. }
  931. /* Only for pre-ILK configs */
  932. static void assert_pll(struct drm_i915_private *dev_priv,
  933. enum pipe pipe, bool state)
  934. {
  935. int reg;
  936. u32 val;
  937. bool cur_state;
  938. reg = DPLL(pipe);
  939. val = I915_READ(reg);
  940. cur_state = !!(val & DPLL_VCO_ENABLE);
  941. WARN(cur_state != state,
  942. "PLL state assertion failure (expected %s, current %s)\n",
  943. state_string(state), state_string(cur_state));
  944. }
  945. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  946. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  947. /* For ILK+ */
  948. static void assert_pch_pll(struct drm_i915_private *dev_priv,
  949. struct intel_pch_pll *pll,
  950. struct intel_crtc *crtc,
  951. bool state)
  952. {
  953. u32 val;
  954. bool cur_state;
  955. if (HAS_PCH_LPT(dev_priv->dev)) {
  956. DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  957. return;
  958. }
  959. if (WARN (!pll,
  960. "asserting PCH PLL %s with no PLL\n", state_string(state)))
  961. return;
  962. val = I915_READ(pll->pll_reg);
  963. cur_state = !!(val & DPLL_VCO_ENABLE);
  964. WARN(cur_state != state,
  965. "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
  966. pll->pll_reg, state_string(state), state_string(cur_state), val);
  967. /* Make sure the selected PLL is correctly attached to the transcoder */
  968. if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
  969. u32 pch_dpll;
  970. pch_dpll = I915_READ(PCH_DPLL_SEL);
  971. cur_state = pll->pll_reg == _PCH_DPLL_B;
  972. if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
  973. "PLL[%d] not attached to this transcoder %c: %08x\n",
  974. cur_state, pipe_name(crtc->pipe), pch_dpll)) {
  975. cur_state = !!(val >> (4*crtc->pipe + 3));
  976. WARN(cur_state != state,
  977. "PLL[%d] not %s on this transcoder %c: %08x\n",
  978. pll->pll_reg == _PCH_DPLL_B,
  979. state_string(state),
  980. pipe_name(crtc->pipe),
  981. val);
  982. }
  983. }
  984. }
  985. #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
  986. #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
  987. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  988. enum pipe pipe, bool state)
  989. {
  990. int reg;
  991. u32 val;
  992. bool cur_state;
  993. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  994. pipe);
  995. if (HAS_DDI(dev_priv->dev)) {
  996. /* DDI does not have a specific FDI_TX register */
  997. reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  998. val = I915_READ(reg);
  999. cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  1000. } else {
  1001. reg = FDI_TX_CTL(pipe);
  1002. val = I915_READ(reg);
  1003. cur_state = !!(val & FDI_TX_ENABLE);
  1004. }
  1005. WARN(cur_state != state,
  1006. "FDI TX state assertion failure (expected %s, current %s)\n",
  1007. state_string(state), state_string(cur_state));
  1008. }
  1009. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  1010. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  1011. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  1012. enum pipe pipe, bool state)
  1013. {
  1014. int reg;
  1015. u32 val;
  1016. bool cur_state;
  1017. reg = FDI_RX_CTL(pipe);
  1018. val = I915_READ(reg);
  1019. cur_state = !!(val & FDI_RX_ENABLE);
  1020. WARN(cur_state != state,
  1021. "FDI RX state assertion failure (expected %s, current %s)\n",
  1022. state_string(state), state_string(cur_state));
  1023. }
  1024. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  1025. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  1026. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  1027. enum pipe pipe)
  1028. {
  1029. int reg;
  1030. u32 val;
  1031. /* ILK FDI PLL is always enabled */
  1032. if (dev_priv->info->gen == 5)
  1033. return;
  1034. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  1035. if (HAS_DDI(dev_priv->dev))
  1036. return;
  1037. reg = FDI_TX_CTL(pipe);
  1038. val = I915_READ(reg);
  1039. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  1040. }
  1041. static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
  1042. enum pipe pipe)
  1043. {
  1044. int reg;
  1045. u32 val;
  1046. reg = FDI_RX_CTL(pipe);
  1047. val = I915_READ(reg);
  1048. WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
  1049. }
  1050. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1051. enum pipe pipe)
  1052. {
  1053. int pp_reg, lvds_reg;
  1054. u32 val;
  1055. enum pipe panel_pipe = PIPE_A;
  1056. bool locked = true;
  1057. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1058. pp_reg = PCH_PP_CONTROL;
  1059. lvds_reg = PCH_LVDS;
  1060. } else {
  1061. pp_reg = PP_CONTROL;
  1062. lvds_reg = LVDS;
  1063. }
  1064. val = I915_READ(pp_reg);
  1065. if (!(val & PANEL_POWER_ON) ||
  1066. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  1067. locked = false;
  1068. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  1069. panel_pipe = PIPE_B;
  1070. WARN(panel_pipe == pipe && locked,
  1071. "panel assertion failure, pipe %c regs locked\n",
  1072. pipe_name(pipe));
  1073. }
  1074. void assert_pipe(struct drm_i915_private *dev_priv,
  1075. enum pipe pipe, bool state)
  1076. {
  1077. int reg;
  1078. u32 val;
  1079. bool cur_state;
  1080. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1081. pipe);
  1082. /* if we need the pipe A quirk it must be always on */
  1083. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  1084. state = true;
  1085. if (!intel_using_power_well(dev_priv->dev) &&
  1086. cpu_transcoder != TRANSCODER_EDP) {
  1087. cur_state = false;
  1088. } else {
  1089. reg = PIPECONF(cpu_transcoder);
  1090. val = I915_READ(reg);
  1091. cur_state = !!(val & PIPECONF_ENABLE);
  1092. }
  1093. WARN(cur_state != state,
  1094. "pipe %c assertion failure (expected %s, current %s)\n",
  1095. pipe_name(pipe), state_string(state), state_string(cur_state));
  1096. }
  1097. static void assert_plane(struct drm_i915_private *dev_priv,
  1098. enum plane plane, bool state)
  1099. {
  1100. int reg;
  1101. u32 val;
  1102. bool cur_state;
  1103. reg = DSPCNTR(plane);
  1104. val = I915_READ(reg);
  1105. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1106. WARN(cur_state != state,
  1107. "plane %c assertion failure (expected %s, current %s)\n",
  1108. plane_name(plane), state_string(state), state_string(cur_state));
  1109. }
  1110. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1111. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1112. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1113. enum pipe pipe)
  1114. {
  1115. int reg, i;
  1116. u32 val;
  1117. int cur_pipe;
  1118. /* Planes are fixed to pipes on ILK+ */
  1119. if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
  1120. reg = DSPCNTR(pipe);
  1121. val = I915_READ(reg);
  1122. WARN((val & DISPLAY_PLANE_ENABLE),
  1123. "plane %c assertion failure, should be disabled but not\n",
  1124. plane_name(pipe));
  1125. return;
  1126. }
  1127. /* Need to check both planes against the pipe */
  1128. for (i = 0; i < 2; i++) {
  1129. reg = DSPCNTR(i);
  1130. val = I915_READ(reg);
  1131. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1132. DISPPLANE_SEL_PIPE_SHIFT;
  1133. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1134. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1135. plane_name(i), pipe_name(pipe));
  1136. }
  1137. }
  1138. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1139. enum pipe pipe)
  1140. {
  1141. int reg, i;
  1142. u32 val;
  1143. if (!IS_VALLEYVIEW(dev_priv->dev))
  1144. return;
  1145. /* Need to check both planes against the pipe */
  1146. for (i = 0; i < dev_priv->num_plane; i++) {
  1147. reg = SPCNTR(pipe, i);
  1148. val = I915_READ(reg);
  1149. WARN((val & SP_ENABLE),
  1150. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1151. sprite_name(pipe, i), pipe_name(pipe));
  1152. }
  1153. }
  1154. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1155. {
  1156. u32 val;
  1157. bool enabled;
  1158. if (HAS_PCH_LPT(dev_priv->dev)) {
  1159. DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1160. return;
  1161. }
  1162. val = I915_READ(PCH_DREF_CONTROL);
  1163. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1164. DREF_SUPERSPREAD_SOURCE_MASK));
  1165. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1166. }
  1167. static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
  1168. enum pipe pipe)
  1169. {
  1170. int reg;
  1171. u32 val;
  1172. bool enabled;
  1173. reg = TRANSCONF(pipe);
  1174. val = I915_READ(reg);
  1175. enabled = !!(val & TRANS_ENABLE);
  1176. WARN(enabled,
  1177. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1178. pipe_name(pipe));
  1179. }
  1180. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1181. enum pipe pipe, u32 port_sel, u32 val)
  1182. {
  1183. if ((val & DP_PORT_EN) == 0)
  1184. return false;
  1185. if (HAS_PCH_CPT(dev_priv->dev)) {
  1186. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1187. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1188. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1189. return false;
  1190. } else {
  1191. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1192. return false;
  1193. }
  1194. return true;
  1195. }
  1196. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1197. enum pipe pipe, u32 val)
  1198. {
  1199. if ((val & SDVO_ENABLE) == 0)
  1200. return false;
  1201. if (HAS_PCH_CPT(dev_priv->dev)) {
  1202. if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1203. return false;
  1204. } else {
  1205. if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1206. return false;
  1207. }
  1208. return true;
  1209. }
  1210. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1211. enum pipe pipe, u32 val)
  1212. {
  1213. if ((val & LVDS_PORT_EN) == 0)
  1214. return false;
  1215. if (HAS_PCH_CPT(dev_priv->dev)) {
  1216. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1217. return false;
  1218. } else {
  1219. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1220. return false;
  1221. }
  1222. return true;
  1223. }
  1224. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1225. enum pipe pipe, u32 val)
  1226. {
  1227. if ((val & ADPA_DAC_ENABLE) == 0)
  1228. return false;
  1229. if (HAS_PCH_CPT(dev_priv->dev)) {
  1230. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1231. return false;
  1232. } else {
  1233. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1234. return false;
  1235. }
  1236. return true;
  1237. }
  1238. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1239. enum pipe pipe, int reg, u32 port_sel)
  1240. {
  1241. u32 val = I915_READ(reg);
  1242. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1243. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1244. reg, pipe_name(pipe));
  1245. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1246. && (val & DP_PIPEB_SELECT),
  1247. "IBX PCH dp port still using transcoder B\n");
  1248. }
  1249. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1250. enum pipe pipe, int reg)
  1251. {
  1252. u32 val = I915_READ(reg);
  1253. WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1254. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1255. reg, pipe_name(pipe));
  1256. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
  1257. && (val & SDVO_PIPE_B_SELECT),
  1258. "IBX PCH hdmi port still using transcoder B\n");
  1259. }
  1260. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1261. enum pipe pipe)
  1262. {
  1263. int reg;
  1264. u32 val;
  1265. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1266. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1267. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1268. reg = PCH_ADPA;
  1269. val = I915_READ(reg);
  1270. WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1271. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1272. pipe_name(pipe));
  1273. reg = PCH_LVDS;
  1274. val = I915_READ(reg);
  1275. WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1276. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1277. pipe_name(pipe));
  1278. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1279. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1280. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1281. }
  1282. /**
  1283. * intel_enable_pll - enable a PLL
  1284. * @dev_priv: i915 private structure
  1285. * @pipe: pipe PLL to enable
  1286. *
  1287. * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
  1288. * make sure the PLL reg is writable first though, since the panel write
  1289. * protect mechanism may be enabled.
  1290. *
  1291. * Note! This is for pre-ILK only.
  1292. *
  1293. * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
  1294. */
  1295. static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1296. {
  1297. int reg;
  1298. u32 val;
  1299. assert_pipe_disabled(dev_priv, pipe);
  1300. /* No really, not for ILK+ */
  1301. BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
  1302. /* PLL is protected by panel, make sure we can write it */
  1303. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1304. assert_panel_unlocked(dev_priv, pipe);
  1305. reg = DPLL(pipe);
  1306. val = I915_READ(reg);
  1307. val |= DPLL_VCO_ENABLE;
  1308. /* We do this three times for luck */
  1309. I915_WRITE(reg, val);
  1310. POSTING_READ(reg);
  1311. udelay(150); /* wait for warmup */
  1312. I915_WRITE(reg, val);
  1313. POSTING_READ(reg);
  1314. udelay(150); /* wait for warmup */
  1315. I915_WRITE(reg, val);
  1316. POSTING_READ(reg);
  1317. udelay(150); /* wait for warmup */
  1318. }
  1319. /**
  1320. * intel_disable_pll - disable a PLL
  1321. * @dev_priv: i915 private structure
  1322. * @pipe: pipe PLL to disable
  1323. *
  1324. * Disable the PLL for @pipe, making sure the pipe is off first.
  1325. *
  1326. * Note! This is for pre-ILK only.
  1327. */
  1328. static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1329. {
  1330. int reg;
  1331. u32 val;
  1332. /* Don't disable pipe A or pipe A PLLs if needed */
  1333. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1334. return;
  1335. /* Make sure the pipe isn't still relying on us */
  1336. assert_pipe_disabled(dev_priv, pipe);
  1337. reg = DPLL(pipe);
  1338. val = I915_READ(reg);
  1339. val &= ~DPLL_VCO_ENABLE;
  1340. I915_WRITE(reg, val);
  1341. POSTING_READ(reg);
  1342. }
  1343. /* SBI access */
  1344. static void
  1345. intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
  1346. enum intel_sbi_destination destination)
  1347. {
  1348. u32 tmp;
  1349. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  1350. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  1351. 100)) {
  1352. DRM_ERROR("timeout waiting for SBI to become ready\n");
  1353. return;
  1354. }
  1355. I915_WRITE(SBI_ADDR, (reg << 16));
  1356. I915_WRITE(SBI_DATA, value);
  1357. if (destination == SBI_ICLK)
  1358. tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
  1359. else
  1360. tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
  1361. I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
  1362. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  1363. 100)) {
  1364. DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
  1365. return;
  1366. }
  1367. }
  1368. static u32
  1369. intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
  1370. enum intel_sbi_destination destination)
  1371. {
  1372. u32 value = 0;
  1373. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  1374. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  1375. 100)) {
  1376. DRM_ERROR("timeout waiting for SBI to become ready\n");
  1377. return 0;
  1378. }
  1379. I915_WRITE(SBI_ADDR, (reg << 16));
  1380. if (destination == SBI_ICLK)
  1381. value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
  1382. else
  1383. value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
  1384. I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
  1385. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  1386. 100)) {
  1387. DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
  1388. return 0;
  1389. }
  1390. return I915_READ(SBI_DATA);
  1391. }
  1392. void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  1393. {
  1394. u32 port_mask;
  1395. if (!port)
  1396. port_mask = DPLL_PORTB_READY_MASK;
  1397. else
  1398. port_mask = DPLL_PORTC_READY_MASK;
  1399. if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
  1400. WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
  1401. 'B' + port, I915_READ(DPLL(0)));
  1402. }
  1403. /**
  1404. * ironlake_enable_pch_pll - enable PCH PLL
  1405. * @dev_priv: i915 private structure
  1406. * @pipe: pipe PLL to enable
  1407. *
  1408. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1409. * drives the transcoder clock.
  1410. */
  1411. static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
  1412. {
  1413. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  1414. struct intel_pch_pll *pll;
  1415. int reg;
  1416. u32 val;
  1417. /* PCH PLLs only available on ILK, SNB and IVB */
  1418. BUG_ON(dev_priv->info->gen < 5);
  1419. pll = intel_crtc->pch_pll;
  1420. if (pll == NULL)
  1421. return;
  1422. if (WARN_ON(pll->refcount == 0))
  1423. return;
  1424. DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
  1425. pll->pll_reg, pll->active, pll->on,
  1426. intel_crtc->base.base.id);
  1427. /* PCH refclock must be enabled first */
  1428. assert_pch_refclk_enabled(dev_priv);
  1429. if (pll->active++ && pll->on) {
  1430. assert_pch_pll_enabled(dev_priv, pll, NULL);
  1431. return;
  1432. }
  1433. DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
  1434. reg = pll->pll_reg;
  1435. val = I915_READ(reg);
  1436. val |= DPLL_VCO_ENABLE;
  1437. I915_WRITE(reg, val);
  1438. POSTING_READ(reg);
  1439. udelay(200);
  1440. pll->on = true;
  1441. }
  1442. static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
  1443. {
  1444. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  1445. struct intel_pch_pll *pll = intel_crtc->pch_pll;
  1446. int reg;
  1447. u32 val;
  1448. /* PCH only available on ILK+ */
  1449. BUG_ON(dev_priv->info->gen < 5);
  1450. if (pll == NULL)
  1451. return;
  1452. if (WARN_ON(pll->refcount == 0))
  1453. return;
  1454. DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
  1455. pll->pll_reg, pll->active, pll->on,
  1456. intel_crtc->base.base.id);
  1457. if (WARN_ON(pll->active == 0)) {
  1458. assert_pch_pll_disabled(dev_priv, pll, NULL);
  1459. return;
  1460. }
  1461. if (--pll->active) {
  1462. assert_pch_pll_enabled(dev_priv, pll, NULL);
  1463. return;
  1464. }
  1465. DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
  1466. /* Make sure transcoder isn't still depending on us */
  1467. assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
  1468. reg = pll->pll_reg;
  1469. val = I915_READ(reg);
  1470. val &= ~DPLL_VCO_ENABLE;
  1471. I915_WRITE(reg, val);
  1472. POSTING_READ(reg);
  1473. udelay(200);
  1474. pll->on = false;
  1475. }
  1476. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1477. enum pipe pipe)
  1478. {
  1479. struct drm_device *dev = dev_priv->dev;
  1480. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1481. uint32_t reg, val, pipeconf_val;
  1482. /* PCH only available on ILK+ */
  1483. BUG_ON(dev_priv->info->gen < 5);
  1484. /* Make sure PCH DPLL is enabled */
  1485. assert_pch_pll_enabled(dev_priv,
  1486. to_intel_crtc(crtc)->pch_pll,
  1487. to_intel_crtc(crtc));
  1488. /* FDI must be feeding us bits for PCH ports */
  1489. assert_fdi_tx_enabled(dev_priv, pipe);
  1490. assert_fdi_rx_enabled(dev_priv, pipe);
  1491. if (HAS_PCH_CPT(dev)) {
  1492. /* Workaround: Set the timing override bit before enabling the
  1493. * pch transcoder. */
  1494. reg = TRANS_CHICKEN2(pipe);
  1495. val = I915_READ(reg);
  1496. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1497. I915_WRITE(reg, val);
  1498. }
  1499. reg = TRANSCONF(pipe);
  1500. val = I915_READ(reg);
  1501. pipeconf_val = I915_READ(PIPECONF(pipe));
  1502. if (HAS_PCH_IBX(dev_priv->dev)) {
  1503. /*
  1504. * make the BPC in transcoder be consistent with
  1505. * that in pipeconf reg.
  1506. */
  1507. val &= ~PIPECONF_BPC_MASK;
  1508. val |= pipeconf_val & PIPECONF_BPC_MASK;
  1509. }
  1510. val &= ~TRANS_INTERLACE_MASK;
  1511. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1512. if (HAS_PCH_IBX(dev_priv->dev) &&
  1513. intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1514. val |= TRANS_LEGACY_INTERLACED_ILK;
  1515. else
  1516. val |= TRANS_INTERLACED;
  1517. else
  1518. val |= TRANS_PROGRESSIVE;
  1519. I915_WRITE(reg, val | TRANS_ENABLE);
  1520. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1521. DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  1522. }
  1523. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1524. enum transcoder cpu_transcoder)
  1525. {
  1526. u32 val, pipeconf_val;
  1527. /* PCH only available on ILK+ */
  1528. BUG_ON(dev_priv->info->gen < 5);
  1529. /* FDI must be feeding us bits for PCH ports */
  1530. assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1531. assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1532. /* Workaround: set timing override bit. */
  1533. val = I915_READ(_TRANSA_CHICKEN2);
  1534. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1535. I915_WRITE(_TRANSA_CHICKEN2, val);
  1536. val = TRANS_ENABLE;
  1537. pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1538. if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1539. PIPECONF_INTERLACED_ILK)
  1540. val |= TRANS_INTERLACED;
  1541. else
  1542. val |= TRANS_PROGRESSIVE;
  1543. I915_WRITE(TRANSCONF(TRANSCODER_A), val);
  1544. if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
  1545. DRM_ERROR("Failed to enable PCH transcoder\n");
  1546. }
  1547. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1548. enum pipe pipe)
  1549. {
  1550. struct drm_device *dev = dev_priv->dev;
  1551. uint32_t reg, val;
  1552. /* FDI relies on the transcoder */
  1553. assert_fdi_tx_disabled(dev_priv, pipe);
  1554. assert_fdi_rx_disabled(dev_priv, pipe);
  1555. /* Ports must be off as well */
  1556. assert_pch_ports_disabled(dev_priv, pipe);
  1557. reg = TRANSCONF(pipe);
  1558. val = I915_READ(reg);
  1559. val &= ~TRANS_ENABLE;
  1560. I915_WRITE(reg, val);
  1561. /* wait for PCH transcoder off, transcoder state */
  1562. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1563. DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  1564. if (!HAS_PCH_IBX(dev)) {
  1565. /* Workaround: Clear the timing override chicken bit again. */
  1566. reg = TRANS_CHICKEN2(pipe);
  1567. val = I915_READ(reg);
  1568. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1569. I915_WRITE(reg, val);
  1570. }
  1571. }
  1572. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1573. {
  1574. u32 val;
  1575. val = I915_READ(_TRANSACONF);
  1576. val &= ~TRANS_ENABLE;
  1577. I915_WRITE(_TRANSACONF, val);
  1578. /* wait for PCH transcoder off, transcoder state */
  1579. if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
  1580. DRM_ERROR("Failed to disable PCH transcoder\n");
  1581. /* Workaround: clear timing override bit. */
  1582. val = I915_READ(_TRANSA_CHICKEN2);
  1583. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1584. I915_WRITE(_TRANSA_CHICKEN2, val);
  1585. }
  1586. /**
  1587. * intel_enable_pipe - enable a pipe, asserting requirements
  1588. * @dev_priv: i915 private structure
  1589. * @pipe: pipe to enable
  1590. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1591. *
  1592. * Enable @pipe, making sure that various hardware specific requirements
  1593. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1594. *
  1595. * @pipe should be %PIPE_A or %PIPE_B.
  1596. *
  1597. * Will wait until the pipe is actually running (i.e. first vblank) before
  1598. * returning.
  1599. */
  1600. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1601. bool pch_port)
  1602. {
  1603. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1604. pipe);
  1605. enum pipe pch_transcoder;
  1606. int reg;
  1607. u32 val;
  1608. assert_planes_disabled(dev_priv, pipe);
  1609. assert_sprites_disabled(dev_priv, pipe);
  1610. if (HAS_PCH_LPT(dev_priv->dev))
  1611. pch_transcoder = TRANSCODER_A;
  1612. else
  1613. pch_transcoder = pipe;
  1614. /*
  1615. * A pipe without a PLL won't actually be able to drive bits from
  1616. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1617. * need the check.
  1618. */
  1619. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1620. assert_pll_enabled(dev_priv, pipe);
  1621. else {
  1622. if (pch_port) {
  1623. /* if driving the PCH, we need FDI enabled */
  1624. assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1625. assert_fdi_tx_pll_enabled(dev_priv,
  1626. (enum pipe) cpu_transcoder);
  1627. }
  1628. /* FIXME: assert CPU port conditions for SNB+ */
  1629. }
  1630. reg = PIPECONF(cpu_transcoder);
  1631. val = I915_READ(reg);
  1632. if (val & PIPECONF_ENABLE)
  1633. return;
  1634. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1635. intel_wait_for_vblank(dev_priv->dev, pipe);
  1636. }
  1637. /**
  1638. * intel_disable_pipe - disable a pipe, asserting requirements
  1639. * @dev_priv: i915 private structure
  1640. * @pipe: pipe to disable
  1641. *
  1642. * Disable @pipe, making sure that various hardware specific requirements
  1643. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1644. *
  1645. * @pipe should be %PIPE_A or %PIPE_B.
  1646. *
  1647. * Will wait until the pipe has shut down before returning.
  1648. */
  1649. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1650. enum pipe pipe)
  1651. {
  1652. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1653. pipe);
  1654. int reg;
  1655. u32 val;
  1656. /*
  1657. * Make sure planes won't keep trying to pump pixels to us,
  1658. * or we might hang the display.
  1659. */
  1660. assert_planes_disabled(dev_priv, pipe);
  1661. assert_sprites_disabled(dev_priv, pipe);
  1662. /* Don't disable pipe A or pipe A PLLs if needed */
  1663. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1664. return;
  1665. reg = PIPECONF(cpu_transcoder);
  1666. val = I915_READ(reg);
  1667. if ((val & PIPECONF_ENABLE) == 0)
  1668. return;
  1669. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1670. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1671. }
  1672. /*
  1673. * Plane regs are double buffered, going from enabled->disabled needs a
  1674. * trigger in order to latch. The display address reg provides this.
  1675. */
  1676. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1677. enum plane plane)
  1678. {
  1679. if (dev_priv->info->gen >= 4)
  1680. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1681. else
  1682. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1683. }
  1684. /**
  1685. * intel_enable_plane - enable a display plane on a given pipe
  1686. * @dev_priv: i915 private structure
  1687. * @plane: plane to enable
  1688. * @pipe: pipe being fed
  1689. *
  1690. * Enable @plane on @pipe, making sure that @pipe is running first.
  1691. */
  1692. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1693. enum plane plane, enum pipe pipe)
  1694. {
  1695. int reg;
  1696. u32 val;
  1697. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1698. assert_pipe_enabled(dev_priv, pipe);
  1699. reg = DSPCNTR(plane);
  1700. val = I915_READ(reg);
  1701. if (val & DISPLAY_PLANE_ENABLE)
  1702. return;
  1703. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1704. intel_flush_display_plane(dev_priv, plane);
  1705. intel_wait_for_vblank(dev_priv->dev, pipe);
  1706. }
  1707. /**
  1708. * intel_disable_plane - disable a display plane
  1709. * @dev_priv: i915 private structure
  1710. * @plane: plane to disable
  1711. * @pipe: pipe consuming the data
  1712. *
  1713. * Disable @plane; should be an independent operation.
  1714. */
  1715. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1716. enum plane plane, enum pipe pipe)
  1717. {
  1718. int reg;
  1719. u32 val;
  1720. reg = DSPCNTR(plane);
  1721. val = I915_READ(reg);
  1722. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1723. return;
  1724. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1725. intel_flush_display_plane(dev_priv, plane);
  1726. intel_wait_for_vblank(dev_priv->dev, pipe);
  1727. }
  1728. static bool need_vtd_wa(struct drm_device *dev)
  1729. {
  1730. #ifdef CONFIG_INTEL_IOMMU
  1731. if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  1732. return true;
  1733. #endif
  1734. return false;
  1735. }
  1736. int
  1737. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1738. struct drm_i915_gem_object *obj,
  1739. struct intel_ring_buffer *pipelined)
  1740. {
  1741. struct drm_i915_private *dev_priv = dev->dev_private;
  1742. u32 alignment;
  1743. int ret;
  1744. switch (obj->tiling_mode) {
  1745. case I915_TILING_NONE:
  1746. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1747. alignment = 128 * 1024;
  1748. else if (INTEL_INFO(dev)->gen >= 4)
  1749. alignment = 4 * 1024;
  1750. else
  1751. alignment = 64 * 1024;
  1752. break;
  1753. case I915_TILING_X:
  1754. /* pin() will align the object as required by fence */
  1755. alignment = 0;
  1756. break;
  1757. case I915_TILING_Y:
  1758. /* Despite that we check this in framebuffer_init userspace can
  1759. * screw us over and change the tiling after the fact. Only
  1760. * pinned buffers can't change their tiling. */
  1761. DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
  1762. return -EINVAL;
  1763. default:
  1764. BUG();
  1765. }
  1766. /* Note that the w/a also requires 64 PTE of padding following the
  1767. * bo. We currently fill all unused PTE with the shadow page and so
  1768. * we should always have valid PTE following the scanout preventing
  1769. * the VT-d warning.
  1770. */
  1771. if (need_vtd_wa(dev) && alignment < 256 * 1024)
  1772. alignment = 256 * 1024;
  1773. dev_priv->mm.interruptible = false;
  1774. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1775. if (ret)
  1776. goto err_interruptible;
  1777. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1778. * fence, whereas 965+ only requires a fence if using
  1779. * framebuffer compression. For simplicity, we always install
  1780. * a fence as the cost is not that onerous.
  1781. */
  1782. ret = i915_gem_object_get_fence(obj);
  1783. if (ret)
  1784. goto err_unpin;
  1785. i915_gem_object_pin_fence(obj);
  1786. dev_priv->mm.interruptible = true;
  1787. return 0;
  1788. err_unpin:
  1789. i915_gem_object_unpin(obj);
  1790. err_interruptible:
  1791. dev_priv->mm.interruptible = true;
  1792. return ret;
  1793. }
  1794. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1795. {
  1796. i915_gem_object_unpin_fence(obj);
  1797. i915_gem_object_unpin(obj);
  1798. }
  1799. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1800. * is assumed to be a power-of-two. */
  1801. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  1802. unsigned int tiling_mode,
  1803. unsigned int cpp,
  1804. unsigned int pitch)
  1805. {
  1806. if (tiling_mode != I915_TILING_NONE) {
  1807. unsigned int tile_rows, tiles;
  1808. tile_rows = *y / 8;
  1809. *y %= 8;
  1810. tiles = *x / (512/cpp);
  1811. *x %= 512/cpp;
  1812. return tile_rows * pitch * 8 + tiles * 4096;
  1813. } else {
  1814. unsigned int offset;
  1815. offset = *y * pitch + *x * cpp;
  1816. *y = 0;
  1817. *x = (offset & 4095) / cpp;
  1818. return offset & -4096;
  1819. }
  1820. }
  1821. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1822. int x, int y)
  1823. {
  1824. struct drm_device *dev = crtc->dev;
  1825. struct drm_i915_private *dev_priv = dev->dev_private;
  1826. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1827. struct intel_framebuffer *intel_fb;
  1828. struct drm_i915_gem_object *obj;
  1829. int plane = intel_crtc->plane;
  1830. unsigned long linear_offset;
  1831. u32 dspcntr;
  1832. u32 reg;
  1833. switch (plane) {
  1834. case 0:
  1835. case 1:
  1836. break;
  1837. default:
  1838. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1839. return -EINVAL;
  1840. }
  1841. intel_fb = to_intel_framebuffer(fb);
  1842. obj = intel_fb->obj;
  1843. reg = DSPCNTR(plane);
  1844. dspcntr = I915_READ(reg);
  1845. /* Mask out pixel format bits in case we change it */
  1846. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1847. switch (fb->pixel_format) {
  1848. case DRM_FORMAT_C8:
  1849. dspcntr |= DISPPLANE_8BPP;
  1850. break;
  1851. case DRM_FORMAT_XRGB1555:
  1852. case DRM_FORMAT_ARGB1555:
  1853. dspcntr |= DISPPLANE_BGRX555;
  1854. break;
  1855. case DRM_FORMAT_RGB565:
  1856. dspcntr |= DISPPLANE_BGRX565;
  1857. break;
  1858. case DRM_FORMAT_XRGB8888:
  1859. case DRM_FORMAT_ARGB8888:
  1860. dspcntr |= DISPPLANE_BGRX888;
  1861. break;
  1862. case DRM_FORMAT_XBGR8888:
  1863. case DRM_FORMAT_ABGR8888:
  1864. dspcntr |= DISPPLANE_RGBX888;
  1865. break;
  1866. case DRM_FORMAT_XRGB2101010:
  1867. case DRM_FORMAT_ARGB2101010:
  1868. dspcntr |= DISPPLANE_BGRX101010;
  1869. break;
  1870. case DRM_FORMAT_XBGR2101010:
  1871. case DRM_FORMAT_ABGR2101010:
  1872. dspcntr |= DISPPLANE_RGBX101010;
  1873. break;
  1874. default:
  1875. BUG();
  1876. }
  1877. if (INTEL_INFO(dev)->gen >= 4) {
  1878. if (obj->tiling_mode != I915_TILING_NONE)
  1879. dspcntr |= DISPPLANE_TILED;
  1880. else
  1881. dspcntr &= ~DISPPLANE_TILED;
  1882. }
  1883. I915_WRITE(reg, dspcntr);
  1884. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1885. if (INTEL_INFO(dev)->gen >= 4) {
  1886. intel_crtc->dspaddr_offset =
  1887. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1888. fb->bits_per_pixel / 8,
  1889. fb->pitches[0]);
  1890. linear_offset -= intel_crtc->dspaddr_offset;
  1891. } else {
  1892. intel_crtc->dspaddr_offset = linear_offset;
  1893. }
  1894. DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
  1895. obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
  1896. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1897. if (INTEL_INFO(dev)->gen >= 4) {
  1898. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1899. obj->gtt_offset + intel_crtc->dspaddr_offset);
  1900. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1901. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1902. } else
  1903. I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
  1904. POSTING_READ(reg);
  1905. return 0;
  1906. }
  1907. static int ironlake_update_plane(struct drm_crtc *crtc,
  1908. struct drm_framebuffer *fb, int x, int y)
  1909. {
  1910. struct drm_device *dev = crtc->dev;
  1911. struct drm_i915_private *dev_priv = dev->dev_private;
  1912. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1913. struct intel_framebuffer *intel_fb;
  1914. struct drm_i915_gem_object *obj;
  1915. int plane = intel_crtc->plane;
  1916. unsigned long linear_offset;
  1917. u32 dspcntr;
  1918. u32 reg;
  1919. switch (plane) {
  1920. case 0:
  1921. case 1:
  1922. case 2:
  1923. break;
  1924. default:
  1925. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1926. return -EINVAL;
  1927. }
  1928. intel_fb = to_intel_framebuffer(fb);
  1929. obj = intel_fb->obj;
  1930. reg = DSPCNTR(plane);
  1931. dspcntr = I915_READ(reg);
  1932. /* Mask out pixel format bits in case we change it */
  1933. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1934. switch (fb->pixel_format) {
  1935. case DRM_FORMAT_C8:
  1936. dspcntr |= DISPPLANE_8BPP;
  1937. break;
  1938. case DRM_FORMAT_RGB565:
  1939. dspcntr |= DISPPLANE_BGRX565;
  1940. break;
  1941. case DRM_FORMAT_XRGB8888:
  1942. case DRM_FORMAT_ARGB8888:
  1943. dspcntr |= DISPPLANE_BGRX888;
  1944. break;
  1945. case DRM_FORMAT_XBGR8888:
  1946. case DRM_FORMAT_ABGR8888:
  1947. dspcntr |= DISPPLANE_RGBX888;
  1948. break;
  1949. case DRM_FORMAT_XRGB2101010:
  1950. case DRM_FORMAT_ARGB2101010:
  1951. dspcntr |= DISPPLANE_BGRX101010;
  1952. break;
  1953. case DRM_FORMAT_XBGR2101010:
  1954. case DRM_FORMAT_ABGR2101010:
  1955. dspcntr |= DISPPLANE_RGBX101010;
  1956. break;
  1957. default:
  1958. BUG();
  1959. }
  1960. if (obj->tiling_mode != I915_TILING_NONE)
  1961. dspcntr |= DISPPLANE_TILED;
  1962. else
  1963. dspcntr &= ~DISPPLANE_TILED;
  1964. /* must disable */
  1965. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1966. I915_WRITE(reg, dspcntr);
  1967. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1968. intel_crtc->dspaddr_offset =
  1969. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1970. fb->bits_per_pixel / 8,
  1971. fb->pitches[0]);
  1972. linear_offset -= intel_crtc->dspaddr_offset;
  1973. DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
  1974. obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
  1975. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1976. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1977. obj->gtt_offset + intel_crtc->dspaddr_offset);
  1978. if (IS_HASWELL(dev)) {
  1979. I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  1980. } else {
  1981. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1982. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1983. }
  1984. POSTING_READ(reg);
  1985. return 0;
  1986. }
  1987. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1988. static int
  1989. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1990. int x, int y, enum mode_set_atomic state)
  1991. {
  1992. struct drm_device *dev = crtc->dev;
  1993. struct drm_i915_private *dev_priv = dev->dev_private;
  1994. if (dev_priv->display.disable_fbc)
  1995. dev_priv->display.disable_fbc(dev);
  1996. intel_increase_pllclock(crtc);
  1997. return dev_priv->display.update_plane(crtc, fb, x, y);
  1998. }
  1999. void intel_display_handle_reset(struct drm_device *dev)
  2000. {
  2001. struct drm_i915_private *dev_priv = dev->dev_private;
  2002. struct drm_crtc *crtc;
  2003. /*
  2004. * Flips in the rings have been nuked by the reset,
  2005. * so complete all pending flips so that user space
  2006. * will get its events and not get stuck.
  2007. *
  2008. * Also update the base address of all primary
  2009. * planes to the the last fb to make sure we're
  2010. * showing the correct fb after a reset.
  2011. *
  2012. * Need to make two loops over the crtcs so that we
  2013. * don't try to grab a crtc mutex before the
  2014. * pending_flip_queue really got woken up.
  2015. */
  2016. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2017. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2018. enum plane plane = intel_crtc->plane;
  2019. intel_prepare_page_flip(dev, plane);
  2020. intel_finish_page_flip_plane(dev, plane);
  2021. }
  2022. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2023. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2024. mutex_lock(&crtc->mutex);
  2025. if (intel_crtc->active)
  2026. dev_priv->display.update_plane(crtc, crtc->fb,
  2027. crtc->x, crtc->y);
  2028. mutex_unlock(&crtc->mutex);
  2029. }
  2030. }
  2031. static int
  2032. intel_finish_fb(struct drm_framebuffer *old_fb)
  2033. {
  2034. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  2035. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  2036. bool was_interruptible = dev_priv->mm.interruptible;
  2037. int ret;
  2038. /* Big Hammer, we also need to ensure that any pending
  2039. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  2040. * current scanout is retired before unpinning the old
  2041. * framebuffer.
  2042. *
  2043. * This should only fail upon a hung GPU, in which case we
  2044. * can safely continue.
  2045. */
  2046. dev_priv->mm.interruptible = false;
  2047. ret = i915_gem_object_finish_gpu(obj);
  2048. dev_priv->mm.interruptible = was_interruptible;
  2049. return ret;
  2050. }
  2051. static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
  2052. {
  2053. struct drm_device *dev = crtc->dev;
  2054. struct drm_i915_master_private *master_priv;
  2055. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2056. if (!dev->primary->master)
  2057. return;
  2058. master_priv = dev->primary->master->driver_priv;
  2059. if (!master_priv->sarea_priv)
  2060. return;
  2061. switch (intel_crtc->pipe) {
  2062. case 0:
  2063. master_priv->sarea_priv->pipeA_x = x;
  2064. master_priv->sarea_priv->pipeA_y = y;
  2065. break;
  2066. case 1:
  2067. master_priv->sarea_priv->pipeB_x = x;
  2068. master_priv->sarea_priv->pipeB_y = y;
  2069. break;
  2070. default:
  2071. break;
  2072. }
  2073. }
  2074. static int
  2075. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  2076. struct drm_framebuffer *fb)
  2077. {
  2078. struct drm_device *dev = crtc->dev;
  2079. struct drm_i915_private *dev_priv = dev->dev_private;
  2080. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2081. struct drm_framebuffer *old_fb;
  2082. int ret;
  2083. /* no fb bound */
  2084. if (!fb) {
  2085. DRM_ERROR("No FB bound\n");
  2086. return 0;
  2087. }
  2088. if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
  2089. DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
  2090. plane_name(intel_crtc->plane),
  2091. INTEL_INFO(dev)->num_pipes);
  2092. return -EINVAL;
  2093. }
  2094. mutex_lock(&dev->struct_mutex);
  2095. ret = intel_pin_and_fence_fb_obj(dev,
  2096. to_intel_framebuffer(fb)->obj,
  2097. NULL);
  2098. if (ret != 0) {
  2099. mutex_unlock(&dev->struct_mutex);
  2100. DRM_ERROR("pin & fence failed\n");
  2101. return ret;
  2102. }
  2103. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  2104. if (ret) {
  2105. intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  2106. mutex_unlock(&dev->struct_mutex);
  2107. DRM_ERROR("failed to update base address\n");
  2108. return ret;
  2109. }
  2110. old_fb = crtc->fb;
  2111. crtc->fb = fb;
  2112. crtc->x = x;
  2113. crtc->y = y;
  2114. if (old_fb) {
  2115. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2116. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  2117. }
  2118. intel_update_fbc(dev);
  2119. mutex_unlock(&dev->struct_mutex);
  2120. intel_crtc_update_sarea_pos(crtc, x, y);
  2121. return 0;
  2122. }
  2123. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2124. {
  2125. struct drm_device *dev = crtc->dev;
  2126. struct drm_i915_private *dev_priv = dev->dev_private;
  2127. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2128. int pipe = intel_crtc->pipe;
  2129. u32 reg, temp;
  2130. /* enable normal train */
  2131. reg = FDI_TX_CTL(pipe);
  2132. temp = I915_READ(reg);
  2133. if (IS_IVYBRIDGE(dev)) {
  2134. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2135. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2136. } else {
  2137. temp &= ~FDI_LINK_TRAIN_NONE;
  2138. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2139. }
  2140. I915_WRITE(reg, temp);
  2141. reg = FDI_RX_CTL(pipe);
  2142. temp = I915_READ(reg);
  2143. if (HAS_PCH_CPT(dev)) {
  2144. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2145. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2146. } else {
  2147. temp &= ~FDI_LINK_TRAIN_NONE;
  2148. temp |= FDI_LINK_TRAIN_NONE;
  2149. }
  2150. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2151. /* wait one idle pattern time */
  2152. POSTING_READ(reg);
  2153. udelay(1000);
  2154. /* IVB wants error correction enabled */
  2155. if (IS_IVYBRIDGE(dev))
  2156. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2157. FDI_FE_ERRC_ENABLE);
  2158. }
  2159. static void ivb_modeset_global_resources(struct drm_device *dev)
  2160. {
  2161. struct drm_i915_private *dev_priv = dev->dev_private;
  2162. struct intel_crtc *pipe_B_crtc =
  2163. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  2164. struct intel_crtc *pipe_C_crtc =
  2165. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
  2166. uint32_t temp;
  2167. /* When everything is off disable fdi C so that we could enable fdi B
  2168. * with all lanes. XXX: This misses the case where a pipe is not using
  2169. * any pch resources and so doesn't need any fdi lanes. */
  2170. if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
  2171. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2172. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  2173. temp = I915_READ(SOUTH_CHICKEN1);
  2174. temp &= ~FDI_BC_BIFURCATION_SELECT;
  2175. DRM_DEBUG_KMS("disabling fdi C rx\n");
  2176. I915_WRITE(SOUTH_CHICKEN1, temp);
  2177. }
  2178. }
  2179. /* The FDI link training functions for ILK/Ibexpeak. */
  2180. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2181. {
  2182. struct drm_device *dev = crtc->dev;
  2183. struct drm_i915_private *dev_priv = dev->dev_private;
  2184. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2185. int pipe = intel_crtc->pipe;
  2186. int plane = intel_crtc->plane;
  2187. u32 reg, temp, tries;
  2188. /* FDI needs bits from pipe & plane first */
  2189. assert_pipe_enabled(dev_priv, pipe);
  2190. assert_plane_enabled(dev_priv, plane);
  2191. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2192. for train result */
  2193. reg = FDI_RX_IMR(pipe);
  2194. temp = I915_READ(reg);
  2195. temp &= ~FDI_RX_SYMBOL_LOCK;
  2196. temp &= ~FDI_RX_BIT_LOCK;
  2197. I915_WRITE(reg, temp);
  2198. I915_READ(reg);
  2199. udelay(150);
  2200. /* enable CPU FDI TX and PCH FDI RX */
  2201. reg = FDI_TX_CTL(pipe);
  2202. temp = I915_READ(reg);
  2203. temp &= ~(7 << 19);
  2204. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2205. temp &= ~FDI_LINK_TRAIN_NONE;
  2206. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2207. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2208. reg = FDI_RX_CTL(pipe);
  2209. temp = I915_READ(reg);
  2210. temp &= ~FDI_LINK_TRAIN_NONE;
  2211. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2212. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2213. POSTING_READ(reg);
  2214. udelay(150);
  2215. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2216. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2217. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2218. FDI_RX_PHASE_SYNC_POINTER_EN);
  2219. reg = FDI_RX_IIR(pipe);
  2220. for (tries = 0; tries < 5; tries++) {
  2221. temp = I915_READ(reg);
  2222. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2223. if ((temp & FDI_RX_BIT_LOCK)) {
  2224. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2225. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2226. break;
  2227. }
  2228. }
  2229. if (tries == 5)
  2230. DRM_ERROR("FDI train 1 fail!\n");
  2231. /* Train 2 */
  2232. reg = FDI_TX_CTL(pipe);
  2233. temp = I915_READ(reg);
  2234. temp &= ~FDI_LINK_TRAIN_NONE;
  2235. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2236. I915_WRITE(reg, temp);
  2237. reg = FDI_RX_CTL(pipe);
  2238. temp = I915_READ(reg);
  2239. temp &= ~FDI_LINK_TRAIN_NONE;
  2240. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2241. I915_WRITE(reg, temp);
  2242. POSTING_READ(reg);
  2243. udelay(150);
  2244. reg = FDI_RX_IIR(pipe);
  2245. for (tries = 0; tries < 5; tries++) {
  2246. temp = I915_READ(reg);
  2247. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2248. if (temp & FDI_RX_SYMBOL_LOCK) {
  2249. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2250. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2251. break;
  2252. }
  2253. }
  2254. if (tries == 5)
  2255. DRM_ERROR("FDI train 2 fail!\n");
  2256. DRM_DEBUG_KMS("FDI train done\n");
  2257. }
  2258. static const int snb_b_fdi_train_param[] = {
  2259. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2260. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2261. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2262. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2263. };
  2264. /* The FDI link training functions for SNB/Cougarpoint. */
  2265. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2266. {
  2267. struct drm_device *dev = crtc->dev;
  2268. struct drm_i915_private *dev_priv = dev->dev_private;
  2269. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2270. int pipe = intel_crtc->pipe;
  2271. u32 reg, temp, i, retry;
  2272. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2273. for train result */
  2274. reg = FDI_RX_IMR(pipe);
  2275. temp = I915_READ(reg);
  2276. temp &= ~FDI_RX_SYMBOL_LOCK;
  2277. temp &= ~FDI_RX_BIT_LOCK;
  2278. I915_WRITE(reg, temp);
  2279. POSTING_READ(reg);
  2280. udelay(150);
  2281. /* enable CPU FDI TX and PCH FDI RX */
  2282. reg = FDI_TX_CTL(pipe);
  2283. temp = I915_READ(reg);
  2284. temp &= ~(7 << 19);
  2285. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2286. temp &= ~FDI_LINK_TRAIN_NONE;
  2287. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2288. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2289. /* SNB-B */
  2290. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2291. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2292. I915_WRITE(FDI_RX_MISC(pipe),
  2293. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2294. reg = FDI_RX_CTL(pipe);
  2295. temp = I915_READ(reg);
  2296. if (HAS_PCH_CPT(dev)) {
  2297. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2298. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2299. } else {
  2300. temp &= ~FDI_LINK_TRAIN_NONE;
  2301. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2302. }
  2303. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2304. POSTING_READ(reg);
  2305. udelay(150);
  2306. for (i = 0; i < 4; i++) {
  2307. reg = FDI_TX_CTL(pipe);
  2308. temp = I915_READ(reg);
  2309. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2310. temp |= snb_b_fdi_train_param[i];
  2311. I915_WRITE(reg, temp);
  2312. POSTING_READ(reg);
  2313. udelay(500);
  2314. for (retry = 0; retry < 5; retry++) {
  2315. reg = FDI_RX_IIR(pipe);
  2316. temp = I915_READ(reg);
  2317. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2318. if (temp & FDI_RX_BIT_LOCK) {
  2319. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2320. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2321. break;
  2322. }
  2323. udelay(50);
  2324. }
  2325. if (retry < 5)
  2326. break;
  2327. }
  2328. if (i == 4)
  2329. DRM_ERROR("FDI train 1 fail!\n");
  2330. /* Train 2 */
  2331. reg = FDI_TX_CTL(pipe);
  2332. temp = I915_READ(reg);
  2333. temp &= ~FDI_LINK_TRAIN_NONE;
  2334. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2335. if (IS_GEN6(dev)) {
  2336. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2337. /* SNB-B */
  2338. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2339. }
  2340. I915_WRITE(reg, temp);
  2341. reg = FDI_RX_CTL(pipe);
  2342. temp = I915_READ(reg);
  2343. if (HAS_PCH_CPT(dev)) {
  2344. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2345. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2346. } else {
  2347. temp &= ~FDI_LINK_TRAIN_NONE;
  2348. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2349. }
  2350. I915_WRITE(reg, temp);
  2351. POSTING_READ(reg);
  2352. udelay(150);
  2353. for (i = 0; i < 4; i++) {
  2354. reg = FDI_TX_CTL(pipe);
  2355. temp = I915_READ(reg);
  2356. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2357. temp |= snb_b_fdi_train_param[i];
  2358. I915_WRITE(reg, temp);
  2359. POSTING_READ(reg);
  2360. udelay(500);
  2361. for (retry = 0; retry < 5; retry++) {
  2362. reg = FDI_RX_IIR(pipe);
  2363. temp = I915_READ(reg);
  2364. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2365. if (temp & FDI_RX_SYMBOL_LOCK) {
  2366. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2367. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2368. break;
  2369. }
  2370. udelay(50);
  2371. }
  2372. if (retry < 5)
  2373. break;
  2374. }
  2375. if (i == 4)
  2376. DRM_ERROR("FDI train 2 fail!\n");
  2377. DRM_DEBUG_KMS("FDI train done.\n");
  2378. }
  2379. /* Manual link training for Ivy Bridge A0 parts */
  2380. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2381. {
  2382. struct drm_device *dev = crtc->dev;
  2383. struct drm_i915_private *dev_priv = dev->dev_private;
  2384. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2385. int pipe = intel_crtc->pipe;
  2386. u32 reg, temp, i;
  2387. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2388. for train result */
  2389. reg = FDI_RX_IMR(pipe);
  2390. temp = I915_READ(reg);
  2391. temp &= ~FDI_RX_SYMBOL_LOCK;
  2392. temp &= ~FDI_RX_BIT_LOCK;
  2393. I915_WRITE(reg, temp);
  2394. POSTING_READ(reg);
  2395. udelay(150);
  2396. DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  2397. I915_READ(FDI_RX_IIR(pipe)));
  2398. /* enable CPU FDI TX and PCH FDI RX */
  2399. reg = FDI_TX_CTL(pipe);
  2400. temp = I915_READ(reg);
  2401. temp &= ~(7 << 19);
  2402. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2403. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2404. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2405. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2406. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2407. temp |= FDI_COMPOSITE_SYNC;
  2408. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2409. I915_WRITE(FDI_RX_MISC(pipe),
  2410. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2411. reg = FDI_RX_CTL(pipe);
  2412. temp = I915_READ(reg);
  2413. temp &= ~FDI_LINK_TRAIN_AUTO;
  2414. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2415. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2416. temp |= FDI_COMPOSITE_SYNC;
  2417. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2418. POSTING_READ(reg);
  2419. udelay(150);
  2420. for (i = 0; i < 4; i++) {
  2421. reg = FDI_TX_CTL(pipe);
  2422. temp = I915_READ(reg);
  2423. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2424. temp |= snb_b_fdi_train_param[i];
  2425. I915_WRITE(reg, temp);
  2426. POSTING_READ(reg);
  2427. udelay(500);
  2428. reg = FDI_RX_IIR(pipe);
  2429. temp = I915_READ(reg);
  2430. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2431. if (temp & FDI_RX_BIT_LOCK ||
  2432. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2433. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2434. DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
  2435. break;
  2436. }
  2437. }
  2438. if (i == 4)
  2439. DRM_ERROR("FDI train 1 fail!\n");
  2440. /* Train 2 */
  2441. reg = FDI_TX_CTL(pipe);
  2442. temp = I915_READ(reg);
  2443. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2444. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2445. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2446. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2447. I915_WRITE(reg, temp);
  2448. reg = FDI_RX_CTL(pipe);
  2449. temp = I915_READ(reg);
  2450. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2451. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2452. I915_WRITE(reg, temp);
  2453. POSTING_READ(reg);
  2454. udelay(150);
  2455. for (i = 0; i < 4; i++) {
  2456. reg = FDI_TX_CTL(pipe);
  2457. temp = I915_READ(reg);
  2458. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2459. temp |= snb_b_fdi_train_param[i];
  2460. I915_WRITE(reg, temp);
  2461. POSTING_READ(reg);
  2462. udelay(500);
  2463. reg = FDI_RX_IIR(pipe);
  2464. temp = I915_READ(reg);
  2465. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2466. if (temp & FDI_RX_SYMBOL_LOCK) {
  2467. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2468. DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
  2469. break;
  2470. }
  2471. }
  2472. if (i == 4)
  2473. DRM_ERROR("FDI train 2 fail!\n");
  2474. DRM_DEBUG_KMS("FDI train done.\n");
  2475. }
  2476. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2477. {
  2478. struct drm_device *dev = intel_crtc->base.dev;
  2479. struct drm_i915_private *dev_priv = dev->dev_private;
  2480. int pipe = intel_crtc->pipe;
  2481. u32 reg, temp;
  2482. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2483. reg = FDI_RX_CTL(pipe);
  2484. temp = I915_READ(reg);
  2485. temp &= ~((0x7 << 19) | (0x7 << 16));
  2486. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2487. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2488. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2489. POSTING_READ(reg);
  2490. udelay(200);
  2491. /* Switch from Rawclk to PCDclk */
  2492. temp = I915_READ(reg);
  2493. I915_WRITE(reg, temp | FDI_PCDCLK);
  2494. POSTING_READ(reg);
  2495. udelay(200);
  2496. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2497. reg = FDI_TX_CTL(pipe);
  2498. temp = I915_READ(reg);
  2499. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2500. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2501. POSTING_READ(reg);
  2502. udelay(100);
  2503. }
  2504. }
  2505. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2506. {
  2507. struct drm_device *dev = intel_crtc->base.dev;
  2508. struct drm_i915_private *dev_priv = dev->dev_private;
  2509. int pipe = intel_crtc->pipe;
  2510. u32 reg, temp;
  2511. /* Switch from PCDclk to Rawclk */
  2512. reg = FDI_RX_CTL(pipe);
  2513. temp = I915_READ(reg);
  2514. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2515. /* Disable CPU FDI TX PLL */
  2516. reg = FDI_TX_CTL(pipe);
  2517. temp = I915_READ(reg);
  2518. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2519. POSTING_READ(reg);
  2520. udelay(100);
  2521. reg = FDI_RX_CTL(pipe);
  2522. temp = I915_READ(reg);
  2523. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2524. /* Wait for the clocks to turn off. */
  2525. POSTING_READ(reg);
  2526. udelay(100);
  2527. }
  2528. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2529. {
  2530. struct drm_device *dev = crtc->dev;
  2531. struct drm_i915_private *dev_priv = dev->dev_private;
  2532. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2533. int pipe = intel_crtc->pipe;
  2534. u32 reg, temp;
  2535. /* disable CPU FDI tx and PCH FDI rx */
  2536. reg = FDI_TX_CTL(pipe);
  2537. temp = I915_READ(reg);
  2538. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2539. POSTING_READ(reg);
  2540. reg = FDI_RX_CTL(pipe);
  2541. temp = I915_READ(reg);
  2542. temp &= ~(0x7 << 16);
  2543. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2544. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2545. POSTING_READ(reg);
  2546. udelay(100);
  2547. /* Ironlake workaround, disable clock pointer after downing FDI */
  2548. if (HAS_PCH_IBX(dev)) {
  2549. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2550. }
  2551. /* still set train pattern 1 */
  2552. reg = FDI_TX_CTL(pipe);
  2553. temp = I915_READ(reg);
  2554. temp &= ~FDI_LINK_TRAIN_NONE;
  2555. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2556. I915_WRITE(reg, temp);
  2557. reg = FDI_RX_CTL(pipe);
  2558. temp = I915_READ(reg);
  2559. if (HAS_PCH_CPT(dev)) {
  2560. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2561. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2562. } else {
  2563. temp &= ~FDI_LINK_TRAIN_NONE;
  2564. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2565. }
  2566. /* BPC in FDI rx is consistent with that in PIPECONF */
  2567. temp &= ~(0x07 << 16);
  2568. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2569. I915_WRITE(reg, temp);
  2570. POSTING_READ(reg);
  2571. udelay(100);
  2572. }
  2573. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  2574. {
  2575. struct drm_device *dev = crtc->dev;
  2576. struct drm_i915_private *dev_priv = dev->dev_private;
  2577. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2578. unsigned long flags;
  2579. bool pending;
  2580. if (i915_reset_in_progress(&dev_priv->gpu_error) ||
  2581. intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  2582. return false;
  2583. spin_lock_irqsave(&dev->event_lock, flags);
  2584. pending = to_intel_crtc(crtc)->unpin_work != NULL;
  2585. spin_unlock_irqrestore(&dev->event_lock, flags);
  2586. return pending;
  2587. }
  2588. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2589. {
  2590. struct drm_device *dev = crtc->dev;
  2591. struct drm_i915_private *dev_priv = dev->dev_private;
  2592. if (crtc->fb == NULL)
  2593. return;
  2594. WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  2595. wait_event(dev_priv->pending_flip_queue,
  2596. !intel_crtc_has_pending_flip(crtc));
  2597. mutex_lock(&dev->struct_mutex);
  2598. intel_finish_fb(crtc->fb);
  2599. mutex_unlock(&dev->struct_mutex);
  2600. }
  2601. /* Program iCLKIP clock to the desired frequency */
  2602. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2603. {
  2604. struct drm_device *dev = crtc->dev;
  2605. struct drm_i915_private *dev_priv = dev->dev_private;
  2606. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2607. u32 temp;
  2608. mutex_lock(&dev_priv->dpio_lock);
  2609. /* It is necessary to ungate the pixclk gate prior to programming
  2610. * the divisors, and gate it back when it is done.
  2611. */
  2612. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2613. /* Disable SSCCTL */
  2614. intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2615. intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
  2616. SBI_SSCCTL_DISABLE,
  2617. SBI_ICLK);
  2618. /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2619. if (crtc->mode.clock == 20000) {
  2620. auxdiv = 1;
  2621. divsel = 0x41;
  2622. phaseinc = 0x20;
  2623. } else {
  2624. /* The iCLK virtual clock root frequency is in MHz,
  2625. * but the crtc->mode.clock in in KHz. To get the divisors,
  2626. * it is necessary to divide one by another, so we
  2627. * convert the virtual clock precision to KHz here for higher
  2628. * precision.
  2629. */
  2630. u32 iclk_virtual_root_freq = 172800 * 1000;
  2631. u32 iclk_pi_range = 64;
  2632. u32 desired_divisor, msb_divisor_value, pi_value;
  2633. desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
  2634. msb_divisor_value = desired_divisor / iclk_pi_range;
  2635. pi_value = desired_divisor % iclk_pi_range;
  2636. auxdiv = 0;
  2637. divsel = msb_divisor_value - 2;
  2638. phaseinc = pi_value;
  2639. }
  2640. /* This should not happen with any sane values */
  2641. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2642. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2643. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2644. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2645. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2646. crtc->mode.clock,
  2647. auxdiv,
  2648. divsel,
  2649. phasedir,
  2650. phaseinc);
  2651. /* Program SSCDIVINTPHASE6 */
  2652. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  2653. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2654. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2655. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2656. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2657. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2658. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2659. intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  2660. /* Program SSCAUXDIV */
  2661. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  2662. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2663. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2664. intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  2665. /* Enable modulator and associated divider */
  2666. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  2667. temp &= ~SBI_SSCCTL_DISABLE;
  2668. intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  2669. /* Wait for initialization time */
  2670. udelay(24);
  2671. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2672. mutex_unlock(&dev_priv->dpio_lock);
  2673. }
  2674. /*
  2675. * Enable PCH resources required for PCH ports:
  2676. * - PCH PLLs
  2677. * - FDI training & RX/TX
  2678. * - update transcoder timings
  2679. * - DP transcoding bits
  2680. * - transcoder
  2681. */
  2682. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2683. {
  2684. struct drm_device *dev = crtc->dev;
  2685. struct drm_i915_private *dev_priv = dev->dev_private;
  2686. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2687. int pipe = intel_crtc->pipe;
  2688. u32 reg, temp;
  2689. assert_transcoder_disabled(dev_priv, pipe);
  2690. /* Write the TU size bits before fdi link training, so that error
  2691. * detection works. */
  2692. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2693. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2694. /* For PCH output, training FDI link */
  2695. dev_priv->display.fdi_link_train(crtc);
  2696. /* XXX: pch pll's can be enabled any time before we enable the PCH
  2697. * transcoder, and we actually should do this to not upset any PCH
  2698. * transcoder that already use the clock when we share it.
  2699. *
  2700. * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
  2701. * unconditionally resets the pll - we need that to have the right LVDS
  2702. * enable sequence. */
  2703. ironlake_enable_pch_pll(intel_crtc);
  2704. if (HAS_PCH_CPT(dev)) {
  2705. u32 sel;
  2706. temp = I915_READ(PCH_DPLL_SEL);
  2707. switch (pipe) {
  2708. default:
  2709. case 0:
  2710. temp |= TRANSA_DPLL_ENABLE;
  2711. sel = TRANSA_DPLLB_SEL;
  2712. break;
  2713. case 1:
  2714. temp |= TRANSB_DPLL_ENABLE;
  2715. sel = TRANSB_DPLLB_SEL;
  2716. break;
  2717. case 2:
  2718. temp |= TRANSC_DPLL_ENABLE;
  2719. sel = TRANSC_DPLLB_SEL;
  2720. break;
  2721. }
  2722. if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
  2723. temp |= sel;
  2724. else
  2725. temp &= ~sel;
  2726. I915_WRITE(PCH_DPLL_SEL, temp);
  2727. }
  2728. /* set transcoder timing, panel must allow it */
  2729. assert_panel_unlocked(dev_priv, pipe);
  2730. I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
  2731. I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
  2732. I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
  2733. I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
  2734. I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
  2735. I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
  2736. I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
  2737. intel_fdi_normal_train(crtc);
  2738. /* For PCH DP, enable TRANS_DP_CTL */
  2739. if (HAS_PCH_CPT(dev) &&
  2740. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2741. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2742. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  2743. reg = TRANS_DP_CTL(pipe);
  2744. temp = I915_READ(reg);
  2745. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2746. TRANS_DP_SYNC_MASK |
  2747. TRANS_DP_BPC_MASK);
  2748. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2749. TRANS_DP_ENH_FRAMING);
  2750. temp |= bpc << 9; /* same format but at 11:9 */
  2751. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2752. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2753. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2754. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2755. switch (intel_trans_dp_port_sel(crtc)) {
  2756. case PCH_DP_B:
  2757. temp |= TRANS_DP_PORT_SEL_B;
  2758. break;
  2759. case PCH_DP_C:
  2760. temp |= TRANS_DP_PORT_SEL_C;
  2761. break;
  2762. case PCH_DP_D:
  2763. temp |= TRANS_DP_PORT_SEL_D;
  2764. break;
  2765. default:
  2766. BUG();
  2767. }
  2768. I915_WRITE(reg, temp);
  2769. }
  2770. ironlake_enable_pch_transcoder(dev_priv, pipe);
  2771. }
  2772. static void lpt_pch_enable(struct drm_crtc *crtc)
  2773. {
  2774. struct drm_device *dev = crtc->dev;
  2775. struct drm_i915_private *dev_priv = dev->dev_private;
  2776. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2777. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  2778. assert_transcoder_disabled(dev_priv, TRANSCODER_A);
  2779. lpt_program_iclkip(crtc);
  2780. /* Set transcoder timing. */
  2781. I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
  2782. I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
  2783. I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
  2784. I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
  2785. I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
  2786. I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
  2787. I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
  2788. lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  2789. }
  2790. static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
  2791. {
  2792. struct intel_pch_pll *pll = intel_crtc->pch_pll;
  2793. if (pll == NULL)
  2794. return;
  2795. if (pll->refcount == 0) {
  2796. WARN(1, "bad PCH PLL refcount\n");
  2797. return;
  2798. }
  2799. --pll->refcount;
  2800. intel_crtc->pch_pll = NULL;
  2801. }
  2802. static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
  2803. {
  2804. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  2805. struct intel_pch_pll *pll;
  2806. int i;
  2807. pll = intel_crtc->pch_pll;
  2808. if (pll) {
  2809. DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
  2810. intel_crtc->base.base.id, pll->pll_reg);
  2811. goto prepare;
  2812. }
  2813. if (HAS_PCH_IBX(dev_priv->dev)) {
  2814. /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  2815. i = intel_crtc->pipe;
  2816. pll = &dev_priv->pch_plls[i];
  2817. DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
  2818. intel_crtc->base.base.id, pll->pll_reg);
  2819. goto found;
  2820. }
  2821. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  2822. pll = &dev_priv->pch_plls[i];
  2823. /* Only want to check enabled timings first */
  2824. if (pll->refcount == 0)
  2825. continue;
  2826. if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
  2827. fp == I915_READ(pll->fp0_reg)) {
  2828. DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
  2829. intel_crtc->base.base.id,
  2830. pll->pll_reg, pll->refcount, pll->active);
  2831. goto found;
  2832. }
  2833. }
  2834. /* Ok no matching timings, maybe there's a free one? */
  2835. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  2836. pll = &dev_priv->pch_plls[i];
  2837. if (pll->refcount == 0) {
  2838. DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
  2839. intel_crtc->base.base.id, pll->pll_reg);
  2840. goto found;
  2841. }
  2842. }
  2843. return NULL;
  2844. found:
  2845. intel_crtc->pch_pll = pll;
  2846. pll->refcount++;
  2847. DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
  2848. prepare: /* separate function? */
  2849. DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
  2850. /* Wait for the clocks to stabilize before rewriting the regs */
  2851. I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
  2852. POSTING_READ(pll->pll_reg);
  2853. udelay(150);
  2854. I915_WRITE(pll->fp0_reg, fp);
  2855. I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
  2856. pll->on = false;
  2857. return pll;
  2858. }
  2859. void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
  2860. {
  2861. struct drm_i915_private *dev_priv = dev->dev_private;
  2862. int dslreg = PIPEDSL(pipe);
  2863. u32 temp;
  2864. temp = I915_READ(dslreg);
  2865. udelay(500);
  2866. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2867. if (wait_for(I915_READ(dslreg) != temp, 5))
  2868. DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
  2869. }
  2870. }
  2871. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2872. {
  2873. struct drm_device *dev = crtc->dev;
  2874. struct drm_i915_private *dev_priv = dev->dev_private;
  2875. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2876. struct intel_encoder *encoder;
  2877. int pipe = intel_crtc->pipe;
  2878. int plane = intel_crtc->plane;
  2879. u32 temp;
  2880. WARN_ON(!crtc->enabled);
  2881. if (intel_crtc->active)
  2882. return;
  2883. intel_crtc->active = true;
  2884. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2885. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  2886. intel_update_watermarks(dev);
  2887. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  2888. temp = I915_READ(PCH_LVDS);
  2889. if ((temp & LVDS_PORT_EN) == 0)
  2890. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  2891. }
  2892. if (intel_crtc->config.has_pch_encoder) {
  2893. /* Note: FDI PLL enabling _must_ be done before we enable the
  2894. * cpu pipes, hence this is separate from all the other fdi/pch
  2895. * enabling. */
  2896. ironlake_fdi_pll_enable(intel_crtc);
  2897. } else {
  2898. assert_fdi_tx_disabled(dev_priv, pipe);
  2899. assert_fdi_rx_disabled(dev_priv, pipe);
  2900. }
  2901. for_each_encoder_on_crtc(dev, crtc, encoder)
  2902. if (encoder->pre_enable)
  2903. encoder->pre_enable(encoder);
  2904. /* Enable panel fitting for LVDS */
  2905. if (dev_priv->pch_pf_size &&
  2906. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
  2907. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2908. /* Force use of hard-coded filter coefficients
  2909. * as some pre-programmed values are broken,
  2910. * e.g. x201.
  2911. */
  2912. if (IS_IVYBRIDGE(dev))
  2913. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  2914. PF_PIPE_SEL_IVB(pipe));
  2915. else
  2916. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2917. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2918. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2919. }
  2920. /*
  2921. * On ILK+ LUT must be loaded before the pipe is running but with
  2922. * clocks enabled
  2923. */
  2924. intel_crtc_load_lut(crtc);
  2925. intel_enable_pipe(dev_priv, pipe,
  2926. intel_crtc->config.has_pch_encoder);
  2927. intel_enable_plane(dev_priv, plane, pipe);
  2928. if (intel_crtc->config.has_pch_encoder)
  2929. ironlake_pch_enable(crtc);
  2930. mutex_lock(&dev->struct_mutex);
  2931. intel_update_fbc(dev);
  2932. mutex_unlock(&dev->struct_mutex);
  2933. intel_crtc_update_cursor(crtc, true);
  2934. for_each_encoder_on_crtc(dev, crtc, encoder)
  2935. encoder->enable(encoder);
  2936. if (HAS_PCH_CPT(dev))
  2937. intel_cpt_verify_modeset(dev, intel_crtc->pipe);
  2938. /*
  2939. * There seems to be a race in PCH platform hw (at least on some
  2940. * outputs) where an enabled pipe still completes any pageflip right
  2941. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2942. * as the first vblank happend, everything works as expected. Hence just
  2943. * wait for one vblank before returning to avoid strange things
  2944. * happening.
  2945. */
  2946. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2947. }
  2948. static void haswell_crtc_enable(struct drm_crtc *crtc)
  2949. {
  2950. struct drm_device *dev = crtc->dev;
  2951. struct drm_i915_private *dev_priv = dev->dev_private;
  2952. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2953. struct intel_encoder *encoder;
  2954. int pipe = intel_crtc->pipe;
  2955. int plane = intel_crtc->plane;
  2956. WARN_ON(!crtc->enabled);
  2957. if (intel_crtc->active)
  2958. return;
  2959. intel_crtc->active = true;
  2960. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2961. if (intel_crtc->config.has_pch_encoder)
  2962. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  2963. intel_update_watermarks(dev);
  2964. if (intel_crtc->config.has_pch_encoder)
  2965. dev_priv->display.fdi_link_train(crtc);
  2966. for_each_encoder_on_crtc(dev, crtc, encoder)
  2967. if (encoder->pre_enable)
  2968. encoder->pre_enable(encoder);
  2969. intel_ddi_enable_pipe_clock(intel_crtc);
  2970. /* Enable panel fitting for eDP */
  2971. if (dev_priv->pch_pf_size &&
  2972. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  2973. /* Force use of hard-coded filter coefficients
  2974. * as some pre-programmed values are broken,
  2975. * e.g. x201.
  2976. */
  2977. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  2978. PF_PIPE_SEL_IVB(pipe));
  2979. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2980. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2981. }
  2982. /*
  2983. * On ILK+ LUT must be loaded before the pipe is running but with
  2984. * clocks enabled
  2985. */
  2986. intel_crtc_load_lut(crtc);
  2987. intel_ddi_set_pipe_settings(crtc);
  2988. intel_ddi_enable_transcoder_func(crtc);
  2989. intel_enable_pipe(dev_priv, pipe,
  2990. intel_crtc->config.has_pch_encoder);
  2991. intel_enable_plane(dev_priv, plane, pipe);
  2992. if (intel_crtc->config.has_pch_encoder)
  2993. lpt_pch_enable(crtc);
  2994. mutex_lock(&dev->struct_mutex);
  2995. intel_update_fbc(dev);
  2996. mutex_unlock(&dev->struct_mutex);
  2997. intel_crtc_update_cursor(crtc, true);
  2998. for_each_encoder_on_crtc(dev, crtc, encoder)
  2999. encoder->enable(encoder);
  3000. /*
  3001. * There seems to be a race in PCH platform hw (at least on some
  3002. * outputs) where an enabled pipe still completes any pageflip right
  3003. * away (as if the pipe is off) instead of waiting for vblank. As soon
  3004. * as the first vblank happend, everything works as expected. Hence just
  3005. * wait for one vblank before returning to avoid strange things
  3006. * happening.
  3007. */
  3008. intel_wait_for_vblank(dev, intel_crtc->pipe);
  3009. }
  3010. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  3011. {
  3012. struct drm_device *dev = crtc->dev;
  3013. struct drm_i915_private *dev_priv = dev->dev_private;
  3014. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3015. struct intel_encoder *encoder;
  3016. int pipe = intel_crtc->pipe;
  3017. int plane = intel_crtc->plane;
  3018. u32 reg, temp;
  3019. if (!intel_crtc->active)
  3020. return;
  3021. for_each_encoder_on_crtc(dev, crtc, encoder)
  3022. encoder->disable(encoder);
  3023. intel_crtc_wait_for_pending_flips(crtc);
  3024. drm_vblank_off(dev, pipe);
  3025. intel_crtc_update_cursor(crtc, false);
  3026. intel_disable_plane(dev_priv, plane, pipe);
  3027. if (dev_priv->cfb_plane == plane)
  3028. intel_disable_fbc(dev);
  3029. intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
  3030. intel_disable_pipe(dev_priv, pipe);
  3031. /* Disable PF */
  3032. I915_WRITE(PF_CTL(pipe), 0);
  3033. I915_WRITE(PF_WIN_SZ(pipe), 0);
  3034. for_each_encoder_on_crtc(dev, crtc, encoder)
  3035. if (encoder->post_disable)
  3036. encoder->post_disable(encoder);
  3037. ironlake_fdi_disable(crtc);
  3038. ironlake_disable_pch_transcoder(dev_priv, pipe);
  3039. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  3040. if (HAS_PCH_CPT(dev)) {
  3041. /* disable TRANS_DP_CTL */
  3042. reg = TRANS_DP_CTL(pipe);
  3043. temp = I915_READ(reg);
  3044. temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  3045. temp |= TRANS_DP_PORT_SEL_NONE;
  3046. I915_WRITE(reg, temp);
  3047. /* disable DPLL_SEL */
  3048. temp = I915_READ(PCH_DPLL_SEL);
  3049. switch (pipe) {
  3050. case 0:
  3051. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  3052. break;
  3053. case 1:
  3054. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  3055. break;
  3056. case 2:
  3057. /* C shares PLL A or B */
  3058. temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
  3059. break;
  3060. default:
  3061. BUG(); /* wtf */
  3062. }
  3063. I915_WRITE(PCH_DPLL_SEL, temp);
  3064. }
  3065. /* disable PCH DPLL */
  3066. intel_disable_pch_pll(intel_crtc);
  3067. ironlake_fdi_pll_disable(intel_crtc);
  3068. intel_crtc->active = false;
  3069. intel_update_watermarks(dev);
  3070. mutex_lock(&dev->struct_mutex);
  3071. intel_update_fbc(dev);
  3072. mutex_unlock(&dev->struct_mutex);
  3073. }
  3074. static void haswell_crtc_disable(struct drm_crtc *crtc)
  3075. {
  3076. struct drm_device *dev = crtc->dev;
  3077. struct drm_i915_private *dev_priv = dev->dev_private;
  3078. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3079. struct intel_encoder *encoder;
  3080. int pipe = intel_crtc->pipe;
  3081. int plane = intel_crtc->plane;
  3082. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3083. if (!intel_crtc->active)
  3084. return;
  3085. for_each_encoder_on_crtc(dev, crtc, encoder)
  3086. encoder->disable(encoder);
  3087. intel_crtc_wait_for_pending_flips(crtc);
  3088. drm_vblank_off(dev, pipe);
  3089. intel_crtc_update_cursor(crtc, false);
  3090. intel_disable_plane(dev_priv, plane, pipe);
  3091. if (dev_priv->cfb_plane == plane)
  3092. intel_disable_fbc(dev);
  3093. if (intel_crtc->config.has_pch_encoder)
  3094. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
  3095. intel_disable_pipe(dev_priv, pipe);
  3096. intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  3097. /* XXX: Once we have proper panel fitter state tracking implemented with
  3098. * hardware state read/check support we should switch to only disable
  3099. * the panel fitter when we know it's used. */
  3100. if (intel_using_power_well(dev)) {
  3101. I915_WRITE(PF_CTL(pipe), 0);
  3102. I915_WRITE(PF_WIN_SZ(pipe), 0);
  3103. }
  3104. intel_ddi_disable_pipe_clock(intel_crtc);
  3105. for_each_encoder_on_crtc(dev, crtc, encoder)
  3106. if (encoder->post_disable)
  3107. encoder->post_disable(encoder);
  3108. if (intel_crtc->config.has_pch_encoder) {
  3109. lpt_disable_pch_transcoder(dev_priv);
  3110. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  3111. intel_ddi_fdi_disable(crtc);
  3112. }
  3113. intel_crtc->active = false;
  3114. intel_update_watermarks(dev);
  3115. mutex_lock(&dev->struct_mutex);
  3116. intel_update_fbc(dev);
  3117. mutex_unlock(&dev->struct_mutex);
  3118. }
  3119. static void ironlake_crtc_off(struct drm_crtc *crtc)
  3120. {
  3121. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3122. intel_put_pch_pll(intel_crtc);
  3123. }
  3124. static void haswell_crtc_off(struct drm_crtc *crtc)
  3125. {
  3126. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3127. /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
  3128. * start using it. */
  3129. intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
  3130. intel_ddi_put_crtc_pll(crtc);
  3131. }
  3132. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  3133. {
  3134. if (!enable && intel_crtc->overlay) {
  3135. struct drm_device *dev = intel_crtc->base.dev;
  3136. struct drm_i915_private *dev_priv = dev->dev_private;
  3137. mutex_lock(&dev->struct_mutex);
  3138. dev_priv->mm.interruptible = false;
  3139. (void) intel_overlay_switch_off(intel_crtc->overlay);
  3140. dev_priv->mm.interruptible = true;
  3141. mutex_unlock(&dev->struct_mutex);
  3142. }
  3143. /* Let userspace switch the overlay on again. In most cases userspace
  3144. * has to recompute where to put it anyway.
  3145. */
  3146. }
  3147. /**
  3148. * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
  3149. * cursor plane briefly if not already running after enabling the display
  3150. * plane.
  3151. * This workaround avoids occasional blank screens when self refresh is
  3152. * enabled.
  3153. */
  3154. static void
  3155. g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
  3156. {
  3157. u32 cntl = I915_READ(CURCNTR(pipe));
  3158. if ((cntl & CURSOR_MODE) == 0) {
  3159. u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
  3160. I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
  3161. I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
  3162. intel_wait_for_vblank(dev_priv->dev, pipe);
  3163. I915_WRITE(CURCNTR(pipe), cntl);
  3164. I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
  3165. I915_WRITE(FW_BLC_SELF, fw_bcl_self);
  3166. }
  3167. }
  3168. static void valleyview_crtc_enable(struct drm_crtc *crtc)
  3169. {
  3170. struct drm_device *dev = crtc->dev;
  3171. struct drm_i915_private *dev_priv = dev->dev_private;
  3172. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3173. struct intel_encoder *encoder;
  3174. int pipe = intel_crtc->pipe;
  3175. int plane = intel_crtc->plane;
  3176. WARN_ON(!crtc->enabled);
  3177. if (intel_crtc->active)
  3178. return;
  3179. intel_crtc->active = true;
  3180. intel_update_watermarks(dev);
  3181. mutex_lock(&dev_priv->dpio_lock);
  3182. for_each_encoder_on_crtc(dev, crtc, encoder)
  3183. if (encoder->pre_pll_enable)
  3184. encoder->pre_pll_enable(encoder);
  3185. intel_enable_pll(dev_priv, pipe);
  3186. for_each_encoder_on_crtc(dev, crtc, encoder)
  3187. if (encoder->pre_enable)
  3188. encoder->pre_enable(encoder);
  3189. /* VLV wants encoder enabling _before_ the pipe is up. */
  3190. for_each_encoder_on_crtc(dev, crtc, encoder)
  3191. encoder->enable(encoder);
  3192. intel_enable_pipe(dev_priv, pipe, false);
  3193. intel_enable_plane(dev_priv, plane, pipe);
  3194. intel_crtc_load_lut(crtc);
  3195. intel_update_fbc(dev);
  3196. /* Give the overlay scaler a chance to enable if it's on this pipe */
  3197. intel_crtc_dpms_overlay(intel_crtc, true);
  3198. intel_crtc_update_cursor(crtc, true);
  3199. mutex_unlock(&dev_priv->dpio_lock);
  3200. }
  3201. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  3202. {
  3203. struct drm_device *dev = crtc->dev;
  3204. struct drm_i915_private *dev_priv = dev->dev_private;
  3205. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3206. struct intel_encoder *encoder;
  3207. int pipe = intel_crtc->pipe;
  3208. int plane = intel_crtc->plane;
  3209. WARN_ON(!crtc->enabled);
  3210. if (intel_crtc->active)
  3211. return;
  3212. intel_crtc->active = true;
  3213. intel_update_watermarks(dev);
  3214. intel_enable_pll(dev_priv, pipe);
  3215. for_each_encoder_on_crtc(dev, crtc, encoder)
  3216. if (encoder->pre_enable)
  3217. encoder->pre_enable(encoder);
  3218. intel_enable_pipe(dev_priv, pipe, false);
  3219. intel_enable_plane(dev_priv, plane, pipe);
  3220. if (IS_G4X(dev))
  3221. g4x_fixup_plane(dev_priv, pipe);
  3222. intel_crtc_load_lut(crtc);
  3223. intel_update_fbc(dev);
  3224. /* Give the overlay scaler a chance to enable if it's on this pipe */
  3225. intel_crtc_dpms_overlay(intel_crtc, true);
  3226. intel_crtc_update_cursor(crtc, true);
  3227. for_each_encoder_on_crtc(dev, crtc, encoder)
  3228. encoder->enable(encoder);
  3229. }
  3230. static void i9xx_pfit_disable(struct intel_crtc *crtc)
  3231. {
  3232. struct drm_device *dev = crtc->base.dev;
  3233. struct drm_i915_private *dev_priv = dev->dev_private;
  3234. enum pipe pipe;
  3235. uint32_t pctl = I915_READ(PFIT_CONTROL);
  3236. assert_pipe_disabled(dev_priv, crtc->pipe);
  3237. if (INTEL_INFO(dev)->gen >= 4)
  3238. pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
  3239. else
  3240. pipe = PIPE_B;
  3241. if (pipe == crtc->pipe) {
  3242. DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
  3243. I915_WRITE(PFIT_CONTROL, 0);
  3244. }
  3245. }
  3246. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  3247. {
  3248. struct drm_device *dev = crtc->dev;
  3249. struct drm_i915_private *dev_priv = dev->dev_private;
  3250. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3251. struct intel_encoder *encoder;
  3252. int pipe = intel_crtc->pipe;
  3253. int plane = intel_crtc->plane;
  3254. if (!intel_crtc->active)
  3255. return;
  3256. for_each_encoder_on_crtc(dev, crtc, encoder)
  3257. encoder->disable(encoder);
  3258. /* Give the overlay scaler a chance to disable if it's on this pipe */
  3259. intel_crtc_wait_for_pending_flips(crtc);
  3260. drm_vblank_off(dev, pipe);
  3261. intel_crtc_dpms_overlay(intel_crtc, false);
  3262. intel_crtc_update_cursor(crtc, false);
  3263. if (dev_priv->cfb_plane == plane)
  3264. intel_disable_fbc(dev);
  3265. intel_disable_plane(dev_priv, plane, pipe);
  3266. intel_disable_pipe(dev_priv, pipe);
  3267. i9xx_pfit_disable(intel_crtc);
  3268. for_each_encoder_on_crtc(dev, crtc, encoder)
  3269. if (encoder->post_disable)
  3270. encoder->post_disable(encoder);
  3271. intel_disable_pll(dev_priv, pipe);
  3272. intel_crtc->active = false;
  3273. intel_update_fbc(dev);
  3274. intel_update_watermarks(dev);
  3275. }
  3276. static void i9xx_crtc_off(struct drm_crtc *crtc)
  3277. {
  3278. }
  3279. static void intel_crtc_update_sarea(struct drm_crtc *crtc,
  3280. bool enabled)
  3281. {
  3282. struct drm_device *dev = crtc->dev;
  3283. struct drm_i915_master_private *master_priv;
  3284. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3285. int pipe = intel_crtc->pipe;
  3286. if (!dev->primary->master)
  3287. return;
  3288. master_priv = dev->primary->master->driver_priv;
  3289. if (!master_priv->sarea_priv)
  3290. return;
  3291. switch (pipe) {
  3292. case 0:
  3293. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  3294. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  3295. break;
  3296. case 1:
  3297. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  3298. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  3299. break;
  3300. default:
  3301. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3302. break;
  3303. }
  3304. }
  3305. /**
  3306. * Sets the power management mode of the pipe and plane.
  3307. */
  3308. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  3309. {
  3310. struct drm_device *dev = crtc->dev;
  3311. struct drm_i915_private *dev_priv = dev->dev_private;
  3312. struct intel_encoder *intel_encoder;
  3313. bool enable = false;
  3314. for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  3315. enable |= intel_encoder->connectors_active;
  3316. if (enable)
  3317. dev_priv->display.crtc_enable(crtc);
  3318. else
  3319. dev_priv->display.crtc_disable(crtc);
  3320. intel_crtc_update_sarea(crtc, enable);
  3321. }
  3322. static void intel_crtc_disable(struct drm_crtc *crtc)
  3323. {
  3324. struct drm_device *dev = crtc->dev;
  3325. struct drm_connector *connector;
  3326. struct drm_i915_private *dev_priv = dev->dev_private;
  3327. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3328. /* crtc should still be enabled when we disable it. */
  3329. WARN_ON(!crtc->enabled);
  3330. intel_crtc->eld_vld = false;
  3331. dev_priv->display.crtc_disable(crtc);
  3332. intel_crtc_update_sarea(crtc, false);
  3333. dev_priv->display.off(crtc);
  3334. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3335. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3336. if (crtc->fb) {
  3337. mutex_lock(&dev->struct_mutex);
  3338. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3339. mutex_unlock(&dev->struct_mutex);
  3340. crtc->fb = NULL;
  3341. }
  3342. /* Update computed state. */
  3343. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3344. if (!connector->encoder || !connector->encoder->crtc)
  3345. continue;
  3346. if (connector->encoder->crtc != crtc)
  3347. continue;
  3348. connector->dpms = DRM_MODE_DPMS_OFF;
  3349. to_intel_encoder(connector->encoder)->connectors_active = false;
  3350. }
  3351. }
  3352. void intel_modeset_disable(struct drm_device *dev)
  3353. {
  3354. struct drm_crtc *crtc;
  3355. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3356. if (crtc->enabled)
  3357. intel_crtc_disable(crtc);
  3358. }
  3359. }
  3360. void intel_encoder_destroy(struct drm_encoder *encoder)
  3361. {
  3362. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3363. drm_encoder_cleanup(encoder);
  3364. kfree(intel_encoder);
  3365. }
  3366. /* Simple dpms helper for encodres with just one connector, no cloning and only
  3367. * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3368. * state of the entire output pipe. */
  3369. void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3370. {
  3371. if (mode == DRM_MODE_DPMS_ON) {
  3372. encoder->connectors_active = true;
  3373. intel_crtc_update_dpms(encoder->base.crtc);
  3374. } else {
  3375. encoder->connectors_active = false;
  3376. intel_crtc_update_dpms(encoder->base.crtc);
  3377. }
  3378. }
  3379. /* Cross check the actual hw state with our own modeset state tracking (and it's
  3380. * internal consistency). */
  3381. static void intel_connector_check_state(struct intel_connector *connector)
  3382. {
  3383. if (connector->get_hw_state(connector)) {
  3384. struct intel_encoder *encoder = connector->encoder;
  3385. struct drm_crtc *crtc;
  3386. bool encoder_enabled;
  3387. enum pipe pipe;
  3388. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  3389. connector->base.base.id,
  3390. drm_get_connector_name(&connector->base));
  3391. WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
  3392. "wrong connector dpms state\n");
  3393. WARN(connector->base.encoder != &encoder->base,
  3394. "active connector not linked to encoder\n");
  3395. WARN(!encoder->connectors_active,
  3396. "encoder->connectors_active not set\n");
  3397. encoder_enabled = encoder->get_hw_state(encoder, &pipe);
  3398. WARN(!encoder_enabled, "encoder not enabled\n");
  3399. if (WARN_ON(!encoder->base.crtc))
  3400. return;
  3401. crtc = encoder->base.crtc;
  3402. WARN(!crtc->enabled, "crtc not enabled\n");
  3403. WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
  3404. WARN(pipe != to_intel_crtc(crtc)->pipe,
  3405. "encoder active on the wrong pipe\n");
  3406. }
  3407. }
  3408. /* Even simpler default implementation, if there's really no special case to
  3409. * consider. */
  3410. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3411. {
  3412. struct intel_encoder *encoder = intel_attached_encoder(connector);
  3413. /* All the simple cases only support two dpms states. */
  3414. if (mode != DRM_MODE_DPMS_ON)
  3415. mode = DRM_MODE_DPMS_OFF;
  3416. if (mode == connector->dpms)
  3417. return;
  3418. connector->dpms = mode;
  3419. /* Only need to change hw state when actually enabled */
  3420. if (encoder->base.crtc)
  3421. intel_encoder_dpms(encoder, mode);
  3422. else
  3423. WARN_ON(encoder->connectors_active != false);
  3424. intel_modeset_check_state(connector->dev);
  3425. }
  3426. /* Simple connector->get_hw_state implementation for encoders that support only
  3427. * one connector and no cloning and hence the encoder state determines the state
  3428. * of the connector. */
  3429. bool intel_connector_get_hw_state(struct intel_connector *connector)
  3430. {
  3431. enum pipe pipe = 0;
  3432. struct intel_encoder *encoder = connector->encoder;
  3433. return encoder->get_hw_state(encoder, &pipe);
  3434. }
  3435. static bool intel_crtc_compute_config(struct drm_crtc *crtc,
  3436. struct intel_crtc_config *pipe_config)
  3437. {
  3438. struct drm_device *dev = crtc->dev;
  3439. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3440. if (HAS_PCH_SPLIT(dev)) {
  3441. /* FDI link clock is fixed at 2.7G */
  3442. if (pipe_config->requested_mode.clock * 3
  3443. > IRONLAKE_FDI_FREQ * 4)
  3444. return false;
  3445. }
  3446. /* All interlaced capable intel hw wants timings in frames. Note though
  3447. * that intel_lvds_mode_fixup does some funny tricks with the crtc
  3448. * timings, so we need to be careful not to clobber these.*/
  3449. if (!pipe_config->timings_set)
  3450. drm_mode_set_crtcinfo(adjusted_mode, 0);
  3451. /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
  3452. * with a hsync front porch of 0.
  3453. */
  3454. if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  3455. adjusted_mode->hsync_start == adjusted_mode->hdisplay)
  3456. return false;
  3457. if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
  3458. pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
  3459. } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
  3460. /* only a 8bpc pipe, with 6bpc dither through the panel fitter
  3461. * for lvds. */
  3462. pipe_config->pipe_bpp = 8*3;
  3463. }
  3464. return true;
  3465. }
  3466. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  3467. {
  3468. return 400000; /* FIXME */
  3469. }
  3470. static int i945_get_display_clock_speed(struct drm_device *dev)
  3471. {
  3472. return 400000;
  3473. }
  3474. static int i915_get_display_clock_speed(struct drm_device *dev)
  3475. {
  3476. return 333000;
  3477. }
  3478. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  3479. {
  3480. return 200000;
  3481. }
  3482. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  3483. {
  3484. u16 gcfgc = 0;
  3485. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3486. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  3487. return 133000;
  3488. else {
  3489. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3490. case GC_DISPLAY_CLOCK_333_MHZ:
  3491. return 333000;
  3492. default:
  3493. case GC_DISPLAY_CLOCK_190_200_MHZ:
  3494. return 190000;
  3495. }
  3496. }
  3497. }
  3498. static int i865_get_display_clock_speed(struct drm_device *dev)
  3499. {
  3500. return 266000;
  3501. }
  3502. static int i855_get_display_clock_speed(struct drm_device *dev)
  3503. {
  3504. u16 hpllcc = 0;
  3505. /* Assume that the hardware is in the high speed state. This
  3506. * should be the default.
  3507. */
  3508. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3509. case GC_CLOCK_133_200:
  3510. case GC_CLOCK_100_200:
  3511. return 200000;
  3512. case GC_CLOCK_166_250:
  3513. return 250000;
  3514. case GC_CLOCK_100_133:
  3515. return 133000;
  3516. }
  3517. /* Shouldn't happen */
  3518. return 0;
  3519. }
  3520. static int i830_get_display_clock_speed(struct drm_device *dev)
  3521. {
  3522. return 133000;
  3523. }
  3524. static void
  3525. intel_reduce_ratio(uint32_t *num, uint32_t *den)
  3526. {
  3527. while (*num > 0xffffff || *den > 0xffffff) {
  3528. *num >>= 1;
  3529. *den >>= 1;
  3530. }
  3531. }
  3532. void
  3533. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  3534. int pixel_clock, int link_clock,
  3535. struct intel_link_m_n *m_n)
  3536. {
  3537. m_n->tu = 64;
  3538. m_n->gmch_m = bits_per_pixel * pixel_clock;
  3539. m_n->gmch_n = link_clock * nlanes * 8;
  3540. intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  3541. m_n->link_m = pixel_clock;
  3542. m_n->link_n = link_clock;
  3543. intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
  3544. }
  3545. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3546. {
  3547. if (i915_panel_use_ssc >= 0)
  3548. return i915_panel_use_ssc != 0;
  3549. return dev_priv->lvds_use_ssc
  3550. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3551. }
  3552. static int vlv_get_refclk(struct drm_crtc *crtc)
  3553. {
  3554. struct drm_device *dev = crtc->dev;
  3555. struct drm_i915_private *dev_priv = dev->dev_private;
  3556. int refclk = 27000; /* for DP & HDMI */
  3557. return 100000; /* only one validated so far */
  3558. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  3559. refclk = 96000;
  3560. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  3561. if (intel_panel_use_ssc(dev_priv))
  3562. refclk = 100000;
  3563. else
  3564. refclk = 96000;
  3565. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  3566. refclk = 100000;
  3567. }
  3568. return refclk;
  3569. }
  3570. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  3571. {
  3572. struct drm_device *dev = crtc->dev;
  3573. struct drm_i915_private *dev_priv = dev->dev_private;
  3574. int refclk;
  3575. if (IS_VALLEYVIEW(dev)) {
  3576. refclk = vlv_get_refclk(crtc);
  3577. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3578. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3579. refclk = dev_priv->lvds_ssc_freq * 1000;
  3580. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3581. refclk / 1000);
  3582. } else if (!IS_GEN2(dev)) {
  3583. refclk = 96000;
  3584. } else {
  3585. refclk = 48000;
  3586. }
  3587. return refclk;
  3588. }
  3589. static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
  3590. {
  3591. unsigned dotclock = crtc->config.adjusted_mode.clock;
  3592. struct dpll *clock = &crtc->config.dpll;
  3593. /* SDVO TV has fixed PLL values depend on its clock range,
  3594. this mirrors vbios setting. */
  3595. if (dotclock >= 100000 && dotclock < 140500) {
  3596. clock->p1 = 2;
  3597. clock->p2 = 10;
  3598. clock->n = 3;
  3599. clock->m1 = 16;
  3600. clock->m2 = 8;
  3601. } else if (dotclock >= 140500 && dotclock <= 200000) {
  3602. clock->p1 = 1;
  3603. clock->p2 = 10;
  3604. clock->n = 6;
  3605. clock->m1 = 12;
  3606. clock->m2 = 8;
  3607. }
  3608. crtc->config.clock_set = true;
  3609. }
  3610. static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
  3611. intel_clock_t *reduced_clock)
  3612. {
  3613. struct drm_device *dev = crtc->base.dev;
  3614. struct drm_i915_private *dev_priv = dev->dev_private;
  3615. int pipe = crtc->pipe;
  3616. u32 fp, fp2 = 0;
  3617. struct dpll *clock = &crtc->config.dpll;
  3618. if (IS_PINEVIEW(dev)) {
  3619. fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
  3620. if (reduced_clock)
  3621. fp2 = (1 << reduced_clock->n) << 16 |
  3622. reduced_clock->m1 << 8 | reduced_clock->m2;
  3623. } else {
  3624. fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
  3625. if (reduced_clock)
  3626. fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
  3627. reduced_clock->m2;
  3628. }
  3629. I915_WRITE(FP0(pipe), fp);
  3630. crtc->lowfreq_avail = false;
  3631. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3632. reduced_clock && i915_powersave) {
  3633. I915_WRITE(FP1(pipe), fp2);
  3634. crtc->lowfreq_avail = true;
  3635. } else {
  3636. I915_WRITE(FP1(pipe), fp);
  3637. }
  3638. }
  3639. static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
  3640. {
  3641. u32 reg_val;
  3642. /*
  3643. * PLLB opamp always calibrates to max value of 0x3f, force enable it
  3644. * and set it to a reasonable value instead.
  3645. */
  3646. reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
  3647. reg_val &= 0xffffff00;
  3648. reg_val |= 0x00000030;
  3649. intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
  3650. reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
  3651. reg_val &= 0x8cffffff;
  3652. reg_val = 0x8c000000;
  3653. intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
  3654. reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
  3655. reg_val &= 0xffffff00;
  3656. intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
  3657. reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
  3658. reg_val &= 0x00ffffff;
  3659. reg_val |= 0xb0000000;
  3660. intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
  3661. }
  3662. static void intel_dp_set_m_n(struct intel_crtc *crtc)
  3663. {
  3664. if (crtc->config.has_pch_encoder)
  3665. intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3666. else
  3667. intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3668. }
  3669. static void vlv_update_pll(struct intel_crtc *crtc)
  3670. {
  3671. struct drm_device *dev = crtc->base.dev;
  3672. struct drm_i915_private *dev_priv = dev->dev_private;
  3673. struct drm_display_mode *adjusted_mode =
  3674. &crtc->config.adjusted_mode;
  3675. struct intel_encoder *encoder;
  3676. int pipe = crtc->pipe;
  3677. u32 dpll, mdiv;
  3678. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  3679. bool is_hdmi;
  3680. u32 coreclk, reg_val, temp;
  3681. mutex_lock(&dev_priv->dpio_lock);
  3682. is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
  3683. bestn = crtc->config.dpll.n;
  3684. bestm1 = crtc->config.dpll.m1;
  3685. bestm2 = crtc->config.dpll.m2;
  3686. bestp1 = crtc->config.dpll.p1;
  3687. bestp2 = crtc->config.dpll.p2;
  3688. /* See eDP HDMI DPIO driver vbios notes doc */
  3689. /* PLL B needs special handling */
  3690. if (pipe)
  3691. vlv_pllb_recal_opamp(dev_priv);
  3692. /* Set up Tx target for periodic Rcomp update */
  3693. intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
  3694. /* Disable target IRef on PLL */
  3695. reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
  3696. reg_val &= 0x00ffffff;
  3697. intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
  3698. /* Disable fast lock */
  3699. intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
  3700. /* Set idtafcrecal before PLL is enabled */
  3701. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  3702. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  3703. mdiv |= ((bestn << DPIO_N_SHIFT));
  3704. mdiv |= (1 << DPIO_K_SHIFT);
  3705. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
  3706. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
  3707. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
  3708. mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
  3709. intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  3710. mdiv |= DPIO_ENABLE_CALIBRATION;
  3711. intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  3712. /* Set HBR and RBR LPF coefficients */
  3713. if (adjusted_mode->clock == 162000 ||
  3714. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
  3715. intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
  3716. 0x005f0021);
  3717. else
  3718. intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
  3719. 0x00d0000f);
  3720. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
  3721. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
  3722. /* Use SSC source */
  3723. if (!pipe)
  3724. intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  3725. 0x0df40000);
  3726. else
  3727. intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  3728. 0x0df70000);
  3729. } else { /* HDMI or VGA */
  3730. /* Use bend source */
  3731. if (!pipe)
  3732. intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  3733. 0x0df70000);
  3734. else
  3735. intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  3736. 0x0df40000);
  3737. }
  3738. coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
  3739. coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
  3740. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
  3741. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
  3742. coreclk |= 0x01000000;
  3743. intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
  3744. intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
  3745. for_each_encoder_on_crtc(dev, &crtc->base, encoder)
  3746. if (encoder->pre_pll_enable)
  3747. encoder->pre_pll_enable(encoder);
  3748. /* Enable DPIO clock input */
  3749. dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
  3750. DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
  3751. if (pipe)
  3752. dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  3753. dpll |= DPLL_VCO_ENABLE;
  3754. I915_WRITE(DPLL(pipe), dpll);
  3755. POSTING_READ(DPLL(pipe));
  3756. udelay(150);
  3757. if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  3758. DRM_ERROR("DPLL %d failed to lock\n", pipe);
  3759. if (is_hdmi) {
  3760. temp = 0;
  3761. if (crtc->config.pixel_multiplier > 1) {
  3762. temp = (crtc->config.pixel_multiplier - 1)
  3763. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3764. }
  3765. I915_WRITE(DPLL_MD(pipe), temp);
  3766. POSTING_READ(DPLL_MD(pipe));
  3767. }
  3768. if (crtc->config.has_dp_encoder)
  3769. intel_dp_set_m_n(crtc);
  3770. mutex_unlock(&dev_priv->dpio_lock);
  3771. }
  3772. static void i9xx_update_pll(struct intel_crtc *crtc,
  3773. intel_clock_t *reduced_clock,
  3774. int num_connectors)
  3775. {
  3776. struct drm_device *dev = crtc->base.dev;
  3777. struct drm_i915_private *dev_priv = dev->dev_private;
  3778. struct intel_encoder *encoder;
  3779. int pipe = crtc->pipe;
  3780. u32 dpll;
  3781. bool is_sdvo;
  3782. struct dpll *clock = &crtc->config.dpll;
  3783. i9xx_update_pll_dividers(crtc, reduced_clock);
  3784. is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
  3785. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
  3786. dpll = DPLL_VGA_MODE_DIS;
  3787. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
  3788. dpll |= DPLLB_MODE_LVDS;
  3789. else
  3790. dpll |= DPLLB_MODE_DAC_SERIAL;
  3791. if (is_sdvo) {
  3792. if ((crtc->config.pixel_multiplier > 1) &&
  3793. (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
  3794. dpll |= (crtc->config.pixel_multiplier - 1)
  3795. << SDVO_MULTIPLIER_SHIFT_HIRES;
  3796. }
  3797. dpll |= DPLL_DVO_HIGH_SPEED;
  3798. }
  3799. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
  3800. dpll |= DPLL_DVO_HIGH_SPEED;
  3801. /* compute bitmask from p1 value */
  3802. if (IS_PINEVIEW(dev))
  3803. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3804. else {
  3805. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3806. if (IS_G4X(dev) && reduced_clock)
  3807. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3808. }
  3809. switch (clock->p2) {
  3810. case 5:
  3811. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3812. break;
  3813. case 7:
  3814. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3815. break;
  3816. case 10:
  3817. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3818. break;
  3819. case 14:
  3820. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3821. break;
  3822. }
  3823. if (INTEL_INFO(dev)->gen >= 4)
  3824. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3825. if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
  3826. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3827. else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
  3828. /* XXX: just matching BIOS for now */
  3829. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3830. dpll |= 3;
  3831. else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3832. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3833. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3834. else
  3835. dpll |= PLL_REF_INPUT_DREFCLK;
  3836. dpll |= DPLL_VCO_ENABLE;
  3837. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3838. POSTING_READ(DPLL(pipe));
  3839. udelay(150);
  3840. for_each_encoder_on_crtc(dev, &crtc->base, encoder)
  3841. if (encoder->pre_pll_enable)
  3842. encoder->pre_pll_enable(encoder);
  3843. if (crtc->config.has_dp_encoder)
  3844. intel_dp_set_m_n(crtc);
  3845. I915_WRITE(DPLL(pipe), dpll);
  3846. /* Wait for the clocks to stabilize. */
  3847. POSTING_READ(DPLL(pipe));
  3848. udelay(150);
  3849. if (INTEL_INFO(dev)->gen >= 4) {
  3850. u32 temp = 0;
  3851. if (is_sdvo) {
  3852. temp = 0;
  3853. if (crtc->config.pixel_multiplier > 1) {
  3854. temp = (crtc->config.pixel_multiplier - 1)
  3855. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3856. }
  3857. }
  3858. I915_WRITE(DPLL_MD(pipe), temp);
  3859. } else {
  3860. /* The pixel multiplier can only be updated once the
  3861. * DPLL is enabled and the clocks are stable.
  3862. *
  3863. * So write it again.
  3864. */
  3865. I915_WRITE(DPLL(pipe), dpll);
  3866. }
  3867. }
  3868. static void i8xx_update_pll(struct intel_crtc *crtc,
  3869. struct drm_display_mode *adjusted_mode,
  3870. intel_clock_t *reduced_clock,
  3871. int num_connectors)
  3872. {
  3873. struct drm_device *dev = crtc->base.dev;
  3874. struct drm_i915_private *dev_priv = dev->dev_private;
  3875. struct intel_encoder *encoder;
  3876. int pipe = crtc->pipe;
  3877. u32 dpll;
  3878. struct dpll *clock = &crtc->config.dpll;
  3879. i9xx_update_pll_dividers(crtc, reduced_clock);
  3880. dpll = DPLL_VGA_MODE_DIS;
  3881. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
  3882. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3883. } else {
  3884. if (clock->p1 == 2)
  3885. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3886. else
  3887. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3888. if (clock->p2 == 4)
  3889. dpll |= PLL_P2_DIVIDE_BY_4;
  3890. }
  3891. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3892. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3893. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3894. else
  3895. dpll |= PLL_REF_INPUT_DREFCLK;
  3896. dpll |= DPLL_VCO_ENABLE;
  3897. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3898. POSTING_READ(DPLL(pipe));
  3899. udelay(150);
  3900. for_each_encoder_on_crtc(dev, &crtc->base, encoder)
  3901. if (encoder->pre_pll_enable)
  3902. encoder->pre_pll_enable(encoder);
  3903. I915_WRITE(DPLL(pipe), dpll);
  3904. /* Wait for the clocks to stabilize. */
  3905. POSTING_READ(DPLL(pipe));
  3906. udelay(150);
  3907. /* The pixel multiplier can only be updated once the
  3908. * DPLL is enabled and the clocks are stable.
  3909. *
  3910. * So write it again.
  3911. */
  3912. I915_WRITE(DPLL(pipe), dpll);
  3913. }
  3914. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
  3915. struct drm_display_mode *mode,
  3916. struct drm_display_mode *adjusted_mode)
  3917. {
  3918. struct drm_device *dev = intel_crtc->base.dev;
  3919. struct drm_i915_private *dev_priv = dev->dev_private;
  3920. enum pipe pipe = intel_crtc->pipe;
  3921. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3922. uint32_t vsyncshift;
  3923. if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3924. /* the chip adds 2 halflines automatically */
  3925. adjusted_mode->crtc_vtotal -= 1;
  3926. adjusted_mode->crtc_vblank_end -= 1;
  3927. vsyncshift = adjusted_mode->crtc_hsync_start
  3928. - adjusted_mode->crtc_htotal / 2;
  3929. } else {
  3930. vsyncshift = 0;
  3931. }
  3932. if (INTEL_INFO(dev)->gen > 3)
  3933. I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  3934. I915_WRITE(HTOTAL(cpu_transcoder),
  3935. (adjusted_mode->crtc_hdisplay - 1) |
  3936. ((adjusted_mode->crtc_htotal - 1) << 16));
  3937. I915_WRITE(HBLANK(cpu_transcoder),
  3938. (adjusted_mode->crtc_hblank_start - 1) |
  3939. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3940. I915_WRITE(HSYNC(cpu_transcoder),
  3941. (adjusted_mode->crtc_hsync_start - 1) |
  3942. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3943. I915_WRITE(VTOTAL(cpu_transcoder),
  3944. (adjusted_mode->crtc_vdisplay - 1) |
  3945. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3946. I915_WRITE(VBLANK(cpu_transcoder),
  3947. (adjusted_mode->crtc_vblank_start - 1) |
  3948. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3949. I915_WRITE(VSYNC(cpu_transcoder),
  3950. (adjusted_mode->crtc_vsync_start - 1) |
  3951. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3952. /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  3953. * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  3954. * documented on the DDI_FUNC_CTL register description, EDP Input Select
  3955. * bits. */
  3956. if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  3957. (pipe == PIPE_B || pipe == PIPE_C))
  3958. I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  3959. /* pipesrc controls the size that is scaled from, which should
  3960. * always be the user's requested size.
  3961. */
  3962. I915_WRITE(PIPESRC(pipe),
  3963. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3964. }
  3965. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
  3966. {
  3967. struct drm_device *dev = intel_crtc->base.dev;
  3968. struct drm_i915_private *dev_priv = dev->dev_private;
  3969. uint32_t pipeconf;
  3970. pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
  3971. if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  3972. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3973. * core speed.
  3974. *
  3975. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3976. * pipe == 0 check?
  3977. */
  3978. if (intel_crtc->config.requested_mode.clock >
  3979. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3980. pipeconf |= PIPECONF_DOUBLE_WIDE;
  3981. else
  3982. pipeconf &= ~PIPECONF_DOUBLE_WIDE;
  3983. }
  3984. /* default to 8bpc */
  3985. pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
  3986. if (intel_crtc->config.has_dp_encoder) {
  3987. if (intel_crtc->config.dither) {
  3988. pipeconf |= PIPECONF_6BPC |
  3989. PIPECONF_DITHER_EN |
  3990. PIPECONF_DITHER_TYPE_SP;
  3991. }
  3992. }
  3993. if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
  3994. INTEL_OUTPUT_EDP)) {
  3995. if (intel_crtc->config.dither) {
  3996. pipeconf |= PIPECONF_6BPC |
  3997. PIPECONF_ENABLE |
  3998. I965_PIPECONF_ACTIVE;
  3999. }
  4000. }
  4001. if (HAS_PIPE_CXSR(dev)) {
  4002. if (intel_crtc->lowfreq_avail) {
  4003. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4004. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4005. } else {
  4006. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4007. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  4008. }
  4009. }
  4010. pipeconf &= ~PIPECONF_INTERLACE_MASK;
  4011. if (!IS_GEN2(dev) &&
  4012. intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4013. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4014. else
  4015. pipeconf |= PIPECONF_PROGRESSIVE;
  4016. if (IS_VALLEYVIEW(dev)) {
  4017. if (intel_crtc->config.limited_color_range)
  4018. pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  4019. else
  4020. pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
  4021. }
  4022. I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
  4023. POSTING_READ(PIPECONF(intel_crtc->pipe));
  4024. }
  4025. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  4026. int x, int y,
  4027. struct drm_framebuffer *fb)
  4028. {
  4029. struct drm_device *dev = crtc->dev;
  4030. struct drm_i915_private *dev_priv = dev->dev_private;
  4031. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4032. struct drm_display_mode *adjusted_mode =
  4033. &intel_crtc->config.adjusted_mode;
  4034. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  4035. int pipe = intel_crtc->pipe;
  4036. int plane = intel_crtc->plane;
  4037. int refclk, num_connectors = 0;
  4038. intel_clock_t clock, reduced_clock;
  4039. u32 dspcntr;
  4040. bool ok, has_reduced_clock = false, is_sdvo = false;
  4041. bool is_lvds = false, is_tv = false;
  4042. struct intel_encoder *encoder;
  4043. const intel_limit_t *limit;
  4044. int ret;
  4045. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4046. switch (encoder->type) {
  4047. case INTEL_OUTPUT_LVDS:
  4048. is_lvds = true;
  4049. break;
  4050. case INTEL_OUTPUT_SDVO:
  4051. case INTEL_OUTPUT_HDMI:
  4052. is_sdvo = true;
  4053. if (encoder->needs_tv_clock)
  4054. is_tv = true;
  4055. break;
  4056. case INTEL_OUTPUT_TVOUT:
  4057. is_tv = true;
  4058. break;
  4059. }
  4060. num_connectors++;
  4061. }
  4062. refclk = i9xx_get_refclk(crtc, num_connectors);
  4063. /*
  4064. * Returns a set of divisors for the desired target clock with the given
  4065. * refclk, or FALSE. The returned values represent the clock equation:
  4066. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4067. */
  4068. limit = intel_limit(crtc, refclk);
  4069. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  4070. &clock);
  4071. if (!ok) {
  4072. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4073. return -EINVAL;
  4074. }
  4075. /* Ensure that the cursor is valid for the new mode before changing... */
  4076. intel_crtc_update_cursor(crtc, true);
  4077. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4078. /*
  4079. * Ensure we match the reduced clock's P to the target clock.
  4080. * If the clocks don't match, we can't switch the display clock
  4081. * by using the FP0/FP1. In such case we will disable the LVDS
  4082. * downclock feature.
  4083. */
  4084. has_reduced_clock = limit->find_pll(limit, crtc,
  4085. dev_priv->lvds_downclock,
  4086. refclk,
  4087. &clock,
  4088. &reduced_clock);
  4089. }
  4090. /* Compat-code for transition, will disappear. */
  4091. if (!intel_crtc->config.clock_set) {
  4092. intel_crtc->config.dpll.n = clock.n;
  4093. intel_crtc->config.dpll.m1 = clock.m1;
  4094. intel_crtc->config.dpll.m2 = clock.m2;
  4095. intel_crtc->config.dpll.p1 = clock.p1;
  4096. intel_crtc->config.dpll.p2 = clock.p2;
  4097. }
  4098. if (is_sdvo && is_tv)
  4099. i9xx_adjust_sdvo_tv_clock(intel_crtc);
  4100. if (IS_GEN2(dev))
  4101. i8xx_update_pll(intel_crtc, adjusted_mode,
  4102. has_reduced_clock ? &reduced_clock : NULL,
  4103. num_connectors);
  4104. else if (IS_VALLEYVIEW(dev))
  4105. vlv_update_pll(intel_crtc);
  4106. else
  4107. i9xx_update_pll(intel_crtc,
  4108. has_reduced_clock ? &reduced_clock : NULL,
  4109. num_connectors);
  4110. /* Set up the display plane register */
  4111. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4112. if (!IS_VALLEYVIEW(dev)) {
  4113. if (pipe == 0)
  4114. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  4115. else
  4116. dspcntr |= DISPPLANE_SEL_PIPE_B;
  4117. }
  4118. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
  4119. drm_mode_debug_printmodeline(mode);
  4120. intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
  4121. /* pipesrc and dspsize control the size that is scaled from,
  4122. * which should always be the user's requested size.
  4123. */
  4124. I915_WRITE(DSPSIZE(plane),
  4125. ((mode->vdisplay - 1) << 16) |
  4126. (mode->hdisplay - 1));
  4127. I915_WRITE(DSPPOS(plane), 0);
  4128. i9xx_set_pipeconf(intel_crtc);
  4129. I915_WRITE(DSPCNTR(plane), dspcntr);
  4130. POSTING_READ(DSPCNTR(plane));
  4131. ret = intel_pipe_set_base(crtc, x, y, fb);
  4132. intel_update_watermarks(dev);
  4133. return ret;
  4134. }
  4135. static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
  4136. struct intel_crtc_config *pipe_config)
  4137. {
  4138. struct drm_device *dev = crtc->base.dev;
  4139. struct drm_i915_private *dev_priv = dev->dev_private;
  4140. uint32_t tmp;
  4141. tmp = I915_READ(PIPECONF(crtc->pipe));
  4142. if (!(tmp & PIPECONF_ENABLE))
  4143. return false;
  4144. return true;
  4145. }
  4146. static void ironlake_init_pch_refclk(struct drm_device *dev)
  4147. {
  4148. struct drm_i915_private *dev_priv = dev->dev_private;
  4149. struct drm_mode_config *mode_config = &dev->mode_config;
  4150. struct intel_encoder *encoder;
  4151. u32 val, final;
  4152. bool has_lvds = false;
  4153. bool has_cpu_edp = false;
  4154. bool has_pch_edp = false;
  4155. bool has_panel = false;
  4156. bool has_ck505 = false;
  4157. bool can_ssc = false;
  4158. /* We need to take the global config into account */
  4159. list_for_each_entry(encoder, &mode_config->encoder_list,
  4160. base.head) {
  4161. switch (encoder->type) {
  4162. case INTEL_OUTPUT_LVDS:
  4163. has_panel = true;
  4164. has_lvds = true;
  4165. break;
  4166. case INTEL_OUTPUT_EDP:
  4167. has_panel = true;
  4168. if (intel_encoder_is_pch_edp(&encoder->base))
  4169. has_pch_edp = true;
  4170. else
  4171. has_cpu_edp = true;
  4172. break;
  4173. }
  4174. }
  4175. if (HAS_PCH_IBX(dev)) {
  4176. has_ck505 = dev_priv->display_clock_mode;
  4177. can_ssc = has_ck505;
  4178. } else {
  4179. has_ck505 = false;
  4180. can_ssc = true;
  4181. }
  4182. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
  4183. has_panel, has_lvds, has_pch_edp, has_cpu_edp,
  4184. has_ck505);
  4185. /* Ironlake: try to setup display ref clock before DPLL
  4186. * enabling. This is only under driver's control after
  4187. * PCH B stepping, previous chipset stepping should be
  4188. * ignoring this setting.
  4189. */
  4190. val = I915_READ(PCH_DREF_CONTROL);
  4191. /* As we must carefully and slowly disable/enable each source in turn,
  4192. * compute the final state we want first and check if we need to
  4193. * make any changes at all.
  4194. */
  4195. final = val;
  4196. final &= ~DREF_NONSPREAD_SOURCE_MASK;
  4197. if (has_ck505)
  4198. final |= DREF_NONSPREAD_CK505_ENABLE;
  4199. else
  4200. final |= DREF_NONSPREAD_SOURCE_ENABLE;
  4201. final &= ~DREF_SSC_SOURCE_MASK;
  4202. final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4203. final &= ~DREF_SSC1_ENABLE;
  4204. if (has_panel) {
  4205. final |= DREF_SSC_SOURCE_ENABLE;
  4206. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4207. final |= DREF_SSC1_ENABLE;
  4208. if (has_cpu_edp) {
  4209. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4210. final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4211. else
  4212. final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4213. } else
  4214. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4215. } else {
  4216. final |= DREF_SSC_SOURCE_DISABLE;
  4217. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4218. }
  4219. if (final == val)
  4220. return;
  4221. /* Always enable nonspread source */
  4222. val &= ~DREF_NONSPREAD_SOURCE_MASK;
  4223. if (has_ck505)
  4224. val |= DREF_NONSPREAD_CK505_ENABLE;
  4225. else
  4226. val |= DREF_NONSPREAD_SOURCE_ENABLE;
  4227. if (has_panel) {
  4228. val &= ~DREF_SSC_SOURCE_MASK;
  4229. val |= DREF_SSC_SOURCE_ENABLE;
  4230. /* SSC must be turned on before enabling the CPU output */
  4231. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4232. DRM_DEBUG_KMS("Using SSC on panel\n");
  4233. val |= DREF_SSC1_ENABLE;
  4234. } else
  4235. val &= ~DREF_SSC1_ENABLE;
  4236. /* Get SSC going before enabling the outputs */
  4237. I915_WRITE(PCH_DREF_CONTROL, val);
  4238. POSTING_READ(PCH_DREF_CONTROL);
  4239. udelay(200);
  4240. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4241. /* Enable CPU source on CPU attached eDP */
  4242. if (has_cpu_edp) {
  4243. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4244. DRM_DEBUG_KMS("Using SSC on eDP\n");
  4245. val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4246. }
  4247. else
  4248. val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4249. } else
  4250. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4251. I915_WRITE(PCH_DREF_CONTROL, val);
  4252. POSTING_READ(PCH_DREF_CONTROL);
  4253. udelay(200);
  4254. } else {
  4255. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  4256. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4257. /* Turn off CPU output */
  4258. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4259. I915_WRITE(PCH_DREF_CONTROL, val);
  4260. POSTING_READ(PCH_DREF_CONTROL);
  4261. udelay(200);
  4262. /* Turn off the SSC source */
  4263. val &= ~DREF_SSC_SOURCE_MASK;
  4264. val |= DREF_SSC_SOURCE_DISABLE;
  4265. /* Turn off SSC1 */
  4266. val &= ~DREF_SSC1_ENABLE;
  4267. I915_WRITE(PCH_DREF_CONTROL, val);
  4268. POSTING_READ(PCH_DREF_CONTROL);
  4269. udelay(200);
  4270. }
  4271. BUG_ON(val != final);
  4272. }
  4273. /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
  4274. static void lpt_init_pch_refclk(struct drm_device *dev)
  4275. {
  4276. struct drm_i915_private *dev_priv = dev->dev_private;
  4277. struct drm_mode_config *mode_config = &dev->mode_config;
  4278. struct intel_encoder *encoder;
  4279. bool has_vga = false;
  4280. bool is_sdv = false;
  4281. u32 tmp;
  4282. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4283. switch (encoder->type) {
  4284. case INTEL_OUTPUT_ANALOG:
  4285. has_vga = true;
  4286. break;
  4287. }
  4288. }
  4289. if (!has_vga)
  4290. return;
  4291. mutex_lock(&dev_priv->dpio_lock);
  4292. /* XXX: Rip out SDV support once Haswell ships for real. */
  4293. if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
  4294. is_sdv = true;
  4295. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4296. tmp &= ~SBI_SSCCTL_DISABLE;
  4297. tmp |= SBI_SSCCTL_PATHALT;
  4298. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4299. udelay(24);
  4300. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4301. tmp &= ~SBI_SSCCTL_PATHALT;
  4302. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4303. if (!is_sdv) {
  4304. tmp = I915_READ(SOUTH_CHICKEN2);
  4305. tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  4306. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4307. if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  4308. FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  4309. DRM_ERROR("FDI mPHY reset assert timeout\n");
  4310. tmp = I915_READ(SOUTH_CHICKEN2);
  4311. tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  4312. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4313. if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  4314. FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
  4315. 100))
  4316. DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  4317. }
  4318. tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  4319. tmp &= ~(0xFF << 24);
  4320. tmp |= (0x12 << 24);
  4321. intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  4322. if (is_sdv) {
  4323. tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
  4324. tmp |= 0x7FFF;
  4325. intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
  4326. }
  4327. tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  4328. tmp |= (1 << 11);
  4329. intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  4330. tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  4331. tmp |= (1 << 11);
  4332. intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  4333. if (is_sdv) {
  4334. tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
  4335. tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
  4336. intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
  4337. tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
  4338. tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
  4339. intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
  4340. tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
  4341. tmp |= (0x3F << 8);
  4342. intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
  4343. tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
  4344. tmp |= (0x3F << 8);
  4345. intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
  4346. }
  4347. tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  4348. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4349. intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  4350. tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  4351. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4352. intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  4353. if (!is_sdv) {
  4354. tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  4355. tmp &= ~(7 << 13);
  4356. tmp |= (5 << 13);
  4357. intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  4358. tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  4359. tmp &= ~(7 << 13);
  4360. tmp |= (5 << 13);
  4361. intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  4362. }
  4363. tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  4364. tmp &= ~0xFF;
  4365. tmp |= 0x1C;
  4366. intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  4367. tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  4368. tmp &= ~0xFF;
  4369. tmp |= 0x1C;
  4370. intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  4371. tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  4372. tmp &= ~(0xFF << 16);
  4373. tmp |= (0x1C << 16);
  4374. intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  4375. tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  4376. tmp &= ~(0xFF << 16);
  4377. tmp |= (0x1C << 16);
  4378. intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  4379. if (!is_sdv) {
  4380. tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  4381. tmp |= (1 << 27);
  4382. intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  4383. tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  4384. tmp |= (1 << 27);
  4385. intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  4386. tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  4387. tmp &= ~(0xF << 28);
  4388. tmp |= (4 << 28);
  4389. intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  4390. tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  4391. tmp &= ~(0xF << 28);
  4392. tmp |= (4 << 28);
  4393. intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  4394. }
  4395. /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
  4396. tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
  4397. tmp |= SBI_DBUFF0_ENABLE;
  4398. intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
  4399. mutex_unlock(&dev_priv->dpio_lock);
  4400. }
  4401. /*
  4402. * Initialize reference clocks when the driver loads
  4403. */
  4404. void intel_init_pch_refclk(struct drm_device *dev)
  4405. {
  4406. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  4407. ironlake_init_pch_refclk(dev);
  4408. else if (HAS_PCH_LPT(dev))
  4409. lpt_init_pch_refclk(dev);
  4410. }
  4411. static int ironlake_get_refclk(struct drm_crtc *crtc)
  4412. {
  4413. struct drm_device *dev = crtc->dev;
  4414. struct drm_i915_private *dev_priv = dev->dev_private;
  4415. struct intel_encoder *encoder;
  4416. struct intel_encoder *edp_encoder = NULL;
  4417. int num_connectors = 0;
  4418. bool is_lvds = false;
  4419. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4420. switch (encoder->type) {
  4421. case INTEL_OUTPUT_LVDS:
  4422. is_lvds = true;
  4423. break;
  4424. case INTEL_OUTPUT_EDP:
  4425. edp_encoder = encoder;
  4426. break;
  4427. }
  4428. num_connectors++;
  4429. }
  4430. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4431. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4432. dev_priv->lvds_ssc_freq);
  4433. return dev_priv->lvds_ssc_freq * 1000;
  4434. }
  4435. return 120000;
  4436. }
  4437. static void ironlake_set_pipeconf(struct drm_crtc *crtc,
  4438. struct drm_display_mode *adjusted_mode,
  4439. bool dither)
  4440. {
  4441. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4442. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4443. int pipe = intel_crtc->pipe;
  4444. uint32_t val;
  4445. val = I915_READ(PIPECONF(pipe));
  4446. val &= ~PIPECONF_BPC_MASK;
  4447. switch (intel_crtc->config.pipe_bpp) {
  4448. case 18:
  4449. val |= PIPECONF_6BPC;
  4450. break;
  4451. case 24:
  4452. val |= PIPECONF_8BPC;
  4453. break;
  4454. case 30:
  4455. val |= PIPECONF_10BPC;
  4456. break;
  4457. case 36:
  4458. val |= PIPECONF_12BPC;
  4459. break;
  4460. default:
  4461. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4462. BUG();
  4463. }
  4464. val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
  4465. if (dither)
  4466. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4467. val &= ~PIPECONF_INTERLACE_MASK;
  4468. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  4469. val |= PIPECONF_INTERLACED_ILK;
  4470. else
  4471. val |= PIPECONF_PROGRESSIVE;
  4472. if (intel_crtc->config.limited_color_range)
  4473. val |= PIPECONF_COLOR_RANGE_SELECT;
  4474. else
  4475. val &= ~PIPECONF_COLOR_RANGE_SELECT;
  4476. I915_WRITE(PIPECONF(pipe), val);
  4477. POSTING_READ(PIPECONF(pipe));
  4478. }
  4479. /*
  4480. * Set up the pipe CSC unit.
  4481. *
  4482. * Currently only full range RGB to limited range RGB conversion
  4483. * is supported, but eventually this should handle various
  4484. * RGB<->YCbCr scenarios as well.
  4485. */
  4486. static void intel_set_pipe_csc(struct drm_crtc *crtc)
  4487. {
  4488. struct drm_device *dev = crtc->dev;
  4489. struct drm_i915_private *dev_priv = dev->dev_private;
  4490. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4491. int pipe = intel_crtc->pipe;
  4492. uint16_t coeff = 0x7800; /* 1.0 */
  4493. /*
  4494. * TODO: Check what kind of values actually come out of the pipe
  4495. * with these coeff/postoff values and adjust to get the best
  4496. * accuracy. Perhaps we even need to take the bpc value into
  4497. * consideration.
  4498. */
  4499. if (intel_crtc->config.limited_color_range)
  4500. coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
  4501. /*
  4502. * GY/GU and RY/RU should be the other way around according
  4503. * to BSpec, but reality doesn't agree. Just set them up in
  4504. * a way that results in the correct picture.
  4505. */
  4506. I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
  4507. I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
  4508. I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
  4509. I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
  4510. I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
  4511. I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
  4512. I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
  4513. I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
  4514. I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
  4515. if (INTEL_INFO(dev)->gen > 6) {
  4516. uint16_t postoff = 0;
  4517. if (intel_crtc->config.limited_color_range)
  4518. postoff = (16 * (1 << 13) / 255) & 0x1fff;
  4519. I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
  4520. I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
  4521. I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
  4522. I915_WRITE(PIPE_CSC_MODE(pipe), 0);
  4523. } else {
  4524. uint32_t mode = CSC_MODE_YUV_TO_RGB;
  4525. if (intel_crtc->config.limited_color_range)
  4526. mode |= CSC_BLACK_SCREEN_OFFSET;
  4527. I915_WRITE(PIPE_CSC_MODE(pipe), mode);
  4528. }
  4529. }
  4530. static void haswell_set_pipeconf(struct drm_crtc *crtc,
  4531. struct drm_display_mode *adjusted_mode,
  4532. bool dither)
  4533. {
  4534. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4535. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4536. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  4537. uint32_t val;
  4538. val = I915_READ(PIPECONF(cpu_transcoder));
  4539. val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
  4540. if (dither)
  4541. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4542. val &= ~PIPECONF_INTERLACE_MASK_HSW;
  4543. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  4544. val |= PIPECONF_INTERLACED_ILK;
  4545. else
  4546. val |= PIPECONF_PROGRESSIVE;
  4547. I915_WRITE(PIPECONF(cpu_transcoder), val);
  4548. POSTING_READ(PIPECONF(cpu_transcoder));
  4549. }
  4550. static bool ironlake_compute_clocks(struct drm_crtc *crtc,
  4551. struct drm_display_mode *adjusted_mode,
  4552. intel_clock_t *clock,
  4553. bool *has_reduced_clock,
  4554. intel_clock_t *reduced_clock)
  4555. {
  4556. struct drm_device *dev = crtc->dev;
  4557. struct drm_i915_private *dev_priv = dev->dev_private;
  4558. struct intel_encoder *intel_encoder;
  4559. int refclk;
  4560. const intel_limit_t *limit;
  4561. bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
  4562. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4563. switch (intel_encoder->type) {
  4564. case INTEL_OUTPUT_LVDS:
  4565. is_lvds = true;
  4566. break;
  4567. case INTEL_OUTPUT_SDVO:
  4568. case INTEL_OUTPUT_HDMI:
  4569. is_sdvo = true;
  4570. if (intel_encoder->needs_tv_clock)
  4571. is_tv = true;
  4572. break;
  4573. case INTEL_OUTPUT_TVOUT:
  4574. is_tv = true;
  4575. break;
  4576. }
  4577. }
  4578. refclk = ironlake_get_refclk(crtc);
  4579. /*
  4580. * Returns a set of divisors for the desired target clock with the given
  4581. * refclk, or FALSE. The returned values represent the clock equation:
  4582. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4583. */
  4584. limit = intel_limit(crtc, refclk);
  4585. ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  4586. clock);
  4587. if (!ret)
  4588. return false;
  4589. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4590. /*
  4591. * Ensure we match the reduced clock's P to the target clock.
  4592. * If the clocks don't match, we can't switch the display clock
  4593. * by using the FP0/FP1. In such case we will disable the LVDS
  4594. * downclock feature.
  4595. */
  4596. *has_reduced_clock = limit->find_pll(limit, crtc,
  4597. dev_priv->lvds_downclock,
  4598. refclk,
  4599. clock,
  4600. reduced_clock);
  4601. }
  4602. if (is_sdvo && is_tv)
  4603. i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
  4604. return true;
  4605. }
  4606. static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
  4607. {
  4608. struct drm_i915_private *dev_priv = dev->dev_private;
  4609. uint32_t temp;
  4610. temp = I915_READ(SOUTH_CHICKEN1);
  4611. if (temp & FDI_BC_BIFURCATION_SELECT)
  4612. return;
  4613. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  4614. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  4615. temp |= FDI_BC_BIFURCATION_SELECT;
  4616. DRM_DEBUG_KMS("enabling fdi C rx\n");
  4617. I915_WRITE(SOUTH_CHICKEN1, temp);
  4618. POSTING_READ(SOUTH_CHICKEN1);
  4619. }
  4620. static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
  4621. {
  4622. struct drm_device *dev = intel_crtc->base.dev;
  4623. struct drm_i915_private *dev_priv = dev->dev_private;
  4624. struct intel_crtc *pipe_B_crtc =
  4625. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  4626. DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
  4627. pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
  4628. if (intel_crtc->fdi_lanes > 4) {
  4629. DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
  4630. pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
  4631. /* Clamp lanes to avoid programming the hw with bogus values. */
  4632. intel_crtc->fdi_lanes = 4;
  4633. return false;
  4634. }
  4635. if (INTEL_INFO(dev)->num_pipes == 2)
  4636. return true;
  4637. switch (intel_crtc->pipe) {
  4638. case PIPE_A:
  4639. return true;
  4640. case PIPE_B:
  4641. if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
  4642. intel_crtc->fdi_lanes > 2) {
  4643. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  4644. pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
  4645. /* Clamp lanes to avoid programming the hw with bogus values. */
  4646. intel_crtc->fdi_lanes = 2;
  4647. return false;
  4648. }
  4649. if (intel_crtc->fdi_lanes > 2)
  4650. WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
  4651. else
  4652. cpt_enable_fdi_bc_bifurcation(dev);
  4653. return true;
  4654. case PIPE_C:
  4655. if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
  4656. if (intel_crtc->fdi_lanes > 2) {
  4657. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  4658. pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
  4659. /* Clamp lanes to avoid programming the hw with bogus values. */
  4660. intel_crtc->fdi_lanes = 2;
  4661. return false;
  4662. }
  4663. } else {
  4664. DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  4665. return false;
  4666. }
  4667. cpt_enable_fdi_bc_bifurcation(dev);
  4668. return true;
  4669. default:
  4670. BUG();
  4671. }
  4672. }
  4673. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  4674. {
  4675. /*
  4676. * Account for spread spectrum to avoid
  4677. * oversubscribing the link. Max center spread
  4678. * is 2.5%; use 5% for safety's sake.
  4679. */
  4680. u32 bps = target_clock * bpp * 21 / 20;
  4681. return bps / (link_bw * 8) + 1;
  4682. }
  4683. void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  4684. struct intel_link_m_n *m_n)
  4685. {
  4686. struct drm_device *dev = crtc->base.dev;
  4687. struct drm_i915_private *dev_priv = dev->dev_private;
  4688. int pipe = crtc->pipe;
  4689. I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  4690. I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
  4691. I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
  4692. I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
  4693. }
  4694. void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  4695. struct intel_link_m_n *m_n)
  4696. {
  4697. struct drm_device *dev = crtc->base.dev;
  4698. struct drm_i915_private *dev_priv = dev->dev_private;
  4699. int pipe = crtc->pipe;
  4700. enum transcoder transcoder = crtc->config.cpu_transcoder;
  4701. if (INTEL_INFO(dev)->gen >= 5) {
  4702. I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
  4703. I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
  4704. I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
  4705. I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
  4706. } else {
  4707. I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  4708. I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
  4709. I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
  4710. I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
  4711. }
  4712. }
  4713. static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
  4714. {
  4715. struct drm_device *dev = crtc->dev;
  4716. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4717. struct drm_display_mode *adjusted_mode =
  4718. &intel_crtc->config.adjusted_mode;
  4719. struct intel_link_m_n m_n = {0};
  4720. int target_clock, lane, link_bw;
  4721. /* FDI is a binary signal running at ~2.7GHz, encoding
  4722. * each output octet as 10 bits. The actual frequency
  4723. * is stored as a divider into a 100MHz clock, and the
  4724. * mode pixel clock is stored in units of 1KHz.
  4725. * Hence the bw of each lane in terms of the mode signal
  4726. * is:
  4727. */
  4728. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  4729. if (intel_crtc->config.pixel_target_clock)
  4730. target_clock = intel_crtc->config.pixel_target_clock;
  4731. else
  4732. target_clock = adjusted_mode->clock;
  4733. lane = ironlake_get_lanes_required(target_clock, link_bw,
  4734. intel_crtc->config.pipe_bpp);
  4735. intel_crtc->fdi_lanes = lane;
  4736. if (intel_crtc->config.pixel_multiplier > 1)
  4737. link_bw *= intel_crtc->config.pixel_multiplier;
  4738. intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
  4739. link_bw, &m_n);
  4740. intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
  4741. }
  4742. static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  4743. intel_clock_t *clock, u32 *fp,
  4744. intel_clock_t *reduced_clock, u32 *fp2)
  4745. {
  4746. struct drm_crtc *crtc = &intel_crtc->base;
  4747. struct drm_device *dev = crtc->dev;
  4748. struct drm_i915_private *dev_priv = dev->dev_private;
  4749. struct intel_encoder *intel_encoder;
  4750. uint32_t dpll;
  4751. int factor, num_connectors = 0;
  4752. bool is_lvds = false, is_sdvo = false, is_tv = false;
  4753. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4754. switch (intel_encoder->type) {
  4755. case INTEL_OUTPUT_LVDS:
  4756. is_lvds = true;
  4757. break;
  4758. case INTEL_OUTPUT_SDVO:
  4759. case INTEL_OUTPUT_HDMI:
  4760. is_sdvo = true;
  4761. if (intel_encoder->needs_tv_clock)
  4762. is_tv = true;
  4763. break;
  4764. case INTEL_OUTPUT_TVOUT:
  4765. is_tv = true;
  4766. break;
  4767. }
  4768. num_connectors++;
  4769. }
  4770. /* Enable autotuning of the PLL clock (if permissible) */
  4771. factor = 21;
  4772. if (is_lvds) {
  4773. if ((intel_panel_use_ssc(dev_priv) &&
  4774. dev_priv->lvds_ssc_freq == 100) ||
  4775. (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
  4776. factor = 25;
  4777. } else if (is_sdvo && is_tv)
  4778. factor = 20;
  4779. if (clock->m < factor * clock->n)
  4780. *fp |= FP_CB_TUNE;
  4781. if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
  4782. *fp2 |= FP_CB_TUNE;
  4783. dpll = 0;
  4784. if (is_lvds)
  4785. dpll |= DPLLB_MODE_LVDS;
  4786. else
  4787. dpll |= DPLLB_MODE_DAC_SERIAL;
  4788. if (is_sdvo) {
  4789. if (intel_crtc->config.pixel_multiplier > 1) {
  4790. dpll |= (intel_crtc->config.pixel_multiplier - 1)
  4791. << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4792. }
  4793. dpll |= DPLL_DVO_HIGH_SPEED;
  4794. }
  4795. if (intel_crtc->config.has_dp_encoder &&
  4796. intel_crtc->config.has_pch_encoder)
  4797. dpll |= DPLL_DVO_HIGH_SPEED;
  4798. /* compute bitmask from p1 value */
  4799. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4800. /* also FPA1 */
  4801. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4802. switch (clock->p2) {
  4803. case 5:
  4804. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4805. break;
  4806. case 7:
  4807. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4808. break;
  4809. case 10:
  4810. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4811. break;
  4812. case 14:
  4813. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4814. break;
  4815. }
  4816. if (is_sdvo && is_tv)
  4817. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4818. else if (is_tv)
  4819. /* XXX: just matching BIOS for now */
  4820. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  4821. dpll |= 3;
  4822. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4823. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4824. else
  4825. dpll |= PLL_REF_INPUT_DREFCLK;
  4826. return dpll;
  4827. }
  4828. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4829. int x, int y,
  4830. struct drm_framebuffer *fb)
  4831. {
  4832. struct drm_device *dev = crtc->dev;
  4833. struct drm_i915_private *dev_priv = dev->dev_private;
  4834. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4835. struct drm_display_mode *adjusted_mode =
  4836. &intel_crtc->config.adjusted_mode;
  4837. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  4838. int pipe = intel_crtc->pipe;
  4839. int plane = intel_crtc->plane;
  4840. int num_connectors = 0;
  4841. intel_clock_t clock, reduced_clock;
  4842. u32 dpll, fp = 0, fp2 = 0;
  4843. bool ok, has_reduced_clock = false;
  4844. bool is_lvds = false;
  4845. struct intel_encoder *encoder;
  4846. int ret;
  4847. bool dither, fdi_config_ok;
  4848. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4849. switch (encoder->type) {
  4850. case INTEL_OUTPUT_LVDS:
  4851. is_lvds = true;
  4852. break;
  4853. }
  4854. num_connectors++;
  4855. }
  4856. WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
  4857. "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
  4858. intel_crtc->config.cpu_transcoder = pipe;
  4859. ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
  4860. &has_reduced_clock, &reduced_clock);
  4861. if (!ok) {
  4862. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4863. return -EINVAL;
  4864. }
  4865. /* Compat-code for transition, will disappear. */
  4866. if (!intel_crtc->config.clock_set) {
  4867. intel_crtc->config.dpll.n = clock.n;
  4868. intel_crtc->config.dpll.m1 = clock.m1;
  4869. intel_crtc->config.dpll.m2 = clock.m2;
  4870. intel_crtc->config.dpll.p1 = clock.p1;
  4871. intel_crtc->config.dpll.p2 = clock.p2;
  4872. }
  4873. /* Ensure that the cursor is valid for the new mode before changing... */
  4874. intel_crtc_update_cursor(crtc, true);
  4875. /* determine panel color depth */
  4876. dither = intel_crtc->config.dither;
  4877. if (is_lvds && dev_priv->lvds_dither)
  4878. dither = true;
  4879. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  4880. if (has_reduced_clock)
  4881. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  4882. reduced_clock.m2;
  4883. dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
  4884. has_reduced_clock ? &fp2 : NULL);
  4885. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
  4886. drm_mode_debug_printmodeline(mode);
  4887. /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  4888. if (intel_crtc->config.has_pch_encoder) {
  4889. struct intel_pch_pll *pll;
  4890. pll = intel_get_pch_pll(intel_crtc, dpll, fp);
  4891. if (pll == NULL) {
  4892. DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
  4893. pipe_name(pipe));
  4894. return -EINVAL;
  4895. }
  4896. } else
  4897. intel_put_pch_pll(intel_crtc);
  4898. if (intel_crtc->config.has_dp_encoder)
  4899. intel_dp_set_m_n(intel_crtc);
  4900. for_each_encoder_on_crtc(dev, crtc, encoder)
  4901. if (encoder->pre_pll_enable)
  4902. encoder->pre_pll_enable(encoder);
  4903. if (intel_crtc->pch_pll) {
  4904. I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
  4905. /* Wait for the clocks to stabilize. */
  4906. POSTING_READ(intel_crtc->pch_pll->pll_reg);
  4907. udelay(150);
  4908. /* The pixel multiplier can only be updated once the
  4909. * DPLL is enabled and the clocks are stable.
  4910. *
  4911. * So write it again.
  4912. */
  4913. I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
  4914. }
  4915. intel_crtc->lowfreq_avail = false;
  4916. if (intel_crtc->pch_pll) {
  4917. if (is_lvds && has_reduced_clock && i915_powersave) {
  4918. I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
  4919. intel_crtc->lowfreq_avail = true;
  4920. } else {
  4921. I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
  4922. }
  4923. }
  4924. intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
  4925. /* Note, this also computes intel_crtc->fdi_lanes which is used below in
  4926. * ironlake_check_fdi_lanes. */
  4927. intel_crtc->fdi_lanes = 0;
  4928. if (intel_crtc->config.has_pch_encoder)
  4929. ironlake_fdi_set_m_n(crtc);
  4930. fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
  4931. ironlake_set_pipeconf(crtc, adjusted_mode, dither);
  4932. /* Set up the display plane register */
  4933. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
  4934. POSTING_READ(DSPCNTR(plane));
  4935. ret = intel_pipe_set_base(crtc, x, y, fb);
  4936. intel_update_watermarks(dev);
  4937. intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
  4938. return fdi_config_ok ? ret : -EINVAL;
  4939. }
  4940. static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
  4941. struct intel_crtc_config *pipe_config)
  4942. {
  4943. struct drm_device *dev = crtc->base.dev;
  4944. struct drm_i915_private *dev_priv = dev->dev_private;
  4945. uint32_t tmp;
  4946. tmp = I915_READ(PIPECONF(crtc->pipe));
  4947. if (!(tmp & PIPECONF_ENABLE))
  4948. return false;
  4949. if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
  4950. pipe_config->has_pch_encoder = true;
  4951. return true;
  4952. }
  4953. static void haswell_modeset_global_resources(struct drm_device *dev)
  4954. {
  4955. struct drm_i915_private *dev_priv = dev->dev_private;
  4956. bool enable = false;
  4957. struct intel_crtc *crtc;
  4958. struct intel_encoder *encoder;
  4959. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  4960. if (crtc->pipe != PIPE_A && crtc->base.enabled)
  4961. enable = true;
  4962. /* XXX: Should check for edp transcoder here, but thanks to init
  4963. * sequence that's not yet available. Just in case desktop eDP
  4964. * on PORT D is possible on haswell, too. */
  4965. }
  4966. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  4967. base.head) {
  4968. if (encoder->type != INTEL_OUTPUT_EDP &&
  4969. encoder->connectors_active)
  4970. enable = true;
  4971. }
  4972. /* Even the eDP panel fitter is outside the always-on well. */
  4973. if (dev_priv->pch_pf_size)
  4974. enable = true;
  4975. intel_set_power_well(dev, enable);
  4976. }
  4977. static int haswell_crtc_mode_set(struct drm_crtc *crtc,
  4978. int x, int y,
  4979. struct drm_framebuffer *fb)
  4980. {
  4981. struct drm_device *dev = crtc->dev;
  4982. struct drm_i915_private *dev_priv = dev->dev_private;
  4983. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4984. struct drm_display_mode *adjusted_mode =
  4985. &intel_crtc->config.adjusted_mode;
  4986. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  4987. int pipe = intel_crtc->pipe;
  4988. int plane = intel_crtc->plane;
  4989. int num_connectors = 0;
  4990. bool is_cpu_edp = false;
  4991. struct intel_encoder *encoder;
  4992. int ret;
  4993. bool dither;
  4994. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4995. switch (encoder->type) {
  4996. case INTEL_OUTPUT_EDP:
  4997. if (!intel_encoder_is_pch_edp(&encoder->base))
  4998. is_cpu_edp = true;
  4999. break;
  5000. }
  5001. num_connectors++;
  5002. }
  5003. if (is_cpu_edp)
  5004. intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
  5005. else
  5006. intel_crtc->config.cpu_transcoder = pipe;
  5007. /* We are not sure yet this won't happen. */
  5008. WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
  5009. INTEL_PCH_TYPE(dev));
  5010. WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
  5011. num_connectors, pipe_name(pipe));
  5012. WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
  5013. (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
  5014. WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
  5015. if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
  5016. return -EINVAL;
  5017. /* Ensure that the cursor is valid for the new mode before changing... */
  5018. intel_crtc_update_cursor(crtc, true);
  5019. /* determine panel color depth */
  5020. dither = intel_crtc->config.dither;
  5021. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
  5022. drm_mode_debug_printmodeline(mode);
  5023. if (intel_crtc->config.has_dp_encoder)
  5024. intel_dp_set_m_n(intel_crtc);
  5025. intel_crtc->lowfreq_avail = false;
  5026. intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
  5027. if (intel_crtc->config.has_pch_encoder)
  5028. ironlake_fdi_set_m_n(crtc);
  5029. haswell_set_pipeconf(crtc, adjusted_mode, dither);
  5030. intel_set_pipe_csc(crtc);
  5031. /* Set up the display plane register */
  5032. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
  5033. POSTING_READ(DSPCNTR(plane));
  5034. ret = intel_pipe_set_base(crtc, x, y, fb);
  5035. intel_update_watermarks(dev);
  5036. intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
  5037. return ret;
  5038. }
  5039. static bool haswell_get_pipe_config(struct intel_crtc *crtc,
  5040. struct intel_crtc_config *pipe_config)
  5041. {
  5042. struct drm_device *dev = crtc->base.dev;
  5043. struct drm_i915_private *dev_priv = dev->dev_private;
  5044. enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
  5045. uint32_t tmp;
  5046. if (!intel_using_power_well(dev_priv->dev) &&
  5047. cpu_transcoder != TRANSCODER_EDP)
  5048. return false;
  5049. tmp = I915_READ(PIPECONF(cpu_transcoder));
  5050. if (!(tmp & PIPECONF_ENABLE))
  5051. return false;
  5052. /*
  5053. * Haswell has only FDI/PCH transcoder A. It is which is connected to
  5054. * DDI E. So just check whether this pipe is wired to DDI E and whether
  5055. * the PCH transcoder is on.
  5056. */
  5057. tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
  5058. if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
  5059. I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
  5060. pipe_config->has_pch_encoder = true;
  5061. return true;
  5062. }
  5063. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  5064. int x, int y,
  5065. struct drm_framebuffer *fb)
  5066. {
  5067. struct drm_device *dev = crtc->dev;
  5068. struct drm_i915_private *dev_priv = dev->dev_private;
  5069. struct drm_encoder_helper_funcs *encoder_funcs;
  5070. struct intel_encoder *encoder;
  5071. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5072. struct drm_display_mode *adjusted_mode =
  5073. &intel_crtc->config.adjusted_mode;
  5074. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  5075. int pipe = intel_crtc->pipe;
  5076. int ret;
  5077. drm_vblank_pre_modeset(dev, pipe);
  5078. ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
  5079. drm_vblank_post_modeset(dev, pipe);
  5080. if (ret != 0)
  5081. return ret;
  5082. for_each_encoder_on_crtc(dev, crtc, encoder) {
  5083. DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
  5084. encoder->base.base.id,
  5085. drm_get_encoder_name(&encoder->base),
  5086. mode->base.id, mode->name);
  5087. if (encoder->mode_set) {
  5088. encoder->mode_set(encoder);
  5089. } else {
  5090. encoder_funcs = encoder->base.helper_private;
  5091. encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
  5092. }
  5093. }
  5094. return 0;
  5095. }
  5096. static bool intel_eld_uptodate(struct drm_connector *connector,
  5097. int reg_eldv, uint32_t bits_eldv,
  5098. int reg_elda, uint32_t bits_elda,
  5099. int reg_edid)
  5100. {
  5101. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5102. uint8_t *eld = connector->eld;
  5103. uint32_t i;
  5104. i = I915_READ(reg_eldv);
  5105. i &= bits_eldv;
  5106. if (!eld[0])
  5107. return !i;
  5108. if (!i)
  5109. return false;
  5110. i = I915_READ(reg_elda);
  5111. i &= ~bits_elda;
  5112. I915_WRITE(reg_elda, i);
  5113. for (i = 0; i < eld[2]; i++)
  5114. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  5115. return false;
  5116. return true;
  5117. }
  5118. static void g4x_write_eld(struct drm_connector *connector,
  5119. struct drm_crtc *crtc)
  5120. {
  5121. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5122. uint8_t *eld = connector->eld;
  5123. uint32_t eldv;
  5124. uint32_t len;
  5125. uint32_t i;
  5126. i = I915_READ(G4X_AUD_VID_DID);
  5127. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  5128. eldv = G4X_ELDV_DEVCL_DEVBLC;
  5129. else
  5130. eldv = G4X_ELDV_DEVCTG;
  5131. if (intel_eld_uptodate(connector,
  5132. G4X_AUD_CNTL_ST, eldv,
  5133. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  5134. G4X_HDMIW_HDMIEDID))
  5135. return;
  5136. i = I915_READ(G4X_AUD_CNTL_ST);
  5137. i &= ~(eldv | G4X_ELD_ADDR);
  5138. len = (i >> 9) & 0x1f; /* ELD buffer size */
  5139. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5140. if (!eld[0])
  5141. return;
  5142. len = min_t(uint8_t, eld[2], len);
  5143. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5144. for (i = 0; i < len; i++)
  5145. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  5146. i = I915_READ(G4X_AUD_CNTL_ST);
  5147. i |= eldv;
  5148. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5149. }
  5150. static void haswell_write_eld(struct drm_connector *connector,
  5151. struct drm_crtc *crtc)
  5152. {
  5153. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5154. uint8_t *eld = connector->eld;
  5155. struct drm_device *dev = crtc->dev;
  5156. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5157. uint32_t eldv;
  5158. uint32_t i;
  5159. int len;
  5160. int pipe = to_intel_crtc(crtc)->pipe;
  5161. int tmp;
  5162. int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  5163. int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  5164. int aud_config = HSW_AUD_CFG(pipe);
  5165. int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  5166. DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  5167. /* Audio output enable */
  5168. DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  5169. tmp = I915_READ(aud_cntrl_st2);
  5170. tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  5171. I915_WRITE(aud_cntrl_st2, tmp);
  5172. /* Wait for 1 vertical blank */
  5173. intel_wait_for_vblank(dev, pipe);
  5174. /* Set ELD valid state */
  5175. tmp = I915_READ(aud_cntrl_st2);
  5176. DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
  5177. tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  5178. I915_WRITE(aud_cntrl_st2, tmp);
  5179. tmp = I915_READ(aud_cntrl_st2);
  5180. DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
  5181. /* Enable HDMI mode */
  5182. tmp = I915_READ(aud_config);
  5183. DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
  5184. /* clear N_programing_enable and N_value_index */
  5185. tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  5186. I915_WRITE(aud_config, tmp);
  5187. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5188. eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  5189. intel_crtc->eld_vld = true;
  5190. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5191. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5192. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5193. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5194. } else
  5195. I915_WRITE(aud_config, 0);
  5196. if (intel_eld_uptodate(connector,
  5197. aud_cntrl_st2, eldv,
  5198. aud_cntl_st, IBX_ELD_ADDRESS,
  5199. hdmiw_hdmiedid))
  5200. return;
  5201. i = I915_READ(aud_cntrl_st2);
  5202. i &= ~eldv;
  5203. I915_WRITE(aud_cntrl_st2, i);
  5204. if (!eld[0])
  5205. return;
  5206. i = I915_READ(aud_cntl_st);
  5207. i &= ~IBX_ELD_ADDRESS;
  5208. I915_WRITE(aud_cntl_st, i);
  5209. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5210. DRM_DEBUG_DRIVER("port num:%d\n", i);
  5211. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5212. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5213. for (i = 0; i < len; i++)
  5214. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5215. i = I915_READ(aud_cntrl_st2);
  5216. i |= eldv;
  5217. I915_WRITE(aud_cntrl_st2, i);
  5218. }
  5219. static void ironlake_write_eld(struct drm_connector *connector,
  5220. struct drm_crtc *crtc)
  5221. {
  5222. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5223. uint8_t *eld = connector->eld;
  5224. uint32_t eldv;
  5225. uint32_t i;
  5226. int len;
  5227. int hdmiw_hdmiedid;
  5228. int aud_config;
  5229. int aud_cntl_st;
  5230. int aud_cntrl_st2;
  5231. int pipe = to_intel_crtc(crtc)->pipe;
  5232. if (HAS_PCH_IBX(connector->dev)) {
  5233. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  5234. aud_config = IBX_AUD_CFG(pipe);
  5235. aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  5236. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  5237. } else {
  5238. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  5239. aud_config = CPT_AUD_CFG(pipe);
  5240. aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  5241. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  5242. }
  5243. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5244. i = I915_READ(aud_cntl_st);
  5245. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5246. if (!i) {
  5247. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  5248. /* operate blindly on all ports */
  5249. eldv = IBX_ELD_VALIDB;
  5250. eldv |= IBX_ELD_VALIDB << 4;
  5251. eldv |= IBX_ELD_VALIDB << 8;
  5252. } else {
  5253. DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
  5254. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  5255. }
  5256. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5257. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5258. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5259. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5260. } else
  5261. I915_WRITE(aud_config, 0);
  5262. if (intel_eld_uptodate(connector,
  5263. aud_cntrl_st2, eldv,
  5264. aud_cntl_st, IBX_ELD_ADDRESS,
  5265. hdmiw_hdmiedid))
  5266. return;
  5267. i = I915_READ(aud_cntrl_st2);
  5268. i &= ~eldv;
  5269. I915_WRITE(aud_cntrl_st2, i);
  5270. if (!eld[0])
  5271. return;
  5272. i = I915_READ(aud_cntl_st);
  5273. i &= ~IBX_ELD_ADDRESS;
  5274. I915_WRITE(aud_cntl_st, i);
  5275. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5276. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5277. for (i = 0; i < len; i++)
  5278. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5279. i = I915_READ(aud_cntrl_st2);
  5280. i |= eldv;
  5281. I915_WRITE(aud_cntrl_st2, i);
  5282. }
  5283. void intel_write_eld(struct drm_encoder *encoder,
  5284. struct drm_display_mode *mode)
  5285. {
  5286. struct drm_crtc *crtc = encoder->crtc;
  5287. struct drm_connector *connector;
  5288. struct drm_device *dev = encoder->dev;
  5289. struct drm_i915_private *dev_priv = dev->dev_private;
  5290. connector = drm_select_eld(encoder, mode);
  5291. if (!connector)
  5292. return;
  5293. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5294. connector->base.id,
  5295. drm_get_connector_name(connector),
  5296. connector->encoder->base.id,
  5297. drm_get_encoder_name(connector->encoder));
  5298. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  5299. if (dev_priv->display.write_eld)
  5300. dev_priv->display.write_eld(connector, crtc);
  5301. }
  5302. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  5303. void intel_crtc_load_lut(struct drm_crtc *crtc)
  5304. {
  5305. struct drm_device *dev = crtc->dev;
  5306. struct drm_i915_private *dev_priv = dev->dev_private;
  5307. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5308. int palreg = PALETTE(intel_crtc->pipe);
  5309. int i;
  5310. /* The clocks have to be on to load the palette. */
  5311. if (!crtc->enabled || !intel_crtc->active)
  5312. return;
  5313. /* use legacy palette for Ironlake */
  5314. if (HAS_PCH_SPLIT(dev))
  5315. palreg = LGC_PALETTE(intel_crtc->pipe);
  5316. for (i = 0; i < 256; i++) {
  5317. I915_WRITE(palreg + 4 * i,
  5318. (intel_crtc->lut_r[i] << 16) |
  5319. (intel_crtc->lut_g[i] << 8) |
  5320. intel_crtc->lut_b[i]);
  5321. }
  5322. }
  5323. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  5324. {
  5325. struct drm_device *dev = crtc->dev;
  5326. struct drm_i915_private *dev_priv = dev->dev_private;
  5327. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5328. bool visible = base != 0;
  5329. u32 cntl;
  5330. if (intel_crtc->cursor_visible == visible)
  5331. return;
  5332. cntl = I915_READ(_CURACNTR);
  5333. if (visible) {
  5334. /* On these chipsets we can only modify the base whilst
  5335. * the cursor is disabled.
  5336. */
  5337. I915_WRITE(_CURABASE, base);
  5338. cntl &= ~(CURSOR_FORMAT_MASK);
  5339. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  5340. cntl |= CURSOR_ENABLE |
  5341. CURSOR_GAMMA_ENABLE |
  5342. CURSOR_FORMAT_ARGB;
  5343. } else
  5344. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  5345. I915_WRITE(_CURACNTR, cntl);
  5346. intel_crtc->cursor_visible = visible;
  5347. }
  5348. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  5349. {
  5350. struct drm_device *dev = crtc->dev;
  5351. struct drm_i915_private *dev_priv = dev->dev_private;
  5352. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5353. int pipe = intel_crtc->pipe;
  5354. bool visible = base != 0;
  5355. if (intel_crtc->cursor_visible != visible) {
  5356. uint32_t cntl = I915_READ(CURCNTR(pipe));
  5357. if (base) {
  5358. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  5359. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5360. cntl |= pipe << 28; /* Connect to correct pipe */
  5361. } else {
  5362. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5363. cntl |= CURSOR_MODE_DISABLE;
  5364. }
  5365. I915_WRITE(CURCNTR(pipe), cntl);
  5366. intel_crtc->cursor_visible = visible;
  5367. }
  5368. /* and commit changes on next vblank */
  5369. I915_WRITE(CURBASE(pipe), base);
  5370. }
  5371. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  5372. {
  5373. struct drm_device *dev = crtc->dev;
  5374. struct drm_i915_private *dev_priv = dev->dev_private;
  5375. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5376. int pipe = intel_crtc->pipe;
  5377. bool visible = base != 0;
  5378. if (intel_crtc->cursor_visible != visible) {
  5379. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  5380. if (base) {
  5381. cntl &= ~CURSOR_MODE;
  5382. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5383. } else {
  5384. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5385. cntl |= CURSOR_MODE_DISABLE;
  5386. }
  5387. if (IS_HASWELL(dev))
  5388. cntl |= CURSOR_PIPE_CSC_ENABLE;
  5389. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  5390. intel_crtc->cursor_visible = visible;
  5391. }
  5392. /* and commit changes on next vblank */
  5393. I915_WRITE(CURBASE_IVB(pipe), base);
  5394. }
  5395. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  5396. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  5397. bool on)
  5398. {
  5399. struct drm_device *dev = crtc->dev;
  5400. struct drm_i915_private *dev_priv = dev->dev_private;
  5401. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5402. int pipe = intel_crtc->pipe;
  5403. int x = intel_crtc->cursor_x;
  5404. int y = intel_crtc->cursor_y;
  5405. u32 base, pos;
  5406. bool visible;
  5407. pos = 0;
  5408. if (on && crtc->enabled && crtc->fb) {
  5409. base = intel_crtc->cursor_addr;
  5410. if (x > (int) crtc->fb->width)
  5411. base = 0;
  5412. if (y > (int) crtc->fb->height)
  5413. base = 0;
  5414. } else
  5415. base = 0;
  5416. if (x < 0) {
  5417. if (x + intel_crtc->cursor_width < 0)
  5418. base = 0;
  5419. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  5420. x = -x;
  5421. }
  5422. pos |= x << CURSOR_X_SHIFT;
  5423. if (y < 0) {
  5424. if (y + intel_crtc->cursor_height < 0)
  5425. base = 0;
  5426. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  5427. y = -y;
  5428. }
  5429. pos |= y << CURSOR_Y_SHIFT;
  5430. visible = base != 0;
  5431. if (!visible && !intel_crtc->cursor_visible)
  5432. return;
  5433. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  5434. I915_WRITE(CURPOS_IVB(pipe), pos);
  5435. ivb_update_cursor(crtc, base);
  5436. } else {
  5437. I915_WRITE(CURPOS(pipe), pos);
  5438. if (IS_845G(dev) || IS_I865G(dev))
  5439. i845_update_cursor(crtc, base);
  5440. else
  5441. i9xx_update_cursor(crtc, base);
  5442. }
  5443. }
  5444. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  5445. struct drm_file *file,
  5446. uint32_t handle,
  5447. uint32_t width, uint32_t height)
  5448. {
  5449. struct drm_device *dev = crtc->dev;
  5450. struct drm_i915_private *dev_priv = dev->dev_private;
  5451. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5452. struct drm_i915_gem_object *obj;
  5453. uint32_t addr;
  5454. int ret;
  5455. /* if we want to turn off the cursor ignore width and height */
  5456. if (!handle) {
  5457. DRM_DEBUG_KMS("cursor off\n");
  5458. addr = 0;
  5459. obj = NULL;
  5460. mutex_lock(&dev->struct_mutex);
  5461. goto finish;
  5462. }
  5463. /* Currently we only support 64x64 cursors */
  5464. if (width != 64 || height != 64) {
  5465. DRM_ERROR("we currently only support 64x64 cursors\n");
  5466. return -EINVAL;
  5467. }
  5468. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  5469. if (&obj->base == NULL)
  5470. return -ENOENT;
  5471. if (obj->base.size < width * height * 4) {
  5472. DRM_ERROR("buffer is to small\n");
  5473. ret = -ENOMEM;
  5474. goto fail;
  5475. }
  5476. /* we only need to pin inside GTT if cursor is non-phy */
  5477. mutex_lock(&dev->struct_mutex);
  5478. if (!dev_priv->info->cursor_needs_physical) {
  5479. unsigned alignment;
  5480. if (obj->tiling_mode) {
  5481. DRM_ERROR("cursor cannot be tiled\n");
  5482. ret = -EINVAL;
  5483. goto fail_locked;
  5484. }
  5485. /* Note that the w/a also requires 2 PTE of padding following
  5486. * the bo. We currently fill all unused PTE with the shadow
  5487. * page and so we should always have valid PTE following the
  5488. * cursor preventing the VT-d warning.
  5489. */
  5490. alignment = 0;
  5491. if (need_vtd_wa(dev))
  5492. alignment = 64*1024;
  5493. ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
  5494. if (ret) {
  5495. DRM_ERROR("failed to move cursor bo into the GTT\n");
  5496. goto fail_locked;
  5497. }
  5498. ret = i915_gem_object_put_fence(obj);
  5499. if (ret) {
  5500. DRM_ERROR("failed to release fence for cursor");
  5501. goto fail_unpin;
  5502. }
  5503. addr = obj->gtt_offset;
  5504. } else {
  5505. int align = IS_I830(dev) ? 16 * 1024 : 256;
  5506. ret = i915_gem_attach_phys_object(dev, obj,
  5507. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  5508. align);
  5509. if (ret) {
  5510. DRM_ERROR("failed to attach phys object\n");
  5511. goto fail_locked;
  5512. }
  5513. addr = obj->phys_obj->handle->busaddr;
  5514. }
  5515. if (IS_GEN2(dev))
  5516. I915_WRITE(CURSIZE, (height << 12) | width);
  5517. finish:
  5518. if (intel_crtc->cursor_bo) {
  5519. if (dev_priv->info->cursor_needs_physical) {
  5520. if (intel_crtc->cursor_bo != obj)
  5521. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  5522. } else
  5523. i915_gem_object_unpin(intel_crtc->cursor_bo);
  5524. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  5525. }
  5526. mutex_unlock(&dev->struct_mutex);
  5527. intel_crtc->cursor_addr = addr;
  5528. intel_crtc->cursor_bo = obj;
  5529. intel_crtc->cursor_width = width;
  5530. intel_crtc->cursor_height = height;
  5531. intel_crtc_update_cursor(crtc, true);
  5532. return 0;
  5533. fail_unpin:
  5534. i915_gem_object_unpin(obj);
  5535. fail_locked:
  5536. mutex_unlock(&dev->struct_mutex);
  5537. fail:
  5538. drm_gem_object_unreference_unlocked(&obj->base);
  5539. return ret;
  5540. }
  5541. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  5542. {
  5543. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5544. intel_crtc->cursor_x = x;
  5545. intel_crtc->cursor_y = y;
  5546. intel_crtc_update_cursor(crtc, true);
  5547. return 0;
  5548. }
  5549. /** Sets the color ramps on behalf of RandR */
  5550. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  5551. u16 blue, int regno)
  5552. {
  5553. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5554. intel_crtc->lut_r[regno] = red >> 8;
  5555. intel_crtc->lut_g[regno] = green >> 8;
  5556. intel_crtc->lut_b[regno] = blue >> 8;
  5557. }
  5558. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  5559. u16 *blue, int regno)
  5560. {
  5561. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5562. *red = intel_crtc->lut_r[regno] << 8;
  5563. *green = intel_crtc->lut_g[regno] << 8;
  5564. *blue = intel_crtc->lut_b[regno] << 8;
  5565. }
  5566. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  5567. u16 *blue, uint32_t start, uint32_t size)
  5568. {
  5569. int end = (start + size > 256) ? 256 : start + size, i;
  5570. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5571. for (i = start; i < end; i++) {
  5572. intel_crtc->lut_r[i] = red[i] >> 8;
  5573. intel_crtc->lut_g[i] = green[i] >> 8;
  5574. intel_crtc->lut_b[i] = blue[i] >> 8;
  5575. }
  5576. intel_crtc_load_lut(crtc);
  5577. }
  5578. /* VESA 640x480x72Hz mode to set on the pipe */
  5579. static struct drm_display_mode load_detect_mode = {
  5580. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  5581. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  5582. };
  5583. static struct drm_framebuffer *
  5584. intel_framebuffer_create(struct drm_device *dev,
  5585. struct drm_mode_fb_cmd2 *mode_cmd,
  5586. struct drm_i915_gem_object *obj)
  5587. {
  5588. struct intel_framebuffer *intel_fb;
  5589. int ret;
  5590. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  5591. if (!intel_fb) {
  5592. drm_gem_object_unreference_unlocked(&obj->base);
  5593. return ERR_PTR(-ENOMEM);
  5594. }
  5595. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  5596. if (ret) {
  5597. drm_gem_object_unreference_unlocked(&obj->base);
  5598. kfree(intel_fb);
  5599. return ERR_PTR(ret);
  5600. }
  5601. return &intel_fb->base;
  5602. }
  5603. static u32
  5604. intel_framebuffer_pitch_for_width(int width, int bpp)
  5605. {
  5606. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  5607. return ALIGN(pitch, 64);
  5608. }
  5609. static u32
  5610. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  5611. {
  5612. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  5613. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  5614. }
  5615. static struct drm_framebuffer *
  5616. intel_framebuffer_create_for_mode(struct drm_device *dev,
  5617. struct drm_display_mode *mode,
  5618. int depth, int bpp)
  5619. {
  5620. struct drm_i915_gem_object *obj;
  5621. struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  5622. obj = i915_gem_alloc_object(dev,
  5623. intel_framebuffer_size_for_mode(mode, bpp));
  5624. if (obj == NULL)
  5625. return ERR_PTR(-ENOMEM);
  5626. mode_cmd.width = mode->hdisplay;
  5627. mode_cmd.height = mode->vdisplay;
  5628. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  5629. bpp);
  5630. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  5631. return intel_framebuffer_create(dev, &mode_cmd, obj);
  5632. }
  5633. static struct drm_framebuffer *
  5634. mode_fits_in_fbdev(struct drm_device *dev,
  5635. struct drm_display_mode *mode)
  5636. {
  5637. struct drm_i915_private *dev_priv = dev->dev_private;
  5638. struct drm_i915_gem_object *obj;
  5639. struct drm_framebuffer *fb;
  5640. if (dev_priv->fbdev == NULL)
  5641. return NULL;
  5642. obj = dev_priv->fbdev->ifb.obj;
  5643. if (obj == NULL)
  5644. return NULL;
  5645. fb = &dev_priv->fbdev->ifb.base;
  5646. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  5647. fb->bits_per_pixel))
  5648. return NULL;
  5649. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  5650. return NULL;
  5651. return fb;
  5652. }
  5653. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  5654. struct drm_display_mode *mode,
  5655. struct intel_load_detect_pipe *old)
  5656. {
  5657. struct intel_crtc *intel_crtc;
  5658. struct intel_encoder *intel_encoder =
  5659. intel_attached_encoder(connector);
  5660. struct drm_crtc *possible_crtc;
  5661. struct drm_encoder *encoder = &intel_encoder->base;
  5662. struct drm_crtc *crtc = NULL;
  5663. struct drm_device *dev = encoder->dev;
  5664. struct drm_framebuffer *fb;
  5665. int i = -1;
  5666. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5667. connector->base.id, drm_get_connector_name(connector),
  5668. encoder->base.id, drm_get_encoder_name(encoder));
  5669. /*
  5670. * Algorithm gets a little messy:
  5671. *
  5672. * - if the connector already has an assigned crtc, use it (but make
  5673. * sure it's on first)
  5674. *
  5675. * - try to find the first unused crtc that can drive this connector,
  5676. * and use that if we find one
  5677. */
  5678. /* See if we already have a CRTC for this connector */
  5679. if (encoder->crtc) {
  5680. crtc = encoder->crtc;
  5681. mutex_lock(&crtc->mutex);
  5682. old->dpms_mode = connector->dpms;
  5683. old->load_detect_temp = false;
  5684. /* Make sure the crtc and connector are running */
  5685. if (connector->dpms != DRM_MODE_DPMS_ON)
  5686. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  5687. return true;
  5688. }
  5689. /* Find an unused one (if possible) */
  5690. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  5691. i++;
  5692. if (!(encoder->possible_crtcs & (1 << i)))
  5693. continue;
  5694. if (!possible_crtc->enabled) {
  5695. crtc = possible_crtc;
  5696. break;
  5697. }
  5698. }
  5699. /*
  5700. * If we didn't find an unused CRTC, don't use any.
  5701. */
  5702. if (!crtc) {
  5703. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  5704. return false;
  5705. }
  5706. mutex_lock(&crtc->mutex);
  5707. intel_encoder->new_crtc = to_intel_crtc(crtc);
  5708. to_intel_connector(connector)->new_encoder = intel_encoder;
  5709. intel_crtc = to_intel_crtc(crtc);
  5710. old->dpms_mode = connector->dpms;
  5711. old->load_detect_temp = true;
  5712. old->release_fb = NULL;
  5713. if (!mode)
  5714. mode = &load_detect_mode;
  5715. /* We need a framebuffer large enough to accommodate all accesses
  5716. * that the plane may generate whilst we perform load detection.
  5717. * We can not rely on the fbcon either being present (we get called
  5718. * during its initialisation to detect all boot displays, or it may
  5719. * not even exist) or that it is large enough to satisfy the
  5720. * requested mode.
  5721. */
  5722. fb = mode_fits_in_fbdev(dev, mode);
  5723. if (fb == NULL) {
  5724. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  5725. fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  5726. old->release_fb = fb;
  5727. } else
  5728. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  5729. if (IS_ERR(fb)) {
  5730. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  5731. mutex_unlock(&crtc->mutex);
  5732. return false;
  5733. }
  5734. if (intel_set_mode(crtc, mode, 0, 0, fb)) {
  5735. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  5736. if (old->release_fb)
  5737. old->release_fb->funcs->destroy(old->release_fb);
  5738. mutex_unlock(&crtc->mutex);
  5739. return false;
  5740. }
  5741. /* let the connector get through one full cycle before testing */
  5742. intel_wait_for_vblank(dev, intel_crtc->pipe);
  5743. return true;
  5744. }
  5745. void intel_release_load_detect_pipe(struct drm_connector *connector,
  5746. struct intel_load_detect_pipe *old)
  5747. {
  5748. struct intel_encoder *intel_encoder =
  5749. intel_attached_encoder(connector);
  5750. struct drm_encoder *encoder = &intel_encoder->base;
  5751. struct drm_crtc *crtc = encoder->crtc;
  5752. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5753. connector->base.id, drm_get_connector_name(connector),
  5754. encoder->base.id, drm_get_encoder_name(encoder));
  5755. if (old->load_detect_temp) {
  5756. to_intel_connector(connector)->new_encoder = NULL;
  5757. intel_encoder->new_crtc = NULL;
  5758. intel_set_mode(crtc, NULL, 0, 0, NULL);
  5759. if (old->release_fb) {
  5760. drm_framebuffer_unregister_private(old->release_fb);
  5761. drm_framebuffer_unreference(old->release_fb);
  5762. }
  5763. mutex_unlock(&crtc->mutex);
  5764. return;
  5765. }
  5766. /* Switch crtc and encoder back off if necessary */
  5767. if (old->dpms_mode != DRM_MODE_DPMS_ON)
  5768. connector->funcs->dpms(connector, old->dpms_mode);
  5769. mutex_unlock(&crtc->mutex);
  5770. }
  5771. /* Returns the clock of the currently programmed mode of the given pipe. */
  5772. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  5773. {
  5774. struct drm_i915_private *dev_priv = dev->dev_private;
  5775. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5776. int pipe = intel_crtc->pipe;
  5777. u32 dpll = I915_READ(DPLL(pipe));
  5778. u32 fp;
  5779. intel_clock_t clock;
  5780. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  5781. fp = I915_READ(FP0(pipe));
  5782. else
  5783. fp = I915_READ(FP1(pipe));
  5784. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  5785. if (IS_PINEVIEW(dev)) {
  5786. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  5787. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5788. } else {
  5789. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  5790. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5791. }
  5792. if (!IS_GEN2(dev)) {
  5793. if (IS_PINEVIEW(dev))
  5794. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  5795. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  5796. else
  5797. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  5798. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5799. switch (dpll & DPLL_MODE_MASK) {
  5800. case DPLLB_MODE_DAC_SERIAL:
  5801. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  5802. 5 : 10;
  5803. break;
  5804. case DPLLB_MODE_LVDS:
  5805. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  5806. 7 : 14;
  5807. break;
  5808. default:
  5809. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  5810. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  5811. return 0;
  5812. }
  5813. /* XXX: Handle the 100Mhz refclk */
  5814. intel_clock(dev, 96000, &clock);
  5815. } else {
  5816. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  5817. if (is_lvds) {
  5818. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  5819. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5820. clock.p2 = 14;
  5821. if ((dpll & PLL_REF_INPUT_MASK) ==
  5822. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  5823. /* XXX: might not be 66MHz */
  5824. intel_clock(dev, 66000, &clock);
  5825. } else
  5826. intel_clock(dev, 48000, &clock);
  5827. } else {
  5828. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  5829. clock.p1 = 2;
  5830. else {
  5831. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  5832. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  5833. }
  5834. if (dpll & PLL_P2_DIVIDE_BY_4)
  5835. clock.p2 = 4;
  5836. else
  5837. clock.p2 = 2;
  5838. intel_clock(dev, 48000, &clock);
  5839. }
  5840. }
  5841. /* XXX: It would be nice to validate the clocks, but we can't reuse
  5842. * i830PllIsValid() because it relies on the xf86_config connector
  5843. * configuration being accurate, which it isn't necessarily.
  5844. */
  5845. return clock.dot;
  5846. }
  5847. /** Returns the currently programmed mode of the given pipe. */
  5848. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  5849. struct drm_crtc *crtc)
  5850. {
  5851. struct drm_i915_private *dev_priv = dev->dev_private;
  5852. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5853. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  5854. struct drm_display_mode *mode;
  5855. int htot = I915_READ(HTOTAL(cpu_transcoder));
  5856. int hsync = I915_READ(HSYNC(cpu_transcoder));
  5857. int vtot = I915_READ(VTOTAL(cpu_transcoder));
  5858. int vsync = I915_READ(VSYNC(cpu_transcoder));
  5859. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  5860. if (!mode)
  5861. return NULL;
  5862. mode->clock = intel_crtc_clock_get(dev, crtc);
  5863. mode->hdisplay = (htot & 0xffff) + 1;
  5864. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  5865. mode->hsync_start = (hsync & 0xffff) + 1;
  5866. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  5867. mode->vdisplay = (vtot & 0xffff) + 1;
  5868. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  5869. mode->vsync_start = (vsync & 0xffff) + 1;
  5870. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  5871. drm_mode_set_name(mode);
  5872. return mode;
  5873. }
  5874. static void intel_increase_pllclock(struct drm_crtc *crtc)
  5875. {
  5876. struct drm_device *dev = crtc->dev;
  5877. drm_i915_private_t *dev_priv = dev->dev_private;
  5878. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5879. int pipe = intel_crtc->pipe;
  5880. int dpll_reg = DPLL(pipe);
  5881. int dpll;
  5882. if (HAS_PCH_SPLIT(dev))
  5883. return;
  5884. if (!dev_priv->lvds_downclock_avail)
  5885. return;
  5886. dpll = I915_READ(dpll_reg);
  5887. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  5888. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  5889. assert_panel_unlocked(dev_priv, pipe);
  5890. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  5891. I915_WRITE(dpll_reg, dpll);
  5892. intel_wait_for_vblank(dev, pipe);
  5893. dpll = I915_READ(dpll_reg);
  5894. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  5895. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  5896. }
  5897. }
  5898. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  5899. {
  5900. struct drm_device *dev = crtc->dev;
  5901. drm_i915_private_t *dev_priv = dev->dev_private;
  5902. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5903. if (HAS_PCH_SPLIT(dev))
  5904. return;
  5905. if (!dev_priv->lvds_downclock_avail)
  5906. return;
  5907. /*
  5908. * Since this is called by a timer, we should never get here in
  5909. * the manual case.
  5910. */
  5911. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  5912. int pipe = intel_crtc->pipe;
  5913. int dpll_reg = DPLL(pipe);
  5914. int dpll;
  5915. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  5916. assert_panel_unlocked(dev_priv, pipe);
  5917. dpll = I915_READ(dpll_reg);
  5918. dpll |= DISPLAY_RATE_SELECT_FPA1;
  5919. I915_WRITE(dpll_reg, dpll);
  5920. intel_wait_for_vblank(dev, pipe);
  5921. dpll = I915_READ(dpll_reg);
  5922. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  5923. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  5924. }
  5925. }
  5926. void intel_mark_busy(struct drm_device *dev)
  5927. {
  5928. i915_update_gfx_val(dev->dev_private);
  5929. }
  5930. void intel_mark_idle(struct drm_device *dev)
  5931. {
  5932. struct drm_crtc *crtc;
  5933. if (!i915_powersave)
  5934. return;
  5935. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5936. if (!crtc->fb)
  5937. continue;
  5938. intel_decrease_pllclock(crtc);
  5939. }
  5940. }
  5941. void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
  5942. {
  5943. struct drm_device *dev = obj->base.dev;
  5944. struct drm_crtc *crtc;
  5945. if (!i915_powersave)
  5946. return;
  5947. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5948. if (!crtc->fb)
  5949. continue;
  5950. if (to_intel_framebuffer(crtc->fb)->obj == obj)
  5951. intel_increase_pllclock(crtc);
  5952. }
  5953. }
  5954. static void intel_crtc_destroy(struct drm_crtc *crtc)
  5955. {
  5956. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5957. struct drm_device *dev = crtc->dev;
  5958. struct intel_unpin_work *work;
  5959. unsigned long flags;
  5960. spin_lock_irqsave(&dev->event_lock, flags);
  5961. work = intel_crtc->unpin_work;
  5962. intel_crtc->unpin_work = NULL;
  5963. spin_unlock_irqrestore(&dev->event_lock, flags);
  5964. if (work) {
  5965. cancel_work_sync(&work->work);
  5966. kfree(work);
  5967. }
  5968. drm_crtc_cleanup(crtc);
  5969. kfree(intel_crtc);
  5970. }
  5971. static void intel_unpin_work_fn(struct work_struct *__work)
  5972. {
  5973. struct intel_unpin_work *work =
  5974. container_of(__work, struct intel_unpin_work, work);
  5975. struct drm_device *dev = work->crtc->dev;
  5976. mutex_lock(&dev->struct_mutex);
  5977. intel_unpin_fb_obj(work->old_fb_obj);
  5978. drm_gem_object_unreference(&work->pending_flip_obj->base);
  5979. drm_gem_object_unreference(&work->old_fb_obj->base);
  5980. intel_update_fbc(dev);
  5981. mutex_unlock(&dev->struct_mutex);
  5982. BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
  5983. atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
  5984. kfree(work);
  5985. }
  5986. static void do_intel_finish_page_flip(struct drm_device *dev,
  5987. struct drm_crtc *crtc)
  5988. {
  5989. drm_i915_private_t *dev_priv = dev->dev_private;
  5990. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5991. struct intel_unpin_work *work;
  5992. unsigned long flags;
  5993. /* Ignore early vblank irqs */
  5994. if (intel_crtc == NULL)
  5995. return;
  5996. spin_lock_irqsave(&dev->event_lock, flags);
  5997. work = intel_crtc->unpin_work;
  5998. /* Ensure we don't miss a work->pending update ... */
  5999. smp_rmb();
  6000. if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  6001. spin_unlock_irqrestore(&dev->event_lock, flags);
  6002. return;
  6003. }
  6004. /* and that the unpin work is consistent wrt ->pending. */
  6005. smp_rmb();
  6006. intel_crtc->unpin_work = NULL;
  6007. if (work->event)
  6008. drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
  6009. drm_vblank_put(dev, intel_crtc->pipe);
  6010. spin_unlock_irqrestore(&dev->event_lock, flags);
  6011. wake_up_all(&dev_priv->pending_flip_queue);
  6012. queue_work(dev_priv->wq, &work->work);
  6013. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  6014. }
  6015. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  6016. {
  6017. drm_i915_private_t *dev_priv = dev->dev_private;
  6018. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  6019. do_intel_finish_page_flip(dev, crtc);
  6020. }
  6021. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  6022. {
  6023. drm_i915_private_t *dev_priv = dev->dev_private;
  6024. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  6025. do_intel_finish_page_flip(dev, crtc);
  6026. }
  6027. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  6028. {
  6029. drm_i915_private_t *dev_priv = dev->dev_private;
  6030. struct intel_crtc *intel_crtc =
  6031. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  6032. unsigned long flags;
  6033. /* NB: An MMIO update of the plane base pointer will also
  6034. * generate a page-flip completion irq, i.e. every modeset
  6035. * is also accompanied by a spurious intel_prepare_page_flip().
  6036. */
  6037. spin_lock_irqsave(&dev->event_lock, flags);
  6038. if (intel_crtc->unpin_work)
  6039. atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  6040. spin_unlock_irqrestore(&dev->event_lock, flags);
  6041. }
  6042. inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
  6043. {
  6044. /* Ensure that the work item is consistent when activating it ... */
  6045. smp_wmb();
  6046. atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
  6047. /* and that it is marked active as soon as the irq could fire. */
  6048. smp_wmb();
  6049. }
  6050. static int intel_gen2_queue_flip(struct drm_device *dev,
  6051. struct drm_crtc *crtc,
  6052. struct drm_framebuffer *fb,
  6053. struct drm_i915_gem_object *obj)
  6054. {
  6055. struct drm_i915_private *dev_priv = dev->dev_private;
  6056. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6057. u32 flip_mask;
  6058. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6059. int ret;
  6060. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6061. if (ret)
  6062. goto err;
  6063. ret = intel_ring_begin(ring, 6);
  6064. if (ret)
  6065. goto err_unpin;
  6066. /* Can't queue multiple flips, so wait for the previous
  6067. * one to finish before executing the next.
  6068. */
  6069. if (intel_crtc->plane)
  6070. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6071. else
  6072. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6073. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6074. intel_ring_emit(ring, MI_NOOP);
  6075. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6076. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6077. intel_ring_emit(ring, fb->pitches[0]);
  6078. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  6079. intel_ring_emit(ring, 0); /* aux display base address, unused */
  6080. intel_mark_page_flip_active(intel_crtc);
  6081. intel_ring_advance(ring);
  6082. return 0;
  6083. err_unpin:
  6084. intel_unpin_fb_obj(obj);
  6085. err:
  6086. return ret;
  6087. }
  6088. static int intel_gen3_queue_flip(struct drm_device *dev,
  6089. struct drm_crtc *crtc,
  6090. struct drm_framebuffer *fb,
  6091. struct drm_i915_gem_object *obj)
  6092. {
  6093. struct drm_i915_private *dev_priv = dev->dev_private;
  6094. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6095. u32 flip_mask;
  6096. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6097. int ret;
  6098. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6099. if (ret)
  6100. goto err;
  6101. ret = intel_ring_begin(ring, 6);
  6102. if (ret)
  6103. goto err_unpin;
  6104. if (intel_crtc->plane)
  6105. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6106. else
  6107. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6108. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6109. intel_ring_emit(ring, MI_NOOP);
  6110. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  6111. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6112. intel_ring_emit(ring, fb->pitches[0]);
  6113. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  6114. intel_ring_emit(ring, MI_NOOP);
  6115. intel_mark_page_flip_active(intel_crtc);
  6116. intel_ring_advance(ring);
  6117. return 0;
  6118. err_unpin:
  6119. intel_unpin_fb_obj(obj);
  6120. err:
  6121. return ret;
  6122. }
  6123. static int intel_gen4_queue_flip(struct drm_device *dev,
  6124. struct drm_crtc *crtc,
  6125. struct drm_framebuffer *fb,
  6126. struct drm_i915_gem_object *obj)
  6127. {
  6128. struct drm_i915_private *dev_priv = dev->dev_private;
  6129. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6130. uint32_t pf, pipesrc;
  6131. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6132. int ret;
  6133. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6134. if (ret)
  6135. goto err;
  6136. ret = intel_ring_begin(ring, 4);
  6137. if (ret)
  6138. goto err_unpin;
  6139. /* i965+ uses the linear or tiled offsets from the
  6140. * Display Registers (which do not change across a page-flip)
  6141. * so we need only reprogram the base address.
  6142. */
  6143. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6144. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6145. intel_ring_emit(ring, fb->pitches[0]);
  6146. intel_ring_emit(ring,
  6147. (obj->gtt_offset + intel_crtc->dspaddr_offset) |
  6148. obj->tiling_mode);
  6149. /* XXX Enabling the panel-fitter across page-flip is so far
  6150. * untested on non-native modes, so ignore it for now.
  6151. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  6152. */
  6153. pf = 0;
  6154. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6155. intel_ring_emit(ring, pf | pipesrc);
  6156. intel_mark_page_flip_active(intel_crtc);
  6157. intel_ring_advance(ring);
  6158. return 0;
  6159. err_unpin:
  6160. intel_unpin_fb_obj(obj);
  6161. err:
  6162. return ret;
  6163. }
  6164. static int intel_gen6_queue_flip(struct drm_device *dev,
  6165. struct drm_crtc *crtc,
  6166. struct drm_framebuffer *fb,
  6167. struct drm_i915_gem_object *obj)
  6168. {
  6169. struct drm_i915_private *dev_priv = dev->dev_private;
  6170. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6171. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6172. uint32_t pf, pipesrc;
  6173. int ret;
  6174. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6175. if (ret)
  6176. goto err;
  6177. ret = intel_ring_begin(ring, 4);
  6178. if (ret)
  6179. goto err_unpin;
  6180. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6181. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6182. intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  6183. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  6184. /* Contrary to the suggestions in the documentation,
  6185. * "Enable Panel Fitter" does not seem to be required when page
  6186. * flipping with a non-native mode, and worse causes a normal
  6187. * modeset to fail.
  6188. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  6189. */
  6190. pf = 0;
  6191. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6192. intel_ring_emit(ring, pf | pipesrc);
  6193. intel_mark_page_flip_active(intel_crtc);
  6194. intel_ring_advance(ring);
  6195. return 0;
  6196. err_unpin:
  6197. intel_unpin_fb_obj(obj);
  6198. err:
  6199. return ret;
  6200. }
  6201. /*
  6202. * On gen7 we currently use the blit ring because (in early silicon at least)
  6203. * the render ring doesn't give us interrpts for page flip completion, which
  6204. * means clients will hang after the first flip is queued. Fortunately the
  6205. * blit ring generates interrupts properly, so use it instead.
  6206. */
  6207. static int intel_gen7_queue_flip(struct drm_device *dev,
  6208. struct drm_crtc *crtc,
  6209. struct drm_framebuffer *fb,
  6210. struct drm_i915_gem_object *obj)
  6211. {
  6212. struct drm_i915_private *dev_priv = dev->dev_private;
  6213. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6214. struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
  6215. uint32_t plane_bit = 0;
  6216. int ret;
  6217. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6218. if (ret)
  6219. goto err;
  6220. switch(intel_crtc->plane) {
  6221. case PLANE_A:
  6222. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  6223. break;
  6224. case PLANE_B:
  6225. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  6226. break;
  6227. case PLANE_C:
  6228. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  6229. break;
  6230. default:
  6231. WARN_ONCE(1, "unknown plane in flip command\n");
  6232. ret = -ENODEV;
  6233. goto err_unpin;
  6234. }
  6235. ret = intel_ring_begin(ring, 4);
  6236. if (ret)
  6237. goto err_unpin;
  6238. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  6239. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  6240. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  6241. intel_ring_emit(ring, (MI_NOOP));
  6242. intel_mark_page_flip_active(intel_crtc);
  6243. intel_ring_advance(ring);
  6244. return 0;
  6245. err_unpin:
  6246. intel_unpin_fb_obj(obj);
  6247. err:
  6248. return ret;
  6249. }
  6250. static int intel_default_queue_flip(struct drm_device *dev,
  6251. struct drm_crtc *crtc,
  6252. struct drm_framebuffer *fb,
  6253. struct drm_i915_gem_object *obj)
  6254. {
  6255. return -ENODEV;
  6256. }
  6257. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  6258. struct drm_framebuffer *fb,
  6259. struct drm_pending_vblank_event *event)
  6260. {
  6261. struct drm_device *dev = crtc->dev;
  6262. struct drm_i915_private *dev_priv = dev->dev_private;
  6263. struct drm_framebuffer *old_fb = crtc->fb;
  6264. struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
  6265. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6266. struct intel_unpin_work *work;
  6267. unsigned long flags;
  6268. int ret;
  6269. /* Can't change pixel format via MI display flips. */
  6270. if (fb->pixel_format != crtc->fb->pixel_format)
  6271. return -EINVAL;
  6272. /*
  6273. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  6274. * Note that pitch changes could also affect these register.
  6275. */
  6276. if (INTEL_INFO(dev)->gen > 3 &&
  6277. (fb->offsets[0] != crtc->fb->offsets[0] ||
  6278. fb->pitches[0] != crtc->fb->pitches[0]))
  6279. return -EINVAL;
  6280. work = kzalloc(sizeof *work, GFP_KERNEL);
  6281. if (work == NULL)
  6282. return -ENOMEM;
  6283. work->event = event;
  6284. work->crtc = crtc;
  6285. work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
  6286. INIT_WORK(&work->work, intel_unpin_work_fn);
  6287. ret = drm_vblank_get(dev, intel_crtc->pipe);
  6288. if (ret)
  6289. goto free_work;
  6290. /* We borrow the event spin lock for protecting unpin_work */
  6291. spin_lock_irqsave(&dev->event_lock, flags);
  6292. if (intel_crtc->unpin_work) {
  6293. spin_unlock_irqrestore(&dev->event_lock, flags);
  6294. kfree(work);
  6295. drm_vblank_put(dev, intel_crtc->pipe);
  6296. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  6297. return -EBUSY;
  6298. }
  6299. intel_crtc->unpin_work = work;
  6300. spin_unlock_irqrestore(&dev->event_lock, flags);
  6301. if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  6302. flush_workqueue(dev_priv->wq);
  6303. ret = i915_mutex_lock_interruptible(dev);
  6304. if (ret)
  6305. goto cleanup;
  6306. /* Reference the objects for the scheduled work. */
  6307. drm_gem_object_reference(&work->old_fb_obj->base);
  6308. drm_gem_object_reference(&obj->base);
  6309. crtc->fb = fb;
  6310. work->pending_flip_obj = obj;
  6311. work->enable_stall_check = true;
  6312. atomic_inc(&intel_crtc->unpin_work_count);
  6313. intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  6314. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
  6315. if (ret)
  6316. goto cleanup_pending;
  6317. intel_disable_fbc(dev);
  6318. intel_mark_fb_busy(obj);
  6319. mutex_unlock(&dev->struct_mutex);
  6320. trace_i915_flip_request(intel_crtc->plane, obj);
  6321. return 0;
  6322. cleanup_pending:
  6323. atomic_dec(&intel_crtc->unpin_work_count);
  6324. crtc->fb = old_fb;
  6325. drm_gem_object_unreference(&work->old_fb_obj->base);
  6326. drm_gem_object_unreference(&obj->base);
  6327. mutex_unlock(&dev->struct_mutex);
  6328. cleanup:
  6329. spin_lock_irqsave(&dev->event_lock, flags);
  6330. intel_crtc->unpin_work = NULL;
  6331. spin_unlock_irqrestore(&dev->event_lock, flags);
  6332. drm_vblank_put(dev, intel_crtc->pipe);
  6333. free_work:
  6334. kfree(work);
  6335. return ret;
  6336. }
  6337. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  6338. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  6339. .load_lut = intel_crtc_load_lut,
  6340. };
  6341. bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
  6342. {
  6343. struct intel_encoder *other_encoder;
  6344. struct drm_crtc *crtc = &encoder->new_crtc->base;
  6345. if (WARN_ON(!crtc))
  6346. return false;
  6347. list_for_each_entry(other_encoder,
  6348. &crtc->dev->mode_config.encoder_list,
  6349. base.head) {
  6350. if (&other_encoder->new_crtc->base != crtc ||
  6351. encoder == other_encoder)
  6352. continue;
  6353. else
  6354. return true;
  6355. }
  6356. return false;
  6357. }
  6358. static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
  6359. struct drm_crtc *crtc)
  6360. {
  6361. struct drm_device *dev;
  6362. struct drm_crtc *tmp;
  6363. int crtc_mask = 1;
  6364. WARN(!crtc, "checking null crtc?\n");
  6365. dev = crtc->dev;
  6366. list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
  6367. if (tmp == crtc)
  6368. break;
  6369. crtc_mask <<= 1;
  6370. }
  6371. if (encoder->possible_crtcs & crtc_mask)
  6372. return true;
  6373. return false;
  6374. }
  6375. /**
  6376. * intel_modeset_update_staged_output_state
  6377. *
  6378. * Updates the staged output configuration state, e.g. after we've read out the
  6379. * current hw state.
  6380. */
  6381. static void intel_modeset_update_staged_output_state(struct drm_device *dev)
  6382. {
  6383. struct intel_encoder *encoder;
  6384. struct intel_connector *connector;
  6385. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6386. base.head) {
  6387. connector->new_encoder =
  6388. to_intel_encoder(connector->base.encoder);
  6389. }
  6390. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6391. base.head) {
  6392. encoder->new_crtc =
  6393. to_intel_crtc(encoder->base.crtc);
  6394. }
  6395. }
  6396. /**
  6397. * intel_modeset_commit_output_state
  6398. *
  6399. * This function copies the stage display pipe configuration to the real one.
  6400. */
  6401. static void intel_modeset_commit_output_state(struct drm_device *dev)
  6402. {
  6403. struct intel_encoder *encoder;
  6404. struct intel_connector *connector;
  6405. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6406. base.head) {
  6407. connector->base.encoder = &connector->new_encoder->base;
  6408. }
  6409. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6410. base.head) {
  6411. encoder->base.crtc = &encoder->new_crtc->base;
  6412. }
  6413. }
  6414. static int
  6415. pipe_config_set_bpp(struct drm_crtc *crtc,
  6416. struct drm_framebuffer *fb,
  6417. struct intel_crtc_config *pipe_config)
  6418. {
  6419. struct drm_device *dev = crtc->dev;
  6420. struct drm_connector *connector;
  6421. int bpp;
  6422. switch (fb->pixel_format) {
  6423. case DRM_FORMAT_C8:
  6424. bpp = 8*3; /* since we go through a colormap */
  6425. break;
  6426. case DRM_FORMAT_XRGB1555:
  6427. case DRM_FORMAT_ARGB1555:
  6428. /* checked in intel_framebuffer_init already */
  6429. if (WARN_ON(INTEL_INFO(dev)->gen > 3))
  6430. return -EINVAL;
  6431. case DRM_FORMAT_RGB565:
  6432. bpp = 6*3; /* min is 18bpp */
  6433. break;
  6434. case DRM_FORMAT_XBGR8888:
  6435. case DRM_FORMAT_ABGR8888:
  6436. /* checked in intel_framebuffer_init already */
  6437. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  6438. return -EINVAL;
  6439. case DRM_FORMAT_XRGB8888:
  6440. case DRM_FORMAT_ARGB8888:
  6441. bpp = 8*3;
  6442. break;
  6443. case DRM_FORMAT_XRGB2101010:
  6444. case DRM_FORMAT_ARGB2101010:
  6445. case DRM_FORMAT_XBGR2101010:
  6446. case DRM_FORMAT_ABGR2101010:
  6447. /* checked in intel_framebuffer_init already */
  6448. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  6449. return -EINVAL;
  6450. bpp = 10*3;
  6451. break;
  6452. /* TODO: gen4+ supports 16 bpc floating point, too. */
  6453. default:
  6454. DRM_DEBUG_KMS("unsupported depth\n");
  6455. return -EINVAL;
  6456. }
  6457. pipe_config->pipe_bpp = bpp;
  6458. /* Clamp display bpp to EDID value */
  6459. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6460. head) {
  6461. if (connector->encoder && connector->encoder->crtc != crtc)
  6462. continue;
  6463. /* Don't use an invalid EDID bpc value */
  6464. if (connector->display_info.bpc &&
  6465. connector->display_info.bpc * 3 < bpp) {
  6466. DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
  6467. bpp, connector->display_info.bpc*3);
  6468. pipe_config->pipe_bpp = connector->display_info.bpc*3;
  6469. }
  6470. /* Clamp bpp to 8 on screens without EDID 1.4 */
  6471. if (connector->display_info.bpc == 0 && bpp > 24) {
  6472. DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
  6473. bpp);
  6474. pipe_config->pipe_bpp = 24;
  6475. }
  6476. }
  6477. return bpp;
  6478. }
  6479. static struct intel_crtc_config *
  6480. intel_modeset_pipe_config(struct drm_crtc *crtc,
  6481. struct drm_framebuffer *fb,
  6482. struct drm_display_mode *mode)
  6483. {
  6484. struct drm_device *dev = crtc->dev;
  6485. struct drm_encoder_helper_funcs *encoder_funcs;
  6486. struct intel_encoder *encoder;
  6487. struct intel_crtc_config *pipe_config;
  6488. int plane_bpp;
  6489. pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
  6490. if (!pipe_config)
  6491. return ERR_PTR(-ENOMEM);
  6492. drm_mode_copy(&pipe_config->adjusted_mode, mode);
  6493. drm_mode_copy(&pipe_config->requested_mode, mode);
  6494. plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
  6495. if (plane_bpp < 0)
  6496. goto fail;
  6497. /* Pass our mode to the connectors and the CRTC to give them a chance to
  6498. * adjust it according to limitations or connector properties, and also
  6499. * a chance to reject the mode entirely.
  6500. */
  6501. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6502. base.head) {
  6503. if (&encoder->new_crtc->base != crtc)
  6504. continue;
  6505. if (encoder->compute_config) {
  6506. if (!(encoder->compute_config(encoder, pipe_config))) {
  6507. DRM_DEBUG_KMS("Encoder config failure\n");
  6508. goto fail;
  6509. }
  6510. continue;
  6511. }
  6512. encoder_funcs = encoder->base.helper_private;
  6513. if (!(encoder_funcs->mode_fixup(&encoder->base,
  6514. &pipe_config->requested_mode,
  6515. &pipe_config->adjusted_mode))) {
  6516. DRM_DEBUG_KMS("Encoder fixup failed\n");
  6517. goto fail;
  6518. }
  6519. }
  6520. if (!(intel_crtc_compute_config(crtc, pipe_config))) {
  6521. DRM_DEBUG_KMS("CRTC fixup failed\n");
  6522. goto fail;
  6523. }
  6524. DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
  6525. pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
  6526. DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
  6527. plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
  6528. return pipe_config;
  6529. fail:
  6530. kfree(pipe_config);
  6531. return ERR_PTR(-EINVAL);
  6532. }
  6533. /* Computes which crtcs are affected and sets the relevant bits in the mask. For
  6534. * simplicity we use the crtc's pipe number (because it's easier to obtain). */
  6535. static void
  6536. intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
  6537. unsigned *prepare_pipes, unsigned *disable_pipes)
  6538. {
  6539. struct intel_crtc *intel_crtc;
  6540. struct drm_device *dev = crtc->dev;
  6541. struct intel_encoder *encoder;
  6542. struct intel_connector *connector;
  6543. struct drm_crtc *tmp_crtc;
  6544. *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
  6545. /* Check which crtcs have changed outputs connected to them, these need
  6546. * to be part of the prepare_pipes mask. We don't (yet) support global
  6547. * modeset across multiple crtcs, so modeset_pipes will only have one
  6548. * bit set at most. */
  6549. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6550. base.head) {
  6551. if (connector->base.encoder == &connector->new_encoder->base)
  6552. continue;
  6553. if (connector->base.encoder) {
  6554. tmp_crtc = connector->base.encoder->crtc;
  6555. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  6556. }
  6557. if (connector->new_encoder)
  6558. *prepare_pipes |=
  6559. 1 << connector->new_encoder->new_crtc->pipe;
  6560. }
  6561. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6562. base.head) {
  6563. if (encoder->base.crtc == &encoder->new_crtc->base)
  6564. continue;
  6565. if (encoder->base.crtc) {
  6566. tmp_crtc = encoder->base.crtc;
  6567. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  6568. }
  6569. if (encoder->new_crtc)
  6570. *prepare_pipes |= 1 << encoder->new_crtc->pipe;
  6571. }
  6572. /* Check for any pipes that will be fully disabled ... */
  6573. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  6574. base.head) {
  6575. bool used = false;
  6576. /* Don't try to disable disabled crtcs. */
  6577. if (!intel_crtc->base.enabled)
  6578. continue;
  6579. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6580. base.head) {
  6581. if (encoder->new_crtc == intel_crtc)
  6582. used = true;
  6583. }
  6584. if (!used)
  6585. *disable_pipes |= 1 << intel_crtc->pipe;
  6586. }
  6587. /* set_mode is also used to update properties on life display pipes. */
  6588. intel_crtc = to_intel_crtc(crtc);
  6589. if (crtc->enabled)
  6590. *prepare_pipes |= 1 << intel_crtc->pipe;
  6591. /*
  6592. * For simplicity do a full modeset on any pipe where the output routing
  6593. * changed. We could be more clever, but that would require us to be
  6594. * more careful with calling the relevant encoder->mode_set functions.
  6595. */
  6596. if (*prepare_pipes)
  6597. *modeset_pipes = *prepare_pipes;
  6598. /* ... and mask these out. */
  6599. *modeset_pipes &= ~(*disable_pipes);
  6600. *prepare_pipes &= ~(*disable_pipes);
  6601. /*
  6602. * HACK: We don't (yet) fully support global modesets. intel_set_config
  6603. * obies this rule, but the modeset restore mode of
  6604. * intel_modeset_setup_hw_state does not.
  6605. */
  6606. *modeset_pipes &= 1 << intel_crtc->pipe;
  6607. *prepare_pipes &= 1 << intel_crtc->pipe;
  6608. DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
  6609. *modeset_pipes, *prepare_pipes, *disable_pipes);
  6610. }
  6611. static bool intel_crtc_in_use(struct drm_crtc *crtc)
  6612. {
  6613. struct drm_encoder *encoder;
  6614. struct drm_device *dev = crtc->dev;
  6615. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
  6616. if (encoder->crtc == crtc)
  6617. return true;
  6618. return false;
  6619. }
  6620. static void
  6621. intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
  6622. {
  6623. struct intel_encoder *intel_encoder;
  6624. struct intel_crtc *intel_crtc;
  6625. struct drm_connector *connector;
  6626. list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
  6627. base.head) {
  6628. if (!intel_encoder->base.crtc)
  6629. continue;
  6630. intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  6631. if (prepare_pipes & (1 << intel_crtc->pipe))
  6632. intel_encoder->connectors_active = false;
  6633. }
  6634. intel_modeset_commit_output_state(dev);
  6635. /* Update computed state. */
  6636. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  6637. base.head) {
  6638. intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
  6639. }
  6640. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  6641. if (!connector->encoder || !connector->encoder->crtc)
  6642. continue;
  6643. intel_crtc = to_intel_crtc(connector->encoder->crtc);
  6644. if (prepare_pipes & (1 << intel_crtc->pipe)) {
  6645. struct drm_property *dpms_property =
  6646. dev->mode_config.dpms_property;
  6647. connector->dpms = DRM_MODE_DPMS_ON;
  6648. drm_object_property_set_value(&connector->base,
  6649. dpms_property,
  6650. DRM_MODE_DPMS_ON);
  6651. intel_encoder = to_intel_encoder(connector->encoder);
  6652. intel_encoder->connectors_active = true;
  6653. }
  6654. }
  6655. }
  6656. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  6657. list_for_each_entry((intel_crtc), \
  6658. &(dev)->mode_config.crtc_list, \
  6659. base.head) \
  6660. if (mask & (1 <<(intel_crtc)->pipe)) \
  6661. static bool
  6662. intel_pipe_config_compare(struct intel_crtc_config *current_config,
  6663. struct intel_crtc_config *pipe_config)
  6664. {
  6665. if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
  6666. DRM_ERROR("mismatch in has_pch_encoder "
  6667. "(expected %i, found %i)\n",
  6668. current_config->has_pch_encoder,
  6669. pipe_config->has_pch_encoder);
  6670. return false;
  6671. }
  6672. return true;
  6673. }
  6674. void
  6675. intel_modeset_check_state(struct drm_device *dev)
  6676. {
  6677. drm_i915_private_t *dev_priv = dev->dev_private;
  6678. struct intel_crtc *crtc;
  6679. struct intel_encoder *encoder;
  6680. struct intel_connector *connector;
  6681. struct intel_crtc_config pipe_config;
  6682. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6683. base.head) {
  6684. /* This also checks the encoder/connector hw state with the
  6685. * ->get_hw_state callbacks. */
  6686. intel_connector_check_state(connector);
  6687. WARN(&connector->new_encoder->base != connector->base.encoder,
  6688. "connector's staged encoder doesn't match current encoder\n");
  6689. }
  6690. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6691. base.head) {
  6692. bool enabled = false;
  6693. bool active = false;
  6694. enum pipe pipe, tracked_pipe;
  6695. DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  6696. encoder->base.base.id,
  6697. drm_get_encoder_name(&encoder->base));
  6698. WARN(&encoder->new_crtc->base != encoder->base.crtc,
  6699. "encoder's stage crtc doesn't match current crtc\n");
  6700. WARN(encoder->connectors_active && !encoder->base.crtc,
  6701. "encoder's active_connectors set, but no crtc\n");
  6702. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6703. base.head) {
  6704. if (connector->base.encoder != &encoder->base)
  6705. continue;
  6706. enabled = true;
  6707. if (connector->base.dpms != DRM_MODE_DPMS_OFF)
  6708. active = true;
  6709. }
  6710. WARN(!!encoder->base.crtc != enabled,
  6711. "encoder's enabled state mismatch "
  6712. "(expected %i, found %i)\n",
  6713. !!encoder->base.crtc, enabled);
  6714. WARN(active && !encoder->base.crtc,
  6715. "active encoder with no crtc\n");
  6716. WARN(encoder->connectors_active != active,
  6717. "encoder's computed active state doesn't match tracked active state "
  6718. "(expected %i, found %i)\n", active, encoder->connectors_active);
  6719. active = encoder->get_hw_state(encoder, &pipe);
  6720. WARN(active != encoder->connectors_active,
  6721. "encoder's hw state doesn't match sw tracking "
  6722. "(expected %i, found %i)\n",
  6723. encoder->connectors_active, active);
  6724. if (!encoder->base.crtc)
  6725. continue;
  6726. tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  6727. WARN(active && pipe != tracked_pipe,
  6728. "active encoder's pipe doesn't match"
  6729. "(expected %i, found %i)\n",
  6730. tracked_pipe, pipe);
  6731. }
  6732. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  6733. base.head) {
  6734. bool enabled = false;
  6735. bool active = false;
  6736. DRM_DEBUG_KMS("[CRTC:%d]\n",
  6737. crtc->base.base.id);
  6738. WARN(crtc->active && !crtc->base.enabled,
  6739. "active crtc, but not enabled in sw tracking\n");
  6740. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6741. base.head) {
  6742. if (encoder->base.crtc != &crtc->base)
  6743. continue;
  6744. enabled = true;
  6745. if (encoder->connectors_active)
  6746. active = true;
  6747. }
  6748. WARN(active != crtc->active,
  6749. "crtc's computed active state doesn't match tracked active state "
  6750. "(expected %i, found %i)\n", active, crtc->active);
  6751. WARN(enabled != crtc->base.enabled,
  6752. "crtc's computed enabled state doesn't match tracked enabled state "
  6753. "(expected %i, found %i)\n", enabled, crtc->base.enabled);
  6754. memset(&pipe_config, 0, sizeof(pipe_config));
  6755. active = dev_priv->display.get_pipe_config(crtc,
  6756. &pipe_config);
  6757. WARN(crtc->active != active,
  6758. "crtc active state doesn't match with hw state "
  6759. "(expected %i, found %i)\n", crtc->active, active);
  6760. WARN(active &&
  6761. !intel_pipe_config_compare(&crtc->config, &pipe_config),
  6762. "pipe state doesn't match!\n");
  6763. }
  6764. }
  6765. static int __intel_set_mode(struct drm_crtc *crtc,
  6766. struct drm_display_mode *mode,
  6767. int x, int y, struct drm_framebuffer *fb)
  6768. {
  6769. struct drm_device *dev = crtc->dev;
  6770. drm_i915_private_t *dev_priv = dev->dev_private;
  6771. struct drm_display_mode *saved_mode, *saved_hwmode;
  6772. struct intel_crtc_config *pipe_config = NULL;
  6773. struct intel_crtc *intel_crtc;
  6774. unsigned disable_pipes, prepare_pipes, modeset_pipes;
  6775. int ret = 0;
  6776. saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
  6777. if (!saved_mode)
  6778. return -ENOMEM;
  6779. saved_hwmode = saved_mode + 1;
  6780. intel_modeset_affected_pipes(crtc, &modeset_pipes,
  6781. &prepare_pipes, &disable_pipes);
  6782. *saved_hwmode = crtc->hwmode;
  6783. *saved_mode = crtc->mode;
  6784. /* Hack: Because we don't (yet) support global modeset on multiple
  6785. * crtcs, we don't keep track of the new mode for more than one crtc.
  6786. * Hence simply check whether any bit is set in modeset_pipes in all the
  6787. * pieces of code that are not yet converted to deal with mutliple crtcs
  6788. * changing their mode at the same time. */
  6789. if (modeset_pipes) {
  6790. pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
  6791. if (IS_ERR(pipe_config)) {
  6792. ret = PTR_ERR(pipe_config);
  6793. pipe_config = NULL;
  6794. goto out;
  6795. }
  6796. }
  6797. for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
  6798. intel_crtc_disable(&intel_crtc->base);
  6799. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
  6800. if (intel_crtc->base.enabled)
  6801. dev_priv->display.crtc_disable(&intel_crtc->base);
  6802. }
  6803. /* crtc->mode is already used by the ->mode_set callbacks, hence we need
  6804. * to set it here already despite that we pass it down the callchain.
  6805. */
  6806. if (modeset_pipes) {
  6807. enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
  6808. crtc->mode = *mode;
  6809. /* mode_set/enable/disable functions rely on a correct pipe
  6810. * config. */
  6811. to_intel_crtc(crtc)->config = *pipe_config;
  6812. to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
  6813. }
  6814. /* Only after disabling all output pipelines that will be changed can we
  6815. * update the the output configuration. */
  6816. intel_modeset_update_state(dev, prepare_pipes);
  6817. if (dev_priv->display.modeset_global_resources)
  6818. dev_priv->display.modeset_global_resources(dev);
  6819. /* Set up the DPLL and any encoders state that needs to adjust or depend
  6820. * on the DPLL.
  6821. */
  6822. for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
  6823. ret = intel_crtc_mode_set(&intel_crtc->base,
  6824. x, y, fb);
  6825. if (ret)
  6826. goto done;
  6827. }
  6828. /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  6829. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
  6830. dev_priv->display.crtc_enable(&intel_crtc->base);
  6831. if (modeset_pipes) {
  6832. /* Store real post-adjustment hardware mode. */
  6833. crtc->hwmode = pipe_config->adjusted_mode;
  6834. /* Calculate and store various constants which
  6835. * are later needed by vblank and swap-completion
  6836. * timestamping. They are derived from true hwmode.
  6837. */
  6838. drm_calc_timestamping_constants(crtc);
  6839. }
  6840. /* FIXME: add subpixel order */
  6841. done:
  6842. if (ret && crtc->enabled) {
  6843. crtc->hwmode = *saved_hwmode;
  6844. crtc->mode = *saved_mode;
  6845. }
  6846. out:
  6847. kfree(pipe_config);
  6848. kfree(saved_mode);
  6849. return ret;
  6850. }
  6851. int intel_set_mode(struct drm_crtc *crtc,
  6852. struct drm_display_mode *mode,
  6853. int x, int y, struct drm_framebuffer *fb)
  6854. {
  6855. int ret;
  6856. ret = __intel_set_mode(crtc, mode, x, y, fb);
  6857. if (ret == 0)
  6858. intel_modeset_check_state(crtc->dev);
  6859. return ret;
  6860. }
  6861. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  6862. {
  6863. intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
  6864. }
  6865. #undef for_each_intel_crtc_masked
  6866. static void intel_set_config_free(struct intel_set_config *config)
  6867. {
  6868. if (!config)
  6869. return;
  6870. kfree(config->save_connector_encoders);
  6871. kfree(config->save_encoder_crtcs);
  6872. kfree(config);
  6873. }
  6874. static int intel_set_config_save_state(struct drm_device *dev,
  6875. struct intel_set_config *config)
  6876. {
  6877. struct drm_encoder *encoder;
  6878. struct drm_connector *connector;
  6879. int count;
  6880. config->save_encoder_crtcs =
  6881. kcalloc(dev->mode_config.num_encoder,
  6882. sizeof(struct drm_crtc *), GFP_KERNEL);
  6883. if (!config->save_encoder_crtcs)
  6884. return -ENOMEM;
  6885. config->save_connector_encoders =
  6886. kcalloc(dev->mode_config.num_connector,
  6887. sizeof(struct drm_encoder *), GFP_KERNEL);
  6888. if (!config->save_connector_encoders)
  6889. return -ENOMEM;
  6890. /* Copy data. Note that driver private data is not affected.
  6891. * Should anything bad happen only the expected state is
  6892. * restored, not the drivers personal bookkeeping.
  6893. */
  6894. count = 0;
  6895. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  6896. config->save_encoder_crtcs[count++] = encoder->crtc;
  6897. }
  6898. count = 0;
  6899. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  6900. config->save_connector_encoders[count++] = connector->encoder;
  6901. }
  6902. return 0;
  6903. }
  6904. static void intel_set_config_restore_state(struct drm_device *dev,
  6905. struct intel_set_config *config)
  6906. {
  6907. struct intel_encoder *encoder;
  6908. struct intel_connector *connector;
  6909. int count;
  6910. count = 0;
  6911. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  6912. encoder->new_crtc =
  6913. to_intel_crtc(config->save_encoder_crtcs[count++]);
  6914. }
  6915. count = 0;
  6916. list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
  6917. connector->new_encoder =
  6918. to_intel_encoder(config->save_connector_encoders[count++]);
  6919. }
  6920. }
  6921. static void
  6922. intel_set_config_compute_mode_changes(struct drm_mode_set *set,
  6923. struct intel_set_config *config)
  6924. {
  6925. /* We should be able to check here if the fb has the same properties
  6926. * and then just flip_or_move it */
  6927. if (set->crtc->fb != set->fb) {
  6928. /* If we have no fb then treat it as a full mode set */
  6929. if (set->crtc->fb == NULL) {
  6930. DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
  6931. config->mode_changed = true;
  6932. } else if (set->fb == NULL) {
  6933. config->mode_changed = true;
  6934. } else if (set->fb->pixel_format !=
  6935. set->crtc->fb->pixel_format) {
  6936. config->mode_changed = true;
  6937. } else
  6938. config->fb_changed = true;
  6939. }
  6940. if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
  6941. config->fb_changed = true;
  6942. if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
  6943. DRM_DEBUG_KMS("modes are different, full mode set\n");
  6944. drm_mode_debug_printmodeline(&set->crtc->mode);
  6945. drm_mode_debug_printmodeline(set->mode);
  6946. config->mode_changed = true;
  6947. }
  6948. }
  6949. static int
  6950. intel_modeset_stage_output_state(struct drm_device *dev,
  6951. struct drm_mode_set *set,
  6952. struct intel_set_config *config)
  6953. {
  6954. struct drm_crtc *new_crtc;
  6955. struct intel_connector *connector;
  6956. struct intel_encoder *encoder;
  6957. int count, ro;
  6958. /* The upper layers ensure that we either disable a crtc or have a list
  6959. * of connectors. For paranoia, double-check this. */
  6960. WARN_ON(!set->fb && (set->num_connectors != 0));
  6961. WARN_ON(set->fb && (set->num_connectors == 0));
  6962. count = 0;
  6963. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6964. base.head) {
  6965. /* Otherwise traverse passed in connector list and get encoders
  6966. * for them. */
  6967. for (ro = 0; ro < set->num_connectors; ro++) {
  6968. if (set->connectors[ro] == &connector->base) {
  6969. connector->new_encoder = connector->encoder;
  6970. break;
  6971. }
  6972. }
  6973. /* If we disable the crtc, disable all its connectors. Also, if
  6974. * the connector is on the changing crtc but not on the new
  6975. * connector list, disable it. */
  6976. if ((!set->fb || ro == set->num_connectors) &&
  6977. connector->base.encoder &&
  6978. connector->base.encoder->crtc == set->crtc) {
  6979. connector->new_encoder = NULL;
  6980. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
  6981. connector->base.base.id,
  6982. drm_get_connector_name(&connector->base));
  6983. }
  6984. if (&connector->new_encoder->base != connector->base.encoder) {
  6985. DRM_DEBUG_KMS("encoder changed, full mode switch\n");
  6986. config->mode_changed = true;
  6987. }
  6988. }
  6989. /* connector->new_encoder is now updated for all connectors. */
  6990. /* Update crtc of enabled connectors. */
  6991. count = 0;
  6992. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6993. base.head) {
  6994. if (!connector->new_encoder)
  6995. continue;
  6996. new_crtc = connector->new_encoder->base.crtc;
  6997. for (ro = 0; ro < set->num_connectors; ro++) {
  6998. if (set->connectors[ro] == &connector->base)
  6999. new_crtc = set->crtc;
  7000. }
  7001. /* Make sure the new CRTC will work with the encoder */
  7002. if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
  7003. new_crtc)) {
  7004. return -EINVAL;
  7005. }
  7006. connector->encoder->new_crtc = to_intel_crtc(new_crtc);
  7007. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
  7008. connector->base.base.id,
  7009. drm_get_connector_name(&connector->base),
  7010. new_crtc->base.id);
  7011. }
  7012. /* Check for any encoders that needs to be disabled. */
  7013. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7014. base.head) {
  7015. list_for_each_entry(connector,
  7016. &dev->mode_config.connector_list,
  7017. base.head) {
  7018. if (connector->new_encoder == encoder) {
  7019. WARN_ON(!connector->new_encoder->new_crtc);
  7020. goto next_encoder;
  7021. }
  7022. }
  7023. encoder->new_crtc = NULL;
  7024. next_encoder:
  7025. /* Only now check for crtc changes so we don't miss encoders
  7026. * that will be disabled. */
  7027. if (&encoder->new_crtc->base != encoder->base.crtc) {
  7028. DRM_DEBUG_KMS("crtc changed, full mode switch\n");
  7029. config->mode_changed = true;
  7030. }
  7031. }
  7032. /* Now we've also updated encoder->new_crtc for all encoders. */
  7033. return 0;
  7034. }
  7035. static int intel_crtc_set_config(struct drm_mode_set *set)
  7036. {
  7037. struct drm_device *dev;
  7038. struct drm_mode_set save_set;
  7039. struct intel_set_config *config;
  7040. int ret;
  7041. BUG_ON(!set);
  7042. BUG_ON(!set->crtc);
  7043. BUG_ON(!set->crtc->helper_private);
  7044. /* Enforce sane interface api - has been abused by the fb helper. */
  7045. BUG_ON(!set->mode && set->fb);
  7046. BUG_ON(set->fb && set->num_connectors == 0);
  7047. if (set->fb) {
  7048. DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
  7049. set->crtc->base.id, set->fb->base.id,
  7050. (int)set->num_connectors, set->x, set->y);
  7051. } else {
  7052. DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
  7053. }
  7054. dev = set->crtc->dev;
  7055. ret = -ENOMEM;
  7056. config = kzalloc(sizeof(*config), GFP_KERNEL);
  7057. if (!config)
  7058. goto out_config;
  7059. ret = intel_set_config_save_state(dev, config);
  7060. if (ret)
  7061. goto out_config;
  7062. save_set.crtc = set->crtc;
  7063. save_set.mode = &set->crtc->mode;
  7064. save_set.x = set->crtc->x;
  7065. save_set.y = set->crtc->y;
  7066. save_set.fb = set->crtc->fb;
  7067. /* Compute whether we need a full modeset, only an fb base update or no
  7068. * change at all. In the future we might also check whether only the
  7069. * mode changed, e.g. for LVDS where we only change the panel fitter in
  7070. * such cases. */
  7071. intel_set_config_compute_mode_changes(set, config);
  7072. ret = intel_modeset_stage_output_state(dev, set, config);
  7073. if (ret)
  7074. goto fail;
  7075. if (config->mode_changed) {
  7076. if (set->mode) {
  7077. DRM_DEBUG_KMS("attempting to set mode from"
  7078. " userspace\n");
  7079. drm_mode_debug_printmodeline(set->mode);
  7080. }
  7081. ret = intel_set_mode(set->crtc, set->mode,
  7082. set->x, set->y, set->fb);
  7083. if (ret) {
  7084. DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
  7085. set->crtc->base.id, ret);
  7086. goto fail;
  7087. }
  7088. } else if (config->fb_changed) {
  7089. intel_crtc_wait_for_pending_flips(set->crtc);
  7090. ret = intel_pipe_set_base(set->crtc,
  7091. set->x, set->y, set->fb);
  7092. }
  7093. intel_set_config_free(config);
  7094. return 0;
  7095. fail:
  7096. intel_set_config_restore_state(dev, config);
  7097. /* Try to restore the config */
  7098. if (config->mode_changed &&
  7099. intel_set_mode(save_set.crtc, save_set.mode,
  7100. save_set.x, save_set.y, save_set.fb))
  7101. DRM_ERROR("failed to restore config after modeset failure\n");
  7102. out_config:
  7103. intel_set_config_free(config);
  7104. return ret;
  7105. }
  7106. static const struct drm_crtc_funcs intel_crtc_funcs = {
  7107. .cursor_set = intel_crtc_cursor_set,
  7108. .cursor_move = intel_crtc_cursor_move,
  7109. .gamma_set = intel_crtc_gamma_set,
  7110. .set_config = intel_crtc_set_config,
  7111. .destroy = intel_crtc_destroy,
  7112. .page_flip = intel_crtc_page_flip,
  7113. };
  7114. static void intel_cpu_pll_init(struct drm_device *dev)
  7115. {
  7116. if (HAS_DDI(dev))
  7117. intel_ddi_pll_init(dev);
  7118. }
  7119. static void intel_pch_pll_init(struct drm_device *dev)
  7120. {
  7121. drm_i915_private_t *dev_priv = dev->dev_private;
  7122. int i;
  7123. if (dev_priv->num_pch_pll == 0) {
  7124. DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
  7125. return;
  7126. }
  7127. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  7128. dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
  7129. dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
  7130. dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
  7131. }
  7132. }
  7133. static void intel_crtc_init(struct drm_device *dev, int pipe)
  7134. {
  7135. drm_i915_private_t *dev_priv = dev->dev_private;
  7136. struct intel_crtc *intel_crtc;
  7137. int i;
  7138. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  7139. if (intel_crtc == NULL)
  7140. return;
  7141. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  7142. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  7143. for (i = 0; i < 256; i++) {
  7144. intel_crtc->lut_r[i] = i;
  7145. intel_crtc->lut_g[i] = i;
  7146. intel_crtc->lut_b[i] = i;
  7147. }
  7148. /* Swap pipes & planes for FBC on pre-965 */
  7149. intel_crtc->pipe = pipe;
  7150. intel_crtc->plane = pipe;
  7151. intel_crtc->config.cpu_transcoder = pipe;
  7152. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  7153. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  7154. intel_crtc->plane = !pipe;
  7155. }
  7156. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  7157. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  7158. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  7159. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  7160. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  7161. }
  7162. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  7163. struct drm_file *file)
  7164. {
  7165. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  7166. struct drm_mode_object *drmmode_obj;
  7167. struct intel_crtc *crtc;
  7168. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  7169. return -ENODEV;
  7170. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  7171. DRM_MODE_OBJECT_CRTC);
  7172. if (!drmmode_obj) {
  7173. DRM_ERROR("no such CRTC id\n");
  7174. return -EINVAL;
  7175. }
  7176. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  7177. pipe_from_crtc_id->pipe = crtc->pipe;
  7178. return 0;
  7179. }
  7180. static int intel_encoder_clones(struct intel_encoder *encoder)
  7181. {
  7182. struct drm_device *dev = encoder->base.dev;
  7183. struct intel_encoder *source_encoder;
  7184. int index_mask = 0;
  7185. int entry = 0;
  7186. list_for_each_entry(source_encoder,
  7187. &dev->mode_config.encoder_list, base.head) {
  7188. if (encoder == source_encoder)
  7189. index_mask |= (1 << entry);
  7190. /* Intel hw has only one MUX where enocoders could be cloned. */
  7191. if (encoder->cloneable && source_encoder->cloneable)
  7192. index_mask |= (1 << entry);
  7193. entry++;
  7194. }
  7195. return index_mask;
  7196. }
  7197. static bool has_edp_a(struct drm_device *dev)
  7198. {
  7199. struct drm_i915_private *dev_priv = dev->dev_private;
  7200. if (!IS_MOBILE(dev))
  7201. return false;
  7202. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  7203. return false;
  7204. if (IS_GEN5(dev) &&
  7205. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  7206. return false;
  7207. return true;
  7208. }
  7209. static void intel_setup_outputs(struct drm_device *dev)
  7210. {
  7211. struct drm_i915_private *dev_priv = dev->dev_private;
  7212. struct intel_encoder *encoder;
  7213. bool dpd_is_edp = false;
  7214. bool has_lvds;
  7215. has_lvds = intel_lvds_init(dev);
  7216. if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
  7217. /* disable the panel fitter on everything but LVDS */
  7218. I915_WRITE(PFIT_CONTROL, 0);
  7219. }
  7220. if (!IS_ULT(dev))
  7221. intel_crt_init(dev);
  7222. if (HAS_DDI(dev)) {
  7223. int found;
  7224. /* Haswell uses DDI functions to detect digital outputs */
  7225. found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  7226. /* DDI A only supports eDP */
  7227. if (found)
  7228. intel_ddi_init(dev, PORT_A);
  7229. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  7230. * register */
  7231. found = I915_READ(SFUSE_STRAP);
  7232. if (found & SFUSE_STRAP_DDIB_DETECTED)
  7233. intel_ddi_init(dev, PORT_B);
  7234. if (found & SFUSE_STRAP_DDIC_DETECTED)
  7235. intel_ddi_init(dev, PORT_C);
  7236. if (found & SFUSE_STRAP_DDID_DETECTED)
  7237. intel_ddi_init(dev, PORT_D);
  7238. } else if (HAS_PCH_SPLIT(dev)) {
  7239. int found;
  7240. dpd_is_edp = intel_dpd_is_edp(dev);
  7241. if (has_edp_a(dev))
  7242. intel_dp_init(dev, DP_A, PORT_A);
  7243. if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
  7244. /* PCH SDVOB multiplex with HDMIB */
  7245. found = intel_sdvo_init(dev, PCH_SDVOB, true);
  7246. if (!found)
  7247. intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
  7248. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  7249. intel_dp_init(dev, PCH_DP_B, PORT_B);
  7250. }
  7251. if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
  7252. intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
  7253. if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
  7254. intel_hdmi_init(dev, PCH_HDMID, PORT_D);
  7255. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  7256. intel_dp_init(dev, PCH_DP_C, PORT_C);
  7257. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  7258. intel_dp_init(dev, PCH_DP_D, PORT_D);
  7259. } else if (IS_VALLEYVIEW(dev)) {
  7260. /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
  7261. if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
  7262. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
  7263. if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
  7264. intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
  7265. PORT_B);
  7266. if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
  7267. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
  7268. }
  7269. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  7270. bool found = false;
  7271. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  7272. DRM_DEBUG_KMS("probing SDVOB\n");
  7273. found = intel_sdvo_init(dev, GEN3_SDVOB, true);
  7274. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  7275. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  7276. intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
  7277. }
  7278. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  7279. DRM_DEBUG_KMS("probing DP_B\n");
  7280. intel_dp_init(dev, DP_B, PORT_B);
  7281. }
  7282. }
  7283. /* Before G4X SDVOC doesn't have its own detect register */
  7284. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  7285. DRM_DEBUG_KMS("probing SDVOC\n");
  7286. found = intel_sdvo_init(dev, GEN3_SDVOC, false);
  7287. }
  7288. if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  7289. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  7290. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  7291. intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
  7292. }
  7293. if (SUPPORTS_INTEGRATED_DP(dev)) {
  7294. DRM_DEBUG_KMS("probing DP_C\n");
  7295. intel_dp_init(dev, DP_C, PORT_C);
  7296. }
  7297. }
  7298. if (SUPPORTS_INTEGRATED_DP(dev) &&
  7299. (I915_READ(DP_D) & DP_DETECTED)) {
  7300. DRM_DEBUG_KMS("probing DP_D\n");
  7301. intel_dp_init(dev, DP_D, PORT_D);
  7302. }
  7303. } else if (IS_GEN2(dev))
  7304. intel_dvo_init(dev);
  7305. if (SUPPORTS_TV(dev))
  7306. intel_tv_init(dev);
  7307. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  7308. encoder->base.possible_crtcs = encoder->crtc_mask;
  7309. encoder->base.possible_clones =
  7310. intel_encoder_clones(encoder);
  7311. }
  7312. intel_init_pch_refclk(dev);
  7313. drm_helper_move_panel_connectors_to_head(dev);
  7314. }
  7315. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  7316. {
  7317. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  7318. drm_framebuffer_cleanup(fb);
  7319. drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
  7320. kfree(intel_fb);
  7321. }
  7322. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  7323. struct drm_file *file,
  7324. unsigned int *handle)
  7325. {
  7326. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  7327. struct drm_i915_gem_object *obj = intel_fb->obj;
  7328. return drm_gem_handle_create(file, &obj->base, handle);
  7329. }
  7330. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  7331. .destroy = intel_user_framebuffer_destroy,
  7332. .create_handle = intel_user_framebuffer_create_handle,
  7333. };
  7334. int intel_framebuffer_init(struct drm_device *dev,
  7335. struct intel_framebuffer *intel_fb,
  7336. struct drm_mode_fb_cmd2 *mode_cmd,
  7337. struct drm_i915_gem_object *obj)
  7338. {
  7339. int ret;
  7340. if (obj->tiling_mode == I915_TILING_Y) {
  7341. DRM_DEBUG("hardware does not support tiling Y\n");
  7342. return -EINVAL;
  7343. }
  7344. if (mode_cmd->pitches[0] & 63) {
  7345. DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
  7346. mode_cmd->pitches[0]);
  7347. return -EINVAL;
  7348. }
  7349. /* FIXME <= Gen4 stride limits are bit unclear */
  7350. if (mode_cmd->pitches[0] > 32768) {
  7351. DRM_DEBUG("pitch (%d) must be at less than 32768\n",
  7352. mode_cmd->pitches[0]);
  7353. return -EINVAL;
  7354. }
  7355. if (obj->tiling_mode != I915_TILING_NONE &&
  7356. mode_cmd->pitches[0] != obj->stride) {
  7357. DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
  7358. mode_cmd->pitches[0], obj->stride);
  7359. return -EINVAL;
  7360. }
  7361. /* Reject formats not supported by any plane early. */
  7362. switch (mode_cmd->pixel_format) {
  7363. case DRM_FORMAT_C8:
  7364. case DRM_FORMAT_RGB565:
  7365. case DRM_FORMAT_XRGB8888:
  7366. case DRM_FORMAT_ARGB8888:
  7367. break;
  7368. case DRM_FORMAT_XRGB1555:
  7369. case DRM_FORMAT_ARGB1555:
  7370. if (INTEL_INFO(dev)->gen > 3) {
  7371. DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
  7372. return -EINVAL;
  7373. }
  7374. break;
  7375. case DRM_FORMAT_XBGR8888:
  7376. case DRM_FORMAT_ABGR8888:
  7377. case DRM_FORMAT_XRGB2101010:
  7378. case DRM_FORMAT_ARGB2101010:
  7379. case DRM_FORMAT_XBGR2101010:
  7380. case DRM_FORMAT_ABGR2101010:
  7381. if (INTEL_INFO(dev)->gen < 4) {
  7382. DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
  7383. return -EINVAL;
  7384. }
  7385. break;
  7386. case DRM_FORMAT_YUYV:
  7387. case DRM_FORMAT_UYVY:
  7388. case DRM_FORMAT_YVYU:
  7389. case DRM_FORMAT_VYUY:
  7390. if (INTEL_INFO(dev)->gen < 5) {
  7391. DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
  7392. return -EINVAL;
  7393. }
  7394. break;
  7395. default:
  7396. DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
  7397. return -EINVAL;
  7398. }
  7399. /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  7400. if (mode_cmd->offsets[0] != 0)
  7401. return -EINVAL;
  7402. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  7403. intel_fb->obj = obj;
  7404. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  7405. if (ret) {
  7406. DRM_ERROR("framebuffer init failed %d\n", ret);
  7407. return ret;
  7408. }
  7409. return 0;
  7410. }
  7411. static struct drm_framebuffer *
  7412. intel_user_framebuffer_create(struct drm_device *dev,
  7413. struct drm_file *filp,
  7414. struct drm_mode_fb_cmd2 *mode_cmd)
  7415. {
  7416. struct drm_i915_gem_object *obj;
  7417. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  7418. mode_cmd->handles[0]));
  7419. if (&obj->base == NULL)
  7420. return ERR_PTR(-ENOENT);
  7421. return intel_framebuffer_create(dev, mode_cmd, obj);
  7422. }
  7423. static const struct drm_mode_config_funcs intel_mode_funcs = {
  7424. .fb_create = intel_user_framebuffer_create,
  7425. .output_poll_changed = intel_fb_output_poll_changed,
  7426. };
  7427. /* Set up chip specific display functions */
  7428. static void intel_init_display(struct drm_device *dev)
  7429. {
  7430. struct drm_i915_private *dev_priv = dev->dev_private;
  7431. if (HAS_DDI(dev)) {
  7432. dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  7433. dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
  7434. dev_priv->display.crtc_enable = haswell_crtc_enable;
  7435. dev_priv->display.crtc_disable = haswell_crtc_disable;
  7436. dev_priv->display.off = haswell_crtc_off;
  7437. dev_priv->display.update_plane = ironlake_update_plane;
  7438. } else if (HAS_PCH_SPLIT(dev)) {
  7439. dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
  7440. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  7441. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  7442. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  7443. dev_priv->display.off = ironlake_crtc_off;
  7444. dev_priv->display.update_plane = ironlake_update_plane;
  7445. } else if (IS_VALLEYVIEW(dev)) {
  7446. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  7447. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  7448. dev_priv->display.crtc_enable = valleyview_crtc_enable;
  7449. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  7450. dev_priv->display.off = i9xx_crtc_off;
  7451. dev_priv->display.update_plane = i9xx_update_plane;
  7452. } else {
  7453. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  7454. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  7455. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  7456. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  7457. dev_priv->display.off = i9xx_crtc_off;
  7458. dev_priv->display.update_plane = i9xx_update_plane;
  7459. }
  7460. /* Returns the core display clock speed */
  7461. if (IS_VALLEYVIEW(dev))
  7462. dev_priv->display.get_display_clock_speed =
  7463. valleyview_get_display_clock_speed;
  7464. else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  7465. dev_priv->display.get_display_clock_speed =
  7466. i945_get_display_clock_speed;
  7467. else if (IS_I915G(dev))
  7468. dev_priv->display.get_display_clock_speed =
  7469. i915_get_display_clock_speed;
  7470. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  7471. dev_priv->display.get_display_clock_speed =
  7472. i9xx_misc_get_display_clock_speed;
  7473. else if (IS_I915GM(dev))
  7474. dev_priv->display.get_display_clock_speed =
  7475. i915gm_get_display_clock_speed;
  7476. else if (IS_I865G(dev))
  7477. dev_priv->display.get_display_clock_speed =
  7478. i865_get_display_clock_speed;
  7479. else if (IS_I85X(dev))
  7480. dev_priv->display.get_display_clock_speed =
  7481. i855_get_display_clock_speed;
  7482. else /* 852, 830 */
  7483. dev_priv->display.get_display_clock_speed =
  7484. i830_get_display_clock_speed;
  7485. if (HAS_PCH_SPLIT(dev)) {
  7486. if (IS_GEN5(dev)) {
  7487. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  7488. dev_priv->display.write_eld = ironlake_write_eld;
  7489. } else if (IS_GEN6(dev)) {
  7490. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  7491. dev_priv->display.write_eld = ironlake_write_eld;
  7492. } else if (IS_IVYBRIDGE(dev)) {
  7493. /* FIXME: detect B0+ stepping and use auto training */
  7494. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  7495. dev_priv->display.write_eld = ironlake_write_eld;
  7496. dev_priv->display.modeset_global_resources =
  7497. ivb_modeset_global_resources;
  7498. } else if (IS_HASWELL(dev)) {
  7499. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  7500. dev_priv->display.write_eld = haswell_write_eld;
  7501. dev_priv->display.modeset_global_resources =
  7502. haswell_modeset_global_resources;
  7503. }
  7504. } else if (IS_G4X(dev)) {
  7505. dev_priv->display.write_eld = g4x_write_eld;
  7506. }
  7507. /* Default just returns -ENODEV to indicate unsupported */
  7508. dev_priv->display.queue_flip = intel_default_queue_flip;
  7509. switch (INTEL_INFO(dev)->gen) {
  7510. case 2:
  7511. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  7512. break;
  7513. case 3:
  7514. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  7515. break;
  7516. case 4:
  7517. case 5:
  7518. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  7519. break;
  7520. case 6:
  7521. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  7522. break;
  7523. case 7:
  7524. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  7525. break;
  7526. }
  7527. }
  7528. /*
  7529. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  7530. * resume, or other times. This quirk makes sure that's the case for
  7531. * affected systems.
  7532. */
  7533. static void quirk_pipea_force(struct drm_device *dev)
  7534. {
  7535. struct drm_i915_private *dev_priv = dev->dev_private;
  7536. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  7537. DRM_INFO("applying pipe a force quirk\n");
  7538. }
  7539. /*
  7540. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  7541. */
  7542. static void quirk_ssc_force_disable(struct drm_device *dev)
  7543. {
  7544. struct drm_i915_private *dev_priv = dev->dev_private;
  7545. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  7546. DRM_INFO("applying lvds SSC disable quirk\n");
  7547. }
  7548. /*
  7549. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  7550. * brightness value
  7551. */
  7552. static void quirk_invert_brightness(struct drm_device *dev)
  7553. {
  7554. struct drm_i915_private *dev_priv = dev->dev_private;
  7555. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  7556. DRM_INFO("applying inverted panel brightness quirk\n");
  7557. }
  7558. struct intel_quirk {
  7559. int device;
  7560. int subsystem_vendor;
  7561. int subsystem_device;
  7562. void (*hook)(struct drm_device *dev);
  7563. };
  7564. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  7565. struct intel_dmi_quirk {
  7566. void (*hook)(struct drm_device *dev);
  7567. const struct dmi_system_id (*dmi_id_list)[];
  7568. };
  7569. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  7570. {
  7571. DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  7572. return 1;
  7573. }
  7574. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  7575. {
  7576. .dmi_id_list = &(const struct dmi_system_id[]) {
  7577. {
  7578. .callback = intel_dmi_reverse_brightness,
  7579. .ident = "NCR Corporation",
  7580. .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  7581. DMI_MATCH(DMI_PRODUCT_NAME, ""),
  7582. },
  7583. },
  7584. { } /* terminating entry */
  7585. },
  7586. .hook = quirk_invert_brightness,
  7587. },
  7588. };
  7589. static struct intel_quirk intel_quirks[] = {
  7590. /* HP Mini needs pipe A force quirk (LP: #322104) */
  7591. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  7592. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  7593. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  7594. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  7595. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  7596. /* 830/845 need to leave pipe A & dpll A up */
  7597. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  7598. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  7599. /* Lenovo U160 cannot use SSC on LVDS */
  7600. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  7601. /* Sony Vaio Y cannot use SSC on LVDS */
  7602. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  7603. /* Acer Aspire 5734Z must invert backlight brightness */
  7604. { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  7605. /* Acer/eMachines G725 */
  7606. { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
  7607. /* Acer/eMachines e725 */
  7608. { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
  7609. /* Acer/Packard Bell NCL20 */
  7610. { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
  7611. /* Acer Aspire 4736Z */
  7612. { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
  7613. };
  7614. static void intel_init_quirks(struct drm_device *dev)
  7615. {
  7616. struct pci_dev *d = dev->pdev;
  7617. int i;
  7618. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  7619. struct intel_quirk *q = &intel_quirks[i];
  7620. if (d->device == q->device &&
  7621. (d->subsystem_vendor == q->subsystem_vendor ||
  7622. q->subsystem_vendor == PCI_ANY_ID) &&
  7623. (d->subsystem_device == q->subsystem_device ||
  7624. q->subsystem_device == PCI_ANY_ID))
  7625. q->hook(dev);
  7626. }
  7627. for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
  7628. if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
  7629. intel_dmi_quirks[i].hook(dev);
  7630. }
  7631. }
  7632. /* Disable the VGA plane that we never use */
  7633. static void i915_disable_vga(struct drm_device *dev)
  7634. {
  7635. struct drm_i915_private *dev_priv = dev->dev_private;
  7636. u8 sr1;
  7637. u32 vga_reg = i915_vgacntrl_reg(dev);
  7638. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  7639. outb(SR01, VGA_SR_INDEX);
  7640. sr1 = inb(VGA_SR_DATA);
  7641. outb(sr1 | 1<<5, VGA_SR_DATA);
  7642. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  7643. udelay(300);
  7644. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  7645. POSTING_READ(vga_reg);
  7646. }
  7647. void intel_modeset_init_hw(struct drm_device *dev)
  7648. {
  7649. intel_init_power_well(dev);
  7650. intel_prepare_ddi(dev);
  7651. intel_init_clock_gating(dev);
  7652. mutex_lock(&dev->struct_mutex);
  7653. intel_enable_gt_powersave(dev);
  7654. mutex_unlock(&dev->struct_mutex);
  7655. }
  7656. void intel_modeset_init(struct drm_device *dev)
  7657. {
  7658. struct drm_i915_private *dev_priv = dev->dev_private;
  7659. int i, j, ret;
  7660. drm_mode_config_init(dev);
  7661. dev->mode_config.min_width = 0;
  7662. dev->mode_config.min_height = 0;
  7663. dev->mode_config.preferred_depth = 24;
  7664. dev->mode_config.prefer_shadow = 1;
  7665. dev->mode_config.funcs = &intel_mode_funcs;
  7666. intel_init_quirks(dev);
  7667. intel_init_pm(dev);
  7668. if (INTEL_INFO(dev)->num_pipes == 0)
  7669. return;
  7670. intel_init_display(dev);
  7671. if (IS_GEN2(dev)) {
  7672. dev->mode_config.max_width = 2048;
  7673. dev->mode_config.max_height = 2048;
  7674. } else if (IS_GEN3(dev)) {
  7675. dev->mode_config.max_width = 4096;
  7676. dev->mode_config.max_height = 4096;
  7677. } else {
  7678. dev->mode_config.max_width = 8192;
  7679. dev->mode_config.max_height = 8192;
  7680. }
  7681. dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
  7682. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  7683. INTEL_INFO(dev)->num_pipes,
  7684. INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
  7685. for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
  7686. intel_crtc_init(dev, i);
  7687. for (j = 0; j < dev_priv->num_plane; j++) {
  7688. ret = intel_plane_init(dev, i, j);
  7689. if (ret)
  7690. DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
  7691. pipe_name(i), sprite_name(i, j), ret);
  7692. }
  7693. }
  7694. intel_cpu_pll_init(dev);
  7695. intel_pch_pll_init(dev);
  7696. /* Just disable it once at startup */
  7697. i915_disable_vga(dev);
  7698. intel_setup_outputs(dev);
  7699. /* Just in case the BIOS is doing something questionable. */
  7700. intel_disable_fbc(dev);
  7701. }
  7702. static void
  7703. intel_connector_break_all_links(struct intel_connector *connector)
  7704. {
  7705. connector->base.dpms = DRM_MODE_DPMS_OFF;
  7706. connector->base.encoder = NULL;
  7707. connector->encoder->connectors_active = false;
  7708. connector->encoder->base.crtc = NULL;
  7709. }
  7710. static void intel_enable_pipe_a(struct drm_device *dev)
  7711. {
  7712. struct intel_connector *connector;
  7713. struct drm_connector *crt = NULL;
  7714. struct intel_load_detect_pipe load_detect_temp;
  7715. /* We can't just switch on the pipe A, we need to set things up with a
  7716. * proper mode and output configuration. As a gross hack, enable pipe A
  7717. * by enabling the load detect pipe once. */
  7718. list_for_each_entry(connector,
  7719. &dev->mode_config.connector_list,
  7720. base.head) {
  7721. if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  7722. crt = &connector->base;
  7723. break;
  7724. }
  7725. }
  7726. if (!crt)
  7727. return;
  7728. if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
  7729. intel_release_load_detect_pipe(crt, &load_detect_temp);
  7730. }
  7731. static bool
  7732. intel_check_plane_mapping(struct intel_crtc *crtc)
  7733. {
  7734. struct drm_device *dev = crtc->base.dev;
  7735. struct drm_i915_private *dev_priv = dev->dev_private;
  7736. u32 reg, val;
  7737. if (INTEL_INFO(dev)->num_pipes == 1)
  7738. return true;
  7739. reg = DSPCNTR(!crtc->plane);
  7740. val = I915_READ(reg);
  7741. if ((val & DISPLAY_PLANE_ENABLE) &&
  7742. (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  7743. return false;
  7744. return true;
  7745. }
  7746. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  7747. {
  7748. struct drm_device *dev = crtc->base.dev;
  7749. struct drm_i915_private *dev_priv = dev->dev_private;
  7750. u32 reg;
  7751. /* Clear any frame start delays used for debugging left by the BIOS */
  7752. reg = PIPECONF(crtc->config.cpu_transcoder);
  7753. I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  7754. /* We need to sanitize the plane -> pipe mapping first because this will
  7755. * disable the crtc (and hence change the state) if it is wrong. Note
  7756. * that gen4+ has a fixed plane -> pipe mapping. */
  7757. if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  7758. struct intel_connector *connector;
  7759. bool plane;
  7760. DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  7761. crtc->base.base.id);
  7762. /* Pipe has the wrong plane attached and the plane is active.
  7763. * Temporarily change the plane mapping and disable everything
  7764. * ... */
  7765. plane = crtc->plane;
  7766. crtc->plane = !plane;
  7767. dev_priv->display.crtc_disable(&crtc->base);
  7768. crtc->plane = plane;
  7769. /* ... and break all links. */
  7770. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7771. base.head) {
  7772. if (connector->encoder->base.crtc != &crtc->base)
  7773. continue;
  7774. intel_connector_break_all_links(connector);
  7775. }
  7776. WARN_ON(crtc->active);
  7777. crtc->base.enabled = false;
  7778. }
  7779. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  7780. crtc->pipe == PIPE_A && !crtc->active) {
  7781. /* BIOS forgot to enable pipe A, this mostly happens after
  7782. * resume. Force-enable the pipe to fix this, the update_dpms
  7783. * call below we restore the pipe to the right state, but leave
  7784. * the required bits on. */
  7785. intel_enable_pipe_a(dev);
  7786. }
  7787. /* Adjust the state of the output pipe according to whether we
  7788. * have active connectors/encoders. */
  7789. intel_crtc_update_dpms(&crtc->base);
  7790. if (crtc->active != crtc->base.enabled) {
  7791. struct intel_encoder *encoder;
  7792. /* This can happen either due to bugs in the get_hw_state
  7793. * functions or because the pipe is force-enabled due to the
  7794. * pipe A quirk. */
  7795. DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  7796. crtc->base.base.id,
  7797. crtc->base.enabled ? "enabled" : "disabled",
  7798. crtc->active ? "enabled" : "disabled");
  7799. crtc->base.enabled = crtc->active;
  7800. /* Because we only establish the connector -> encoder ->
  7801. * crtc links if something is active, this means the
  7802. * crtc is now deactivated. Break the links. connector
  7803. * -> encoder links are only establish when things are
  7804. * actually up, hence no need to break them. */
  7805. WARN_ON(crtc->active);
  7806. for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
  7807. WARN_ON(encoder->connectors_active);
  7808. encoder->base.crtc = NULL;
  7809. }
  7810. }
  7811. }
  7812. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  7813. {
  7814. struct intel_connector *connector;
  7815. struct drm_device *dev = encoder->base.dev;
  7816. /* We need to check both for a crtc link (meaning that the
  7817. * encoder is active and trying to read from a pipe) and the
  7818. * pipe itself being active. */
  7819. bool has_active_crtc = encoder->base.crtc &&
  7820. to_intel_crtc(encoder->base.crtc)->active;
  7821. if (encoder->connectors_active && !has_active_crtc) {
  7822. DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  7823. encoder->base.base.id,
  7824. drm_get_encoder_name(&encoder->base));
  7825. /* Connector is active, but has no active pipe. This is
  7826. * fallout from our resume register restoring. Disable
  7827. * the encoder manually again. */
  7828. if (encoder->base.crtc) {
  7829. DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  7830. encoder->base.base.id,
  7831. drm_get_encoder_name(&encoder->base));
  7832. encoder->disable(encoder);
  7833. }
  7834. /* Inconsistent output/port/pipe state happens presumably due to
  7835. * a bug in one of the get_hw_state functions. Or someplace else
  7836. * in our code, like the register restore mess on resume. Clamp
  7837. * things to off as a safer default. */
  7838. list_for_each_entry(connector,
  7839. &dev->mode_config.connector_list,
  7840. base.head) {
  7841. if (connector->encoder != encoder)
  7842. continue;
  7843. intel_connector_break_all_links(connector);
  7844. }
  7845. }
  7846. /* Enabled encoders without active connectors will be fixed in
  7847. * the crtc fixup. */
  7848. }
  7849. void i915_redisable_vga(struct drm_device *dev)
  7850. {
  7851. struct drm_i915_private *dev_priv = dev->dev_private;
  7852. u32 vga_reg = i915_vgacntrl_reg(dev);
  7853. if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
  7854. DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  7855. i915_disable_vga(dev);
  7856. }
  7857. }
  7858. /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  7859. * and i915 state tracking structures. */
  7860. void intel_modeset_setup_hw_state(struct drm_device *dev,
  7861. bool force_restore)
  7862. {
  7863. struct drm_i915_private *dev_priv = dev->dev_private;
  7864. enum pipe pipe;
  7865. u32 tmp;
  7866. struct drm_plane *plane;
  7867. struct intel_crtc *crtc;
  7868. struct intel_encoder *encoder;
  7869. struct intel_connector *connector;
  7870. if (HAS_DDI(dev)) {
  7871. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  7872. if (tmp & TRANS_DDI_FUNC_ENABLE) {
  7873. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  7874. case TRANS_DDI_EDP_INPUT_A_ON:
  7875. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  7876. pipe = PIPE_A;
  7877. break;
  7878. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  7879. pipe = PIPE_B;
  7880. break;
  7881. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  7882. pipe = PIPE_C;
  7883. break;
  7884. default:
  7885. /* A bogus value has been programmed, disable
  7886. * the transcoder */
  7887. WARN(1, "Bogus eDP source %08x\n", tmp);
  7888. intel_ddi_disable_transcoder_func(dev_priv,
  7889. TRANSCODER_EDP);
  7890. goto setup_pipes;
  7891. }
  7892. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  7893. crtc->config.cpu_transcoder = TRANSCODER_EDP;
  7894. DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
  7895. pipe_name(pipe));
  7896. }
  7897. }
  7898. setup_pipes:
  7899. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7900. base.head) {
  7901. enum transcoder tmp = crtc->config.cpu_transcoder;
  7902. memset(&crtc->config, 0, sizeof(crtc->config));
  7903. crtc->config.cpu_transcoder = tmp;
  7904. crtc->active = dev_priv->display.get_pipe_config(crtc,
  7905. &crtc->config);
  7906. crtc->base.enabled = crtc->active;
  7907. DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  7908. crtc->base.base.id,
  7909. crtc->active ? "enabled" : "disabled");
  7910. }
  7911. if (HAS_DDI(dev))
  7912. intel_ddi_setup_hw_pll_state(dev);
  7913. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7914. base.head) {
  7915. pipe = 0;
  7916. if (encoder->get_hw_state(encoder, &pipe)) {
  7917. encoder->base.crtc =
  7918. dev_priv->pipe_to_crtc_mapping[pipe];
  7919. } else {
  7920. encoder->base.crtc = NULL;
  7921. }
  7922. encoder->connectors_active = false;
  7923. DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
  7924. encoder->base.base.id,
  7925. drm_get_encoder_name(&encoder->base),
  7926. encoder->base.crtc ? "enabled" : "disabled",
  7927. pipe);
  7928. }
  7929. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7930. base.head) {
  7931. if (connector->get_hw_state(connector)) {
  7932. connector->base.dpms = DRM_MODE_DPMS_ON;
  7933. connector->encoder->connectors_active = true;
  7934. connector->base.encoder = &connector->encoder->base;
  7935. } else {
  7936. connector->base.dpms = DRM_MODE_DPMS_OFF;
  7937. connector->base.encoder = NULL;
  7938. }
  7939. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  7940. connector->base.base.id,
  7941. drm_get_connector_name(&connector->base),
  7942. connector->base.encoder ? "enabled" : "disabled");
  7943. }
  7944. /* HW state is read out, now we need to sanitize this mess. */
  7945. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7946. base.head) {
  7947. intel_sanitize_encoder(encoder);
  7948. }
  7949. for_each_pipe(pipe) {
  7950. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  7951. intel_sanitize_crtc(crtc);
  7952. }
  7953. if (force_restore) {
  7954. /*
  7955. * We need to use raw interfaces for restoring state to avoid
  7956. * checking (bogus) intermediate states.
  7957. */
  7958. for_each_pipe(pipe) {
  7959. struct drm_crtc *crtc =
  7960. dev_priv->pipe_to_crtc_mapping[pipe];
  7961. __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  7962. crtc->fb);
  7963. }
  7964. list_for_each_entry(plane, &dev->mode_config.plane_list, head)
  7965. intel_plane_restore(plane);
  7966. i915_redisable_vga(dev);
  7967. } else {
  7968. intel_modeset_update_staged_output_state(dev);
  7969. }
  7970. intel_modeset_check_state(dev);
  7971. drm_mode_config_reset(dev);
  7972. }
  7973. void intel_modeset_gem_init(struct drm_device *dev)
  7974. {
  7975. intel_modeset_init_hw(dev);
  7976. intel_setup_overlay(dev);
  7977. intel_modeset_setup_hw_state(dev, false);
  7978. }
  7979. void intel_modeset_cleanup(struct drm_device *dev)
  7980. {
  7981. struct drm_i915_private *dev_priv = dev->dev_private;
  7982. struct drm_crtc *crtc;
  7983. struct intel_crtc *intel_crtc;
  7984. /*
  7985. * Interrupts and polling as the first thing to avoid creating havoc.
  7986. * Too much stuff here (turning of rps, connectors, ...) would
  7987. * experience fancy races otherwise.
  7988. */
  7989. drm_irq_uninstall(dev);
  7990. cancel_work_sync(&dev_priv->hotplug_work);
  7991. /*
  7992. * Due to the hpd irq storm handling the hotplug work can re-arm the
  7993. * poll handlers. Hence disable polling after hpd handling is shut down.
  7994. */
  7995. drm_kms_helper_poll_fini(dev);
  7996. mutex_lock(&dev->struct_mutex);
  7997. intel_unregister_dsm_handler();
  7998. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7999. /* Skip inactive CRTCs */
  8000. if (!crtc->fb)
  8001. continue;
  8002. intel_crtc = to_intel_crtc(crtc);
  8003. intel_increase_pllclock(crtc);
  8004. }
  8005. intel_disable_fbc(dev);
  8006. intel_disable_gt_powersave(dev);
  8007. ironlake_teardown_rc6(dev);
  8008. mutex_unlock(&dev->struct_mutex);
  8009. /* flush any delayed tasks or pending work */
  8010. flush_scheduled_work();
  8011. /* destroy backlight, if any, before the connectors */
  8012. intel_panel_destroy_backlight(dev);
  8013. drm_mode_config_cleanup(dev);
  8014. intel_cleanup_overlay(dev);
  8015. }
  8016. /*
  8017. * Return which encoder is currently attached for connector.
  8018. */
  8019. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  8020. {
  8021. return &intel_attached_encoder(connector)->base;
  8022. }
  8023. void intel_connector_attach_encoder(struct intel_connector *connector,
  8024. struct intel_encoder *encoder)
  8025. {
  8026. connector->encoder = encoder;
  8027. drm_mode_connector_attach_encoder(&connector->base,
  8028. &encoder->base);
  8029. }
  8030. /*
  8031. * set vga decode state - true == enable VGA decode
  8032. */
  8033. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  8034. {
  8035. struct drm_i915_private *dev_priv = dev->dev_private;
  8036. u16 gmch_ctrl;
  8037. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  8038. if (state)
  8039. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  8040. else
  8041. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  8042. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  8043. return 0;
  8044. }
  8045. #ifdef CONFIG_DEBUG_FS
  8046. #include <linux/seq_file.h>
  8047. struct intel_display_error_state {
  8048. struct intel_cursor_error_state {
  8049. u32 control;
  8050. u32 position;
  8051. u32 base;
  8052. u32 size;
  8053. } cursor[I915_MAX_PIPES];
  8054. struct intel_pipe_error_state {
  8055. u32 conf;
  8056. u32 source;
  8057. u32 htotal;
  8058. u32 hblank;
  8059. u32 hsync;
  8060. u32 vtotal;
  8061. u32 vblank;
  8062. u32 vsync;
  8063. } pipe[I915_MAX_PIPES];
  8064. struct intel_plane_error_state {
  8065. u32 control;
  8066. u32 stride;
  8067. u32 size;
  8068. u32 pos;
  8069. u32 addr;
  8070. u32 surface;
  8071. u32 tile_offset;
  8072. } plane[I915_MAX_PIPES];
  8073. };
  8074. struct intel_display_error_state *
  8075. intel_display_capture_error_state(struct drm_device *dev)
  8076. {
  8077. drm_i915_private_t *dev_priv = dev->dev_private;
  8078. struct intel_display_error_state *error;
  8079. enum transcoder cpu_transcoder;
  8080. int i;
  8081. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  8082. if (error == NULL)
  8083. return NULL;
  8084. for_each_pipe(i) {
  8085. cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
  8086. if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
  8087. error->cursor[i].control = I915_READ(CURCNTR(i));
  8088. error->cursor[i].position = I915_READ(CURPOS(i));
  8089. error->cursor[i].base = I915_READ(CURBASE(i));
  8090. } else {
  8091. error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
  8092. error->cursor[i].position = I915_READ(CURPOS_IVB(i));
  8093. error->cursor[i].base = I915_READ(CURBASE_IVB(i));
  8094. }
  8095. error->plane[i].control = I915_READ(DSPCNTR(i));
  8096. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  8097. if (INTEL_INFO(dev)->gen <= 3) {
  8098. error->plane[i].size = I915_READ(DSPSIZE(i));
  8099. error->plane[i].pos = I915_READ(DSPPOS(i));
  8100. }
  8101. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  8102. error->plane[i].addr = I915_READ(DSPADDR(i));
  8103. if (INTEL_INFO(dev)->gen >= 4) {
  8104. error->plane[i].surface = I915_READ(DSPSURF(i));
  8105. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  8106. }
  8107. error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  8108. error->pipe[i].source = I915_READ(PIPESRC(i));
  8109. error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  8110. error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  8111. error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  8112. error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  8113. error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  8114. error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  8115. }
  8116. return error;
  8117. }
  8118. void
  8119. intel_display_print_error_state(struct seq_file *m,
  8120. struct drm_device *dev,
  8121. struct intel_display_error_state *error)
  8122. {
  8123. int i;
  8124. seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
  8125. for_each_pipe(i) {
  8126. seq_printf(m, "Pipe [%d]:\n", i);
  8127. seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
  8128. seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
  8129. seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
  8130. seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
  8131. seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
  8132. seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
  8133. seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
  8134. seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
  8135. seq_printf(m, "Plane [%d]:\n", i);
  8136. seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
  8137. seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  8138. if (INTEL_INFO(dev)->gen <= 3) {
  8139. seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
  8140. seq_printf(m, " POS: %08x\n", error->plane[i].pos);
  8141. }
  8142. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  8143. seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  8144. if (INTEL_INFO(dev)->gen >= 4) {
  8145. seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
  8146. seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  8147. }
  8148. seq_printf(m, "Cursor [%d]:\n", i);
  8149. seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  8150. seq_printf(m, " POS: %08x\n", error->cursor[i].position);
  8151. seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
  8152. }
  8153. }
  8154. #endif