i915_irq.c 85 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/sysrq.h>
  30. #include <linux/slab.h>
  31. #include <drm/drmP.h>
  32. #include <drm/i915_drm.h>
  33. #include "i915_drv.h"
  34. #include "i915_trace.h"
  35. #include "intel_drv.h"
  36. static const u32 hpd_ibx[] = {
  37. [HPD_CRT] = SDE_CRT_HOTPLUG,
  38. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  39. [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  40. [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  41. [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  42. };
  43. static const u32 hpd_cpt[] = {
  44. [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  45. [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  46. [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  47. [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  48. [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  49. };
  50. static const u32 hpd_mask_i915[] = {
  51. [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  52. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  53. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  54. [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  55. [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  56. [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  57. };
  58. static const u32 hpd_status_gen4[] = {
  59. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  60. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  61. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  62. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  63. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  64. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  65. };
  66. static const u32 hpd_status_i965[] = {
  67. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  68. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
  69. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
  70. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  71. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  72. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  73. };
  74. static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75. [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76. [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77. [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78. [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79. [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80. [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81. };
  82. /* For display hotplug interrupt */
  83. static void
  84. ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  85. {
  86. if ((dev_priv->irq_mask & mask) != 0) {
  87. dev_priv->irq_mask &= ~mask;
  88. I915_WRITE(DEIMR, dev_priv->irq_mask);
  89. POSTING_READ(DEIMR);
  90. }
  91. }
  92. static void
  93. ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  94. {
  95. if ((dev_priv->irq_mask & mask) != mask) {
  96. dev_priv->irq_mask |= mask;
  97. I915_WRITE(DEIMR, dev_priv->irq_mask);
  98. POSTING_READ(DEIMR);
  99. }
  100. }
  101. void
  102. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  103. {
  104. u32 reg = PIPESTAT(pipe);
  105. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  106. if ((pipestat & mask) == mask)
  107. return;
  108. /* Enable the interrupt, clear any pending status */
  109. pipestat |= mask | (mask >> 16);
  110. I915_WRITE(reg, pipestat);
  111. POSTING_READ(reg);
  112. }
  113. void
  114. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  115. {
  116. u32 reg = PIPESTAT(pipe);
  117. u32 pipestat = I915_READ(reg) & 0x7fff0000;
  118. if ((pipestat & mask) == 0)
  119. return;
  120. pipestat &= ~mask;
  121. I915_WRITE(reg, pipestat);
  122. POSTING_READ(reg);
  123. }
  124. /**
  125. * intel_enable_asle - enable ASLE interrupt for OpRegion
  126. */
  127. void intel_enable_asle(struct drm_device *dev)
  128. {
  129. drm_i915_private_t *dev_priv = dev->dev_private;
  130. unsigned long irqflags;
  131. /* FIXME: opregion/asle for VLV */
  132. if (IS_VALLEYVIEW(dev))
  133. return;
  134. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  135. if (HAS_PCH_SPLIT(dev))
  136. ironlake_enable_display_irq(dev_priv, DE_GSE);
  137. else {
  138. i915_enable_pipestat(dev_priv, 1,
  139. PIPE_LEGACY_BLC_EVENT_ENABLE);
  140. if (INTEL_INFO(dev)->gen >= 4)
  141. i915_enable_pipestat(dev_priv, 0,
  142. PIPE_LEGACY_BLC_EVENT_ENABLE);
  143. }
  144. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  145. }
  146. /**
  147. * i915_pipe_enabled - check if a pipe is enabled
  148. * @dev: DRM device
  149. * @pipe: pipe to check
  150. *
  151. * Reading certain registers when the pipe is disabled can hang the chip.
  152. * Use this routine to make sure the PLL is running and the pipe is active
  153. * before reading such registers if unsure.
  154. */
  155. static int
  156. i915_pipe_enabled(struct drm_device *dev, int pipe)
  157. {
  158. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  159. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  160. pipe);
  161. return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
  162. }
  163. /* Called from drm generic code, passed a 'crtc', which
  164. * we use as a pipe index
  165. */
  166. static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  167. {
  168. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  169. unsigned long high_frame;
  170. unsigned long low_frame;
  171. u32 high1, high2, low;
  172. if (!i915_pipe_enabled(dev, pipe)) {
  173. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  174. "pipe %c\n", pipe_name(pipe));
  175. return 0;
  176. }
  177. high_frame = PIPEFRAME(pipe);
  178. low_frame = PIPEFRAMEPIXEL(pipe);
  179. /*
  180. * High & low register fields aren't synchronized, so make sure
  181. * we get a low value that's stable across two reads of the high
  182. * register.
  183. */
  184. do {
  185. high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  186. low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
  187. high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
  188. } while (high1 != high2);
  189. high1 >>= PIPE_FRAME_HIGH_SHIFT;
  190. low >>= PIPE_FRAME_LOW_SHIFT;
  191. return (high1 << 8) | low;
  192. }
  193. static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  194. {
  195. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  196. int reg = PIPE_FRMCOUNT_GM45(pipe);
  197. if (!i915_pipe_enabled(dev, pipe)) {
  198. DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
  199. "pipe %c\n", pipe_name(pipe));
  200. return 0;
  201. }
  202. return I915_READ(reg);
  203. }
  204. static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
  205. int *vpos, int *hpos)
  206. {
  207. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  208. u32 vbl = 0, position = 0;
  209. int vbl_start, vbl_end, htotal, vtotal;
  210. bool in_vbl = true;
  211. int ret = 0;
  212. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  213. pipe);
  214. if (!i915_pipe_enabled(dev, pipe)) {
  215. DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
  216. "pipe %c\n", pipe_name(pipe));
  217. return 0;
  218. }
  219. /* Get vtotal. */
  220. vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  221. if (INTEL_INFO(dev)->gen >= 4) {
  222. /* No obvious pixelcount register. Only query vertical
  223. * scanout position from Display scan line register.
  224. */
  225. position = I915_READ(PIPEDSL(pipe));
  226. /* Decode into vertical scanout position. Don't have
  227. * horizontal scanout position.
  228. */
  229. *vpos = position & 0x1fff;
  230. *hpos = 0;
  231. } else {
  232. /* Have access to pixelcount since start of frame.
  233. * We can split this into vertical and horizontal
  234. * scanout position.
  235. */
  236. position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
  237. htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
  238. *vpos = position / htotal;
  239. *hpos = position - (*vpos * htotal);
  240. }
  241. /* Query vblank area. */
  242. vbl = I915_READ(VBLANK(cpu_transcoder));
  243. /* Test position against vblank region. */
  244. vbl_start = vbl & 0x1fff;
  245. vbl_end = (vbl >> 16) & 0x1fff;
  246. if ((*vpos < vbl_start) || (*vpos > vbl_end))
  247. in_vbl = false;
  248. /* Inside "upper part" of vblank area? Apply corrective offset: */
  249. if (in_vbl && (*vpos >= vbl_start))
  250. *vpos = *vpos - vtotal;
  251. /* Readouts valid? */
  252. if (vbl > 0)
  253. ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
  254. /* In vblank? */
  255. if (in_vbl)
  256. ret |= DRM_SCANOUTPOS_INVBL;
  257. return ret;
  258. }
  259. static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
  260. int *max_error,
  261. struct timeval *vblank_time,
  262. unsigned flags)
  263. {
  264. struct drm_crtc *crtc;
  265. if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
  266. DRM_ERROR("Invalid crtc %d\n", pipe);
  267. return -EINVAL;
  268. }
  269. /* Get drm_crtc to timestamp: */
  270. crtc = intel_get_crtc_for_pipe(dev, pipe);
  271. if (crtc == NULL) {
  272. DRM_ERROR("Invalid crtc %d\n", pipe);
  273. return -EINVAL;
  274. }
  275. if (!crtc->enabled) {
  276. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  277. return -EBUSY;
  278. }
  279. /* Helper routine in DRM core does all the work: */
  280. return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
  281. vblank_time, flags,
  282. crtc);
  283. }
  284. /*
  285. * Handle hotplug events outside the interrupt handler proper.
  286. */
  287. static void i915_hotplug_work_func(struct work_struct *work)
  288. {
  289. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  290. hotplug_work);
  291. struct drm_device *dev = dev_priv->dev;
  292. struct drm_mode_config *mode_config = &dev->mode_config;
  293. struct intel_encoder *encoder;
  294. /* HPD irq before everything is fully set up. */
  295. if (!dev_priv->enable_hotplug_processing)
  296. return;
  297. mutex_lock(&mode_config->mutex);
  298. DRM_DEBUG_KMS("running encoder hotplug functions\n");
  299. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  300. if (encoder->hot_plug)
  301. encoder->hot_plug(encoder);
  302. mutex_unlock(&mode_config->mutex);
  303. /* Just fire off a uevent and let userspace tell us what to do */
  304. drm_helper_hpd_irq_event(dev);
  305. }
  306. static void ironlake_handle_rps_change(struct drm_device *dev)
  307. {
  308. drm_i915_private_t *dev_priv = dev->dev_private;
  309. u32 busy_up, busy_down, max_avg, min_avg;
  310. u8 new_delay;
  311. unsigned long flags;
  312. spin_lock_irqsave(&mchdev_lock, flags);
  313. I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
  314. new_delay = dev_priv->ips.cur_delay;
  315. I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
  316. busy_up = I915_READ(RCPREVBSYTUPAVG);
  317. busy_down = I915_READ(RCPREVBSYTDNAVG);
  318. max_avg = I915_READ(RCBMAXAVG);
  319. min_avg = I915_READ(RCBMINAVG);
  320. /* Handle RCS change request from hw */
  321. if (busy_up > max_avg) {
  322. if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
  323. new_delay = dev_priv->ips.cur_delay - 1;
  324. if (new_delay < dev_priv->ips.max_delay)
  325. new_delay = dev_priv->ips.max_delay;
  326. } else if (busy_down < min_avg) {
  327. if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
  328. new_delay = dev_priv->ips.cur_delay + 1;
  329. if (new_delay > dev_priv->ips.min_delay)
  330. new_delay = dev_priv->ips.min_delay;
  331. }
  332. if (ironlake_set_drps(dev, new_delay))
  333. dev_priv->ips.cur_delay = new_delay;
  334. spin_unlock_irqrestore(&mchdev_lock, flags);
  335. return;
  336. }
  337. static void notify_ring(struct drm_device *dev,
  338. struct intel_ring_buffer *ring)
  339. {
  340. struct drm_i915_private *dev_priv = dev->dev_private;
  341. if (ring->obj == NULL)
  342. return;
  343. trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
  344. wake_up_all(&ring->irq_queue);
  345. if (i915_enable_hangcheck) {
  346. dev_priv->gpu_error.hangcheck_count = 0;
  347. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  348. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  349. }
  350. }
  351. static void gen6_pm_rps_work(struct work_struct *work)
  352. {
  353. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  354. rps.work);
  355. u32 pm_iir, pm_imr;
  356. u8 new_delay;
  357. spin_lock_irq(&dev_priv->rps.lock);
  358. pm_iir = dev_priv->rps.pm_iir;
  359. dev_priv->rps.pm_iir = 0;
  360. pm_imr = I915_READ(GEN6_PMIMR);
  361. I915_WRITE(GEN6_PMIMR, 0);
  362. spin_unlock_irq(&dev_priv->rps.lock);
  363. if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
  364. return;
  365. mutex_lock(&dev_priv->rps.hw_lock);
  366. if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
  367. new_delay = dev_priv->rps.cur_delay + 1;
  368. else
  369. new_delay = dev_priv->rps.cur_delay - 1;
  370. /* sysfs frequency interfaces may have snuck in while servicing the
  371. * interrupt
  372. */
  373. if (!(new_delay > dev_priv->rps.max_delay ||
  374. new_delay < dev_priv->rps.min_delay)) {
  375. gen6_set_rps(dev_priv->dev, new_delay);
  376. }
  377. mutex_unlock(&dev_priv->rps.hw_lock);
  378. }
  379. /**
  380. * ivybridge_parity_work - Workqueue called when a parity error interrupt
  381. * occurred.
  382. * @work: workqueue struct
  383. *
  384. * Doesn't actually do anything except notify userspace. As a consequence of
  385. * this event, userspace should try to remap the bad rows since statistically
  386. * it is likely the same row is more likely to go bad again.
  387. */
  388. static void ivybridge_parity_work(struct work_struct *work)
  389. {
  390. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  391. l3_parity.error_work);
  392. u32 error_status, row, bank, subbank;
  393. char *parity_event[5];
  394. uint32_t misccpctl;
  395. unsigned long flags;
  396. /* We must turn off DOP level clock gating to access the L3 registers.
  397. * In order to prevent a get/put style interface, acquire struct mutex
  398. * any time we access those registers.
  399. */
  400. mutex_lock(&dev_priv->dev->struct_mutex);
  401. misccpctl = I915_READ(GEN7_MISCCPCTL);
  402. I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
  403. POSTING_READ(GEN7_MISCCPCTL);
  404. error_status = I915_READ(GEN7_L3CDERRST1);
  405. row = GEN7_PARITY_ERROR_ROW(error_status);
  406. bank = GEN7_PARITY_ERROR_BANK(error_status);
  407. subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
  408. I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
  409. GEN7_L3CDERRST1_ENABLE);
  410. POSTING_READ(GEN7_L3CDERRST1);
  411. I915_WRITE(GEN7_MISCCPCTL, misccpctl);
  412. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  413. dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  414. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  415. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  416. mutex_unlock(&dev_priv->dev->struct_mutex);
  417. parity_event[0] = "L3_PARITY_ERROR=1";
  418. parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
  419. parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
  420. parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
  421. parity_event[4] = NULL;
  422. kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
  423. KOBJ_CHANGE, parity_event);
  424. DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
  425. row, bank, subbank);
  426. kfree(parity_event[3]);
  427. kfree(parity_event[2]);
  428. kfree(parity_event[1]);
  429. }
  430. static void ivybridge_handle_parity_error(struct drm_device *dev)
  431. {
  432. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  433. unsigned long flags;
  434. if (!HAS_L3_GPU_CACHE(dev))
  435. return;
  436. spin_lock_irqsave(&dev_priv->irq_lock, flags);
  437. dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  438. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  439. spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
  440. queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
  441. }
  442. static void snb_gt_irq_handler(struct drm_device *dev,
  443. struct drm_i915_private *dev_priv,
  444. u32 gt_iir)
  445. {
  446. if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
  447. GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
  448. notify_ring(dev, &dev_priv->ring[RCS]);
  449. if (gt_iir & GEN6_BSD_USER_INTERRUPT)
  450. notify_ring(dev, &dev_priv->ring[VCS]);
  451. if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
  452. notify_ring(dev, &dev_priv->ring[BCS]);
  453. if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
  454. GT_GEN6_BSD_CS_ERROR_INTERRUPT |
  455. GT_RENDER_CS_ERROR_INTERRUPT)) {
  456. DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
  457. i915_handle_error(dev, false);
  458. }
  459. if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
  460. ivybridge_handle_parity_error(dev);
  461. }
  462. static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
  463. u32 pm_iir)
  464. {
  465. unsigned long flags;
  466. /*
  467. * IIR bits should never already be set because IMR should
  468. * prevent an interrupt from being shown in IIR. The warning
  469. * displays a case where we've unsafely cleared
  470. * dev_priv->rps.pm_iir. Although missing an interrupt of the same
  471. * type is not a problem, it displays a problem in the logic.
  472. *
  473. * The mask bit in IMR is cleared by dev_priv->rps.work.
  474. */
  475. spin_lock_irqsave(&dev_priv->rps.lock, flags);
  476. dev_priv->rps.pm_iir |= pm_iir;
  477. I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
  478. POSTING_READ(GEN6_PMIMR);
  479. spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
  480. queue_work(dev_priv->wq, &dev_priv->rps.work);
  481. }
  482. #define HPD_STORM_DETECT_PERIOD 1000
  483. #define HPD_STORM_THRESHOLD 5
  484. static inline void hotplug_irq_storm_detect(struct drm_device *dev,
  485. u32 hotplug_trigger,
  486. const u32 *hpd)
  487. {
  488. drm_i915_private_t *dev_priv = dev->dev_private;
  489. unsigned long irqflags;
  490. int i;
  491. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  492. for (i = 1; i < HPD_NUM_PINS; i++) {
  493. if (!(hpd[i] & hotplug_trigger) ||
  494. dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
  495. continue;
  496. if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
  497. dev_priv->hpd_stats[i].hpd_last_jiffies
  498. + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
  499. dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
  500. dev_priv->hpd_stats[i].hpd_cnt = 0;
  501. } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
  502. dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
  503. DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
  504. } else {
  505. dev_priv->hpd_stats[i].hpd_cnt++;
  506. }
  507. }
  508. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  509. }
  510. static void gmbus_irq_handler(struct drm_device *dev)
  511. {
  512. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  513. wake_up_all(&dev_priv->gmbus_wait_queue);
  514. }
  515. static void dp_aux_irq_handler(struct drm_device *dev)
  516. {
  517. struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
  518. wake_up_all(&dev_priv->gmbus_wait_queue);
  519. }
  520. static irqreturn_t valleyview_irq_handler(int irq, void *arg)
  521. {
  522. struct drm_device *dev = (struct drm_device *) arg;
  523. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  524. u32 iir, gt_iir, pm_iir;
  525. irqreturn_t ret = IRQ_NONE;
  526. unsigned long irqflags;
  527. int pipe;
  528. u32 pipe_stats[I915_MAX_PIPES];
  529. atomic_inc(&dev_priv->irq_received);
  530. while (true) {
  531. iir = I915_READ(VLV_IIR);
  532. gt_iir = I915_READ(GTIIR);
  533. pm_iir = I915_READ(GEN6_PMIIR);
  534. if (gt_iir == 0 && pm_iir == 0 && iir == 0)
  535. goto out;
  536. ret = IRQ_HANDLED;
  537. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  538. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  539. for_each_pipe(pipe) {
  540. int reg = PIPESTAT(pipe);
  541. pipe_stats[pipe] = I915_READ(reg);
  542. /*
  543. * Clear the PIPE*STAT regs before the IIR
  544. */
  545. if (pipe_stats[pipe] & 0x8000ffff) {
  546. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  547. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  548. pipe_name(pipe));
  549. I915_WRITE(reg, pipe_stats[pipe]);
  550. }
  551. }
  552. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  553. for_each_pipe(pipe) {
  554. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
  555. drm_handle_vblank(dev, pipe);
  556. if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
  557. intel_prepare_page_flip(dev, pipe);
  558. intel_finish_page_flip(dev, pipe);
  559. }
  560. }
  561. /* Consume port. Then clear IIR or we'll miss events */
  562. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  563. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  564. u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  565. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  566. hotplug_status);
  567. if (hotplug_trigger) {
  568. hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915);
  569. queue_work(dev_priv->wq,
  570. &dev_priv->hotplug_work);
  571. }
  572. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  573. I915_READ(PORT_HOTPLUG_STAT);
  574. }
  575. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  576. gmbus_irq_handler(dev);
  577. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  578. gen6_queue_rps_work(dev_priv, pm_iir);
  579. I915_WRITE(GTIIR, gt_iir);
  580. I915_WRITE(GEN6_PMIIR, pm_iir);
  581. I915_WRITE(VLV_IIR, iir);
  582. }
  583. out:
  584. return ret;
  585. }
  586. static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
  587. {
  588. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  589. int pipe;
  590. u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
  591. if (hotplug_trigger) {
  592. hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx);
  593. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  594. }
  595. if (pch_iir & SDE_AUDIO_POWER_MASK)
  596. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  597. (pch_iir & SDE_AUDIO_POWER_MASK) >>
  598. SDE_AUDIO_POWER_SHIFT);
  599. if (pch_iir & SDE_AUX_MASK)
  600. dp_aux_irq_handler(dev);
  601. if (pch_iir & SDE_GMBUS)
  602. gmbus_irq_handler(dev);
  603. if (pch_iir & SDE_AUDIO_HDCP_MASK)
  604. DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
  605. if (pch_iir & SDE_AUDIO_TRANS_MASK)
  606. DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
  607. if (pch_iir & SDE_POISON)
  608. DRM_ERROR("PCH poison interrupt\n");
  609. if (pch_iir & SDE_FDI_MASK)
  610. for_each_pipe(pipe)
  611. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  612. pipe_name(pipe),
  613. I915_READ(FDI_RX_IIR(pipe)));
  614. if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
  615. DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
  616. if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
  617. DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
  618. if (pch_iir & SDE_TRANSB_FIFO_UNDER)
  619. DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
  620. if (pch_iir & SDE_TRANSA_FIFO_UNDER)
  621. DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
  622. }
  623. static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
  624. {
  625. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  626. int pipe;
  627. u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
  628. if (hotplug_trigger) {
  629. hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt);
  630. queue_work(dev_priv->wq, &dev_priv->hotplug_work);
  631. }
  632. if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
  633. DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
  634. (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
  635. SDE_AUDIO_POWER_SHIFT_CPT);
  636. if (pch_iir & SDE_AUX_MASK_CPT)
  637. dp_aux_irq_handler(dev);
  638. if (pch_iir & SDE_GMBUS_CPT)
  639. gmbus_irq_handler(dev);
  640. if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
  641. DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
  642. if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
  643. DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
  644. if (pch_iir & SDE_FDI_MASK_CPT)
  645. for_each_pipe(pipe)
  646. DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
  647. pipe_name(pipe),
  648. I915_READ(FDI_RX_IIR(pipe)));
  649. }
  650. static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
  651. {
  652. struct drm_device *dev = (struct drm_device *) arg;
  653. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  654. u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
  655. irqreturn_t ret = IRQ_NONE;
  656. int i;
  657. atomic_inc(&dev_priv->irq_received);
  658. /* disable master interrupt before clearing iir */
  659. de_ier = I915_READ(DEIER);
  660. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  661. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  662. * interrupts will will be stored on its back queue, and then we'll be
  663. * able to process them after we restore SDEIER (as soon as we restore
  664. * it, we'll get an interrupt if SDEIIR still has something to process
  665. * due to its back queue). */
  666. if (!HAS_PCH_NOP(dev)) {
  667. sde_ier = I915_READ(SDEIER);
  668. I915_WRITE(SDEIER, 0);
  669. POSTING_READ(SDEIER);
  670. }
  671. gt_iir = I915_READ(GTIIR);
  672. if (gt_iir) {
  673. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  674. I915_WRITE(GTIIR, gt_iir);
  675. ret = IRQ_HANDLED;
  676. }
  677. de_iir = I915_READ(DEIIR);
  678. if (de_iir) {
  679. if (de_iir & DE_AUX_CHANNEL_A_IVB)
  680. dp_aux_irq_handler(dev);
  681. if (de_iir & DE_GSE_IVB)
  682. intel_opregion_gse_intr(dev);
  683. for (i = 0; i < 3; i++) {
  684. if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
  685. drm_handle_vblank(dev, i);
  686. if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
  687. intel_prepare_page_flip(dev, i);
  688. intel_finish_page_flip_plane(dev, i);
  689. }
  690. }
  691. /* check event from PCH */
  692. if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
  693. u32 pch_iir = I915_READ(SDEIIR);
  694. cpt_irq_handler(dev, pch_iir);
  695. /* clear PCH hotplug event before clear CPU irq */
  696. I915_WRITE(SDEIIR, pch_iir);
  697. }
  698. I915_WRITE(DEIIR, de_iir);
  699. ret = IRQ_HANDLED;
  700. }
  701. pm_iir = I915_READ(GEN6_PMIIR);
  702. if (pm_iir) {
  703. if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
  704. gen6_queue_rps_work(dev_priv, pm_iir);
  705. I915_WRITE(GEN6_PMIIR, pm_iir);
  706. ret = IRQ_HANDLED;
  707. }
  708. I915_WRITE(DEIER, de_ier);
  709. POSTING_READ(DEIER);
  710. if (!HAS_PCH_NOP(dev)) {
  711. I915_WRITE(SDEIER, sde_ier);
  712. POSTING_READ(SDEIER);
  713. }
  714. return ret;
  715. }
  716. static void ilk_gt_irq_handler(struct drm_device *dev,
  717. struct drm_i915_private *dev_priv,
  718. u32 gt_iir)
  719. {
  720. if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
  721. notify_ring(dev, &dev_priv->ring[RCS]);
  722. if (gt_iir & GT_BSD_USER_INTERRUPT)
  723. notify_ring(dev, &dev_priv->ring[VCS]);
  724. }
  725. static irqreturn_t ironlake_irq_handler(int irq, void *arg)
  726. {
  727. struct drm_device *dev = (struct drm_device *) arg;
  728. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  729. int ret = IRQ_NONE;
  730. u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
  731. atomic_inc(&dev_priv->irq_received);
  732. /* disable master interrupt before clearing iir */
  733. de_ier = I915_READ(DEIER);
  734. I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
  735. POSTING_READ(DEIER);
  736. /* Disable south interrupts. We'll only write to SDEIIR once, so further
  737. * interrupts will will be stored on its back queue, and then we'll be
  738. * able to process them after we restore SDEIER (as soon as we restore
  739. * it, we'll get an interrupt if SDEIIR still has something to process
  740. * due to its back queue). */
  741. sde_ier = I915_READ(SDEIER);
  742. I915_WRITE(SDEIER, 0);
  743. POSTING_READ(SDEIER);
  744. de_iir = I915_READ(DEIIR);
  745. gt_iir = I915_READ(GTIIR);
  746. pm_iir = I915_READ(GEN6_PMIIR);
  747. if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
  748. goto done;
  749. ret = IRQ_HANDLED;
  750. if (IS_GEN5(dev))
  751. ilk_gt_irq_handler(dev, dev_priv, gt_iir);
  752. else
  753. snb_gt_irq_handler(dev, dev_priv, gt_iir);
  754. if (de_iir & DE_AUX_CHANNEL_A)
  755. dp_aux_irq_handler(dev);
  756. if (de_iir & DE_GSE)
  757. intel_opregion_gse_intr(dev);
  758. if (de_iir & DE_PIPEA_VBLANK)
  759. drm_handle_vblank(dev, 0);
  760. if (de_iir & DE_PIPEB_VBLANK)
  761. drm_handle_vblank(dev, 1);
  762. if (de_iir & DE_PLANEA_FLIP_DONE) {
  763. intel_prepare_page_flip(dev, 0);
  764. intel_finish_page_flip_plane(dev, 0);
  765. }
  766. if (de_iir & DE_PLANEB_FLIP_DONE) {
  767. intel_prepare_page_flip(dev, 1);
  768. intel_finish_page_flip_plane(dev, 1);
  769. }
  770. /* check event from PCH */
  771. if (de_iir & DE_PCH_EVENT) {
  772. u32 pch_iir = I915_READ(SDEIIR);
  773. if (HAS_PCH_CPT(dev))
  774. cpt_irq_handler(dev, pch_iir);
  775. else
  776. ibx_irq_handler(dev, pch_iir);
  777. /* should clear PCH hotplug event before clear CPU irq */
  778. I915_WRITE(SDEIIR, pch_iir);
  779. }
  780. if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
  781. ironlake_handle_rps_change(dev);
  782. if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
  783. gen6_queue_rps_work(dev_priv, pm_iir);
  784. I915_WRITE(GTIIR, gt_iir);
  785. I915_WRITE(DEIIR, de_iir);
  786. I915_WRITE(GEN6_PMIIR, pm_iir);
  787. done:
  788. I915_WRITE(DEIER, de_ier);
  789. POSTING_READ(DEIER);
  790. I915_WRITE(SDEIER, sde_ier);
  791. POSTING_READ(SDEIER);
  792. return ret;
  793. }
  794. /**
  795. * i915_error_work_func - do process context error handling work
  796. * @work: work struct
  797. *
  798. * Fire an error uevent so userspace can see that a hang or error
  799. * was detected.
  800. */
  801. static void i915_error_work_func(struct work_struct *work)
  802. {
  803. struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
  804. work);
  805. drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
  806. gpu_error);
  807. struct drm_device *dev = dev_priv->dev;
  808. struct intel_ring_buffer *ring;
  809. char *error_event[] = { "ERROR=1", NULL };
  810. char *reset_event[] = { "RESET=1", NULL };
  811. char *reset_done_event[] = { "ERROR=0", NULL };
  812. int i, ret;
  813. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  814. /*
  815. * Note that there's only one work item which does gpu resets, so we
  816. * need not worry about concurrent gpu resets potentially incrementing
  817. * error->reset_counter twice. We only need to take care of another
  818. * racing irq/hangcheck declaring the gpu dead for a second time. A
  819. * quick check for that is good enough: schedule_work ensures the
  820. * correct ordering between hang detection and this work item, and since
  821. * the reset in-progress bit is only ever set by code outside of this
  822. * work we don't need to worry about any other races.
  823. */
  824. if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
  825. DRM_DEBUG_DRIVER("resetting chip\n");
  826. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
  827. reset_event);
  828. ret = i915_reset(dev);
  829. if (ret == 0) {
  830. /*
  831. * After all the gem state is reset, increment the reset
  832. * counter and wake up everyone waiting for the reset to
  833. * complete.
  834. *
  835. * Since unlock operations are a one-sided barrier only,
  836. * we need to insert a barrier here to order any seqno
  837. * updates before
  838. * the counter increment.
  839. */
  840. smp_mb__before_atomic_inc();
  841. atomic_inc(&dev_priv->gpu_error.reset_counter);
  842. kobject_uevent_env(&dev->primary->kdev.kobj,
  843. KOBJ_CHANGE, reset_done_event);
  844. } else {
  845. atomic_set(&error->reset_counter, I915_WEDGED);
  846. }
  847. for_each_ring(ring, dev_priv, i)
  848. wake_up_all(&ring->irq_queue);
  849. intel_display_handle_reset(dev);
  850. wake_up_all(&dev_priv->gpu_error.reset_queue);
  851. }
  852. }
  853. /* NB: please notice the memset */
  854. static void i915_get_extra_instdone(struct drm_device *dev,
  855. uint32_t *instdone)
  856. {
  857. struct drm_i915_private *dev_priv = dev->dev_private;
  858. memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
  859. switch(INTEL_INFO(dev)->gen) {
  860. case 2:
  861. case 3:
  862. instdone[0] = I915_READ(INSTDONE);
  863. break;
  864. case 4:
  865. case 5:
  866. case 6:
  867. instdone[0] = I915_READ(INSTDONE_I965);
  868. instdone[1] = I915_READ(INSTDONE1);
  869. break;
  870. default:
  871. WARN_ONCE(1, "Unsupported platform\n");
  872. case 7:
  873. instdone[0] = I915_READ(GEN7_INSTDONE_1);
  874. instdone[1] = I915_READ(GEN7_SC_INSTDONE);
  875. instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
  876. instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
  877. break;
  878. }
  879. }
  880. #ifdef CONFIG_DEBUG_FS
  881. static struct drm_i915_error_object *
  882. i915_error_object_create_sized(struct drm_i915_private *dev_priv,
  883. struct drm_i915_gem_object *src,
  884. const int num_pages)
  885. {
  886. struct drm_i915_error_object *dst;
  887. int i;
  888. u32 reloc_offset;
  889. if (src == NULL || src->pages == NULL)
  890. return NULL;
  891. dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
  892. if (dst == NULL)
  893. return NULL;
  894. reloc_offset = src->gtt_offset;
  895. for (i = 0; i < num_pages; i++) {
  896. unsigned long flags;
  897. void *d;
  898. d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
  899. if (d == NULL)
  900. goto unwind;
  901. local_irq_save(flags);
  902. if (reloc_offset < dev_priv->gtt.mappable_end &&
  903. src->has_global_gtt_mapping) {
  904. void __iomem *s;
  905. /* Simply ignore tiling or any overlapping fence.
  906. * It's part of the error state, and this hopefully
  907. * captures what the GPU read.
  908. */
  909. s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
  910. reloc_offset);
  911. memcpy_fromio(d, s, PAGE_SIZE);
  912. io_mapping_unmap_atomic(s);
  913. } else if (src->stolen) {
  914. unsigned long offset;
  915. offset = dev_priv->mm.stolen_base;
  916. offset += src->stolen->start;
  917. offset += i << PAGE_SHIFT;
  918. memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
  919. } else {
  920. struct page *page;
  921. void *s;
  922. page = i915_gem_object_get_page(src, i);
  923. drm_clflush_pages(&page, 1);
  924. s = kmap_atomic(page);
  925. memcpy(d, s, PAGE_SIZE);
  926. kunmap_atomic(s);
  927. drm_clflush_pages(&page, 1);
  928. }
  929. local_irq_restore(flags);
  930. dst->pages[i] = d;
  931. reloc_offset += PAGE_SIZE;
  932. }
  933. dst->page_count = num_pages;
  934. dst->gtt_offset = src->gtt_offset;
  935. return dst;
  936. unwind:
  937. while (i--)
  938. kfree(dst->pages[i]);
  939. kfree(dst);
  940. return NULL;
  941. }
  942. #define i915_error_object_create(dev_priv, src) \
  943. i915_error_object_create_sized((dev_priv), (src), \
  944. (src)->base.size>>PAGE_SHIFT)
  945. static void
  946. i915_error_object_free(struct drm_i915_error_object *obj)
  947. {
  948. int page;
  949. if (obj == NULL)
  950. return;
  951. for (page = 0; page < obj->page_count; page++)
  952. kfree(obj->pages[page]);
  953. kfree(obj);
  954. }
  955. void
  956. i915_error_state_free(struct kref *error_ref)
  957. {
  958. struct drm_i915_error_state *error = container_of(error_ref,
  959. typeof(*error), ref);
  960. int i;
  961. for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
  962. i915_error_object_free(error->ring[i].batchbuffer);
  963. i915_error_object_free(error->ring[i].ringbuffer);
  964. kfree(error->ring[i].requests);
  965. }
  966. kfree(error->active_bo);
  967. kfree(error->overlay);
  968. kfree(error);
  969. }
  970. static void capture_bo(struct drm_i915_error_buffer *err,
  971. struct drm_i915_gem_object *obj)
  972. {
  973. err->size = obj->base.size;
  974. err->name = obj->base.name;
  975. err->rseqno = obj->last_read_seqno;
  976. err->wseqno = obj->last_write_seqno;
  977. err->gtt_offset = obj->gtt_offset;
  978. err->read_domains = obj->base.read_domains;
  979. err->write_domain = obj->base.write_domain;
  980. err->fence_reg = obj->fence_reg;
  981. err->pinned = 0;
  982. if (obj->pin_count > 0)
  983. err->pinned = 1;
  984. if (obj->user_pin_count > 0)
  985. err->pinned = -1;
  986. err->tiling = obj->tiling_mode;
  987. err->dirty = obj->dirty;
  988. err->purgeable = obj->madv != I915_MADV_WILLNEED;
  989. err->ring = obj->ring ? obj->ring->id : -1;
  990. err->cache_level = obj->cache_level;
  991. }
  992. static u32 capture_active_bo(struct drm_i915_error_buffer *err,
  993. int count, struct list_head *head)
  994. {
  995. struct drm_i915_gem_object *obj;
  996. int i = 0;
  997. list_for_each_entry(obj, head, mm_list) {
  998. capture_bo(err++, obj);
  999. if (++i == count)
  1000. break;
  1001. }
  1002. return i;
  1003. }
  1004. static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
  1005. int count, struct list_head *head)
  1006. {
  1007. struct drm_i915_gem_object *obj;
  1008. int i = 0;
  1009. list_for_each_entry(obj, head, gtt_list) {
  1010. if (obj->pin_count == 0)
  1011. continue;
  1012. capture_bo(err++, obj);
  1013. if (++i == count)
  1014. break;
  1015. }
  1016. return i;
  1017. }
  1018. static void i915_gem_record_fences(struct drm_device *dev,
  1019. struct drm_i915_error_state *error)
  1020. {
  1021. struct drm_i915_private *dev_priv = dev->dev_private;
  1022. int i;
  1023. /* Fences */
  1024. switch (INTEL_INFO(dev)->gen) {
  1025. case 7:
  1026. case 6:
  1027. for (i = 0; i < dev_priv->num_fence_regs; i++)
  1028. error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
  1029. break;
  1030. case 5:
  1031. case 4:
  1032. for (i = 0; i < 16; i++)
  1033. error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
  1034. break;
  1035. case 3:
  1036. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  1037. for (i = 0; i < 8; i++)
  1038. error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
  1039. case 2:
  1040. for (i = 0; i < 8; i++)
  1041. error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
  1042. break;
  1043. default:
  1044. BUG();
  1045. }
  1046. }
  1047. static struct drm_i915_error_object *
  1048. i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
  1049. struct intel_ring_buffer *ring)
  1050. {
  1051. struct drm_i915_gem_object *obj;
  1052. u32 seqno;
  1053. if (!ring->get_seqno)
  1054. return NULL;
  1055. if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
  1056. u32 acthd = I915_READ(ACTHD);
  1057. if (WARN_ON(ring->id != RCS))
  1058. return NULL;
  1059. obj = ring->private;
  1060. if (acthd >= obj->gtt_offset &&
  1061. acthd < obj->gtt_offset + obj->base.size)
  1062. return i915_error_object_create(dev_priv, obj);
  1063. }
  1064. seqno = ring->get_seqno(ring, false);
  1065. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
  1066. if (obj->ring != ring)
  1067. continue;
  1068. if (i915_seqno_passed(seqno, obj->last_read_seqno))
  1069. continue;
  1070. if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
  1071. continue;
  1072. /* We need to copy these to an anonymous buffer as the simplest
  1073. * method to avoid being overwritten by userspace.
  1074. */
  1075. return i915_error_object_create(dev_priv, obj);
  1076. }
  1077. return NULL;
  1078. }
  1079. static void i915_record_ring_state(struct drm_device *dev,
  1080. struct drm_i915_error_state *error,
  1081. struct intel_ring_buffer *ring)
  1082. {
  1083. struct drm_i915_private *dev_priv = dev->dev_private;
  1084. if (INTEL_INFO(dev)->gen >= 6) {
  1085. error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
  1086. error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
  1087. error->semaphore_mboxes[ring->id][0]
  1088. = I915_READ(RING_SYNC_0(ring->mmio_base));
  1089. error->semaphore_mboxes[ring->id][1]
  1090. = I915_READ(RING_SYNC_1(ring->mmio_base));
  1091. error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
  1092. error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
  1093. }
  1094. if (INTEL_INFO(dev)->gen >= 4) {
  1095. error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
  1096. error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
  1097. error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
  1098. error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
  1099. error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
  1100. if (ring->id == RCS)
  1101. error->bbaddr = I915_READ64(BB_ADDR);
  1102. } else {
  1103. error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
  1104. error->ipeir[ring->id] = I915_READ(IPEIR);
  1105. error->ipehr[ring->id] = I915_READ(IPEHR);
  1106. error->instdone[ring->id] = I915_READ(INSTDONE);
  1107. }
  1108. error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
  1109. error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
  1110. error->seqno[ring->id] = ring->get_seqno(ring, false);
  1111. error->acthd[ring->id] = intel_ring_get_active_head(ring);
  1112. error->head[ring->id] = I915_READ_HEAD(ring);
  1113. error->tail[ring->id] = I915_READ_TAIL(ring);
  1114. error->ctl[ring->id] = I915_READ_CTL(ring);
  1115. error->cpu_ring_head[ring->id] = ring->head;
  1116. error->cpu_ring_tail[ring->id] = ring->tail;
  1117. }
  1118. static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
  1119. struct drm_i915_error_state *error,
  1120. struct drm_i915_error_ring *ering)
  1121. {
  1122. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1123. struct drm_i915_gem_object *obj;
  1124. /* Currently render ring is the only HW context user */
  1125. if (ring->id != RCS || !error->ccid)
  1126. return;
  1127. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
  1128. if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
  1129. ering->ctx = i915_error_object_create_sized(dev_priv,
  1130. obj, 1);
  1131. }
  1132. }
  1133. }
  1134. static void i915_gem_record_rings(struct drm_device *dev,
  1135. struct drm_i915_error_state *error)
  1136. {
  1137. struct drm_i915_private *dev_priv = dev->dev_private;
  1138. struct intel_ring_buffer *ring;
  1139. struct drm_i915_gem_request *request;
  1140. int i, count;
  1141. for_each_ring(ring, dev_priv, i) {
  1142. i915_record_ring_state(dev, error, ring);
  1143. error->ring[i].batchbuffer =
  1144. i915_error_first_batchbuffer(dev_priv, ring);
  1145. error->ring[i].ringbuffer =
  1146. i915_error_object_create(dev_priv, ring->obj);
  1147. i915_gem_record_active_context(ring, error, &error->ring[i]);
  1148. count = 0;
  1149. list_for_each_entry(request, &ring->request_list, list)
  1150. count++;
  1151. error->ring[i].num_requests = count;
  1152. error->ring[i].requests =
  1153. kmalloc(count*sizeof(struct drm_i915_error_request),
  1154. GFP_ATOMIC);
  1155. if (error->ring[i].requests == NULL) {
  1156. error->ring[i].num_requests = 0;
  1157. continue;
  1158. }
  1159. count = 0;
  1160. list_for_each_entry(request, &ring->request_list, list) {
  1161. struct drm_i915_error_request *erq;
  1162. erq = &error->ring[i].requests[count++];
  1163. erq->seqno = request->seqno;
  1164. erq->jiffies = request->emitted_jiffies;
  1165. erq->tail = request->tail;
  1166. }
  1167. }
  1168. }
  1169. /**
  1170. * i915_capture_error_state - capture an error record for later analysis
  1171. * @dev: drm device
  1172. *
  1173. * Should be called when an error is detected (either a hang or an error
  1174. * interrupt) to capture error state from the time of the error. Fills
  1175. * out a structure which becomes available in debugfs for user level tools
  1176. * to pick up.
  1177. */
  1178. static void i915_capture_error_state(struct drm_device *dev)
  1179. {
  1180. struct drm_i915_private *dev_priv = dev->dev_private;
  1181. struct drm_i915_gem_object *obj;
  1182. struct drm_i915_error_state *error;
  1183. unsigned long flags;
  1184. int i, pipe;
  1185. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1186. error = dev_priv->gpu_error.first_error;
  1187. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1188. if (error)
  1189. return;
  1190. /* Account for pipe specific data like PIPE*STAT */
  1191. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  1192. if (!error) {
  1193. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  1194. return;
  1195. }
  1196. DRM_INFO("capturing error event; look for more information in "
  1197. "/sys/kernel/debug/dri/%d/i915_error_state\n",
  1198. dev->primary->index);
  1199. kref_init(&error->ref);
  1200. error->eir = I915_READ(EIR);
  1201. error->pgtbl_er = I915_READ(PGTBL_ER);
  1202. if (HAS_HW_CONTEXTS(dev))
  1203. error->ccid = I915_READ(CCID);
  1204. if (HAS_PCH_SPLIT(dev))
  1205. error->ier = I915_READ(DEIER) | I915_READ(GTIER);
  1206. else if (IS_VALLEYVIEW(dev))
  1207. error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
  1208. else if (IS_GEN2(dev))
  1209. error->ier = I915_READ16(IER);
  1210. else
  1211. error->ier = I915_READ(IER);
  1212. if (INTEL_INFO(dev)->gen >= 6)
  1213. error->derrmr = I915_READ(DERRMR);
  1214. if (IS_VALLEYVIEW(dev))
  1215. error->forcewake = I915_READ(FORCEWAKE_VLV);
  1216. else if (INTEL_INFO(dev)->gen >= 7)
  1217. error->forcewake = I915_READ(FORCEWAKE_MT);
  1218. else if (INTEL_INFO(dev)->gen == 6)
  1219. error->forcewake = I915_READ(FORCEWAKE);
  1220. if (!HAS_PCH_SPLIT(dev))
  1221. for_each_pipe(pipe)
  1222. error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
  1223. if (INTEL_INFO(dev)->gen >= 6) {
  1224. error->error = I915_READ(ERROR_GEN6);
  1225. error->done_reg = I915_READ(DONE_REG);
  1226. }
  1227. if (INTEL_INFO(dev)->gen == 7)
  1228. error->err_int = I915_READ(GEN7_ERR_INT);
  1229. i915_get_extra_instdone(dev, error->extra_instdone);
  1230. i915_gem_record_fences(dev, error);
  1231. i915_gem_record_rings(dev, error);
  1232. /* Record buffers on the active and pinned lists. */
  1233. error->active_bo = NULL;
  1234. error->pinned_bo = NULL;
  1235. i = 0;
  1236. list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
  1237. i++;
  1238. error->active_bo_count = i;
  1239. list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
  1240. if (obj->pin_count)
  1241. i++;
  1242. error->pinned_bo_count = i - error->active_bo_count;
  1243. error->active_bo = NULL;
  1244. error->pinned_bo = NULL;
  1245. if (i) {
  1246. error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
  1247. GFP_ATOMIC);
  1248. if (error->active_bo)
  1249. error->pinned_bo =
  1250. error->active_bo + error->active_bo_count;
  1251. }
  1252. if (error->active_bo)
  1253. error->active_bo_count =
  1254. capture_active_bo(error->active_bo,
  1255. error->active_bo_count,
  1256. &dev_priv->mm.active_list);
  1257. if (error->pinned_bo)
  1258. error->pinned_bo_count =
  1259. capture_pinned_bo(error->pinned_bo,
  1260. error->pinned_bo_count,
  1261. &dev_priv->mm.bound_list);
  1262. do_gettimeofday(&error->time);
  1263. error->overlay = intel_overlay_capture_error_state(dev);
  1264. error->display = intel_display_capture_error_state(dev);
  1265. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1266. if (dev_priv->gpu_error.first_error == NULL) {
  1267. dev_priv->gpu_error.first_error = error;
  1268. error = NULL;
  1269. }
  1270. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1271. if (error)
  1272. i915_error_state_free(&error->ref);
  1273. }
  1274. void i915_destroy_error_state(struct drm_device *dev)
  1275. {
  1276. struct drm_i915_private *dev_priv = dev->dev_private;
  1277. struct drm_i915_error_state *error;
  1278. unsigned long flags;
  1279. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1280. error = dev_priv->gpu_error.first_error;
  1281. dev_priv->gpu_error.first_error = NULL;
  1282. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1283. if (error)
  1284. kref_put(&error->ref, i915_error_state_free);
  1285. }
  1286. #else
  1287. #define i915_capture_error_state(x)
  1288. #endif
  1289. static void i915_report_and_clear_eir(struct drm_device *dev)
  1290. {
  1291. struct drm_i915_private *dev_priv = dev->dev_private;
  1292. uint32_t instdone[I915_NUM_INSTDONE_REG];
  1293. u32 eir = I915_READ(EIR);
  1294. int pipe, i;
  1295. if (!eir)
  1296. return;
  1297. pr_err("render error detected, EIR: 0x%08x\n", eir);
  1298. i915_get_extra_instdone(dev, instdone);
  1299. if (IS_G4X(dev)) {
  1300. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  1301. u32 ipeir = I915_READ(IPEIR_I965);
  1302. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1303. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1304. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1305. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1306. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1307. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1308. I915_WRITE(IPEIR_I965, ipeir);
  1309. POSTING_READ(IPEIR_I965);
  1310. }
  1311. if (eir & GM45_ERROR_PAGE_TABLE) {
  1312. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1313. pr_err("page table error\n");
  1314. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1315. I915_WRITE(PGTBL_ER, pgtbl_err);
  1316. POSTING_READ(PGTBL_ER);
  1317. }
  1318. }
  1319. if (!IS_GEN2(dev)) {
  1320. if (eir & I915_ERROR_PAGE_TABLE) {
  1321. u32 pgtbl_err = I915_READ(PGTBL_ER);
  1322. pr_err("page table error\n");
  1323. pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
  1324. I915_WRITE(PGTBL_ER, pgtbl_err);
  1325. POSTING_READ(PGTBL_ER);
  1326. }
  1327. }
  1328. if (eir & I915_ERROR_MEMORY_REFRESH) {
  1329. pr_err("memory refresh error:\n");
  1330. for_each_pipe(pipe)
  1331. pr_err("pipe %c stat: 0x%08x\n",
  1332. pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
  1333. /* pipestat has already been acked */
  1334. }
  1335. if (eir & I915_ERROR_INSTRUCTION) {
  1336. pr_err("instruction error\n");
  1337. pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
  1338. for (i = 0; i < ARRAY_SIZE(instdone); i++)
  1339. pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
  1340. if (INTEL_INFO(dev)->gen < 4) {
  1341. u32 ipeir = I915_READ(IPEIR);
  1342. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
  1343. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
  1344. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
  1345. I915_WRITE(IPEIR, ipeir);
  1346. POSTING_READ(IPEIR);
  1347. } else {
  1348. u32 ipeir = I915_READ(IPEIR_I965);
  1349. pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
  1350. pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
  1351. pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
  1352. pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
  1353. I915_WRITE(IPEIR_I965, ipeir);
  1354. POSTING_READ(IPEIR_I965);
  1355. }
  1356. }
  1357. I915_WRITE(EIR, eir);
  1358. POSTING_READ(EIR);
  1359. eir = I915_READ(EIR);
  1360. if (eir) {
  1361. /*
  1362. * some errors might have become stuck,
  1363. * mask them.
  1364. */
  1365. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  1366. I915_WRITE(EMR, I915_READ(EMR) | eir);
  1367. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1368. }
  1369. }
  1370. /**
  1371. * i915_handle_error - handle an error interrupt
  1372. * @dev: drm device
  1373. *
  1374. * Do some basic checking of regsiter state at error interrupt time and
  1375. * dump it to the syslog. Also call i915_capture_error_state() to make
  1376. * sure we get a record and make it available in debugfs. Fire a uevent
  1377. * so userspace knows something bad happened (should trigger collection
  1378. * of a ring dump etc.).
  1379. */
  1380. void i915_handle_error(struct drm_device *dev, bool wedged)
  1381. {
  1382. struct drm_i915_private *dev_priv = dev->dev_private;
  1383. struct intel_ring_buffer *ring;
  1384. int i;
  1385. i915_capture_error_state(dev);
  1386. i915_report_and_clear_eir(dev);
  1387. if (wedged) {
  1388. atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
  1389. &dev_priv->gpu_error.reset_counter);
  1390. /*
  1391. * Wakeup waiting processes so that the reset work item
  1392. * doesn't deadlock trying to grab various locks.
  1393. */
  1394. for_each_ring(ring, dev_priv, i)
  1395. wake_up_all(&ring->irq_queue);
  1396. }
  1397. queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
  1398. }
  1399. static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
  1400. {
  1401. drm_i915_private_t *dev_priv = dev->dev_private;
  1402. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1403. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1404. struct drm_i915_gem_object *obj;
  1405. struct intel_unpin_work *work;
  1406. unsigned long flags;
  1407. bool stall_detected;
  1408. /* Ignore early vblank irqs */
  1409. if (intel_crtc == NULL)
  1410. return;
  1411. spin_lock_irqsave(&dev->event_lock, flags);
  1412. work = intel_crtc->unpin_work;
  1413. if (work == NULL ||
  1414. atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
  1415. !work->enable_stall_check) {
  1416. /* Either the pending flip IRQ arrived, or we're too early. Don't check */
  1417. spin_unlock_irqrestore(&dev->event_lock, flags);
  1418. return;
  1419. }
  1420. /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
  1421. obj = work->pending_flip_obj;
  1422. if (INTEL_INFO(dev)->gen >= 4) {
  1423. int dspsurf = DSPSURF(intel_crtc->plane);
  1424. stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
  1425. obj->gtt_offset;
  1426. } else {
  1427. int dspaddr = DSPADDR(intel_crtc->plane);
  1428. stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
  1429. crtc->y * crtc->fb->pitches[0] +
  1430. crtc->x * crtc->fb->bits_per_pixel/8);
  1431. }
  1432. spin_unlock_irqrestore(&dev->event_lock, flags);
  1433. if (stall_detected) {
  1434. DRM_DEBUG_DRIVER("Pageflip stall detected\n");
  1435. intel_prepare_page_flip(dev, intel_crtc->plane);
  1436. }
  1437. }
  1438. /* Called from drm generic code, passed 'crtc' which
  1439. * we use as a pipe index
  1440. */
  1441. static int i915_enable_vblank(struct drm_device *dev, int pipe)
  1442. {
  1443. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1444. unsigned long irqflags;
  1445. if (!i915_pipe_enabled(dev, pipe))
  1446. return -EINVAL;
  1447. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1448. if (INTEL_INFO(dev)->gen >= 4)
  1449. i915_enable_pipestat(dev_priv, pipe,
  1450. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1451. else
  1452. i915_enable_pipestat(dev_priv, pipe,
  1453. PIPE_VBLANK_INTERRUPT_ENABLE);
  1454. /* maintain vblank delivery even in deep C-states */
  1455. if (dev_priv->info->gen == 3)
  1456. I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
  1457. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1458. return 0;
  1459. }
  1460. static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
  1461. {
  1462. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1463. unsigned long irqflags;
  1464. if (!i915_pipe_enabled(dev, pipe))
  1465. return -EINVAL;
  1466. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1467. ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
  1468. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1469. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1470. return 0;
  1471. }
  1472. static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
  1473. {
  1474. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1475. unsigned long irqflags;
  1476. if (!i915_pipe_enabled(dev, pipe))
  1477. return -EINVAL;
  1478. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1479. ironlake_enable_display_irq(dev_priv,
  1480. DE_PIPEA_VBLANK_IVB << (5 * pipe));
  1481. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1482. return 0;
  1483. }
  1484. static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
  1485. {
  1486. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1487. unsigned long irqflags;
  1488. u32 imr;
  1489. if (!i915_pipe_enabled(dev, pipe))
  1490. return -EINVAL;
  1491. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1492. imr = I915_READ(VLV_IMR);
  1493. if (pipe == 0)
  1494. imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1495. else
  1496. imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1497. I915_WRITE(VLV_IMR, imr);
  1498. i915_enable_pipestat(dev_priv, pipe,
  1499. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1500. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1501. return 0;
  1502. }
  1503. /* Called from drm generic code, passed 'crtc' which
  1504. * we use as a pipe index
  1505. */
  1506. static void i915_disable_vblank(struct drm_device *dev, int pipe)
  1507. {
  1508. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1509. unsigned long irqflags;
  1510. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1511. if (dev_priv->info->gen == 3)
  1512. I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
  1513. i915_disable_pipestat(dev_priv, pipe,
  1514. PIPE_VBLANK_INTERRUPT_ENABLE |
  1515. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1516. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1517. }
  1518. static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
  1519. {
  1520. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1521. unsigned long irqflags;
  1522. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1523. ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
  1524. DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
  1525. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1526. }
  1527. static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
  1528. {
  1529. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1530. unsigned long irqflags;
  1531. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1532. ironlake_disable_display_irq(dev_priv,
  1533. DE_PIPEA_VBLANK_IVB << (pipe * 5));
  1534. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1535. }
  1536. static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
  1537. {
  1538. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1539. unsigned long irqflags;
  1540. u32 imr;
  1541. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  1542. i915_disable_pipestat(dev_priv, pipe,
  1543. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  1544. imr = I915_READ(VLV_IMR);
  1545. if (pipe == 0)
  1546. imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
  1547. else
  1548. imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1549. I915_WRITE(VLV_IMR, imr);
  1550. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  1551. }
  1552. static u32
  1553. ring_last_seqno(struct intel_ring_buffer *ring)
  1554. {
  1555. return list_entry(ring->request_list.prev,
  1556. struct drm_i915_gem_request, list)->seqno;
  1557. }
  1558. static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
  1559. {
  1560. if (list_empty(&ring->request_list) ||
  1561. i915_seqno_passed(ring->get_seqno(ring, false),
  1562. ring_last_seqno(ring))) {
  1563. /* Issue a wake-up to catch stuck h/w. */
  1564. if (waitqueue_active(&ring->irq_queue)) {
  1565. DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
  1566. ring->name);
  1567. wake_up_all(&ring->irq_queue);
  1568. *err = true;
  1569. }
  1570. return true;
  1571. }
  1572. return false;
  1573. }
  1574. static bool semaphore_passed(struct intel_ring_buffer *ring)
  1575. {
  1576. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  1577. u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
  1578. struct intel_ring_buffer *signaller;
  1579. u32 cmd, ipehr, acthd_min;
  1580. ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
  1581. if ((ipehr & ~(0x3 << 16)) !=
  1582. (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
  1583. return false;
  1584. /* ACTHD is likely pointing to the dword after the actual command,
  1585. * so scan backwards until we find the MBOX.
  1586. */
  1587. acthd_min = max((int)acthd - 3 * 4, 0);
  1588. do {
  1589. cmd = ioread32(ring->virtual_start + acthd);
  1590. if (cmd == ipehr)
  1591. break;
  1592. acthd -= 4;
  1593. if (acthd < acthd_min)
  1594. return false;
  1595. } while (1);
  1596. signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
  1597. return i915_seqno_passed(signaller->get_seqno(signaller, false),
  1598. ioread32(ring->virtual_start+acthd+4)+1);
  1599. }
  1600. static bool kick_ring(struct intel_ring_buffer *ring)
  1601. {
  1602. struct drm_device *dev = ring->dev;
  1603. struct drm_i915_private *dev_priv = dev->dev_private;
  1604. u32 tmp = I915_READ_CTL(ring);
  1605. if (tmp & RING_WAIT) {
  1606. DRM_ERROR("Kicking stuck wait on %s\n",
  1607. ring->name);
  1608. I915_WRITE_CTL(ring, tmp);
  1609. return true;
  1610. }
  1611. if (INTEL_INFO(dev)->gen >= 6 &&
  1612. tmp & RING_WAIT_SEMAPHORE &&
  1613. semaphore_passed(ring)) {
  1614. DRM_ERROR("Kicking stuck semaphore on %s\n",
  1615. ring->name);
  1616. I915_WRITE_CTL(ring, tmp);
  1617. return true;
  1618. }
  1619. return false;
  1620. }
  1621. static bool i915_hangcheck_hung(struct drm_device *dev)
  1622. {
  1623. drm_i915_private_t *dev_priv = dev->dev_private;
  1624. if (dev_priv->gpu_error.hangcheck_count++ > 1) {
  1625. bool hung = true;
  1626. DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
  1627. i915_handle_error(dev, true);
  1628. if (!IS_GEN2(dev)) {
  1629. struct intel_ring_buffer *ring;
  1630. int i;
  1631. /* Is the chip hanging on a WAIT_FOR_EVENT?
  1632. * If so we can simply poke the RB_WAIT bit
  1633. * and break the hang. This should work on
  1634. * all but the second generation chipsets.
  1635. */
  1636. for_each_ring(ring, dev_priv, i)
  1637. hung &= !kick_ring(ring);
  1638. }
  1639. return hung;
  1640. }
  1641. return false;
  1642. }
  1643. /**
  1644. * This is called when the chip hasn't reported back with completed
  1645. * batchbuffers in a long time. The first time this is called we simply record
  1646. * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  1647. * again, we assume the chip is wedged and try to fix it.
  1648. */
  1649. void i915_hangcheck_elapsed(unsigned long data)
  1650. {
  1651. struct drm_device *dev = (struct drm_device *)data;
  1652. drm_i915_private_t *dev_priv = dev->dev_private;
  1653. uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
  1654. struct intel_ring_buffer *ring;
  1655. bool err = false, idle;
  1656. int i;
  1657. if (!i915_enable_hangcheck)
  1658. return;
  1659. memset(acthd, 0, sizeof(acthd));
  1660. idle = true;
  1661. for_each_ring(ring, dev_priv, i) {
  1662. idle &= i915_hangcheck_ring_idle(ring, &err);
  1663. acthd[i] = intel_ring_get_active_head(ring);
  1664. }
  1665. /* If all work is done then ACTHD clearly hasn't advanced. */
  1666. if (idle) {
  1667. if (err) {
  1668. if (i915_hangcheck_hung(dev))
  1669. return;
  1670. goto repeat;
  1671. }
  1672. dev_priv->gpu_error.hangcheck_count = 0;
  1673. return;
  1674. }
  1675. i915_get_extra_instdone(dev, instdone);
  1676. if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
  1677. sizeof(acthd)) == 0 &&
  1678. memcmp(dev_priv->gpu_error.prev_instdone, instdone,
  1679. sizeof(instdone)) == 0) {
  1680. if (i915_hangcheck_hung(dev))
  1681. return;
  1682. } else {
  1683. dev_priv->gpu_error.hangcheck_count = 0;
  1684. memcpy(dev_priv->gpu_error.last_acthd, acthd,
  1685. sizeof(acthd));
  1686. memcpy(dev_priv->gpu_error.prev_instdone, instdone,
  1687. sizeof(instdone));
  1688. }
  1689. repeat:
  1690. /* Reset timer case chip hangs without another request being added */
  1691. mod_timer(&dev_priv->gpu_error.hangcheck_timer,
  1692. round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
  1693. }
  1694. /* drm_dma.h hooks
  1695. */
  1696. static void ironlake_irq_preinstall(struct drm_device *dev)
  1697. {
  1698. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1699. atomic_set(&dev_priv->irq_received, 0);
  1700. I915_WRITE(HWSTAM, 0xeffe);
  1701. /* XXX hotplug from PCH */
  1702. I915_WRITE(DEIMR, 0xffffffff);
  1703. I915_WRITE(DEIER, 0x0);
  1704. POSTING_READ(DEIER);
  1705. /* and GT */
  1706. I915_WRITE(GTIMR, 0xffffffff);
  1707. I915_WRITE(GTIER, 0x0);
  1708. POSTING_READ(GTIER);
  1709. if (HAS_PCH_NOP(dev))
  1710. return;
  1711. /* south display irq */
  1712. I915_WRITE(SDEIMR, 0xffffffff);
  1713. /*
  1714. * SDEIER is also touched by the interrupt handler to work around missed
  1715. * PCH interrupts. Hence we can't update it after the interrupt handler
  1716. * is enabled - instead we unconditionally enable all PCH interrupt
  1717. * sources here, but then only unmask them as needed with SDEIMR.
  1718. */
  1719. I915_WRITE(SDEIER, 0xffffffff);
  1720. POSTING_READ(SDEIER);
  1721. }
  1722. static void valleyview_irq_preinstall(struct drm_device *dev)
  1723. {
  1724. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1725. int pipe;
  1726. atomic_set(&dev_priv->irq_received, 0);
  1727. /* VLV magic */
  1728. I915_WRITE(VLV_IMR, 0);
  1729. I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
  1730. I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
  1731. I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
  1732. /* and GT */
  1733. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1734. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1735. I915_WRITE(GTIMR, 0xffffffff);
  1736. I915_WRITE(GTIER, 0x0);
  1737. POSTING_READ(GTIER);
  1738. I915_WRITE(DPINVGTT, 0xff);
  1739. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1740. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1741. for_each_pipe(pipe)
  1742. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1743. I915_WRITE(VLV_IIR, 0xffffffff);
  1744. I915_WRITE(VLV_IMR, 0xffffffff);
  1745. I915_WRITE(VLV_IER, 0x0);
  1746. POSTING_READ(VLV_IER);
  1747. }
  1748. static void ibx_hpd_irq_setup(struct drm_device *dev)
  1749. {
  1750. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1751. struct drm_mode_config *mode_config = &dev->mode_config;
  1752. struct intel_encoder *intel_encoder;
  1753. u32 mask = ~I915_READ(SDEIMR);
  1754. u32 hotplug;
  1755. if (HAS_PCH_IBX(dev)) {
  1756. mask &= ~SDE_HOTPLUG_MASK;
  1757. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  1758. mask |= hpd_ibx[intel_encoder->hpd_pin];
  1759. } else {
  1760. mask &= ~SDE_HOTPLUG_MASK_CPT;
  1761. list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
  1762. mask |= hpd_cpt[intel_encoder->hpd_pin];
  1763. }
  1764. I915_WRITE(SDEIMR, ~mask);
  1765. /*
  1766. * Enable digital hotplug on the PCH, and configure the DP short pulse
  1767. * duration to 2ms (which is the minimum in the Display Port spec)
  1768. *
  1769. * This register is the same on all known PCH chips.
  1770. */
  1771. hotplug = I915_READ(PCH_PORT_HOTPLUG);
  1772. hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
  1773. hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
  1774. hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
  1775. hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
  1776. I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
  1777. }
  1778. static void ibx_irq_postinstall(struct drm_device *dev)
  1779. {
  1780. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1781. u32 mask;
  1782. if (HAS_PCH_IBX(dev))
  1783. mask = SDE_GMBUS | SDE_AUX_MASK;
  1784. else
  1785. mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
  1786. if (HAS_PCH_NOP(dev))
  1787. return;
  1788. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1789. I915_WRITE(SDEIMR, ~mask);
  1790. }
  1791. static int ironlake_irq_postinstall(struct drm_device *dev)
  1792. {
  1793. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1794. /* enable kind of interrupts always enabled */
  1795. u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
  1796. DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
  1797. DE_AUX_CHANNEL_A;
  1798. u32 render_irqs;
  1799. dev_priv->irq_mask = ~display_mask;
  1800. /* should always can generate irq */
  1801. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1802. I915_WRITE(DEIMR, dev_priv->irq_mask);
  1803. I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
  1804. POSTING_READ(DEIER);
  1805. dev_priv->gt_irq_mask = ~0;
  1806. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1807. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1808. if (IS_GEN6(dev))
  1809. render_irqs =
  1810. GT_USER_INTERRUPT |
  1811. GEN6_BSD_USER_INTERRUPT |
  1812. GEN6_BLITTER_USER_INTERRUPT;
  1813. else
  1814. render_irqs =
  1815. GT_USER_INTERRUPT |
  1816. GT_PIPE_NOTIFY |
  1817. GT_BSD_USER_INTERRUPT;
  1818. I915_WRITE(GTIER, render_irqs);
  1819. POSTING_READ(GTIER);
  1820. ibx_irq_postinstall(dev);
  1821. if (IS_IRONLAKE_M(dev)) {
  1822. /* Clear & enable PCU event interrupts */
  1823. I915_WRITE(DEIIR, DE_PCU_EVENT);
  1824. I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
  1825. ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
  1826. }
  1827. return 0;
  1828. }
  1829. static int ivybridge_irq_postinstall(struct drm_device *dev)
  1830. {
  1831. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1832. /* enable kind of interrupts always enabled */
  1833. u32 display_mask =
  1834. DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
  1835. DE_PLANEC_FLIP_DONE_IVB |
  1836. DE_PLANEB_FLIP_DONE_IVB |
  1837. DE_PLANEA_FLIP_DONE_IVB |
  1838. DE_AUX_CHANNEL_A_IVB;
  1839. u32 render_irqs;
  1840. dev_priv->irq_mask = ~display_mask;
  1841. /* should always can generate irq */
  1842. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1843. I915_WRITE(DEIMR, dev_priv->irq_mask);
  1844. I915_WRITE(DEIER,
  1845. display_mask |
  1846. DE_PIPEC_VBLANK_IVB |
  1847. DE_PIPEB_VBLANK_IVB |
  1848. DE_PIPEA_VBLANK_IVB);
  1849. POSTING_READ(DEIER);
  1850. dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  1851. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1852. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1853. render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
  1854. GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
  1855. I915_WRITE(GTIER, render_irqs);
  1856. POSTING_READ(GTIER);
  1857. ibx_irq_postinstall(dev);
  1858. return 0;
  1859. }
  1860. static int valleyview_irq_postinstall(struct drm_device *dev)
  1861. {
  1862. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1863. u32 enable_mask;
  1864. u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
  1865. u32 render_irqs;
  1866. u16 msid;
  1867. enable_mask = I915_DISPLAY_PORT_INTERRUPT;
  1868. enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1869. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  1870. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1871. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1872. /*
  1873. *Leave vblank interrupts masked initially. enable/disable will
  1874. * toggle them based on usage.
  1875. */
  1876. dev_priv->irq_mask = (~enable_mask) |
  1877. I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
  1878. I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
  1879. /* Hack for broken MSIs on VLV */
  1880. pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
  1881. pci_read_config_word(dev->pdev, 0x98, &msid);
  1882. msid &= 0xff; /* mask out delivery bits */
  1883. msid |= (1<<14);
  1884. pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
  1885. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1886. POSTING_READ(PORT_HOTPLUG_EN);
  1887. I915_WRITE(VLV_IMR, dev_priv->irq_mask);
  1888. I915_WRITE(VLV_IER, enable_mask);
  1889. I915_WRITE(VLV_IIR, 0xffffffff);
  1890. I915_WRITE(PIPESTAT(0), 0xffff);
  1891. I915_WRITE(PIPESTAT(1), 0xffff);
  1892. POSTING_READ(VLV_IER);
  1893. i915_enable_pipestat(dev_priv, 0, pipestat_enable);
  1894. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  1895. i915_enable_pipestat(dev_priv, 1, pipestat_enable);
  1896. I915_WRITE(VLV_IIR, 0xffffffff);
  1897. I915_WRITE(VLV_IIR, 0xffffffff);
  1898. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1899. I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
  1900. render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
  1901. GEN6_BLITTER_USER_INTERRUPT;
  1902. I915_WRITE(GTIER, render_irqs);
  1903. POSTING_READ(GTIER);
  1904. /* ack & enable invalid PTE error interrupts */
  1905. #if 0 /* FIXME: add support to irq handler for checking these bits */
  1906. I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
  1907. I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
  1908. #endif
  1909. I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
  1910. return 0;
  1911. }
  1912. static void valleyview_irq_uninstall(struct drm_device *dev)
  1913. {
  1914. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1915. int pipe;
  1916. if (!dev_priv)
  1917. return;
  1918. for_each_pipe(pipe)
  1919. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1920. I915_WRITE(HWSTAM, 0xffffffff);
  1921. I915_WRITE(PORT_HOTPLUG_EN, 0);
  1922. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  1923. for_each_pipe(pipe)
  1924. I915_WRITE(PIPESTAT(pipe), 0xffff);
  1925. I915_WRITE(VLV_IIR, 0xffffffff);
  1926. I915_WRITE(VLV_IMR, 0xffffffff);
  1927. I915_WRITE(VLV_IER, 0x0);
  1928. POSTING_READ(VLV_IER);
  1929. }
  1930. static void ironlake_irq_uninstall(struct drm_device *dev)
  1931. {
  1932. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1933. if (!dev_priv)
  1934. return;
  1935. I915_WRITE(HWSTAM, 0xffffffff);
  1936. I915_WRITE(DEIMR, 0xffffffff);
  1937. I915_WRITE(DEIER, 0x0);
  1938. I915_WRITE(DEIIR, I915_READ(DEIIR));
  1939. I915_WRITE(GTIMR, 0xffffffff);
  1940. I915_WRITE(GTIER, 0x0);
  1941. I915_WRITE(GTIIR, I915_READ(GTIIR));
  1942. if (HAS_PCH_NOP(dev))
  1943. return;
  1944. I915_WRITE(SDEIMR, 0xffffffff);
  1945. I915_WRITE(SDEIER, 0x0);
  1946. I915_WRITE(SDEIIR, I915_READ(SDEIIR));
  1947. }
  1948. static void i8xx_irq_preinstall(struct drm_device * dev)
  1949. {
  1950. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1951. int pipe;
  1952. atomic_set(&dev_priv->irq_received, 0);
  1953. for_each_pipe(pipe)
  1954. I915_WRITE(PIPESTAT(pipe), 0);
  1955. I915_WRITE16(IMR, 0xffff);
  1956. I915_WRITE16(IER, 0x0);
  1957. POSTING_READ16(IER);
  1958. }
  1959. static int i8xx_irq_postinstall(struct drm_device *dev)
  1960. {
  1961. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  1962. I915_WRITE16(EMR,
  1963. ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  1964. /* Unmask the interrupts that we always want on. */
  1965. dev_priv->irq_mask =
  1966. ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1967. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1968. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  1969. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  1970. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  1971. I915_WRITE16(IMR, dev_priv->irq_mask);
  1972. I915_WRITE16(IER,
  1973. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  1974. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  1975. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  1976. I915_USER_INTERRUPT);
  1977. POSTING_READ16(IER);
  1978. return 0;
  1979. }
  1980. /*
  1981. * Returns true when a page flip has completed.
  1982. */
  1983. static bool i8xx_handle_vblank(struct drm_device *dev,
  1984. int pipe, u16 iir)
  1985. {
  1986. drm_i915_private_t *dev_priv = dev->dev_private;
  1987. u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
  1988. if (!drm_handle_vblank(dev, pipe))
  1989. return false;
  1990. if ((iir & flip_pending) == 0)
  1991. return false;
  1992. intel_prepare_page_flip(dev, pipe);
  1993. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  1994. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  1995. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  1996. * the flip is completed (no longer pending). Since this doesn't raise
  1997. * an interrupt per se, we watch for the change at vblank.
  1998. */
  1999. if (I915_READ16(ISR) & flip_pending)
  2000. return false;
  2001. intel_finish_page_flip(dev, pipe);
  2002. return true;
  2003. }
  2004. static irqreturn_t i8xx_irq_handler(int irq, void *arg)
  2005. {
  2006. struct drm_device *dev = (struct drm_device *) arg;
  2007. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2008. u16 iir, new_iir;
  2009. u32 pipe_stats[2];
  2010. unsigned long irqflags;
  2011. int irq_received;
  2012. int pipe;
  2013. u16 flip_mask =
  2014. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2015. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2016. atomic_inc(&dev_priv->irq_received);
  2017. iir = I915_READ16(IIR);
  2018. if (iir == 0)
  2019. return IRQ_NONE;
  2020. while (iir & ~flip_mask) {
  2021. /* Can't rely on pipestat interrupt bit in iir as it might
  2022. * have been cleared after the pipestat interrupt was received.
  2023. * It doesn't set the bit in iir again, but it still produces
  2024. * interrupts (for non-MSI).
  2025. */
  2026. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2027. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2028. i915_handle_error(dev, false);
  2029. for_each_pipe(pipe) {
  2030. int reg = PIPESTAT(pipe);
  2031. pipe_stats[pipe] = I915_READ(reg);
  2032. /*
  2033. * Clear the PIPE*STAT regs before the IIR
  2034. */
  2035. if (pipe_stats[pipe] & 0x8000ffff) {
  2036. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2037. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2038. pipe_name(pipe));
  2039. I915_WRITE(reg, pipe_stats[pipe]);
  2040. irq_received = 1;
  2041. }
  2042. }
  2043. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2044. I915_WRITE16(IIR, iir & ~flip_mask);
  2045. new_iir = I915_READ16(IIR); /* Flush posted writes */
  2046. i915_update_dri1_breadcrumb(dev);
  2047. if (iir & I915_USER_INTERRUPT)
  2048. notify_ring(dev, &dev_priv->ring[RCS]);
  2049. if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2050. i8xx_handle_vblank(dev, 0, iir))
  2051. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
  2052. if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2053. i8xx_handle_vblank(dev, 1, iir))
  2054. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
  2055. iir = new_iir;
  2056. }
  2057. return IRQ_HANDLED;
  2058. }
  2059. static void i8xx_irq_uninstall(struct drm_device * dev)
  2060. {
  2061. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2062. int pipe;
  2063. for_each_pipe(pipe) {
  2064. /* Clear enable bits; then clear status bits */
  2065. I915_WRITE(PIPESTAT(pipe), 0);
  2066. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2067. }
  2068. I915_WRITE16(IMR, 0xffff);
  2069. I915_WRITE16(IER, 0x0);
  2070. I915_WRITE16(IIR, I915_READ16(IIR));
  2071. }
  2072. static void i915_irq_preinstall(struct drm_device * dev)
  2073. {
  2074. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2075. int pipe;
  2076. atomic_set(&dev_priv->irq_received, 0);
  2077. if (I915_HAS_HOTPLUG(dev)) {
  2078. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2079. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2080. }
  2081. I915_WRITE16(HWSTAM, 0xeffe);
  2082. for_each_pipe(pipe)
  2083. I915_WRITE(PIPESTAT(pipe), 0);
  2084. I915_WRITE(IMR, 0xffffffff);
  2085. I915_WRITE(IER, 0x0);
  2086. POSTING_READ(IER);
  2087. }
  2088. static int i915_irq_postinstall(struct drm_device *dev)
  2089. {
  2090. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2091. u32 enable_mask;
  2092. I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
  2093. /* Unmask the interrupts that we always want on. */
  2094. dev_priv->irq_mask =
  2095. ~(I915_ASLE_INTERRUPT |
  2096. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2097. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2098. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2099. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2100. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2101. enable_mask =
  2102. I915_ASLE_INTERRUPT |
  2103. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2104. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2105. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
  2106. I915_USER_INTERRUPT;
  2107. if (I915_HAS_HOTPLUG(dev)) {
  2108. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2109. POSTING_READ(PORT_HOTPLUG_EN);
  2110. /* Enable in IER... */
  2111. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  2112. /* and unmask in IMR */
  2113. dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
  2114. }
  2115. I915_WRITE(IMR, dev_priv->irq_mask);
  2116. I915_WRITE(IER, enable_mask);
  2117. POSTING_READ(IER);
  2118. intel_opregion_enable_asle(dev);
  2119. return 0;
  2120. }
  2121. /*
  2122. * Returns true when a page flip has completed.
  2123. */
  2124. static bool i915_handle_vblank(struct drm_device *dev,
  2125. int plane, int pipe, u32 iir)
  2126. {
  2127. drm_i915_private_t *dev_priv = dev->dev_private;
  2128. u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
  2129. if (!drm_handle_vblank(dev, pipe))
  2130. return false;
  2131. if ((iir & flip_pending) == 0)
  2132. return false;
  2133. intel_prepare_page_flip(dev, plane);
  2134. /* We detect FlipDone by looking for the change in PendingFlip from '1'
  2135. * to '0' on the following vblank, i.e. IIR has the Pendingflip
  2136. * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
  2137. * the flip is completed (no longer pending). Since this doesn't raise
  2138. * an interrupt per se, we watch for the change at vblank.
  2139. */
  2140. if (I915_READ(ISR) & flip_pending)
  2141. return false;
  2142. intel_finish_page_flip(dev, pipe);
  2143. return true;
  2144. }
  2145. static irqreturn_t i915_irq_handler(int irq, void *arg)
  2146. {
  2147. struct drm_device *dev = (struct drm_device *) arg;
  2148. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2149. u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
  2150. unsigned long irqflags;
  2151. u32 flip_mask =
  2152. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2153. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2154. int pipe, ret = IRQ_NONE;
  2155. atomic_inc(&dev_priv->irq_received);
  2156. iir = I915_READ(IIR);
  2157. do {
  2158. bool irq_received = (iir & ~flip_mask) != 0;
  2159. bool blc_event = false;
  2160. /* Can't rely on pipestat interrupt bit in iir as it might
  2161. * have been cleared after the pipestat interrupt was received.
  2162. * It doesn't set the bit in iir again, but it still produces
  2163. * interrupts (for non-MSI).
  2164. */
  2165. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2166. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2167. i915_handle_error(dev, false);
  2168. for_each_pipe(pipe) {
  2169. int reg = PIPESTAT(pipe);
  2170. pipe_stats[pipe] = I915_READ(reg);
  2171. /* Clear the PIPE*STAT regs before the IIR */
  2172. if (pipe_stats[pipe] & 0x8000ffff) {
  2173. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2174. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2175. pipe_name(pipe));
  2176. I915_WRITE(reg, pipe_stats[pipe]);
  2177. irq_received = true;
  2178. }
  2179. }
  2180. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2181. if (!irq_received)
  2182. break;
  2183. /* Consume port. Then clear IIR or we'll miss events */
  2184. if ((I915_HAS_HOTPLUG(dev)) &&
  2185. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  2186. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2187. u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
  2188. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2189. hotplug_status);
  2190. if (hotplug_trigger) {
  2191. hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915);
  2192. queue_work(dev_priv->wq,
  2193. &dev_priv->hotplug_work);
  2194. }
  2195. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2196. POSTING_READ(PORT_HOTPLUG_STAT);
  2197. }
  2198. I915_WRITE(IIR, iir & ~flip_mask);
  2199. new_iir = I915_READ(IIR); /* Flush posted writes */
  2200. if (iir & I915_USER_INTERRUPT)
  2201. notify_ring(dev, &dev_priv->ring[RCS]);
  2202. for_each_pipe(pipe) {
  2203. int plane = pipe;
  2204. if (IS_MOBILE(dev))
  2205. plane = !plane;
  2206. if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
  2207. i915_handle_vblank(dev, plane, pipe, iir))
  2208. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
  2209. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2210. blc_event = true;
  2211. }
  2212. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2213. intel_opregion_asle_intr(dev);
  2214. /* With MSI, interrupts are only generated when iir
  2215. * transitions from zero to nonzero. If another bit got
  2216. * set while we were handling the existing iir bits, then
  2217. * we would never get another interrupt.
  2218. *
  2219. * This is fine on non-MSI as well, as if we hit this path
  2220. * we avoid exiting the interrupt handler only to generate
  2221. * another one.
  2222. *
  2223. * Note that for MSI this could cause a stray interrupt report
  2224. * if an interrupt landed in the time between writing IIR and
  2225. * the posting read. This should be rare enough to never
  2226. * trigger the 99% of 100,000 interrupts test for disabling
  2227. * stray interrupts.
  2228. */
  2229. ret = IRQ_HANDLED;
  2230. iir = new_iir;
  2231. } while (iir & ~flip_mask);
  2232. i915_update_dri1_breadcrumb(dev);
  2233. return ret;
  2234. }
  2235. static void i915_irq_uninstall(struct drm_device * dev)
  2236. {
  2237. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2238. int pipe;
  2239. if (I915_HAS_HOTPLUG(dev)) {
  2240. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2241. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2242. }
  2243. I915_WRITE16(HWSTAM, 0xffff);
  2244. for_each_pipe(pipe) {
  2245. /* Clear enable bits; then clear status bits */
  2246. I915_WRITE(PIPESTAT(pipe), 0);
  2247. I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
  2248. }
  2249. I915_WRITE(IMR, 0xffffffff);
  2250. I915_WRITE(IER, 0x0);
  2251. I915_WRITE(IIR, I915_READ(IIR));
  2252. }
  2253. static void i965_irq_preinstall(struct drm_device * dev)
  2254. {
  2255. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2256. int pipe;
  2257. atomic_set(&dev_priv->irq_received, 0);
  2258. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2259. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2260. I915_WRITE(HWSTAM, 0xeffe);
  2261. for_each_pipe(pipe)
  2262. I915_WRITE(PIPESTAT(pipe), 0);
  2263. I915_WRITE(IMR, 0xffffffff);
  2264. I915_WRITE(IER, 0x0);
  2265. POSTING_READ(IER);
  2266. }
  2267. static int i965_irq_postinstall(struct drm_device *dev)
  2268. {
  2269. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2270. u32 enable_mask;
  2271. u32 error_mask;
  2272. /* Unmask the interrupts that we always want on. */
  2273. dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
  2274. I915_DISPLAY_PORT_INTERRUPT |
  2275. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
  2276. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
  2277. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2278. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
  2279. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  2280. enable_mask = ~dev_priv->irq_mask;
  2281. enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2282. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
  2283. enable_mask |= I915_USER_INTERRUPT;
  2284. if (IS_G4X(dev))
  2285. enable_mask |= I915_BSD_USER_INTERRUPT;
  2286. i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
  2287. /*
  2288. * Enable some error detection, note the instruction error mask
  2289. * bit is reserved, so we leave it masked.
  2290. */
  2291. if (IS_G4X(dev)) {
  2292. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  2293. GM45_ERROR_MEM_PRIV |
  2294. GM45_ERROR_CP_PRIV |
  2295. I915_ERROR_MEMORY_REFRESH);
  2296. } else {
  2297. error_mask = ~(I915_ERROR_PAGE_TABLE |
  2298. I915_ERROR_MEMORY_REFRESH);
  2299. }
  2300. I915_WRITE(EMR, error_mask);
  2301. I915_WRITE(IMR, dev_priv->irq_mask);
  2302. I915_WRITE(IER, enable_mask);
  2303. POSTING_READ(IER);
  2304. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2305. POSTING_READ(PORT_HOTPLUG_EN);
  2306. intel_opregion_enable_asle(dev);
  2307. return 0;
  2308. }
  2309. static void i915_hpd_irq_setup(struct drm_device *dev)
  2310. {
  2311. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2312. struct drm_mode_config *mode_config = &dev->mode_config;
  2313. struct intel_encoder *encoder;
  2314. u32 hotplug_en;
  2315. if (I915_HAS_HOTPLUG(dev)) {
  2316. hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  2317. hotplug_en &= ~HOTPLUG_INT_EN_MASK;
  2318. /* Note HDMI and DP share hotplug bits */
  2319. /* enable bits are the same for all generations */
  2320. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  2321. hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
  2322. /* Programming the CRT detection parameters tends
  2323. to generate a spurious hotplug event about three
  2324. seconds later. So just do it once.
  2325. */
  2326. if (IS_G4X(dev))
  2327. hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
  2328. hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
  2329. hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
  2330. /* Ignore TV since it's buggy */
  2331. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  2332. }
  2333. }
  2334. static irqreturn_t i965_irq_handler(int irq, void *arg)
  2335. {
  2336. struct drm_device *dev = (struct drm_device *) arg;
  2337. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2338. u32 iir, new_iir;
  2339. u32 pipe_stats[I915_MAX_PIPES];
  2340. unsigned long irqflags;
  2341. int irq_received;
  2342. int ret = IRQ_NONE, pipe;
  2343. u32 flip_mask =
  2344. I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
  2345. I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
  2346. atomic_inc(&dev_priv->irq_received);
  2347. iir = I915_READ(IIR);
  2348. for (;;) {
  2349. bool blc_event = false;
  2350. irq_received = (iir & ~flip_mask) != 0;
  2351. /* Can't rely on pipestat interrupt bit in iir as it might
  2352. * have been cleared after the pipestat interrupt was received.
  2353. * It doesn't set the bit in iir again, but it still produces
  2354. * interrupts (for non-MSI).
  2355. */
  2356. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  2357. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  2358. i915_handle_error(dev, false);
  2359. for_each_pipe(pipe) {
  2360. int reg = PIPESTAT(pipe);
  2361. pipe_stats[pipe] = I915_READ(reg);
  2362. /*
  2363. * Clear the PIPE*STAT regs before the IIR
  2364. */
  2365. if (pipe_stats[pipe] & 0x8000ffff) {
  2366. if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
  2367. DRM_DEBUG_DRIVER("pipe %c underrun\n",
  2368. pipe_name(pipe));
  2369. I915_WRITE(reg, pipe_stats[pipe]);
  2370. irq_received = 1;
  2371. }
  2372. }
  2373. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  2374. if (!irq_received)
  2375. break;
  2376. ret = IRQ_HANDLED;
  2377. /* Consume port. Then clear IIR or we'll miss events */
  2378. if (iir & I915_DISPLAY_PORT_INTERRUPT) {
  2379. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  2380. u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
  2381. HOTPLUG_INT_STATUS_G4X :
  2382. HOTPLUG_INT_STATUS_I965);
  2383. DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
  2384. hotplug_status);
  2385. if (hotplug_trigger) {
  2386. hotplug_irq_storm_detect(dev, hotplug_trigger,
  2387. IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965);
  2388. queue_work(dev_priv->wq,
  2389. &dev_priv->hotplug_work);
  2390. }
  2391. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  2392. I915_READ(PORT_HOTPLUG_STAT);
  2393. }
  2394. I915_WRITE(IIR, iir & ~flip_mask);
  2395. new_iir = I915_READ(IIR); /* Flush posted writes */
  2396. if (iir & I915_USER_INTERRUPT)
  2397. notify_ring(dev, &dev_priv->ring[RCS]);
  2398. if (iir & I915_BSD_USER_INTERRUPT)
  2399. notify_ring(dev, &dev_priv->ring[VCS]);
  2400. for_each_pipe(pipe) {
  2401. if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
  2402. i915_handle_vblank(dev, pipe, pipe, iir))
  2403. flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
  2404. if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
  2405. blc_event = true;
  2406. }
  2407. if (blc_event || (iir & I915_ASLE_INTERRUPT))
  2408. intel_opregion_asle_intr(dev);
  2409. if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
  2410. gmbus_irq_handler(dev);
  2411. /* With MSI, interrupts are only generated when iir
  2412. * transitions from zero to nonzero. If another bit got
  2413. * set while we were handling the existing iir bits, then
  2414. * we would never get another interrupt.
  2415. *
  2416. * This is fine on non-MSI as well, as if we hit this path
  2417. * we avoid exiting the interrupt handler only to generate
  2418. * another one.
  2419. *
  2420. * Note that for MSI this could cause a stray interrupt report
  2421. * if an interrupt landed in the time between writing IIR and
  2422. * the posting read. This should be rare enough to never
  2423. * trigger the 99% of 100,000 interrupts test for disabling
  2424. * stray interrupts.
  2425. */
  2426. iir = new_iir;
  2427. }
  2428. i915_update_dri1_breadcrumb(dev);
  2429. return ret;
  2430. }
  2431. static void i965_irq_uninstall(struct drm_device * dev)
  2432. {
  2433. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  2434. int pipe;
  2435. if (!dev_priv)
  2436. return;
  2437. I915_WRITE(PORT_HOTPLUG_EN, 0);
  2438. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  2439. I915_WRITE(HWSTAM, 0xffffffff);
  2440. for_each_pipe(pipe)
  2441. I915_WRITE(PIPESTAT(pipe), 0);
  2442. I915_WRITE(IMR, 0xffffffff);
  2443. I915_WRITE(IER, 0x0);
  2444. for_each_pipe(pipe)
  2445. I915_WRITE(PIPESTAT(pipe),
  2446. I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
  2447. I915_WRITE(IIR, I915_READ(IIR));
  2448. }
  2449. void intel_irq_init(struct drm_device *dev)
  2450. {
  2451. struct drm_i915_private *dev_priv = dev->dev_private;
  2452. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  2453. INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
  2454. INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
  2455. INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
  2456. setup_timer(&dev_priv->gpu_error.hangcheck_timer,
  2457. i915_hangcheck_elapsed,
  2458. (unsigned long) dev);
  2459. pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
  2460. dev->driver->get_vblank_counter = i915_get_vblank_counter;
  2461. dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
  2462. if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
  2463. dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
  2464. dev->driver->get_vblank_counter = gm45_get_vblank_counter;
  2465. }
  2466. if (drm_core_check_feature(dev, DRIVER_MODESET))
  2467. dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
  2468. else
  2469. dev->driver->get_vblank_timestamp = NULL;
  2470. dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
  2471. if (IS_VALLEYVIEW(dev)) {
  2472. dev->driver->irq_handler = valleyview_irq_handler;
  2473. dev->driver->irq_preinstall = valleyview_irq_preinstall;
  2474. dev->driver->irq_postinstall = valleyview_irq_postinstall;
  2475. dev->driver->irq_uninstall = valleyview_irq_uninstall;
  2476. dev->driver->enable_vblank = valleyview_enable_vblank;
  2477. dev->driver->disable_vblank = valleyview_disable_vblank;
  2478. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2479. } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  2480. /* Share pre & uninstall handlers with ILK/SNB */
  2481. dev->driver->irq_handler = ivybridge_irq_handler;
  2482. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2483. dev->driver->irq_postinstall = ivybridge_irq_postinstall;
  2484. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2485. dev->driver->enable_vblank = ivybridge_enable_vblank;
  2486. dev->driver->disable_vblank = ivybridge_disable_vblank;
  2487. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2488. } else if (HAS_PCH_SPLIT(dev)) {
  2489. dev->driver->irq_handler = ironlake_irq_handler;
  2490. dev->driver->irq_preinstall = ironlake_irq_preinstall;
  2491. dev->driver->irq_postinstall = ironlake_irq_postinstall;
  2492. dev->driver->irq_uninstall = ironlake_irq_uninstall;
  2493. dev->driver->enable_vblank = ironlake_enable_vblank;
  2494. dev->driver->disable_vblank = ironlake_disable_vblank;
  2495. dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
  2496. } else {
  2497. if (INTEL_INFO(dev)->gen == 2) {
  2498. dev->driver->irq_preinstall = i8xx_irq_preinstall;
  2499. dev->driver->irq_postinstall = i8xx_irq_postinstall;
  2500. dev->driver->irq_handler = i8xx_irq_handler;
  2501. dev->driver->irq_uninstall = i8xx_irq_uninstall;
  2502. } else if (INTEL_INFO(dev)->gen == 3) {
  2503. dev->driver->irq_preinstall = i915_irq_preinstall;
  2504. dev->driver->irq_postinstall = i915_irq_postinstall;
  2505. dev->driver->irq_uninstall = i915_irq_uninstall;
  2506. dev->driver->irq_handler = i915_irq_handler;
  2507. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2508. } else {
  2509. dev->driver->irq_preinstall = i965_irq_preinstall;
  2510. dev->driver->irq_postinstall = i965_irq_postinstall;
  2511. dev->driver->irq_uninstall = i965_irq_uninstall;
  2512. dev->driver->irq_handler = i965_irq_handler;
  2513. dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
  2514. }
  2515. dev->driver->enable_vblank = i915_enable_vblank;
  2516. dev->driver->disable_vblank = i915_disable_vblank;
  2517. }
  2518. }
  2519. void intel_hpd_init(struct drm_device *dev)
  2520. {
  2521. struct drm_i915_private *dev_priv = dev->dev_private;
  2522. struct drm_mode_config *mode_config = &dev->mode_config;
  2523. struct drm_connector *connector;
  2524. int i;
  2525. for (i = 1; i < HPD_NUM_PINS; i++) {
  2526. dev_priv->hpd_stats[i].hpd_cnt = 0;
  2527. dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
  2528. }
  2529. list_for_each_entry(connector, &mode_config->connector_list, head) {
  2530. struct intel_connector *intel_connector = to_intel_connector(connector);
  2531. connector->polled = intel_connector->polled;
  2532. if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
  2533. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2534. }
  2535. if (dev_priv->display.hpd_irq_setup)
  2536. dev_priv->display.hpd_irq_setup(dev);
  2537. }