dsi.c 135 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/dsi.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define DSS_SUBSYS_NAME "DSI"
  20. #include <linux/kernel.h>
  21. #include <linux/io.h>
  22. #include <linux/clk.h>
  23. #include <linux/device.h>
  24. #include <linux/err.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/delay.h>
  27. #include <linux/mutex.h>
  28. #include <linux/module.h>
  29. #include <linux/semaphore.h>
  30. #include <linux/seq_file.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/regulator/consumer.h>
  33. #include <linux/wait.h>
  34. #include <linux/workqueue.h>
  35. #include <linux/sched.h>
  36. #include <linux/slab.h>
  37. #include <linux/debugfs.h>
  38. #include <linux/pm_runtime.h>
  39. #include <video/omapdss.h>
  40. #include <video/mipi_display.h>
  41. #include "dss.h"
  42. #include "dss_features.h"
  43. #define DSI_CATCH_MISSING_TE
  44. struct dsi_reg { u16 idx; };
  45. #define DSI_REG(idx) ((const struct dsi_reg) { idx })
  46. #define DSI_SZ_REGS SZ_1K
  47. /* DSI Protocol Engine */
  48. #define DSI_REVISION DSI_REG(0x0000)
  49. #define DSI_SYSCONFIG DSI_REG(0x0010)
  50. #define DSI_SYSSTATUS DSI_REG(0x0014)
  51. #define DSI_IRQSTATUS DSI_REG(0x0018)
  52. #define DSI_IRQENABLE DSI_REG(0x001C)
  53. #define DSI_CTRL DSI_REG(0x0040)
  54. #define DSI_GNQ DSI_REG(0x0044)
  55. #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
  56. #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
  57. #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
  58. #define DSI_CLK_CTRL DSI_REG(0x0054)
  59. #define DSI_TIMING1 DSI_REG(0x0058)
  60. #define DSI_TIMING2 DSI_REG(0x005C)
  61. #define DSI_VM_TIMING1 DSI_REG(0x0060)
  62. #define DSI_VM_TIMING2 DSI_REG(0x0064)
  63. #define DSI_VM_TIMING3 DSI_REG(0x0068)
  64. #define DSI_CLK_TIMING DSI_REG(0x006C)
  65. #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
  66. #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
  67. #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
  68. #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
  69. #define DSI_VM_TIMING4 DSI_REG(0x0080)
  70. #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
  71. #define DSI_VM_TIMING5 DSI_REG(0x0088)
  72. #define DSI_VM_TIMING6 DSI_REG(0x008C)
  73. #define DSI_VM_TIMING7 DSI_REG(0x0090)
  74. #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
  75. #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
  76. #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
  77. #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
  78. #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
  79. #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
  80. #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
  81. #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
  82. /* DSIPHY_SCP */
  83. #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
  84. #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
  85. #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
  86. #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
  87. #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
  88. /* DSI_PLL_CTRL_SCP */
  89. #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
  90. #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
  91. #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
  92. #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
  93. #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
  94. #define REG_GET(dsidev, idx, start, end) \
  95. FLD_GET(dsi_read_reg(dsidev, idx), start, end)
  96. #define REG_FLD_MOD(dsidev, idx, val, start, end) \
  97. dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
  98. /* Global interrupts */
  99. #define DSI_IRQ_VC0 (1 << 0)
  100. #define DSI_IRQ_VC1 (1 << 1)
  101. #define DSI_IRQ_VC2 (1 << 2)
  102. #define DSI_IRQ_VC3 (1 << 3)
  103. #define DSI_IRQ_WAKEUP (1 << 4)
  104. #define DSI_IRQ_RESYNC (1 << 5)
  105. #define DSI_IRQ_PLL_LOCK (1 << 7)
  106. #define DSI_IRQ_PLL_UNLOCK (1 << 8)
  107. #define DSI_IRQ_PLL_RECALL (1 << 9)
  108. #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
  109. #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
  110. #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
  111. #define DSI_IRQ_TE_TRIGGER (1 << 16)
  112. #define DSI_IRQ_ACK_TRIGGER (1 << 17)
  113. #define DSI_IRQ_SYNC_LOST (1 << 18)
  114. #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
  115. #define DSI_IRQ_TA_TIMEOUT (1 << 20)
  116. #define DSI_IRQ_ERROR_MASK \
  117. (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
  118. DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
  119. #define DSI_IRQ_CHANNEL_MASK 0xf
  120. /* Virtual channel interrupts */
  121. #define DSI_VC_IRQ_CS (1 << 0)
  122. #define DSI_VC_IRQ_ECC_CORR (1 << 1)
  123. #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
  124. #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
  125. #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
  126. #define DSI_VC_IRQ_BTA (1 << 5)
  127. #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
  128. #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
  129. #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
  130. #define DSI_VC_IRQ_ERROR_MASK \
  131. (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
  132. DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
  133. DSI_VC_IRQ_FIFO_TX_UDF)
  134. /* ComplexIO interrupts */
  135. #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
  136. #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
  137. #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
  138. #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
  139. #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
  140. #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
  141. #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
  142. #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
  143. #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
  144. #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
  145. #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
  146. #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
  147. #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
  148. #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
  149. #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
  150. #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
  151. #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
  152. #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
  153. #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
  154. #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
  155. #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
  156. #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
  157. #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
  158. #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
  159. #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
  160. #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
  161. #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
  162. #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
  163. #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
  164. #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
  165. #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
  166. #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
  167. #define DSI_CIO_IRQ_ERROR_MASK \
  168. (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
  169. DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
  170. DSI_CIO_IRQ_ERRSYNCESC5 | \
  171. DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
  172. DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
  173. DSI_CIO_IRQ_ERRESC5 | \
  174. DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
  175. DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
  176. DSI_CIO_IRQ_ERRCONTROL5 | \
  177. DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
  178. DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
  179. DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
  180. DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
  181. DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
  182. typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
  183. static int dsi_display_init_dispc(struct platform_device *dsidev,
  184. struct omap_overlay_manager *mgr);
  185. static void dsi_display_uninit_dispc(struct platform_device *dsidev,
  186. struct omap_overlay_manager *mgr);
  187. #define DSI_MAX_NR_ISRS 2
  188. #define DSI_MAX_NR_LANES 5
  189. enum dsi_lane_function {
  190. DSI_LANE_UNUSED = 0,
  191. DSI_LANE_CLK,
  192. DSI_LANE_DATA1,
  193. DSI_LANE_DATA2,
  194. DSI_LANE_DATA3,
  195. DSI_LANE_DATA4,
  196. };
  197. struct dsi_lane_config {
  198. enum dsi_lane_function function;
  199. u8 polarity;
  200. };
  201. struct dsi_isr_data {
  202. omap_dsi_isr_t isr;
  203. void *arg;
  204. u32 mask;
  205. };
  206. enum fifo_size {
  207. DSI_FIFO_SIZE_0 = 0,
  208. DSI_FIFO_SIZE_32 = 1,
  209. DSI_FIFO_SIZE_64 = 2,
  210. DSI_FIFO_SIZE_96 = 3,
  211. DSI_FIFO_SIZE_128 = 4,
  212. };
  213. enum dsi_vc_source {
  214. DSI_VC_SOURCE_L4 = 0,
  215. DSI_VC_SOURCE_VP,
  216. };
  217. struct dsi_irq_stats {
  218. unsigned long last_reset;
  219. unsigned irq_count;
  220. unsigned dsi_irqs[32];
  221. unsigned vc_irqs[4][32];
  222. unsigned cio_irqs[32];
  223. };
  224. struct dsi_isr_tables {
  225. struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
  226. struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
  227. struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
  228. };
  229. struct dsi_data {
  230. struct platform_device *pdev;
  231. void __iomem *base;
  232. int module_id;
  233. int irq;
  234. struct clk *dss_clk;
  235. struct clk *sys_clk;
  236. struct dispc_clock_info user_dispc_cinfo;
  237. struct dsi_clock_info user_dsi_cinfo;
  238. enum omap_dss_clk_source user_dispc_fclk_src;
  239. enum omap_dss_clk_source user_lcd_clk_src;
  240. enum omap_dss_clk_source user_dsi_fclk_src;
  241. struct dsi_clock_info current_cinfo;
  242. bool vdds_dsi_enabled;
  243. struct regulator *vdds_dsi_reg;
  244. struct {
  245. enum dsi_vc_source source;
  246. struct omap_dss_device *dssdev;
  247. enum fifo_size fifo_size;
  248. int vc_id;
  249. } vc[4];
  250. struct mutex lock;
  251. struct semaphore bus_lock;
  252. unsigned pll_locked;
  253. spinlock_t irq_lock;
  254. struct dsi_isr_tables isr_tables;
  255. /* space for a copy used by the interrupt handler */
  256. struct dsi_isr_tables isr_tables_copy;
  257. int update_channel;
  258. #ifdef DEBUG
  259. unsigned update_bytes;
  260. #endif
  261. bool te_enabled;
  262. bool ulps_enabled;
  263. void (*framedone_callback)(int, void *);
  264. void *framedone_data;
  265. struct delayed_work framedone_timeout_work;
  266. #ifdef DSI_CATCH_MISSING_TE
  267. struct timer_list te_timer;
  268. #endif
  269. unsigned long cache_req_pck;
  270. unsigned long cache_clk_freq;
  271. struct dsi_clock_info cache_cinfo;
  272. u32 errors;
  273. spinlock_t errors_lock;
  274. #ifdef DEBUG
  275. ktime_t perf_setup_time;
  276. ktime_t perf_start_time;
  277. #endif
  278. int debug_read;
  279. int debug_write;
  280. #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
  281. spinlock_t irq_stats_lock;
  282. struct dsi_irq_stats irq_stats;
  283. #endif
  284. /* DSI PLL Parameter Ranges */
  285. unsigned long regm_max, regn_max;
  286. unsigned long regm_dispc_max, regm_dsi_max;
  287. unsigned long fint_min, fint_max;
  288. unsigned long lpdiv_max;
  289. unsigned num_lanes_supported;
  290. unsigned line_buffer_size;
  291. struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
  292. unsigned num_lanes_used;
  293. unsigned scp_clk_refcount;
  294. struct dss_lcd_mgr_config mgr_config;
  295. struct omap_video_timings timings;
  296. enum omap_dss_dsi_pixel_format pix_fmt;
  297. enum omap_dss_dsi_mode mode;
  298. struct omap_dss_dsi_videomode_timings vm_timings;
  299. struct omap_dss_output output;
  300. };
  301. struct dsi_packet_sent_handler_data {
  302. struct platform_device *dsidev;
  303. struct completion *completion;
  304. };
  305. #ifdef DEBUG
  306. static bool dsi_perf;
  307. module_param(dsi_perf, bool, 0644);
  308. #endif
  309. static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
  310. {
  311. return dev_get_drvdata(&dsidev->dev);
  312. }
  313. static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
  314. {
  315. return dssdev->output->pdev;
  316. }
  317. struct platform_device *dsi_get_dsidev_from_id(int module)
  318. {
  319. struct omap_dss_output *out;
  320. enum omap_dss_output_id id;
  321. switch (module) {
  322. case 0:
  323. id = OMAP_DSS_OUTPUT_DSI1;
  324. break;
  325. case 1:
  326. id = OMAP_DSS_OUTPUT_DSI2;
  327. break;
  328. default:
  329. return NULL;
  330. }
  331. out = omap_dss_get_output(id);
  332. return out ? out->pdev : NULL;
  333. }
  334. static inline void dsi_write_reg(struct platform_device *dsidev,
  335. const struct dsi_reg idx, u32 val)
  336. {
  337. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  338. __raw_writel(val, dsi->base + idx.idx);
  339. }
  340. static inline u32 dsi_read_reg(struct platform_device *dsidev,
  341. const struct dsi_reg idx)
  342. {
  343. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  344. return __raw_readl(dsi->base + idx.idx);
  345. }
  346. void dsi_bus_lock(struct omap_dss_device *dssdev)
  347. {
  348. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  349. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  350. down(&dsi->bus_lock);
  351. }
  352. EXPORT_SYMBOL(dsi_bus_lock);
  353. void dsi_bus_unlock(struct omap_dss_device *dssdev)
  354. {
  355. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  356. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  357. up(&dsi->bus_lock);
  358. }
  359. EXPORT_SYMBOL(dsi_bus_unlock);
  360. static bool dsi_bus_is_locked(struct platform_device *dsidev)
  361. {
  362. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  363. return dsi->bus_lock.count == 0;
  364. }
  365. static void dsi_completion_handler(void *data, u32 mask)
  366. {
  367. complete((struct completion *)data);
  368. }
  369. static inline int wait_for_bit_change(struct platform_device *dsidev,
  370. const struct dsi_reg idx, int bitnum, int value)
  371. {
  372. unsigned long timeout;
  373. ktime_t wait;
  374. int t;
  375. /* first busyloop to see if the bit changes right away */
  376. t = 100;
  377. while (t-- > 0) {
  378. if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
  379. return value;
  380. }
  381. /* then loop for 500ms, sleeping for 1ms in between */
  382. timeout = jiffies + msecs_to_jiffies(500);
  383. while (time_before(jiffies, timeout)) {
  384. if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
  385. return value;
  386. wait = ns_to_ktime(1000 * 1000);
  387. set_current_state(TASK_UNINTERRUPTIBLE);
  388. schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
  389. }
  390. return !value;
  391. }
  392. u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
  393. {
  394. switch (fmt) {
  395. case OMAP_DSS_DSI_FMT_RGB888:
  396. case OMAP_DSS_DSI_FMT_RGB666:
  397. return 24;
  398. case OMAP_DSS_DSI_FMT_RGB666_PACKED:
  399. return 18;
  400. case OMAP_DSS_DSI_FMT_RGB565:
  401. return 16;
  402. default:
  403. BUG();
  404. return 0;
  405. }
  406. }
  407. #ifdef DEBUG
  408. static void dsi_perf_mark_setup(struct platform_device *dsidev)
  409. {
  410. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  411. dsi->perf_setup_time = ktime_get();
  412. }
  413. static void dsi_perf_mark_start(struct platform_device *dsidev)
  414. {
  415. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  416. dsi->perf_start_time = ktime_get();
  417. }
  418. static void dsi_perf_show(struct platform_device *dsidev, const char *name)
  419. {
  420. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  421. ktime_t t, setup_time, trans_time;
  422. u32 total_bytes;
  423. u32 setup_us, trans_us, total_us;
  424. if (!dsi_perf)
  425. return;
  426. t = ktime_get();
  427. setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
  428. setup_us = (u32)ktime_to_us(setup_time);
  429. if (setup_us == 0)
  430. setup_us = 1;
  431. trans_time = ktime_sub(t, dsi->perf_start_time);
  432. trans_us = (u32)ktime_to_us(trans_time);
  433. if (trans_us == 0)
  434. trans_us = 1;
  435. total_us = setup_us + trans_us;
  436. total_bytes = dsi->update_bytes;
  437. printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
  438. "%u bytes, %u kbytes/sec\n",
  439. name,
  440. setup_us,
  441. trans_us,
  442. total_us,
  443. 1000*1000 / total_us,
  444. total_bytes,
  445. total_bytes * 1000 / total_us);
  446. }
  447. #else
  448. static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
  449. {
  450. }
  451. static inline void dsi_perf_mark_start(struct platform_device *dsidev)
  452. {
  453. }
  454. static inline void dsi_perf_show(struct platform_device *dsidev,
  455. const char *name)
  456. {
  457. }
  458. #endif
  459. static int verbose_irq;
  460. static void print_irq_status(u32 status)
  461. {
  462. if (status == 0)
  463. return;
  464. if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
  465. return;
  466. #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
  467. pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
  468. status,
  469. verbose_irq ? PIS(VC0) : "",
  470. verbose_irq ? PIS(VC1) : "",
  471. verbose_irq ? PIS(VC2) : "",
  472. verbose_irq ? PIS(VC3) : "",
  473. PIS(WAKEUP),
  474. PIS(RESYNC),
  475. PIS(PLL_LOCK),
  476. PIS(PLL_UNLOCK),
  477. PIS(PLL_RECALL),
  478. PIS(COMPLEXIO_ERR),
  479. PIS(HS_TX_TIMEOUT),
  480. PIS(LP_RX_TIMEOUT),
  481. PIS(TE_TRIGGER),
  482. PIS(ACK_TRIGGER),
  483. PIS(SYNC_LOST),
  484. PIS(LDO_POWER_GOOD),
  485. PIS(TA_TIMEOUT));
  486. #undef PIS
  487. }
  488. static void print_irq_status_vc(int channel, u32 status)
  489. {
  490. if (status == 0)
  491. return;
  492. if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
  493. return;
  494. #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
  495. pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
  496. channel,
  497. status,
  498. PIS(CS),
  499. PIS(ECC_CORR),
  500. PIS(ECC_NO_CORR),
  501. verbose_irq ? PIS(PACKET_SENT) : "",
  502. PIS(BTA),
  503. PIS(FIFO_TX_OVF),
  504. PIS(FIFO_RX_OVF),
  505. PIS(FIFO_TX_UDF),
  506. PIS(PP_BUSY_CHANGE));
  507. #undef PIS
  508. }
  509. static void print_irq_status_cio(u32 status)
  510. {
  511. if (status == 0)
  512. return;
  513. #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
  514. pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
  515. status,
  516. PIS(ERRSYNCESC1),
  517. PIS(ERRSYNCESC2),
  518. PIS(ERRSYNCESC3),
  519. PIS(ERRESC1),
  520. PIS(ERRESC2),
  521. PIS(ERRESC3),
  522. PIS(ERRCONTROL1),
  523. PIS(ERRCONTROL2),
  524. PIS(ERRCONTROL3),
  525. PIS(STATEULPS1),
  526. PIS(STATEULPS2),
  527. PIS(STATEULPS3),
  528. PIS(ERRCONTENTIONLP0_1),
  529. PIS(ERRCONTENTIONLP1_1),
  530. PIS(ERRCONTENTIONLP0_2),
  531. PIS(ERRCONTENTIONLP1_2),
  532. PIS(ERRCONTENTIONLP0_3),
  533. PIS(ERRCONTENTIONLP1_3),
  534. PIS(ULPSACTIVENOT_ALL0),
  535. PIS(ULPSACTIVENOT_ALL1));
  536. #undef PIS
  537. }
  538. #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
  539. static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
  540. u32 *vcstatus, u32 ciostatus)
  541. {
  542. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  543. int i;
  544. spin_lock(&dsi->irq_stats_lock);
  545. dsi->irq_stats.irq_count++;
  546. dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
  547. for (i = 0; i < 4; ++i)
  548. dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
  549. dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
  550. spin_unlock(&dsi->irq_stats_lock);
  551. }
  552. #else
  553. #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
  554. #endif
  555. static int debug_irq;
  556. static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
  557. u32 *vcstatus, u32 ciostatus)
  558. {
  559. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  560. int i;
  561. if (irqstatus & DSI_IRQ_ERROR_MASK) {
  562. DSSERR("DSI error, irqstatus %x\n", irqstatus);
  563. print_irq_status(irqstatus);
  564. spin_lock(&dsi->errors_lock);
  565. dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
  566. spin_unlock(&dsi->errors_lock);
  567. } else if (debug_irq) {
  568. print_irq_status(irqstatus);
  569. }
  570. for (i = 0; i < 4; ++i) {
  571. if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
  572. DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
  573. i, vcstatus[i]);
  574. print_irq_status_vc(i, vcstatus[i]);
  575. } else if (debug_irq) {
  576. print_irq_status_vc(i, vcstatus[i]);
  577. }
  578. }
  579. if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
  580. DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
  581. print_irq_status_cio(ciostatus);
  582. } else if (debug_irq) {
  583. print_irq_status_cio(ciostatus);
  584. }
  585. }
  586. static void dsi_call_isrs(struct dsi_isr_data *isr_array,
  587. unsigned isr_array_size, u32 irqstatus)
  588. {
  589. struct dsi_isr_data *isr_data;
  590. int i;
  591. for (i = 0; i < isr_array_size; i++) {
  592. isr_data = &isr_array[i];
  593. if (isr_data->isr && isr_data->mask & irqstatus)
  594. isr_data->isr(isr_data->arg, irqstatus);
  595. }
  596. }
  597. static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
  598. u32 irqstatus, u32 *vcstatus, u32 ciostatus)
  599. {
  600. int i;
  601. dsi_call_isrs(isr_tables->isr_table,
  602. ARRAY_SIZE(isr_tables->isr_table),
  603. irqstatus);
  604. for (i = 0; i < 4; ++i) {
  605. if (vcstatus[i] == 0)
  606. continue;
  607. dsi_call_isrs(isr_tables->isr_table_vc[i],
  608. ARRAY_SIZE(isr_tables->isr_table_vc[i]),
  609. vcstatus[i]);
  610. }
  611. if (ciostatus != 0)
  612. dsi_call_isrs(isr_tables->isr_table_cio,
  613. ARRAY_SIZE(isr_tables->isr_table_cio),
  614. ciostatus);
  615. }
  616. static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
  617. {
  618. struct platform_device *dsidev;
  619. struct dsi_data *dsi;
  620. u32 irqstatus, vcstatus[4], ciostatus;
  621. int i;
  622. dsidev = (struct platform_device *) arg;
  623. dsi = dsi_get_dsidrv_data(dsidev);
  624. spin_lock(&dsi->irq_lock);
  625. irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
  626. /* IRQ is not for us */
  627. if (!irqstatus) {
  628. spin_unlock(&dsi->irq_lock);
  629. return IRQ_NONE;
  630. }
  631. dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
  632. /* flush posted write */
  633. dsi_read_reg(dsidev, DSI_IRQSTATUS);
  634. for (i = 0; i < 4; ++i) {
  635. if ((irqstatus & (1 << i)) == 0) {
  636. vcstatus[i] = 0;
  637. continue;
  638. }
  639. vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
  640. dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
  641. /* flush posted write */
  642. dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
  643. }
  644. if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
  645. ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
  646. dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
  647. /* flush posted write */
  648. dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
  649. } else {
  650. ciostatus = 0;
  651. }
  652. #ifdef DSI_CATCH_MISSING_TE
  653. if (irqstatus & DSI_IRQ_TE_TRIGGER)
  654. del_timer(&dsi->te_timer);
  655. #endif
  656. /* make a copy and unlock, so that isrs can unregister
  657. * themselves */
  658. memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
  659. sizeof(dsi->isr_tables));
  660. spin_unlock(&dsi->irq_lock);
  661. dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
  662. dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
  663. dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
  664. return IRQ_HANDLED;
  665. }
  666. /* dsi->irq_lock has to be locked by the caller */
  667. static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
  668. struct dsi_isr_data *isr_array,
  669. unsigned isr_array_size, u32 default_mask,
  670. const struct dsi_reg enable_reg,
  671. const struct dsi_reg status_reg)
  672. {
  673. struct dsi_isr_data *isr_data;
  674. u32 mask;
  675. u32 old_mask;
  676. int i;
  677. mask = default_mask;
  678. for (i = 0; i < isr_array_size; i++) {
  679. isr_data = &isr_array[i];
  680. if (isr_data->isr == NULL)
  681. continue;
  682. mask |= isr_data->mask;
  683. }
  684. old_mask = dsi_read_reg(dsidev, enable_reg);
  685. /* clear the irqstatus for newly enabled irqs */
  686. dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
  687. dsi_write_reg(dsidev, enable_reg, mask);
  688. /* flush posted writes */
  689. dsi_read_reg(dsidev, enable_reg);
  690. dsi_read_reg(dsidev, status_reg);
  691. }
  692. /* dsi->irq_lock has to be locked by the caller */
  693. static void _omap_dsi_set_irqs(struct platform_device *dsidev)
  694. {
  695. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  696. u32 mask = DSI_IRQ_ERROR_MASK;
  697. #ifdef DSI_CATCH_MISSING_TE
  698. mask |= DSI_IRQ_TE_TRIGGER;
  699. #endif
  700. _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
  701. ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
  702. DSI_IRQENABLE, DSI_IRQSTATUS);
  703. }
  704. /* dsi->irq_lock has to be locked by the caller */
  705. static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
  706. {
  707. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  708. _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
  709. ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
  710. DSI_VC_IRQ_ERROR_MASK,
  711. DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
  712. }
  713. /* dsi->irq_lock has to be locked by the caller */
  714. static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
  715. {
  716. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  717. _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
  718. ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
  719. DSI_CIO_IRQ_ERROR_MASK,
  720. DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
  721. }
  722. static void _dsi_initialize_irq(struct platform_device *dsidev)
  723. {
  724. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  725. unsigned long flags;
  726. int vc;
  727. spin_lock_irqsave(&dsi->irq_lock, flags);
  728. memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
  729. _omap_dsi_set_irqs(dsidev);
  730. for (vc = 0; vc < 4; ++vc)
  731. _omap_dsi_set_irqs_vc(dsidev, vc);
  732. _omap_dsi_set_irqs_cio(dsidev);
  733. spin_unlock_irqrestore(&dsi->irq_lock, flags);
  734. }
  735. static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
  736. struct dsi_isr_data *isr_array, unsigned isr_array_size)
  737. {
  738. struct dsi_isr_data *isr_data;
  739. int free_idx;
  740. int i;
  741. BUG_ON(isr == NULL);
  742. /* check for duplicate entry and find a free slot */
  743. free_idx = -1;
  744. for (i = 0; i < isr_array_size; i++) {
  745. isr_data = &isr_array[i];
  746. if (isr_data->isr == isr && isr_data->arg == arg &&
  747. isr_data->mask == mask) {
  748. return -EINVAL;
  749. }
  750. if (isr_data->isr == NULL && free_idx == -1)
  751. free_idx = i;
  752. }
  753. if (free_idx == -1)
  754. return -EBUSY;
  755. isr_data = &isr_array[free_idx];
  756. isr_data->isr = isr;
  757. isr_data->arg = arg;
  758. isr_data->mask = mask;
  759. return 0;
  760. }
  761. static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
  762. struct dsi_isr_data *isr_array, unsigned isr_array_size)
  763. {
  764. struct dsi_isr_data *isr_data;
  765. int i;
  766. for (i = 0; i < isr_array_size; i++) {
  767. isr_data = &isr_array[i];
  768. if (isr_data->isr != isr || isr_data->arg != arg ||
  769. isr_data->mask != mask)
  770. continue;
  771. isr_data->isr = NULL;
  772. isr_data->arg = NULL;
  773. isr_data->mask = 0;
  774. return 0;
  775. }
  776. return -EINVAL;
  777. }
  778. static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
  779. void *arg, u32 mask)
  780. {
  781. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  782. unsigned long flags;
  783. int r;
  784. spin_lock_irqsave(&dsi->irq_lock, flags);
  785. r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
  786. ARRAY_SIZE(dsi->isr_tables.isr_table));
  787. if (r == 0)
  788. _omap_dsi_set_irqs(dsidev);
  789. spin_unlock_irqrestore(&dsi->irq_lock, flags);
  790. return r;
  791. }
  792. static int dsi_unregister_isr(struct platform_device *dsidev,
  793. omap_dsi_isr_t isr, void *arg, u32 mask)
  794. {
  795. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  796. unsigned long flags;
  797. int r;
  798. spin_lock_irqsave(&dsi->irq_lock, flags);
  799. r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
  800. ARRAY_SIZE(dsi->isr_tables.isr_table));
  801. if (r == 0)
  802. _omap_dsi_set_irqs(dsidev);
  803. spin_unlock_irqrestore(&dsi->irq_lock, flags);
  804. return r;
  805. }
  806. static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
  807. omap_dsi_isr_t isr, void *arg, u32 mask)
  808. {
  809. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  810. unsigned long flags;
  811. int r;
  812. spin_lock_irqsave(&dsi->irq_lock, flags);
  813. r = _dsi_register_isr(isr, arg, mask,
  814. dsi->isr_tables.isr_table_vc[channel],
  815. ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
  816. if (r == 0)
  817. _omap_dsi_set_irqs_vc(dsidev, channel);
  818. spin_unlock_irqrestore(&dsi->irq_lock, flags);
  819. return r;
  820. }
  821. static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
  822. omap_dsi_isr_t isr, void *arg, u32 mask)
  823. {
  824. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  825. unsigned long flags;
  826. int r;
  827. spin_lock_irqsave(&dsi->irq_lock, flags);
  828. r = _dsi_unregister_isr(isr, arg, mask,
  829. dsi->isr_tables.isr_table_vc[channel],
  830. ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
  831. if (r == 0)
  832. _omap_dsi_set_irqs_vc(dsidev, channel);
  833. spin_unlock_irqrestore(&dsi->irq_lock, flags);
  834. return r;
  835. }
  836. static int dsi_register_isr_cio(struct platform_device *dsidev,
  837. omap_dsi_isr_t isr, void *arg, u32 mask)
  838. {
  839. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  840. unsigned long flags;
  841. int r;
  842. spin_lock_irqsave(&dsi->irq_lock, flags);
  843. r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
  844. ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
  845. if (r == 0)
  846. _omap_dsi_set_irqs_cio(dsidev);
  847. spin_unlock_irqrestore(&dsi->irq_lock, flags);
  848. return r;
  849. }
  850. static int dsi_unregister_isr_cio(struct platform_device *dsidev,
  851. omap_dsi_isr_t isr, void *arg, u32 mask)
  852. {
  853. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  854. unsigned long flags;
  855. int r;
  856. spin_lock_irqsave(&dsi->irq_lock, flags);
  857. r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
  858. ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
  859. if (r == 0)
  860. _omap_dsi_set_irqs_cio(dsidev);
  861. spin_unlock_irqrestore(&dsi->irq_lock, flags);
  862. return r;
  863. }
  864. static u32 dsi_get_errors(struct platform_device *dsidev)
  865. {
  866. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  867. unsigned long flags;
  868. u32 e;
  869. spin_lock_irqsave(&dsi->errors_lock, flags);
  870. e = dsi->errors;
  871. dsi->errors = 0;
  872. spin_unlock_irqrestore(&dsi->errors_lock, flags);
  873. return e;
  874. }
  875. int dsi_runtime_get(struct platform_device *dsidev)
  876. {
  877. int r;
  878. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  879. DSSDBG("dsi_runtime_get\n");
  880. r = pm_runtime_get_sync(&dsi->pdev->dev);
  881. WARN_ON(r < 0);
  882. return r < 0 ? r : 0;
  883. }
  884. void dsi_runtime_put(struct platform_device *dsidev)
  885. {
  886. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  887. int r;
  888. DSSDBG("dsi_runtime_put\n");
  889. r = pm_runtime_put_sync(&dsi->pdev->dev);
  890. WARN_ON(r < 0 && r != -ENOSYS);
  891. }
  892. /* source clock for DSI PLL. this could also be PCLKFREE */
  893. static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
  894. bool enable)
  895. {
  896. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  897. if (enable)
  898. clk_prepare_enable(dsi->sys_clk);
  899. else
  900. clk_disable_unprepare(dsi->sys_clk);
  901. if (enable && dsi->pll_locked) {
  902. if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
  903. DSSERR("cannot lock PLL when enabling clocks\n");
  904. }
  905. }
  906. static void _dsi_print_reset_status(struct platform_device *dsidev)
  907. {
  908. u32 l;
  909. int b0, b1, b2;
  910. /* A dummy read using the SCP interface to any DSIPHY register is
  911. * required after DSIPHY reset to complete the reset of the DSI complex
  912. * I/O. */
  913. l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
  914. if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
  915. b0 = 28;
  916. b1 = 27;
  917. b2 = 26;
  918. } else {
  919. b0 = 24;
  920. b1 = 25;
  921. b2 = 26;
  922. }
  923. #define DSI_FLD_GET(fld, start, end)\
  924. FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
  925. pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
  926. DSI_FLD_GET(PLL_STATUS, 0, 0),
  927. DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
  928. DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
  929. DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
  930. DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
  931. DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
  932. DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
  933. DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
  934. #undef DSI_FLD_GET
  935. }
  936. static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
  937. {
  938. DSSDBG("dsi_if_enable(%d)\n", enable);
  939. enable = enable ? 1 : 0;
  940. REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
  941. if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
  942. DSSERR("Failed to set dsi_if_enable to %d\n", enable);
  943. return -EIO;
  944. }
  945. return 0;
  946. }
  947. unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
  948. {
  949. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  950. return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
  951. }
  952. static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
  953. {
  954. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  955. return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
  956. }
  957. static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
  958. {
  959. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  960. return dsi->current_cinfo.clkin4ddr / 16;
  961. }
  962. static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
  963. {
  964. unsigned long r;
  965. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  966. if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
  967. /* DSI FCLK source is DSS_CLK_FCK */
  968. r = clk_get_rate(dsi->dss_clk);
  969. } else {
  970. /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
  971. r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
  972. }
  973. return r;
  974. }
  975. static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
  976. {
  977. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  978. unsigned long dsi_fclk;
  979. unsigned lp_clk_div;
  980. unsigned long lp_clk;
  981. lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
  982. if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
  983. return -EINVAL;
  984. dsi_fclk = dsi_fclk_rate(dsidev);
  985. lp_clk = dsi_fclk / 2 / lp_clk_div;
  986. DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
  987. dsi->current_cinfo.lp_clk = lp_clk;
  988. dsi->current_cinfo.lp_clk_div = lp_clk_div;
  989. /* LP_CLK_DIVISOR */
  990. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
  991. /* LP_RX_SYNCHRO_ENABLE */
  992. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
  993. return 0;
  994. }
  995. static void dsi_enable_scp_clk(struct platform_device *dsidev)
  996. {
  997. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  998. if (dsi->scp_clk_refcount++ == 0)
  999. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
  1000. }
  1001. static void dsi_disable_scp_clk(struct platform_device *dsidev)
  1002. {
  1003. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1004. WARN_ON(dsi->scp_clk_refcount == 0);
  1005. if (--dsi->scp_clk_refcount == 0)
  1006. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
  1007. }
  1008. enum dsi_pll_power_state {
  1009. DSI_PLL_POWER_OFF = 0x0,
  1010. DSI_PLL_POWER_ON_HSCLK = 0x1,
  1011. DSI_PLL_POWER_ON_ALL = 0x2,
  1012. DSI_PLL_POWER_ON_DIV = 0x3,
  1013. };
  1014. static int dsi_pll_power(struct platform_device *dsidev,
  1015. enum dsi_pll_power_state state)
  1016. {
  1017. int t = 0;
  1018. /* DSI-PLL power command 0x3 is not working */
  1019. if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
  1020. state == DSI_PLL_POWER_ON_DIV)
  1021. state = DSI_PLL_POWER_ON_ALL;
  1022. /* PLL_PWR_CMD */
  1023. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
  1024. /* PLL_PWR_STATUS */
  1025. while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
  1026. if (++t > 1000) {
  1027. DSSERR("Failed to set DSI PLL power mode to %d\n",
  1028. state);
  1029. return -ENODEV;
  1030. }
  1031. udelay(1);
  1032. }
  1033. return 0;
  1034. }
  1035. /* calculate clock rates using dividers in cinfo */
  1036. static int dsi_calc_clock_rates(struct platform_device *dsidev,
  1037. struct dsi_clock_info *cinfo)
  1038. {
  1039. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1040. if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
  1041. return -EINVAL;
  1042. if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
  1043. return -EINVAL;
  1044. if (cinfo->regm_dispc > dsi->regm_dispc_max)
  1045. return -EINVAL;
  1046. if (cinfo->regm_dsi > dsi->regm_dsi_max)
  1047. return -EINVAL;
  1048. cinfo->clkin = clk_get_rate(dsi->sys_clk);
  1049. cinfo->fint = cinfo->clkin / cinfo->regn;
  1050. if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
  1051. return -EINVAL;
  1052. cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
  1053. if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
  1054. return -EINVAL;
  1055. if (cinfo->regm_dispc > 0)
  1056. cinfo->dsi_pll_hsdiv_dispc_clk =
  1057. cinfo->clkin4ddr / cinfo->regm_dispc;
  1058. else
  1059. cinfo->dsi_pll_hsdiv_dispc_clk = 0;
  1060. if (cinfo->regm_dsi > 0)
  1061. cinfo->dsi_pll_hsdiv_dsi_clk =
  1062. cinfo->clkin4ddr / cinfo->regm_dsi;
  1063. else
  1064. cinfo->dsi_pll_hsdiv_dsi_clk = 0;
  1065. return 0;
  1066. }
  1067. int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
  1068. unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
  1069. struct dispc_clock_info *dispc_cinfo)
  1070. {
  1071. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1072. struct dsi_clock_info cur, best;
  1073. struct dispc_clock_info best_dispc;
  1074. int min_fck_per_pck;
  1075. int match = 0;
  1076. unsigned long dss_sys_clk, max_dss_fck;
  1077. dss_sys_clk = clk_get_rate(dsi->sys_clk);
  1078. max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
  1079. if (req_pck == dsi->cache_req_pck &&
  1080. dsi->cache_cinfo.clkin == dss_sys_clk) {
  1081. DSSDBG("DSI clock info found from cache\n");
  1082. *dsi_cinfo = dsi->cache_cinfo;
  1083. dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
  1084. dispc_cinfo);
  1085. return 0;
  1086. }
  1087. min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
  1088. if (min_fck_per_pck &&
  1089. req_pck * min_fck_per_pck > max_dss_fck) {
  1090. DSSERR("Requested pixel clock not possible with the current "
  1091. "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
  1092. "the constraint off.\n");
  1093. min_fck_per_pck = 0;
  1094. }
  1095. DSSDBG("dsi_pll_calc\n");
  1096. retry:
  1097. memset(&best, 0, sizeof(best));
  1098. memset(&best_dispc, 0, sizeof(best_dispc));
  1099. memset(&cur, 0, sizeof(cur));
  1100. cur.clkin = dss_sys_clk;
  1101. /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
  1102. /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
  1103. for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
  1104. cur.fint = cur.clkin / cur.regn;
  1105. if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
  1106. continue;
  1107. /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
  1108. for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
  1109. unsigned long a, b;
  1110. a = 2 * cur.regm * (cur.clkin/1000);
  1111. b = cur.regn;
  1112. cur.clkin4ddr = a / b * 1000;
  1113. if (cur.clkin4ddr > 1800 * 1000 * 1000)
  1114. break;
  1115. /* dsi_pll_hsdiv_dispc_clk(MHz) =
  1116. * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
  1117. for (cur.regm_dispc = 1; cur.regm_dispc <
  1118. dsi->regm_dispc_max; ++cur.regm_dispc) {
  1119. struct dispc_clock_info cur_dispc;
  1120. cur.dsi_pll_hsdiv_dispc_clk =
  1121. cur.clkin4ddr / cur.regm_dispc;
  1122. if (cur.regm_dispc > 1 &&
  1123. cur.regm_dispc % 2 != 0 &&
  1124. req_pck >= 1000000)
  1125. continue;
  1126. /* this will narrow down the search a bit,
  1127. * but still give pixclocks below what was
  1128. * requested */
  1129. if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
  1130. break;
  1131. if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
  1132. continue;
  1133. if (min_fck_per_pck &&
  1134. cur.dsi_pll_hsdiv_dispc_clk <
  1135. req_pck * min_fck_per_pck)
  1136. continue;
  1137. match = 1;
  1138. dispc_find_clk_divs(req_pck,
  1139. cur.dsi_pll_hsdiv_dispc_clk,
  1140. &cur_dispc);
  1141. if (abs(cur_dispc.pck - req_pck) <
  1142. abs(best_dispc.pck - req_pck)) {
  1143. best = cur;
  1144. best_dispc = cur_dispc;
  1145. if (cur_dispc.pck == req_pck)
  1146. goto found;
  1147. }
  1148. }
  1149. }
  1150. }
  1151. found:
  1152. if (!match) {
  1153. if (min_fck_per_pck) {
  1154. DSSERR("Could not find suitable clock settings.\n"
  1155. "Turning FCK/PCK constraint off and"
  1156. "trying again.\n");
  1157. min_fck_per_pck = 0;
  1158. goto retry;
  1159. }
  1160. DSSERR("Could not find suitable clock settings.\n");
  1161. return -EINVAL;
  1162. }
  1163. /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
  1164. best.regm_dsi = 0;
  1165. best.dsi_pll_hsdiv_dsi_clk = 0;
  1166. if (dsi_cinfo)
  1167. *dsi_cinfo = best;
  1168. if (dispc_cinfo)
  1169. *dispc_cinfo = best_dispc;
  1170. dsi->cache_req_pck = req_pck;
  1171. dsi->cache_clk_freq = 0;
  1172. dsi->cache_cinfo = best;
  1173. return 0;
  1174. }
  1175. static int dsi_pll_calc_ddrfreq(struct platform_device *dsidev,
  1176. unsigned long req_clkin4ddr, struct dsi_clock_info *cinfo)
  1177. {
  1178. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1179. struct dsi_clock_info cur, best;
  1180. DSSDBG("dsi_pll_calc_ddrfreq\n");
  1181. memset(&best, 0, sizeof(best));
  1182. memset(&cur, 0, sizeof(cur));
  1183. cur.clkin = clk_get_rate(dsi->sys_clk);
  1184. for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
  1185. cur.fint = cur.clkin / cur.regn;
  1186. if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
  1187. continue;
  1188. /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
  1189. for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
  1190. unsigned long a, b;
  1191. a = 2 * cur.regm * (cur.clkin/1000);
  1192. b = cur.regn;
  1193. cur.clkin4ddr = a / b * 1000;
  1194. if (cur.clkin4ddr > 1800 * 1000 * 1000)
  1195. break;
  1196. if (abs(cur.clkin4ddr - req_clkin4ddr) <
  1197. abs(best.clkin4ddr - req_clkin4ddr)) {
  1198. best = cur;
  1199. DSSDBG("best %ld\n", best.clkin4ddr);
  1200. }
  1201. if (cur.clkin4ddr == req_clkin4ddr)
  1202. goto found;
  1203. }
  1204. }
  1205. found:
  1206. if (cinfo)
  1207. *cinfo = best;
  1208. return 0;
  1209. }
  1210. static void dsi_pll_calc_dsi_fck(struct platform_device *dsidev,
  1211. struct dsi_clock_info *cinfo)
  1212. {
  1213. unsigned long max_dsi_fck;
  1214. max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
  1215. cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
  1216. cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
  1217. }
  1218. static int dsi_pll_calc_dispc_fck(struct platform_device *dsidev,
  1219. unsigned long req_pck, struct dsi_clock_info *cinfo,
  1220. struct dispc_clock_info *dispc_cinfo)
  1221. {
  1222. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1223. unsigned regm_dispc, best_regm_dispc;
  1224. unsigned long dispc_clk, best_dispc_clk;
  1225. int min_fck_per_pck;
  1226. unsigned long max_dss_fck;
  1227. struct dispc_clock_info best_dispc;
  1228. bool match;
  1229. max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
  1230. min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
  1231. if (min_fck_per_pck &&
  1232. req_pck * min_fck_per_pck > max_dss_fck) {
  1233. DSSERR("Requested pixel clock not possible with the current "
  1234. "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
  1235. "the constraint off.\n");
  1236. min_fck_per_pck = 0;
  1237. }
  1238. retry:
  1239. best_regm_dispc = 0;
  1240. best_dispc_clk = 0;
  1241. memset(&best_dispc, 0, sizeof(best_dispc));
  1242. match = false;
  1243. for (regm_dispc = 1; regm_dispc < dsi->regm_dispc_max; ++regm_dispc) {
  1244. struct dispc_clock_info cur_dispc;
  1245. dispc_clk = cinfo->clkin4ddr / regm_dispc;
  1246. /* this will narrow down the search a bit,
  1247. * but still give pixclocks below what was
  1248. * requested */
  1249. if (dispc_clk < req_pck)
  1250. break;
  1251. if (dispc_clk > max_dss_fck)
  1252. continue;
  1253. if (min_fck_per_pck && dispc_clk < req_pck * min_fck_per_pck)
  1254. continue;
  1255. match = true;
  1256. dispc_find_clk_divs(req_pck, dispc_clk, &cur_dispc);
  1257. if (abs(cur_dispc.pck - req_pck) <
  1258. abs(best_dispc.pck - req_pck)) {
  1259. best_regm_dispc = regm_dispc;
  1260. best_dispc_clk = dispc_clk;
  1261. best_dispc = cur_dispc;
  1262. if (cur_dispc.pck == req_pck)
  1263. goto found;
  1264. }
  1265. }
  1266. if (!match) {
  1267. if (min_fck_per_pck) {
  1268. DSSERR("Could not find suitable clock settings.\n"
  1269. "Turning FCK/PCK constraint off and"
  1270. "trying again.\n");
  1271. min_fck_per_pck = 0;
  1272. goto retry;
  1273. }
  1274. DSSERR("Could not find suitable clock settings.\n");
  1275. return -EINVAL;
  1276. }
  1277. found:
  1278. cinfo->regm_dispc = best_regm_dispc;
  1279. cinfo->dsi_pll_hsdiv_dispc_clk = best_dispc_clk;
  1280. *dispc_cinfo = best_dispc;
  1281. return 0;
  1282. }
  1283. int dsi_pll_set_clock_div(struct platform_device *dsidev,
  1284. struct dsi_clock_info *cinfo)
  1285. {
  1286. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1287. int r = 0;
  1288. u32 l;
  1289. int f = 0;
  1290. u8 regn_start, regn_end, regm_start, regm_end;
  1291. u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
  1292. DSSDBG("DSI PLL clock config starts");
  1293. dsi->current_cinfo.clkin = cinfo->clkin;
  1294. dsi->current_cinfo.fint = cinfo->fint;
  1295. dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
  1296. dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
  1297. cinfo->dsi_pll_hsdiv_dispc_clk;
  1298. dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
  1299. cinfo->dsi_pll_hsdiv_dsi_clk;
  1300. dsi->current_cinfo.regn = cinfo->regn;
  1301. dsi->current_cinfo.regm = cinfo->regm;
  1302. dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
  1303. dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
  1304. DSSDBG("DSI Fint %ld\n", cinfo->fint);
  1305. DSSDBG("clkin rate %ld\n", cinfo->clkin);
  1306. /* DSIPHY == CLKIN4DDR */
  1307. DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
  1308. cinfo->regm,
  1309. cinfo->regn,
  1310. cinfo->clkin,
  1311. cinfo->clkin4ddr);
  1312. DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
  1313. cinfo->clkin4ddr / 1000 / 1000 / 2);
  1314. DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
  1315. DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
  1316. dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
  1317. dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
  1318. cinfo->dsi_pll_hsdiv_dispc_clk);
  1319. DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
  1320. dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
  1321. dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
  1322. cinfo->dsi_pll_hsdiv_dsi_clk);
  1323. dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
  1324. dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
  1325. dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
  1326. &regm_dispc_end);
  1327. dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
  1328. &regm_dsi_end);
  1329. /* DSI_PLL_AUTOMODE = manual */
  1330. REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
  1331. l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
  1332. l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
  1333. /* DSI_PLL_REGN */
  1334. l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
  1335. /* DSI_PLL_REGM */
  1336. l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
  1337. /* DSI_CLOCK_DIV */
  1338. l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
  1339. regm_dispc_start, regm_dispc_end);
  1340. /* DSIPROTO_CLOCK_DIV */
  1341. l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
  1342. regm_dsi_start, regm_dsi_end);
  1343. dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
  1344. BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
  1345. l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
  1346. if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
  1347. f = cinfo->fint < 1000000 ? 0x3 :
  1348. cinfo->fint < 1250000 ? 0x4 :
  1349. cinfo->fint < 1500000 ? 0x5 :
  1350. cinfo->fint < 1750000 ? 0x6 :
  1351. 0x7;
  1352. l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
  1353. } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
  1354. f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
  1355. l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
  1356. }
  1357. l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
  1358. l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
  1359. l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
  1360. if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
  1361. l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
  1362. dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
  1363. REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
  1364. if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
  1365. DSSERR("dsi pll go bit not going down.\n");
  1366. r = -EIO;
  1367. goto err;
  1368. }
  1369. if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
  1370. DSSERR("cannot lock PLL\n");
  1371. r = -EIO;
  1372. goto err;
  1373. }
  1374. dsi->pll_locked = 1;
  1375. l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
  1376. l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
  1377. l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
  1378. l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
  1379. l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
  1380. l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
  1381. l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
  1382. l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
  1383. l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
  1384. l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
  1385. l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
  1386. l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
  1387. l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
  1388. l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
  1389. l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
  1390. dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
  1391. DSSDBG("PLL config done\n");
  1392. err:
  1393. return r;
  1394. }
  1395. int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
  1396. bool enable_hsdiv)
  1397. {
  1398. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1399. int r = 0;
  1400. enum dsi_pll_power_state pwstate;
  1401. DSSDBG("PLL init\n");
  1402. /*
  1403. * It seems that on many OMAPs we need to enable both to have a
  1404. * functional HSDivider.
  1405. */
  1406. enable_hsclk = enable_hsdiv = true;
  1407. if (dsi->vdds_dsi_reg == NULL) {
  1408. struct regulator *vdds_dsi;
  1409. vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
  1410. /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
  1411. if (IS_ERR(vdds_dsi))
  1412. vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
  1413. if (IS_ERR(vdds_dsi)) {
  1414. DSSERR("can't get VDDS_DSI regulator\n");
  1415. return PTR_ERR(vdds_dsi);
  1416. }
  1417. dsi->vdds_dsi_reg = vdds_dsi;
  1418. }
  1419. dsi_enable_pll_clock(dsidev, 1);
  1420. /*
  1421. * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
  1422. */
  1423. dsi_enable_scp_clk(dsidev);
  1424. if (!dsi->vdds_dsi_enabled) {
  1425. r = regulator_enable(dsi->vdds_dsi_reg);
  1426. if (r)
  1427. goto err0;
  1428. dsi->vdds_dsi_enabled = true;
  1429. }
  1430. /* XXX PLL does not come out of reset without this... */
  1431. dispc_pck_free_enable(1);
  1432. if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
  1433. DSSERR("PLL not coming out of reset.\n");
  1434. r = -ENODEV;
  1435. dispc_pck_free_enable(0);
  1436. goto err1;
  1437. }
  1438. /* XXX ... but if left on, we get problems when planes do not
  1439. * fill the whole display. No idea about this */
  1440. dispc_pck_free_enable(0);
  1441. if (enable_hsclk && enable_hsdiv)
  1442. pwstate = DSI_PLL_POWER_ON_ALL;
  1443. else if (enable_hsclk)
  1444. pwstate = DSI_PLL_POWER_ON_HSCLK;
  1445. else if (enable_hsdiv)
  1446. pwstate = DSI_PLL_POWER_ON_DIV;
  1447. else
  1448. pwstate = DSI_PLL_POWER_OFF;
  1449. r = dsi_pll_power(dsidev, pwstate);
  1450. if (r)
  1451. goto err1;
  1452. DSSDBG("PLL init done\n");
  1453. return 0;
  1454. err1:
  1455. if (dsi->vdds_dsi_enabled) {
  1456. regulator_disable(dsi->vdds_dsi_reg);
  1457. dsi->vdds_dsi_enabled = false;
  1458. }
  1459. err0:
  1460. dsi_disable_scp_clk(dsidev);
  1461. dsi_enable_pll_clock(dsidev, 0);
  1462. return r;
  1463. }
  1464. void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
  1465. {
  1466. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1467. dsi->pll_locked = 0;
  1468. dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
  1469. if (disconnect_lanes) {
  1470. WARN_ON(!dsi->vdds_dsi_enabled);
  1471. regulator_disable(dsi->vdds_dsi_reg);
  1472. dsi->vdds_dsi_enabled = false;
  1473. }
  1474. dsi_disable_scp_clk(dsidev);
  1475. dsi_enable_pll_clock(dsidev, 0);
  1476. DSSDBG("PLL uninit done\n");
  1477. }
  1478. static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
  1479. struct seq_file *s)
  1480. {
  1481. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1482. struct dsi_clock_info *cinfo = &dsi->current_cinfo;
  1483. enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
  1484. int dsi_module = dsi->module_id;
  1485. dispc_clk_src = dss_get_dispc_clk_source();
  1486. dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
  1487. if (dsi_runtime_get(dsidev))
  1488. return;
  1489. seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
  1490. seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
  1491. seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
  1492. seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
  1493. cinfo->clkin4ddr, cinfo->regm);
  1494. seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
  1495. dss_feat_get_clk_source_name(dsi_module == 0 ?
  1496. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
  1497. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
  1498. cinfo->dsi_pll_hsdiv_dispc_clk,
  1499. cinfo->regm_dispc,
  1500. dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
  1501. "off" : "on");
  1502. seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
  1503. dss_feat_get_clk_source_name(dsi_module == 0 ?
  1504. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
  1505. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
  1506. cinfo->dsi_pll_hsdiv_dsi_clk,
  1507. cinfo->regm_dsi,
  1508. dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
  1509. "off" : "on");
  1510. seq_printf(s, "- DSI%d -\n", dsi_module + 1);
  1511. seq_printf(s, "dsi fclk source = %s (%s)\n",
  1512. dss_get_generic_clk_source_name(dsi_clk_src),
  1513. dss_feat_get_clk_source_name(dsi_clk_src));
  1514. seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
  1515. seq_printf(s, "DDR_CLK\t\t%lu\n",
  1516. cinfo->clkin4ddr / 4);
  1517. seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
  1518. seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
  1519. dsi_runtime_put(dsidev);
  1520. }
  1521. void dsi_dump_clocks(struct seq_file *s)
  1522. {
  1523. struct platform_device *dsidev;
  1524. int i;
  1525. for (i = 0; i < MAX_NUM_DSI; i++) {
  1526. dsidev = dsi_get_dsidev_from_id(i);
  1527. if (dsidev)
  1528. dsi_dump_dsidev_clocks(dsidev, s);
  1529. }
  1530. }
  1531. #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
  1532. static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
  1533. struct seq_file *s)
  1534. {
  1535. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1536. unsigned long flags;
  1537. struct dsi_irq_stats stats;
  1538. spin_lock_irqsave(&dsi->irq_stats_lock, flags);
  1539. stats = dsi->irq_stats;
  1540. memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
  1541. dsi->irq_stats.last_reset = jiffies;
  1542. spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
  1543. seq_printf(s, "period %u ms\n",
  1544. jiffies_to_msecs(jiffies - stats.last_reset));
  1545. seq_printf(s, "irqs %d\n", stats.irq_count);
  1546. #define PIS(x) \
  1547. seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
  1548. seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
  1549. PIS(VC0);
  1550. PIS(VC1);
  1551. PIS(VC2);
  1552. PIS(VC3);
  1553. PIS(WAKEUP);
  1554. PIS(RESYNC);
  1555. PIS(PLL_LOCK);
  1556. PIS(PLL_UNLOCK);
  1557. PIS(PLL_RECALL);
  1558. PIS(COMPLEXIO_ERR);
  1559. PIS(HS_TX_TIMEOUT);
  1560. PIS(LP_RX_TIMEOUT);
  1561. PIS(TE_TRIGGER);
  1562. PIS(ACK_TRIGGER);
  1563. PIS(SYNC_LOST);
  1564. PIS(LDO_POWER_GOOD);
  1565. PIS(TA_TIMEOUT);
  1566. #undef PIS
  1567. #define PIS(x) \
  1568. seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
  1569. stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
  1570. stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
  1571. stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
  1572. stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
  1573. seq_printf(s, "-- VC interrupts --\n");
  1574. PIS(CS);
  1575. PIS(ECC_CORR);
  1576. PIS(PACKET_SENT);
  1577. PIS(FIFO_TX_OVF);
  1578. PIS(FIFO_RX_OVF);
  1579. PIS(BTA);
  1580. PIS(ECC_NO_CORR);
  1581. PIS(FIFO_TX_UDF);
  1582. PIS(PP_BUSY_CHANGE);
  1583. #undef PIS
  1584. #define PIS(x) \
  1585. seq_printf(s, "%-20s %10d\n", #x, \
  1586. stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
  1587. seq_printf(s, "-- CIO interrupts --\n");
  1588. PIS(ERRSYNCESC1);
  1589. PIS(ERRSYNCESC2);
  1590. PIS(ERRSYNCESC3);
  1591. PIS(ERRESC1);
  1592. PIS(ERRESC2);
  1593. PIS(ERRESC3);
  1594. PIS(ERRCONTROL1);
  1595. PIS(ERRCONTROL2);
  1596. PIS(ERRCONTROL3);
  1597. PIS(STATEULPS1);
  1598. PIS(STATEULPS2);
  1599. PIS(STATEULPS3);
  1600. PIS(ERRCONTENTIONLP0_1);
  1601. PIS(ERRCONTENTIONLP1_1);
  1602. PIS(ERRCONTENTIONLP0_2);
  1603. PIS(ERRCONTENTIONLP1_2);
  1604. PIS(ERRCONTENTIONLP0_3);
  1605. PIS(ERRCONTENTIONLP1_3);
  1606. PIS(ULPSACTIVENOT_ALL0);
  1607. PIS(ULPSACTIVENOT_ALL1);
  1608. #undef PIS
  1609. }
  1610. static void dsi1_dump_irqs(struct seq_file *s)
  1611. {
  1612. struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
  1613. dsi_dump_dsidev_irqs(dsidev, s);
  1614. }
  1615. static void dsi2_dump_irqs(struct seq_file *s)
  1616. {
  1617. struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
  1618. dsi_dump_dsidev_irqs(dsidev, s);
  1619. }
  1620. #endif
  1621. static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
  1622. struct seq_file *s)
  1623. {
  1624. #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
  1625. if (dsi_runtime_get(dsidev))
  1626. return;
  1627. dsi_enable_scp_clk(dsidev);
  1628. DUMPREG(DSI_REVISION);
  1629. DUMPREG(DSI_SYSCONFIG);
  1630. DUMPREG(DSI_SYSSTATUS);
  1631. DUMPREG(DSI_IRQSTATUS);
  1632. DUMPREG(DSI_IRQENABLE);
  1633. DUMPREG(DSI_CTRL);
  1634. DUMPREG(DSI_COMPLEXIO_CFG1);
  1635. DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
  1636. DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
  1637. DUMPREG(DSI_CLK_CTRL);
  1638. DUMPREG(DSI_TIMING1);
  1639. DUMPREG(DSI_TIMING2);
  1640. DUMPREG(DSI_VM_TIMING1);
  1641. DUMPREG(DSI_VM_TIMING2);
  1642. DUMPREG(DSI_VM_TIMING3);
  1643. DUMPREG(DSI_CLK_TIMING);
  1644. DUMPREG(DSI_TX_FIFO_VC_SIZE);
  1645. DUMPREG(DSI_RX_FIFO_VC_SIZE);
  1646. DUMPREG(DSI_COMPLEXIO_CFG2);
  1647. DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
  1648. DUMPREG(DSI_VM_TIMING4);
  1649. DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
  1650. DUMPREG(DSI_VM_TIMING5);
  1651. DUMPREG(DSI_VM_TIMING6);
  1652. DUMPREG(DSI_VM_TIMING7);
  1653. DUMPREG(DSI_STOPCLK_TIMING);
  1654. DUMPREG(DSI_VC_CTRL(0));
  1655. DUMPREG(DSI_VC_TE(0));
  1656. DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
  1657. DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
  1658. DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
  1659. DUMPREG(DSI_VC_IRQSTATUS(0));
  1660. DUMPREG(DSI_VC_IRQENABLE(0));
  1661. DUMPREG(DSI_VC_CTRL(1));
  1662. DUMPREG(DSI_VC_TE(1));
  1663. DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
  1664. DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
  1665. DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
  1666. DUMPREG(DSI_VC_IRQSTATUS(1));
  1667. DUMPREG(DSI_VC_IRQENABLE(1));
  1668. DUMPREG(DSI_VC_CTRL(2));
  1669. DUMPREG(DSI_VC_TE(2));
  1670. DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
  1671. DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
  1672. DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
  1673. DUMPREG(DSI_VC_IRQSTATUS(2));
  1674. DUMPREG(DSI_VC_IRQENABLE(2));
  1675. DUMPREG(DSI_VC_CTRL(3));
  1676. DUMPREG(DSI_VC_TE(3));
  1677. DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
  1678. DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
  1679. DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
  1680. DUMPREG(DSI_VC_IRQSTATUS(3));
  1681. DUMPREG(DSI_VC_IRQENABLE(3));
  1682. DUMPREG(DSI_DSIPHY_CFG0);
  1683. DUMPREG(DSI_DSIPHY_CFG1);
  1684. DUMPREG(DSI_DSIPHY_CFG2);
  1685. DUMPREG(DSI_DSIPHY_CFG5);
  1686. DUMPREG(DSI_PLL_CONTROL);
  1687. DUMPREG(DSI_PLL_STATUS);
  1688. DUMPREG(DSI_PLL_GO);
  1689. DUMPREG(DSI_PLL_CONFIGURATION1);
  1690. DUMPREG(DSI_PLL_CONFIGURATION2);
  1691. dsi_disable_scp_clk(dsidev);
  1692. dsi_runtime_put(dsidev);
  1693. #undef DUMPREG
  1694. }
  1695. static void dsi1_dump_regs(struct seq_file *s)
  1696. {
  1697. struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
  1698. dsi_dump_dsidev_regs(dsidev, s);
  1699. }
  1700. static void dsi2_dump_regs(struct seq_file *s)
  1701. {
  1702. struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
  1703. dsi_dump_dsidev_regs(dsidev, s);
  1704. }
  1705. enum dsi_cio_power_state {
  1706. DSI_COMPLEXIO_POWER_OFF = 0x0,
  1707. DSI_COMPLEXIO_POWER_ON = 0x1,
  1708. DSI_COMPLEXIO_POWER_ULPS = 0x2,
  1709. };
  1710. static int dsi_cio_power(struct platform_device *dsidev,
  1711. enum dsi_cio_power_state state)
  1712. {
  1713. int t = 0;
  1714. /* PWR_CMD */
  1715. REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
  1716. /* PWR_STATUS */
  1717. while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
  1718. 26, 25) != state) {
  1719. if (++t > 1000) {
  1720. DSSERR("failed to set complexio power state to "
  1721. "%d\n", state);
  1722. return -ENODEV;
  1723. }
  1724. udelay(1);
  1725. }
  1726. return 0;
  1727. }
  1728. static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
  1729. {
  1730. int val;
  1731. /* line buffer on OMAP3 is 1024 x 24bits */
  1732. /* XXX: for some reason using full buffer size causes
  1733. * considerable TX slowdown with update sizes that fill the
  1734. * whole buffer */
  1735. if (!dss_has_feature(FEAT_DSI_GNQ))
  1736. return 1023 * 3;
  1737. val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
  1738. switch (val) {
  1739. case 1:
  1740. return 512 * 3; /* 512x24 bits */
  1741. case 2:
  1742. return 682 * 3; /* 682x24 bits */
  1743. case 3:
  1744. return 853 * 3; /* 853x24 bits */
  1745. case 4:
  1746. return 1024 * 3; /* 1024x24 bits */
  1747. case 5:
  1748. return 1194 * 3; /* 1194x24 bits */
  1749. case 6:
  1750. return 1365 * 3; /* 1365x24 bits */
  1751. case 7:
  1752. return 1920 * 3; /* 1920x24 bits */
  1753. default:
  1754. BUG();
  1755. return 0;
  1756. }
  1757. }
  1758. static int dsi_set_lane_config(struct platform_device *dsidev)
  1759. {
  1760. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1761. static const u8 offsets[] = { 0, 4, 8, 12, 16 };
  1762. static const enum dsi_lane_function functions[] = {
  1763. DSI_LANE_CLK,
  1764. DSI_LANE_DATA1,
  1765. DSI_LANE_DATA2,
  1766. DSI_LANE_DATA3,
  1767. DSI_LANE_DATA4,
  1768. };
  1769. u32 r;
  1770. int i;
  1771. r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
  1772. for (i = 0; i < dsi->num_lanes_used; ++i) {
  1773. unsigned offset = offsets[i];
  1774. unsigned polarity, lane_number;
  1775. unsigned t;
  1776. for (t = 0; t < dsi->num_lanes_supported; ++t)
  1777. if (dsi->lanes[t].function == functions[i])
  1778. break;
  1779. if (t == dsi->num_lanes_supported)
  1780. return -EINVAL;
  1781. lane_number = t;
  1782. polarity = dsi->lanes[t].polarity;
  1783. r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
  1784. r = FLD_MOD(r, polarity, offset + 3, offset + 3);
  1785. }
  1786. /* clear the unused lanes */
  1787. for (; i < dsi->num_lanes_supported; ++i) {
  1788. unsigned offset = offsets[i];
  1789. r = FLD_MOD(r, 0, offset + 2, offset);
  1790. r = FLD_MOD(r, 0, offset + 3, offset + 3);
  1791. }
  1792. dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
  1793. return 0;
  1794. }
  1795. static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
  1796. {
  1797. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1798. /* convert time in ns to ddr ticks, rounding up */
  1799. unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
  1800. return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
  1801. }
  1802. static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
  1803. {
  1804. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1805. unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
  1806. return ddr * 1000 * 1000 / (ddr_clk / 1000);
  1807. }
  1808. static void dsi_cio_timings(struct platform_device *dsidev)
  1809. {
  1810. u32 r;
  1811. u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
  1812. u32 tlpx_half, tclk_trail, tclk_zero;
  1813. u32 tclk_prepare;
  1814. /* calculate timings */
  1815. /* 1 * DDR_CLK = 2 * UI */
  1816. /* min 40ns + 4*UI max 85ns + 6*UI */
  1817. ths_prepare = ns2ddr(dsidev, 70) + 2;
  1818. /* min 145ns + 10*UI */
  1819. ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
  1820. /* min max(8*UI, 60ns+4*UI) */
  1821. ths_trail = ns2ddr(dsidev, 60) + 5;
  1822. /* min 100ns */
  1823. ths_exit = ns2ddr(dsidev, 145);
  1824. /* tlpx min 50n */
  1825. tlpx_half = ns2ddr(dsidev, 25);
  1826. /* min 60ns */
  1827. tclk_trail = ns2ddr(dsidev, 60) + 2;
  1828. /* min 38ns, max 95ns */
  1829. tclk_prepare = ns2ddr(dsidev, 65);
  1830. /* min tclk-prepare + tclk-zero = 300ns */
  1831. tclk_zero = ns2ddr(dsidev, 260);
  1832. DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
  1833. ths_prepare, ddr2ns(dsidev, ths_prepare),
  1834. ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
  1835. DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
  1836. ths_trail, ddr2ns(dsidev, ths_trail),
  1837. ths_exit, ddr2ns(dsidev, ths_exit));
  1838. DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
  1839. "tclk_zero %u (%uns)\n",
  1840. tlpx_half, ddr2ns(dsidev, tlpx_half),
  1841. tclk_trail, ddr2ns(dsidev, tclk_trail),
  1842. tclk_zero, ddr2ns(dsidev, tclk_zero));
  1843. DSSDBG("tclk_prepare %u (%uns)\n",
  1844. tclk_prepare, ddr2ns(dsidev, tclk_prepare));
  1845. /* program timings */
  1846. r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
  1847. r = FLD_MOD(r, ths_prepare, 31, 24);
  1848. r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
  1849. r = FLD_MOD(r, ths_trail, 15, 8);
  1850. r = FLD_MOD(r, ths_exit, 7, 0);
  1851. dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
  1852. r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
  1853. r = FLD_MOD(r, tlpx_half, 20, 16);
  1854. r = FLD_MOD(r, tclk_trail, 15, 8);
  1855. r = FLD_MOD(r, tclk_zero, 7, 0);
  1856. if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
  1857. r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
  1858. r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
  1859. r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
  1860. }
  1861. dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
  1862. r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
  1863. r = FLD_MOD(r, tclk_prepare, 7, 0);
  1864. dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
  1865. }
  1866. /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
  1867. static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
  1868. unsigned mask_p, unsigned mask_n)
  1869. {
  1870. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1871. int i;
  1872. u32 l;
  1873. u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
  1874. l = 0;
  1875. for (i = 0; i < dsi->num_lanes_supported; ++i) {
  1876. unsigned p = dsi->lanes[i].polarity;
  1877. if (mask_p & (1 << i))
  1878. l |= 1 << (i * 2 + (p ? 0 : 1));
  1879. if (mask_n & (1 << i))
  1880. l |= 1 << (i * 2 + (p ? 1 : 0));
  1881. }
  1882. /*
  1883. * Bits in REGLPTXSCPDAT4TO0DXDY:
  1884. * 17: DY0 18: DX0
  1885. * 19: DY1 20: DX1
  1886. * 21: DY2 22: DX2
  1887. * 23: DY3 24: DX3
  1888. * 25: DY4 26: DX4
  1889. */
  1890. /* Set the lane override configuration */
  1891. /* REGLPTXSCPDAT4TO0DXDY */
  1892. REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
  1893. /* Enable lane override */
  1894. /* ENLPTXSCPDAT */
  1895. REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
  1896. }
  1897. static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
  1898. {
  1899. /* Disable lane override */
  1900. REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
  1901. /* Reset the lane override configuration */
  1902. /* REGLPTXSCPDAT4TO0DXDY */
  1903. REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
  1904. }
  1905. static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
  1906. {
  1907. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1908. int t, i;
  1909. bool in_use[DSI_MAX_NR_LANES];
  1910. static const u8 offsets_old[] = { 28, 27, 26 };
  1911. static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
  1912. const u8 *offsets;
  1913. if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
  1914. offsets = offsets_old;
  1915. else
  1916. offsets = offsets_new;
  1917. for (i = 0; i < dsi->num_lanes_supported; ++i)
  1918. in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
  1919. t = 100000;
  1920. while (true) {
  1921. u32 l;
  1922. int ok;
  1923. l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
  1924. ok = 0;
  1925. for (i = 0; i < dsi->num_lanes_supported; ++i) {
  1926. if (!in_use[i] || (l & (1 << offsets[i])))
  1927. ok++;
  1928. }
  1929. if (ok == dsi->num_lanes_supported)
  1930. break;
  1931. if (--t == 0) {
  1932. for (i = 0; i < dsi->num_lanes_supported; ++i) {
  1933. if (!in_use[i] || (l & (1 << offsets[i])))
  1934. continue;
  1935. DSSERR("CIO TXCLKESC%d domain not coming " \
  1936. "out of reset\n", i);
  1937. }
  1938. return -EIO;
  1939. }
  1940. }
  1941. return 0;
  1942. }
  1943. /* return bitmask of enabled lanes, lane0 being the lsb */
  1944. static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
  1945. {
  1946. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1947. unsigned mask = 0;
  1948. int i;
  1949. for (i = 0; i < dsi->num_lanes_supported; ++i) {
  1950. if (dsi->lanes[i].function != DSI_LANE_UNUSED)
  1951. mask |= 1 << i;
  1952. }
  1953. return mask;
  1954. }
  1955. static int dsi_cio_init(struct platform_device *dsidev)
  1956. {
  1957. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  1958. int r;
  1959. u32 l;
  1960. DSSDBG("DSI CIO init starts");
  1961. r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
  1962. if (r)
  1963. return r;
  1964. dsi_enable_scp_clk(dsidev);
  1965. /* A dummy read using the SCP interface to any DSIPHY register is
  1966. * required after DSIPHY reset to complete the reset of the DSI complex
  1967. * I/O. */
  1968. dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
  1969. if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
  1970. DSSERR("CIO SCP Clock domain not coming out of reset.\n");
  1971. r = -EIO;
  1972. goto err_scp_clk_dom;
  1973. }
  1974. r = dsi_set_lane_config(dsidev);
  1975. if (r)
  1976. goto err_scp_clk_dom;
  1977. /* set TX STOP MODE timer to maximum for this operation */
  1978. l = dsi_read_reg(dsidev, DSI_TIMING1);
  1979. l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
  1980. l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
  1981. l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
  1982. l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
  1983. dsi_write_reg(dsidev, DSI_TIMING1, l);
  1984. if (dsi->ulps_enabled) {
  1985. unsigned mask_p;
  1986. int i;
  1987. DSSDBG("manual ulps exit\n");
  1988. /* ULPS is exited by Mark-1 state for 1ms, followed by
  1989. * stop state. DSS HW cannot do this via the normal
  1990. * ULPS exit sequence, as after reset the DSS HW thinks
  1991. * that we are not in ULPS mode, and refuses to send the
  1992. * sequence. So we need to send the ULPS exit sequence
  1993. * manually by setting positive lines high and negative lines
  1994. * low for 1ms.
  1995. */
  1996. mask_p = 0;
  1997. for (i = 0; i < dsi->num_lanes_supported; ++i) {
  1998. if (dsi->lanes[i].function == DSI_LANE_UNUSED)
  1999. continue;
  2000. mask_p |= 1 << i;
  2001. }
  2002. dsi_cio_enable_lane_override(dsidev, mask_p, 0);
  2003. }
  2004. r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
  2005. if (r)
  2006. goto err_cio_pwr;
  2007. if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
  2008. DSSERR("CIO PWR clock domain not coming out of reset.\n");
  2009. r = -ENODEV;
  2010. goto err_cio_pwr_dom;
  2011. }
  2012. dsi_if_enable(dsidev, true);
  2013. dsi_if_enable(dsidev, false);
  2014. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
  2015. r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
  2016. if (r)
  2017. goto err_tx_clk_esc_rst;
  2018. if (dsi->ulps_enabled) {
  2019. /* Keep Mark-1 state for 1ms (as per DSI spec) */
  2020. ktime_t wait = ns_to_ktime(1000 * 1000);
  2021. set_current_state(TASK_UNINTERRUPTIBLE);
  2022. schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
  2023. /* Disable the override. The lanes should be set to Mark-11
  2024. * state by the HW */
  2025. dsi_cio_disable_lane_override(dsidev);
  2026. }
  2027. /* FORCE_TX_STOP_MODE_IO */
  2028. REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
  2029. dsi_cio_timings(dsidev);
  2030. if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
  2031. /* DDR_CLK_ALWAYS_ON */
  2032. REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
  2033. dsi->vm_timings.ddr_clk_always_on, 13, 13);
  2034. }
  2035. dsi->ulps_enabled = false;
  2036. DSSDBG("CIO init done\n");
  2037. return 0;
  2038. err_tx_clk_esc_rst:
  2039. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
  2040. err_cio_pwr_dom:
  2041. dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
  2042. err_cio_pwr:
  2043. if (dsi->ulps_enabled)
  2044. dsi_cio_disable_lane_override(dsidev);
  2045. err_scp_clk_dom:
  2046. dsi_disable_scp_clk(dsidev);
  2047. dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
  2048. return r;
  2049. }
  2050. static void dsi_cio_uninit(struct platform_device *dsidev)
  2051. {
  2052. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2053. /* DDR_CLK_ALWAYS_ON */
  2054. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
  2055. dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
  2056. dsi_disable_scp_clk(dsidev);
  2057. dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
  2058. }
  2059. static void dsi_config_tx_fifo(struct platform_device *dsidev,
  2060. enum fifo_size size1, enum fifo_size size2,
  2061. enum fifo_size size3, enum fifo_size size4)
  2062. {
  2063. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2064. u32 r = 0;
  2065. int add = 0;
  2066. int i;
  2067. dsi->vc[0].fifo_size = size1;
  2068. dsi->vc[1].fifo_size = size2;
  2069. dsi->vc[2].fifo_size = size3;
  2070. dsi->vc[3].fifo_size = size4;
  2071. for (i = 0; i < 4; i++) {
  2072. u8 v;
  2073. int size = dsi->vc[i].fifo_size;
  2074. if (add + size > 4) {
  2075. DSSERR("Illegal FIFO configuration\n");
  2076. BUG();
  2077. return;
  2078. }
  2079. v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
  2080. r |= v << (8 * i);
  2081. /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
  2082. add += size;
  2083. }
  2084. dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
  2085. }
  2086. static void dsi_config_rx_fifo(struct platform_device *dsidev,
  2087. enum fifo_size size1, enum fifo_size size2,
  2088. enum fifo_size size3, enum fifo_size size4)
  2089. {
  2090. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2091. u32 r = 0;
  2092. int add = 0;
  2093. int i;
  2094. dsi->vc[0].fifo_size = size1;
  2095. dsi->vc[1].fifo_size = size2;
  2096. dsi->vc[2].fifo_size = size3;
  2097. dsi->vc[3].fifo_size = size4;
  2098. for (i = 0; i < 4; i++) {
  2099. u8 v;
  2100. int size = dsi->vc[i].fifo_size;
  2101. if (add + size > 4) {
  2102. DSSERR("Illegal FIFO configuration\n");
  2103. BUG();
  2104. return;
  2105. }
  2106. v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
  2107. r |= v << (8 * i);
  2108. /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
  2109. add += size;
  2110. }
  2111. dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
  2112. }
  2113. static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
  2114. {
  2115. u32 r;
  2116. r = dsi_read_reg(dsidev, DSI_TIMING1);
  2117. r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
  2118. dsi_write_reg(dsidev, DSI_TIMING1, r);
  2119. if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
  2120. DSSERR("TX_STOP bit not going down\n");
  2121. return -EIO;
  2122. }
  2123. return 0;
  2124. }
  2125. static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
  2126. {
  2127. return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
  2128. }
  2129. static void dsi_packet_sent_handler_vp(void *data, u32 mask)
  2130. {
  2131. struct dsi_packet_sent_handler_data *vp_data =
  2132. (struct dsi_packet_sent_handler_data *) data;
  2133. struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
  2134. const int channel = dsi->update_channel;
  2135. u8 bit = dsi->te_enabled ? 30 : 31;
  2136. if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
  2137. complete(vp_data->completion);
  2138. }
  2139. static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
  2140. {
  2141. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2142. DECLARE_COMPLETION_ONSTACK(completion);
  2143. struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
  2144. int r = 0;
  2145. u8 bit;
  2146. bit = dsi->te_enabled ? 30 : 31;
  2147. r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
  2148. &vp_data, DSI_VC_IRQ_PACKET_SENT);
  2149. if (r)
  2150. goto err0;
  2151. /* Wait for completion only if TE_EN/TE_START is still set */
  2152. if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
  2153. if (wait_for_completion_timeout(&completion,
  2154. msecs_to_jiffies(10)) == 0) {
  2155. DSSERR("Failed to complete previous frame transfer\n");
  2156. r = -EIO;
  2157. goto err1;
  2158. }
  2159. }
  2160. dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
  2161. &vp_data, DSI_VC_IRQ_PACKET_SENT);
  2162. return 0;
  2163. err1:
  2164. dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
  2165. &vp_data, DSI_VC_IRQ_PACKET_SENT);
  2166. err0:
  2167. return r;
  2168. }
  2169. static void dsi_packet_sent_handler_l4(void *data, u32 mask)
  2170. {
  2171. struct dsi_packet_sent_handler_data *l4_data =
  2172. (struct dsi_packet_sent_handler_data *) data;
  2173. struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
  2174. const int channel = dsi->update_channel;
  2175. if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
  2176. complete(l4_data->completion);
  2177. }
  2178. static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
  2179. {
  2180. DECLARE_COMPLETION_ONSTACK(completion);
  2181. struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
  2182. int r = 0;
  2183. r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
  2184. &l4_data, DSI_VC_IRQ_PACKET_SENT);
  2185. if (r)
  2186. goto err0;
  2187. /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
  2188. if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
  2189. if (wait_for_completion_timeout(&completion,
  2190. msecs_to_jiffies(10)) == 0) {
  2191. DSSERR("Failed to complete previous l4 transfer\n");
  2192. r = -EIO;
  2193. goto err1;
  2194. }
  2195. }
  2196. dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
  2197. &l4_data, DSI_VC_IRQ_PACKET_SENT);
  2198. return 0;
  2199. err1:
  2200. dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
  2201. &l4_data, DSI_VC_IRQ_PACKET_SENT);
  2202. err0:
  2203. return r;
  2204. }
  2205. static int dsi_sync_vc(struct platform_device *dsidev, int channel)
  2206. {
  2207. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2208. WARN_ON(!dsi_bus_is_locked(dsidev));
  2209. WARN_ON(in_interrupt());
  2210. if (!dsi_vc_is_enabled(dsidev, channel))
  2211. return 0;
  2212. switch (dsi->vc[channel].source) {
  2213. case DSI_VC_SOURCE_VP:
  2214. return dsi_sync_vc_vp(dsidev, channel);
  2215. case DSI_VC_SOURCE_L4:
  2216. return dsi_sync_vc_l4(dsidev, channel);
  2217. default:
  2218. BUG();
  2219. return -EINVAL;
  2220. }
  2221. }
  2222. static int dsi_vc_enable(struct platform_device *dsidev, int channel,
  2223. bool enable)
  2224. {
  2225. DSSDBG("dsi_vc_enable channel %d, enable %d\n",
  2226. channel, enable);
  2227. enable = enable ? 1 : 0;
  2228. REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
  2229. if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
  2230. 0, enable) != enable) {
  2231. DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
  2232. return -EIO;
  2233. }
  2234. return 0;
  2235. }
  2236. static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
  2237. {
  2238. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2239. u32 r;
  2240. DSSDBG("Initial config of virtual channel %d", channel);
  2241. r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
  2242. if (FLD_GET(r, 15, 15)) /* VC_BUSY */
  2243. DSSERR("VC(%d) busy when trying to configure it!\n",
  2244. channel);
  2245. r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
  2246. r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
  2247. r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
  2248. r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
  2249. r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
  2250. r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
  2251. r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
  2252. if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
  2253. r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
  2254. r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
  2255. r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
  2256. dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
  2257. dsi->vc[channel].source = DSI_VC_SOURCE_L4;
  2258. }
  2259. static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
  2260. enum dsi_vc_source source)
  2261. {
  2262. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2263. if (dsi->vc[channel].source == source)
  2264. return 0;
  2265. DSSDBG("Source config of virtual channel %d", channel);
  2266. dsi_sync_vc(dsidev, channel);
  2267. dsi_vc_enable(dsidev, channel, 0);
  2268. /* VC_BUSY */
  2269. if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
  2270. DSSERR("vc(%d) busy when trying to config for VP\n", channel);
  2271. return -EIO;
  2272. }
  2273. /* SOURCE, 0 = L4, 1 = video port */
  2274. REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
  2275. /* DCS_CMD_ENABLE */
  2276. if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
  2277. bool enable = source == DSI_VC_SOURCE_VP;
  2278. REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
  2279. }
  2280. dsi_vc_enable(dsidev, channel, 1);
  2281. dsi->vc[channel].source = source;
  2282. return 0;
  2283. }
  2284. void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
  2285. bool enable)
  2286. {
  2287. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2288. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2289. DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
  2290. WARN_ON(!dsi_bus_is_locked(dsidev));
  2291. dsi_vc_enable(dsidev, channel, 0);
  2292. dsi_if_enable(dsidev, 0);
  2293. REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
  2294. dsi_vc_enable(dsidev, channel, 1);
  2295. dsi_if_enable(dsidev, 1);
  2296. dsi_force_tx_stop_mode_io(dsidev);
  2297. /* start the DDR clock by sending a NULL packet */
  2298. if (dsi->vm_timings.ddr_clk_always_on && enable)
  2299. dsi_vc_send_null(dssdev, channel);
  2300. }
  2301. EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
  2302. static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
  2303. {
  2304. while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
  2305. u32 val;
  2306. val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
  2307. DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
  2308. (val >> 0) & 0xff,
  2309. (val >> 8) & 0xff,
  2310. (val >> 16) & 0xff,
  2311. (val >> 24) & 0xff);
  2312. }
  2313. }
  2314. static void dsi_show_rx_ack_with_err(u16 err)
  2315. {
  2316. DSSERR("\tACK with ERROR (%#x):\n", err);
  2317. if (err & (1 << 0))
  2318. DSSERR("\t\tSoT Error\n");
  2319. if (err & (1 << 1))
  2320. DSSERR("\t\tSoT Sync Error\n");
  2321. if (err & (1 << 2))
  2322. DSSERR("\t\tEoT Sync Error\n");
  2323. if (err & (1 << 3))
  2324. DSSERR("\t\tEscape Mode Entry Command Error\n");
  2325. if (err & (1 << 4))
  2326. DSSERR("\t\tLP Transmit Sync Error\n");
  2327. if (err & (1 << 5))
  2328. DSSERR("\t\tHS Receive Timeout Error\n");
  2329. if (err & (1 << 6))
  2330. DSSERR("\t\tFalse Control Error\n");
  2331. if (err & (1 << 7))
  2332. DSSERR("\t\t(reserved7)\n");
  2333. if (err & (1 << 8))
  2334. DSSERR("\t\tECC Error, single-bit (corrected)\n");
  2335. if (err & (1 << 9))
  2336. DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
  2337. if (err & (1 << 10))
  2338. DSSERR("\t\tChecksum Error\n");
  2339. if (err & (1 << 11))
  2340. DSSERR("\t\tData type not recognized\n");
  2341. if (err & (1 << 12))
  2342. DSSERR("\t\tInvalid VC ID\n");
  2343. if (err & (1 << 13))
  2344. DSSERR("\t\tInvalid Transmission Length\n");
  2345. if (err & (1 << 14))
  2346. DSSERR("\t\t(reserved14)\n");
  2347. if (err & (1 << 15))
  2348. DSSERR("\t\tDSI Protocol Violation\n");
  2349. }
  2350. static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
  2351. int channel)
  2352. {
  2353. /* RX_FIFO_NOT_EMPTY */
  2354. while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
  2355. u32 val;
  2356. u8 dt;
  2357. val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
  2358. DSSERR("\trawval %#08x\n", val);
  2359. dt = FLD_GET(val, 5, 0);
  2360. if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
  2361. u16 err = FLD_GET(val, 23, 8);
  2362. dsi_show_rx_ack_with_err(err);
  2363. } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
  2364. DSSERR("\tDCS short response, 1 byte: %#x\n",
  2365. FLD_GET(val, 23, 8));
  2366. } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
  2367. DSSERR("\tDCS short response, 2 byte: %#x\n",
  2368. FLD_GET(val, 23, 8));
  2369. } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
  2370. DSSERR("\tDCS long response, len %d\n",
  2371. FLD_GET(val, 23, 8));
  2372. dsi_vc_flush_long_data(dsidev, channel);
  2373. } else {
  2374. DSSERR("\tunknown datatype 0x%02x\n", dt);
  2375. }
  2376. }
  2377. return 0;
  2378. }
  2379. static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
  2380. {
  2381. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2382. if (dsi->debug_write || dsi->debug_read)
  2383. DSSDBG("dsi_vc_send_bta %d\n", channel);
  2384. WARN_ON(!dsi_bus_is_locked(dsidev));
  2385. /* RX_FIFO_NOT_EMPTY */
  2386. if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
  2387. DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
  2388. dsi_vc_flush_receive_data(dsidev, channel);
  2389. }
  2390. REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
  2391. /* flush posted write */
  2392. dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
  2393. return 0;
  2394. }
  2395. int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
  2396. {
  2397. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2398. DECLARE_COMPLETION_ONSTACK(completion);
  2399. int r = 0;
  2400. u32 err;
  2401. r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
  2402. &completion, DSI_VC_IRQ_BTA);
  2403. if (r)
  2404. goto err0;
  2405. r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
  2406. DSI_IRQ_ERROR_MASK);
  2407. if (r)
  2408. goto err1;
  2409. r = dsi_vc_send_bta(dsidev, channel);
  2410. if (r)
  2411. goto err2;
  2412. if (wait_for_completion_timeout(&completion,
  2413. msecs_to_jiffies(500)) == 0) {
  2414. DSSERR("Failed to receive BTA\n");
  2415. r = -EIO;
  2416. goto err2;
  2417. }
  2418. err = dsi_get_errors(dsidev);
  2419. if (err) {
  2420. DSSERR("Error while sending BTA: %x\n", err);
  2421. r = -EIO;
  2422. goto err2;
  2423. }
  2424. err2:
  2425. dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
  2426. DSI_IRQ_ERROR_MASK);
  2427. err1:
  2428. dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
  2429. &completion, DSI_VC_IRQ_BTA);
  2430. err0:
  2431. return r;
  2432. }
  2433. EXPORT_SYMBOL(dsi_vc_send_bta_sync);
  2434. static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
  2435. int channel, u8 data_type, u16 len, u8 ecc)
  2436. {
  2437. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2438. u32 val;
  2439. u8 data_id;
  2440. WARN_ON(!dsi_bus_is_locked(dsidev));
  2441. data_id = data_type | dsi->vc[channel].vc_id << 6;
  2442. val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
  2443. FLD_VAL(ecc, 31, 24);
  2444. dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
  2445. }
  2446. static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
  2447. int channel, u8 b1, u8 b2, u8 b3, u8 b4)
  2448. {
  2449. u32 val;
  2450. val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
  2451. /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
  2452. b1, b2, b3, b4, val); */
  2453. dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
  2454. }
  2455. static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
  2456. u8 data_type, u8 *data, u16 len, u8 ecc)
  2457. {
  2458. /*u32 val; */
  2459. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2460. int i;
  2461. u8 *p;
  2462. int r = 0;
  2463. u8 b1, b2, b3, b4;
  2464. if (dsi->debug_write)
  2465. DSSDBG("dsi_vc_send_long, %d bytes\n", len);
  2466. /* len + header */
  2467. if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
  2468. DSSERR("unable to send long packet: packet too long.\n");
  2469. return -EINVAL;
  2470. }
  2471. dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
  2472. dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
  2473. p = data;
  2474. for (i = 0; i < len >> 2; i++) {
  2475. if (dsi->debug_write)
  2476. DSSDBG("\tsending full packet %d\n", i);
  2477. b1 = *p++;
  2478. b2 = *p++;
  2479. b3 = *p++;
  2480. b4 = *p++;
  2481. dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
  2482. }
  2483. i = len % 4;
  2484. if (i) {
  2485. b1 = 0; b2 = 0; b3 = 0;
  2486. if (dsi->debug_write)
  2487. DSSDBG("\tsending remainder bytes %d\n", i);
  2488. switch (i) {
  2489. case 3:
  2490. b1 = *p++;
  2491. b2 = *p++;
  2492. b3 = *p++;
  2493. break;
  2494. case 2:
  2495. b1 = *p++;
  2496. b2 = *p++;
  2497. break;
  2498. case 1:
  2499. b1 = *p++;
  2500. break;
  2501. }
  2502. dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
  2503. }
  2504. return r;
  2505. }
  2506. static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
  2507. u8 data_type, u16 data, u8 ecc)
  2508. {
  2509. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2510. u32 r;
  2511. u8 data_id;
  2512. WARN_ON(!dsi_bus_is_locked(dsidev));
  2513. if (dsi->debug_write)
  2514. DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
  2515. channel,
  2516. data_type, data & 0xff, (data >> 8) & 0xff);
  2517. dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
  2518. if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
  2519. DSSERR("ERROR FIFO FULL, aborting transfer\n");
  2520. return -EINVAL;
  2521. }
  2522. data_id = data_type | dsi->vc[channel].vc_id << 6;
  2523. r = (data_id << 0) | (data << 8) | (ecc << 24);
  2524. dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
  2525. return 0;
  2526. }
  2527. int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
  2528. {
  2529. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2530. return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
  2531. 0, 0);
  2532. }
  2533. EXPORT_SYMBOL(dsi_vc_send_null);
  2534. static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
  2535. int channel, u8 *data, int len, enum dss_dsi_content_type type)
  2536. {
  2537. int r;
  2538. if (len == 0) {
  2539. BUG_ON(type == DSS_DSI_CONTENT_DCS);
  2540. r = dsi_vc_send_short(dsidev, channel,
  2541. MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
  2542. } else if (len == 1) {
  2543. r = dsi_vc_send_short(dsidev, channel,
  2544. type == DSS_DSI_CONTENT_GENERIC ?
  2545. MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
  2546. MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
  2547. } else if (len == 2) {
  2548. r = dsi_vc_send_short(dsidev, channel,
  2549. type == DSS_DSI_CONTENT_GENERIC ?
  2550. MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
  2551. MIPI_DSI_DCS_SHORT_WRITE_PARAM,
  2552. data[0] | (data[1] << 8), 0);
  2553. } else {
  2554. r = dsi_vc_send_long(dsidev, channel,
  2555. type == DSS_DSI_CONTENT_GENERIC ?
  2556. MIPI_DSI_GENERIC_LONG_WRITE :
  2557. MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
  2558. }
  2559. return r;
  2560. }
  2561. int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
  2562. u8 *data, int len)
  2563. {
  2564. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2565. return dsi_vc_write_nosync_common(dsidev, channel, data, len,
  2566. DSS_DSI_CONTENT_DCS);
  2567. }
  2568. EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
  2569. int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
  2570. u8 *data, int len)
  2571. {
  2572. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2573. return dsi_vc_write_nosync_common(dsidev, channel, data, len,
  2574. DSS_DSI_CONTENT_GENERIC);
  2575. }
  2576. EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
  2577. static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
  2578. u8 *data, int len, enum dss_dsi_content_type type)
  2579. {
  2580. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2581. int r;
  2582. r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
  2583. if (r)
  2584. goto err;
  2585. r = dsi_vc_send_bta_sync(dssdev, channel);
  2586. if (r)
  2587. goto err;
  2588. /* RX_FIFO_NOT_EMPTY */
  2589. if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
  2590. DSSERR("rx fifo not empty after write, dumping data:\n");
  2591. dsi_vc_flush_receive_data(dsidev, channel);
  2592. r = -EIO;
  2593. goto err;
  2594. }
  2595. return 0;
  2596. err:
  2597. DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
  2598. channel, data[0], len);
  2599. return r;
  2600. }
  2601. int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
  2602. int len)
  2603. {
  2604. return dsi_vc_write_common(dssdev, channel, data, len,
  2605. DSS_DSI_CONTENT_DCS);
  2606. }
  2607. EXPORT_SYMBOL(dsi_vc_dcs_write);
  2608. int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
  2609. int len)
  2610. {
  2611. return dsi_vc_write_common(dssdev, channel, data, len,
  2612. DSS_DSI_CONTENT_GENERIC);
  2613. }
  2614. EXPORT_SYMBOL(dsi_vc_generic_write);
  2615. int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
  2616. {
  2617. return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
  2618. }
  2619. EXPORT_SYMBOL(dsi_vc_dcs_write_0);
  2620. int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
  2621. {
  2622. return dsi_vc_generic_write(dssdev, channel, NULL, 0);
  2623. }
  2624. EXPORT_SYMBOL(dsi_vc_generic_write_0);
  2625. int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
  2626. u8 param)
  2627. {
  2628. u8 buf[2];
  2629. buf[0] = dcs_cmd;
  2630. buf[1] = param;
  2631. return dsi_vc_dcs_write(dssdev, channel, buf, 2);
  2632. }
  2633. EXPORT_SYMBOL(dsi_vc_dcs_write_1);
  2634. int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
  2635. u8 param)
  2636. {
  2637. return dsi_vc_generic_write(dssdev, channel, &param, 1);
  2638. }
  2639. EXPORT_SYMBOL(dsi_vc_generic_write_1);
  2640. int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
  2641. u8 param1, u8 param2)
  2642. {
  2643. u8 buf[2];
  2644. buf[0] = param1;
  2645. buf[1] = param2;
  2646. return dsi_vc_generic_write(dssdev, channel, buf, 2);
  2647. }
  2648. EXPORT_SYMBOL(dsi_vc_generic_write_2);
  2649. static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
  2650. int channel, u8 dcs_cmd)
  2651. {
  2652. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2653. int r;
  2654. if (dsi->debug_read)
  2655. DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
  2656. channel, dcs_cmd);
  2657. r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
  2658. if (r) {
  2659. DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
  2660. " failed\n", channel, dcs_cmd);
  2661. return r;
  2662. }
  2663. return 0;
  2664. }
  2665. static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
  2666. int channel, u8 *reqdata, int reqlen)
  2667. {
  2668. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2669. u16 data;
  2670. u8 data_type;
  2671. int r;
  2672. if (dsi->debug_read)
  2673. DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
  2674. channel, reqlen);
  2675. if (reqlen == 0) {
  2676. data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
  2677. data = 0;
  2678. } else if (reqlen == 1) {
  2679. data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
  2680. data = reqdata[0];
  2681. } else if (reqlen == 2) {
  2682. data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
  2683. data = reqdata[0] | (reqdata[1] << 8);
  2684. } else {
  2685. BUG();
  2686. return -EINVAL;
  2687. }
  2688. r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
  2689. if (r) {
  2690. DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
  2691. " failed\n", channel, reqlen);
  2692. return r;
  2693. }
  2694. return 0;
  2695. }
  2696. static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
  2697. u8 *buf, int buflen, enum dss_dsi_content_type type)
  2698. {
  2699. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2700. u32 val;
  2701. u8 dt;
  2702. int r;
  2703. /* RX_FIFO_NOT_EMPTY */
  2704. if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
  2705. DSSERR("RX fifo empty when trying to read.\n");
  2706. r = -EIO;
  2707. goto err;
  2708. }
  2709. val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
  2710. if (dsi->debug_read)
  2711. DSSDBG("\theader: %08x\n", val);
  2712. dt = FLD_GET(val, 5, 0);
  2713. if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
  2714. u16 err = FLD_GET(val, 23, 8);
  2715. dsi_show_rx_ack_with_err(err);
  2716. r = -EIO;
  2717. goto err;
  2718. } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
  2719. MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
  2720. MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
  2721. u8 data = FLD_GET(val, 15, 8);
  2722. if (dsi->debug_read)
  2723. DSSDBG("\t%s short response, 1 byte: %02x\n",
  2724. type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
  2725. "DCS", data);
  2726. if (buflen < 1) {
  2727. r = -EIO;
  2728. goto err;
  2729. }
  2730. buf[0] = data;
  2731. return 1;
  2732. } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
  2733. MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
  2734. MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
  2735. u16 data = FLD_GET(val, 23, 8);
  2736. if (dsi->debug_read)
  2737. DSSDBG("\t%s short response, 2 byte: %04x\n",
  2738. type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
  2739. "DCS", data);
  2740. if (buflen < 2) {
  2741. r = -EIO;
  2742. goto err;
  2743. }
  2744. buf[0] = data & 0xff;
  2745. buf[1] = (data >> 8) & 0xff;
  2746. return 2;
  2747. } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
  2748. MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
  2749. MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
  2750. int w;
  2751. int len = FLD_GET(val, 23, 8);
  2752. if (dsi->debug_read)
  2753. DSSDBG("\t%s long response, len %d\n",
  2754. type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
  2755. "DCS", len);
  2756. if (len > buflen) {
  2757. r = -EIO;
  2758. goto err;
  2759. }
  2760. /* two byte checksum ends the packet, not included in len */
  2761. for (w = 0; w < len + 2;) {
  2762. int b;
  2763. val = dsi_read_reg(dsidev,
  2764. DSI_VC_SHORT_PACKET_HEADER(channel));
  2765. if (dsi->debug_read)
  2766. DSSDBG("\t\t%02x %02x %02x %02x\n",
  2767. (val >> 0) & 0xff,
  2768. (val >> 8) & 0xff,
  2769. (val >> 16) & 0xff,
  2770. (val >> 24) & 0xff);
  2771. for (b = 0; b < 4; ++b) {
  2772. if (w < len)
  2773. buf[w] = (val >> (b * 8)) & 0xff;
  2774. /* we discard the 2 byte checksum */
  2775. ++w;
  2776. }
  2777. }
  2778. return len;
  2779. } else {
  2780. DSSERR("\tunknown datatype 0x%02x\n", dt);
  2781. r = -EIO;
  2782. goto err;
  2783. }
  2784. err:
  2785. DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
  2786. type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
  2787. return r;
  2788. }
  2789. int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
  2790. u8 *buf, int buflen)
  2791. {
  2792. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2793. int r;
  2794. r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
  2795. if (r)
  2796. goto err;
  2797. r = dsi_vc_send_bta_sync(dssdev, channel);
  2798. if (r)
  2799. goto err;
  2800. r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
  2801. DSS_DSI_CONTENT_DCS);
  2802. if (r < 0)
  2803. goto err;
  2804. if (r != buflen) {
  2805. r = -EIO;
  2806. goto err;
  2807. }
  2808. return 0;
  2809. err:
  2810. DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
  2811. return r;
  2812. }
  2813. EXPORT_SYMBOL(dsi_vc_dcs_read);
  2814. static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
  2815. u8 *reqdata, int reqlen, u8 *buf, int buflen)
  2816. {
  2817. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2818. int r;
  2819. r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
  2820. if (r)
  2821. return r;
  2822. r = dsi_vc_send_bta_sync(dssdev, channel);
  2823. if (r)
  2824. return r;
  2825. r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
  2826. DSS_DSI_CONTENT_GENERIC);
  2827. if (r < 0)
  2828. return r;
  2829. if (r != buflen) {
  2830. r = -EIO;
  2831. return r;
  2832. }
  2833. return 0;
  2834. }
  2835. int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
  2836. int buflen)
  2837. {
  2838. int r;
  2839. r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
  2840. if (r) {
  2841. DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
  2842. return r;
  2843. }
  2844. return 0;
  2845. }
  2846. EXPORT_SYMBOL(dsi_vc_generic_read_0);
  2847. int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
  2848. u8 *buf, int buflen)
  2849. {
  2850. int r;
  2851. r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
  2852. if (r) {
  2853. DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
  2854. return r;
  2855. }
  2856. return 0;
  2857. }
  2858. EXPORT_SYMBOL(dsi_vc_generic_read_1);
  2859. int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
  2860. u8 param1, u8 param2, u8 *buf, int buflen)
  2861. {
  2862. int r;
  2863. u8 reqdata[2];
  2864. reqdata[0] = param1;
  2865. reqdata[1] = param2;
  2866. r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
  2867. if (r) {
  2868. DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
  2869. return r;
  2870. }
  2871. return 0;
  2872. }
  2873. EXPORT_SYMBOL(dsi_vc_generic_read_2);
  2874. int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
  2875. u16 len)
  2876. {
  2877. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  2878. return dsi_vc_send_short(dsidev, channel,
  2879. MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
  2880. }
  2881. EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
  2882. static int dsi_enter_ulps(struct platform_device *dsidev)
  2883. {
  2884. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  2885. DECLARE_COMPLETION_ONSTACK(completion);
  2886. int r, i;
  2887. unsigned mask;
  2888. DSSDBG("Entering ULPS");
  2889. WARN_ON(!dsi_bus_is_locked(dsidev));
  2890. WARN_ON(dsi->ulps_enabled);
  2891. if (dsi->ulps_enabled)
  2892. return 0;
  2893. /* DDR_CLK_ALWAYS_ON */
  2894. if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
  2895. dsi_if_enable(dsidev, 0);
  2896. REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
  2897. dsi_if_enable(dsidev, 1);
  2898. }
  2899. dsi_sync_vc(dsidev, 0);
  2900. dsi_sync_vc(dsidev, 1);
  2901. dsi_sync_vc(dsidev, 2);
  2902. dsi_sync_vc(dsidev, 3);
  2903. dsi_force_tx_stop_mode_io(dsidev);
  2904. dsi_vc_enable(dsidev, 0, false);
  2905. dsi_vc_enable(dsidev, 1, false);
  2906. dsi_vc_enable(dsidev, 2, false);
  2907. dsi_vc_enable(dsidev, 3, false);
  2908. if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
  2909. DSSERR("HS busy when enabling ULPS\n");
  2910. return -EIO;
  2911. }
  2912. if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
  2913. DSSERR("LP busy when enabling ULPS\n");
  2914. return -EIO;
  2915. }
  2916. r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
  2917. DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
  2918. if (r)
  2919. return r;
  2920. mask = 0;
  2921. for (i = 0; i < dsi->num_lanes_supported; ++i) {
  2922. if (dsi->lanes[i].function == DSI_LANE_UNUSED)
  2923. continue;
  2924. mask |= 1 << i;
  2925. }
  2926. /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
  2927. /* LANEx_ULPS_SIG2 */
  2928. REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
  2929. /* flush posted write and wait for SCP interface to finish the write */
  2930. dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
  2931. if (wait_for_completion_timeout(&completion,
  2932. msecs_to_jiffies(1000)) == 0) {
  2933. DSSERR("ULPS enable timeout\n");
  2934. r = -EIO;
  2935. goto err;
  2936. }
  2937. dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
  2938. DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
  2939. /* Reset LANEx_ULPS_SIG2 */
  2940. REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
  2941. /* flush posted write and wait for SCP interface to finish the write */
  2942. dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
  2943. dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
  2944. dsi_if_enable(dsidev, false);
  2945. dsi->ulps_enabled = true;
  2946. return 0;
  2947. err:
  2948. dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
  2949. DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
  2950. return r;
  2951. }
  2952. static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
  2953. unsigned ticks, bool x4, bool x16)
  2954. {
  2955. unsigned long fck;
  2956. unsigned long total_ticks;
  2957. u32 r;
  2958. BUG_ON(ticks > 0x1fff);
  2959. /* ticks in DSI_FCK */
  2960. fck = dsi_fclk_rate(dsidev);
  2961. r = dsi_read_reg(dsidev, DSI_TIMING2);
  2962. r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
  2963. r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
  2964. r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
  2965. r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
  2966. dsi_write_reg(dsidev, DSI_TIMING2, r);
  2967. total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
  2968. DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
  2969. total_ticks,
  2970. ticks, x4 ? " x4" : "", x16 ? " x16" : "",
  2971. (total_ticks * 1000) / (fck / 1000 / 1000));
  2972. }
  2973. static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
  2974. bool x8, bool x16)
  2975. {
  2976. unsigned long fck;
  2977. unsigned long total_ticks;
  2978. u32 r;
  2979. BUG_ON(ticks > 0x1fff);
  2980. /* ticks in DSI_FCK */
  2981. fck = dsi_fclk_rate(dsidev);
  2982. r = dsi_read_reg(dsidev, DSI_TIMING1);
  2983. r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
  2984. r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
  2985. r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
  2986. r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
  2987. dsi_write_reg(dsidev, DSI_TIMING1, r);
  2988. total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
  2989. DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
  2990. total_ticks,
  2991. ticks, x8 ? " x8" : "", x16 ? " x16" : "",
  2992. (total_ticks * 1000) / (fck / 1000 / 1000));
  2993. }
  2994. static void dsi_set_stop_state_counter(struct platform_device *dsidev,
  2995. unsigned ticks, bool x4, bool x16)
  2996. {
  2997. unsigned long fck;
  2998. unsigned long total_ticks;
  2999. u32 r;
  3000. BUG_ON(ticks > 0x1fff);
  3001. /* ticks in DSI_FCK */
  3002. fck = dsi_fclk_rate(dsidev);
  3003. r = dsi_read_reg(dsidev, DSI_TIMING1);
  3004. r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
  3005. r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
  3006. r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
  3007. r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
  3008. dsi_write_reg(dsidev, DSI_TIMING1, r);
  3009. total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
  3010. DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
  3011. total_ticks,
  3012. ticks, x4 ? " x4" : "", x16 ? " x16" : "",
  3013. (total_ticks * 1000) / (fck / 1000 / 1000));
  3014. }
  3015. static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
  3016. unsigned ticks, bool x4, bool x16)
  3017. {
  3018. unsigned long fck;
  3019. unsigned long total_ticks;
  3020. u32 r;
  3021. BUG_ON(ticks > 0x1fff);
  3022. /* ticks in TxByteClkHS */
  3023. fck = dsi_get_txbyteclkhs(dsidev);
  3024. r = dsi_read_reg(dsidev, DSI_TIMING2);
  3025. r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
  3026. r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
  3027. r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
  3028. r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
  3029. dsi_write_reg(dsidev, DSI_TIMING2, r);
  3030. total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
  3031. DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
  3032. total_ticks,
  3033. ticks, x4 ? " x4" : "", x16 ? " x16" : "",
  3034. (total_ticks * 1000) / (fck / 1000 / 1000));
  3035. }
  3036. static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
  3037. {
  3038. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3039. int num_line_buffers;
  3040. if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
  3041. int bpp = dsi_get_pixel_size(dsi->pix_fmt);
  3042. struct omap_video_timings *timings = &dsi->timings;
  3043. /*
  3044. * Don't use line buffers if width is greater than the video
  3045. * port's line buffer size
  3046. */
  3047. if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
  3048. num_line_buffers = 0;
  3049. else
  3050. num_line_buffers = 2;
  3051. } else {
  3052. /* Use maximum number of line buffers in command mode */
  3053. num_line_buffers = 2;
  3054. }
  3055. /* LINE_BUFFER */
  3056. REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
  3057. }
  3058. static void dsi_config_vp_sync_events(struct platform_device *dsidev)
  3059. {
  3060. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3061. bool vsync_end = dsi->vm_timings.vp_vsync_end;
  3062. bool hsync_end = dsi->vm_timings.vp_hsync_end;
  3063. u32 r;
  3064. r = dsi_read_reg(dsidev, DSI_CTRL);
  3065. r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
  3066. r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
  3067. r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
  3068. r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
  3069. r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
  3070. r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
  3071. r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
  3072. dsi_write_reg(dsidev, DSI_CTRL, r);
  3073. }
  3074. static void dsi_config_blanking_modes(struct platform_device *dsidev)
  3075. {
  3076. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3077. int blanking_mode = dsi->vm_timings.blanking_mode;
  3078. int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
  3079. int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
  3080. int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
  3081. u32 r;
  3082. /*
  3083. * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
  3084. * 1 = Long blanking packets are sent in corresponding blanking periods
  3085. */
  3086. r = dsi_read_reg(dsidev, DSI_CTRL);
  3087. r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
  3088. r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
  3089. r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
  3090. r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
  3091. dsi_write_reg(dsidev, DSI_CTRL, r);
  3092. }
  3093. /*
  3094. * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
  3095. * results in maximum transition time for data and clock lanes to enter and
  3096. * exit HS mode. Hence, this is the scenario where the least amount of command
  3097. * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
  3098. * clock cycles that can be used to interleave command mode data in HS so that
  3099. * all scenarios are satisfied.
  3100. */
  3101. static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
  3102. int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
  3103. {
  3104. int transition;
  3105. /*
  3106. * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
  3107. * time of data lanes only, if it isn't set, we need to consider HS
  3108. * transition time of both data and clock lanes. HS transition time
  3109. * of Scenario 3 is considered.
  3110. */
  3111. if (ddr_alwon) {
  3112. transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
  3113. } else {
  3114. int trans1, trans2;
  3115. trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
  3116. trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
  3117. enter_hs + 1;
  3118. transition = max(trans1, trans2);
  3119. }
  3120. return blank > transition ? blank - transition : 0;
  3121. }
  3122. /*
  3123. * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
  3124. * results in maximum transition time for data lanes to enter and exit LP mode.
  3125. * Hence, this is the scenario where the least amount of command mode data can
  3126. * be interleaved. We program the minimum amount of bytes that can be
  3127. * interleaved in LP so that all scenarios are satisfied.
  3128. */
  3129. static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
  3130. int lp_clk_div, int tdsi_fclk)
  3131. {
  3132. int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
  3133. int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
  3134. int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
  3135. int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
  3136. int lp_inter; /* cmd mode data that can be interleaved, in bytes */
  3137. /* maximum LP transition time according to Scenario 1 */
  3138. trans_lp = exit_hs + max(enter_hs, 2) + 1;
  3139. /* CLKIN4DDR = 16 * TXBYTECLKHS */
  3140. tlp_avail = thsbyte_clk * (blank - trans_lp);
  3141. ttxclkesc = tdsi_fclk * lp_clk_div;
  3142. lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
  3143. 26) / 16;
  3144. return max(lp_inter, 0);
  3145. }
  3146. static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
  3147. {
  3148. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3149. int blanking_mode;
  3150. int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
  3151. int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
  3152. int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
  3153. int tclk_trail, ths_exit, exiths_clk;
  3154. bool ddr_alwon;
  3155. struct omap_video_timings *timings = &dsi->timings;
  3156. int bpp = dsi_get_pixel_size(dsi->pix_fmt);
  3157. int ndl = dsi->num_lanes_used - 1;
  3158. int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1;
  3159. int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
  3160. int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
  3161. int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
  3162. int bl_interleave_hs = 0, bl_interleave_lp = 0;
  3163. u32 r;
  3164. r = dsi_read_reg(dsidev, DSI_CTRL);
  3165. blanking_mode = FLD_GET(r, 20, 20);
  3166. hfp_blanking_mode = FLD_GET(r, 21, 21);
  3167. hbp_blanking_mode = FLD_GET(r, 22, 22);
  3168. hsa_blanking_mode = FLD_GET(r, 23, 23);
  3169. r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
  3170. hbp = FLD_GET(r, 11, 0);
  3171. hfp = FLD_GET(r, 23, 12);
  3172. hsa = FLD_GET(r, 31, 24);
  3173. r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
  3174. ddr_clk_post = FLD_GET(r, 7, 0);
  3175. ddr_clk_pre = FLD_GET(r, 15, 8);
  3176. r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
  3177. exit_hs_mode_lat = FLD_GET(r, 15, 0);
  3178. enter_hs_mode_lat = FLD_GET(r, 31, 16);
  3179. r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
  3180. lp_clk_div = FLD_GET(r, 12, 0);
  3181. ddr_alwon = FLD_GET(r, 13, 13);
  3182. r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
  3183. ths_exit = FLD_GET(r, 7, 0);
  3184. r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
  3185. tclk_trail = FLD_GET(r, 15, 8);
  3186. exiths_clk = ths_exit + tclk_trail;
  3187. width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
  3188. bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
  3189. if (!hsa_blanking_mode) {
  3190. hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
  3191. enter_hs_mode_lat, exit_hs_mode_lat,
  3192. exiths_clk, ddr_clk_pre, ddr_clk_post);
  3193. hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
  3194. enter_hs_mode_lat, exit_hs_mode_lat,
  3195. lp_clk_div, dsi_fclk_hsdiv);
  3196. }
  3197. if (!hfp_blanking_mode) {
  3198. hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
  3199. enter_hs_mode_lat, exit_hs_mode_lat,
  3200. exiths_clk, ddr_clk_pre, ddr_clk_post);
  3201. hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
  3202. enter_hs_mode_lat, exit_hs_mode_lat,
  3203. lp_clk_div, dsi_fclk_hsdiv);
  3204. }
  3205. if (!hbp_blanking_mode) {
  3206. hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
  3207. enter_hs_mode_lat, exit_hs_mode_lat,
  3208. exiths_clk, ddr_clk_pre, ddr_clk_post);
  3209. hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
  3210. enter_hs_mode_lat, exit_hs_mode_lat,
  3211. lp_clk_div, dsi_fclk_hsdiv);
  3212. }
  3213. if (!blanking_mode) {
  3214. bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
  3215. enter_hs_mode_lat, exit_hs_mode_lat,
  3216. exiths_clk, ddr_clk_pre, ddr_clk_post);
  3217. bl_interleave_lp = dsi_compute_interleave_lp(bllp,
  3218. enter_hs_mode_lat, exit_hs_mode_lat,
  3219. lp_clk_div, dsi_fclk_hsdiv);
  3220. }
  3221. DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
  3222. hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
  3223. bl_interleave_hs);
  3224. DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
  3225. hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
  3226. bl_interleave_lp);
  3227. r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
  3228. r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
  3229. r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
  3230. r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
  3231. dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
  3232. r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
  3233. r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
  3234. r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
  3235. r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
  3236. dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
  3237. r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
  3238. r = FLD_MOD(r, bl_interleave_hs, 31, 15);
  3239. r = FLD_MOD(r, bl_interleave_lp, 16, 0);
  3240. dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
  3241. }
  3242. static int dsi_proto_config(struct platform_device *dsidev)
  3243. {
  3244. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3245. u32 r;
  3246. int buswidth = 0;
  3247. dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
  3248. DSI_FIFO_SIZE_32,
  3249. DSI_FIFO_SIZE_32,
  3250. DSI_FIFO_SIZE_32);
  3251. dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
  3252. DSI_FIFO_SIZE_32,
  3253. DSI_FIFO_SIZE_32,
  3254. DSI_FIFO_SIZE_32);
  3255. /* XXX what values for the timeouts? */
  3256. dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
  3257. dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
  3258. dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
  3259. dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
  3260. switch (dsi_get_pixel_size(dsi->pix_fmt)) {
  3261. case 16:
  3262. buswidth = 0;
  3263. break;
  3264. case 18:
  3265. buswidth = 1;
  3266. break;
  3267. case 24:
  3268. buswidth = 2;
  3269. break;
  3270. default:
  3271. BUG();
  3272. return -EINVAL;
  3273. }
  3274. r = dsi_read_reg(dsidev, DSI_CTRL);
  3275. r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
  3276. r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
  3277. r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
  3278. r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
  3279. r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
  3280. r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
  3281. r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
  3282. r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
  3283. if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
  3284. r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
  3285. /* DCS_CMD_CODE, 1=start, 0=continue */
  3286. r = FLD_MOD(r, 0, 25, 25);
  3287. }
  3288. dsi_write_reg(dsidev, DSI_CTRL, r);
  3289. dsi_config_vp_num_line_buffers(dsidev);
  3290. if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
  3291. dsi_config_vp_sync_events(dsidev);
  3292. dsi_config_blanking_modes(dsidev);
  3293. dsi_config_cmd_mode_interleaving(dsidev);
  3294. }
  3295. dsi_vc_initial_config(dsidev, 0);
  3296. dsi_vc_initial_config(dsidev, 1);
  3297. dsi_vc_initial_config(dsidev, 2);
  3298. dsi_vc_initial_config(dsidev, 3);
  3299. return 0;
  3300. }
  3301. static void dsi_proto_timings(struct platform_device *dsidev)
  3302. {
  3303. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3304. unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
  3305. unsigned tclk_pre, tclk_post;
  3306. unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
  3307. unsigned ths_trail, ths_exit;
  3308. unsigned ddr_clk_pre, ddr_clk_post;
  3309. unsigned enter_hs_mode_lat, exit_hs_mode_lat;
  3310. unsigned ths_eot;
  3311. int ndl = dsi->num_lanes_used - 1;
  3312. u32 r;
  3313. r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
  3314. ths_prepare = FLD_GET(r, 31, 24);
  3315. ths_prepare_ths_zero = FLD_GET(r, 23, 16);
  3316. ths_zero = ths_prepare_ths_zero - ths_prepare;
  3317. ths_trail = FLD_GET(r, 15, 8);
  3318. ths_exit = FLD_GET(r, 7, 0);
  3319. r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
  3320. tlpx = FLD_GET(r, 20, 16) * 2;
  3321. tclk_trail = FLD_GET(r, 15, 8);
  3322. tclk_zero = FLD_GET(r, 7, 0);
  3323. r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
  3324. tclk_prepare = FLD_GET(r, 7, 0);
  3325. /* min 8*UI */
  3326. tclk_pre = 20;
  3327. /* min 60ns + 52*UI */
  3328. tclk_post = ns2ddr(dsidev, 60) + 26;
  3329. ths_eot = DIV_ROUND_UP(4, ndl);
  3330. ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
  3331. 4);
  3332. ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
  3333. BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
  3334. BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
  3335. r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
  3336. r = FLD_MOD(r, ddr_clk_pre, 15, 8);
  3337. r = FLD_MOD(r, ddr_clk_post, 7, 0);
  3338. dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
  3339. DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
  3340. ddr_clk_pre,
  3341. ddr_clk_post);
  3342. enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
  3343. DIV_ROUND_UP(ths_prepare, 4) +
  3344. DIV_ROUND_UP(ths_zero + 3, 4);
  3345. exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
  3346. r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
  3347. FLD_VAL(exit_hs_mode_lat, 15, 0);
  3348. dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
  3349. DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
  3350. enter_hs_mode_lat, exit_hs_mode_lat);
  3351. if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
  3352. /* TODO: Implement a video mode check_timings function */
  3353. int hsa = dsi->vm_timings.hsa;
  3354. int hfp = dsi->vm_timings.hfp;
  3355. int hbp = dsi->vm_timings.hbp;
  3356. int vsa = dsi->vm_timings.vsa;
  3357. int vfp = dsi->vm_timings.vfp;
  3358. int vbp = dsi->vm_timings.vbp;
  3359. int window_sync = dsi->vm_timings.window_sync;
  3360. bool hsync_end = dsi->vm_timings.vp_hsync_end;
  3361. struct omap_video_timings *timings = &dsi->timings;
  3362. int bpp = dsi_get_pixel_size(dsi->pix_fmt);
  3363. int tl, t_he, width_bytes;
  3364. t_he = hsync_end ?
  3365. ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
  3366. width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
  3367. /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
  3368. tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
  3369. DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
  3370. DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
  3371. hfp, hsync_end ? hsa : 0, tl);
  3372. DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
  3373. vsa, timings->y_res);
  3374. r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
  3375. r = FLD_MOD(r, hbp, 11, 0); /* HBP */
  3376. r = FLD_MOD(r, hfp, 23, 12); /* HFP */
  3377. r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
  3378. dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
  3379. r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
  3380. r = FLD_MOD(r, vbp, 7, 0); /* VBP */
  3381. r = FLD_MOD(r, vfp, 15, 8); /* VFP */
  3382. r = FLD_MOD(r, vsa, 23, 16); /* VSA */
  3383. r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
  3384. dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
  3385. r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
  3386. r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
  3387. r = FLD_MOD(r, tl, 31, 16); /* TL */
  3388. dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
  3389. }
  3390. }
  3391. int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
  3392. const struct omap_dsi_pin_config *pin_cfg)
  3393. {
  3394. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3395. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3396. int num_pins;
  3397. const int *pins;
  3398. struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
  3399. int num_lanes;
  3400. int i;
  3401. static const enum dsi_lane_function functions[] = {
  3402. DSI_LANE_CLK,
  3403. DSI_LANE_DATA1,
  3404. DSI_LANE_DATA2,
  3405. DSI_LANE_DATA3,
  3406. DSI_LANE_DATA4,
  3407. };
  3408. num_pins = pin_cfg->num_pins;
  3409. pins = pin_cfg->pins;
  3410. if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
  3411. || num_pins % 2 != 0)
  3412. return -EINVAL;
  3413. for (i = 0; i < DSI_MAX_NR_LANES; ++i)
  3414. lanes[i].function = DSI_LANE_UNUSED;
  3415. num_lanes = 0;
  3416. for (i = 0; i < num_pins; i += 2) {
  3417. u8 lane, pol;
  3418. int dx, dy;
  3419. dx = pins[i];
  3420. dy = pins[i + 1];
  3421. if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
  3422. return -EINVAL;
  3423. if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
  3424. return -EINVAL;
  3425. if (dx & 1) {
  3426. if (dy != dx - 1)
  3427. return -EINVAL;
  3428. pol = 1;
  3429. } else {
  3430. if (dy != dx + 1)
  3431. return -EINVAL;
  3432. pol = 0;
  3433. }
  3434. lane = dx / 2;
  3435. lanes[lane].function = functions[i / 2];
  3436. lanes[lane].polarity = pol;
  3437. num_lanes++;
  3438. }
  3439. memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
  3440. dsi->num_lanes_used = num_lanes;
  3441. return 0;
  3442. }
  3443. EXPORT_SYMBOL(omapdss_dsi_configure_pins);
  3444. static int dsi_set_clocks(struct omap_dss_device *dssdev,
  3445. unsigned long ddr_clk, unsigned long lp_clk)
  3446. {
  3447. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3448. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3449. struct dsi_clock_info cinfo;
  3450. struct dispc_clock_info dispc_cinfo;
  3451. unsigned lp_clk_div;
  3452. unsigned long dsi_fclk;
  3453. int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
  3454. unsigned long pck;
  3455. int r;
  3456. DSSDBG("Setting DSI clocks: ddr_clk %lu, lp_clk %lu", ddr_clk, lp_clk);
  3457. /* Calculate PLL output clock */
  3458. r = dsi_pll_calc_ddrfreq(dsidev, ddr_clk * 4, &cinfo);
  3459. if (r)
  3460. goto err;
  3461. /* Calculate PLL's DSI clock */
  3462. dsi_pll_calc_dsi_fck(dsidev, &cinfo);
  3463. /* Calculate PLL's DISPC clock and pck & lck divs */
  3464. pck = cinfo.clkin4ddr / 16 * (dsi->num_lanes_used - 1) * 8 / bpp;
  3465. DSSDBG("finding dispc dividers for pck %lu\n", pck);
  3466. r = dsi_pll_calc_dispc_fck(dsidev, pck, &cinfo, &dispc_cinfo);
  3467. if (r)
  3468. goto err;
  3469. /* Calculate LP clock */
  3470. dsi_fclk = cinfo.dsi_pll_hsdiv_dsi_clk;
  3471. lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk * 2);
  3472. dsi->user_dsi_cinfo.regn = cinfo.regn;
  3473. dsi->user_dsi_cinfo.regm = cinfo.regm;
  3474. dsi->user_dsi_cinfo.regm_dispc = cinfo.regm_dispc;
  3475. dsi->user_dsi_cinfo.regm_dsi = cinfo.regm_dsi;
  3476. dsi->user_dsi_cinfo.lp_clk_div = lp_clk_div;
  3477. dsi->user_dispc_cinfo.lck_div = dispc_cinfo.lck_div;
  3478. dsi->user_dispc_cinfo.pck_div = dispc_cinfo.pck_div;
  3479. dsi->user_dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK;
  3480. dsi->user_lcd_clk_src =
  3481. dsi->module_id == 0 ?
  3482. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
  3483. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
  3484. dsi->user_dsi_fclk_src =
  3485. dsi->module_id == 0 ?
  3486. OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
  3487. OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI;
  3488. return 0;
  3489. err:
  3490. return r;
  3491. }
  3492. int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
  3493. {
  3494. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3495. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3496. struct omap_overlay_manager *mgr = dsi->output.manager;
  3497. int bpp = dsi_get_pixel_size(dsi->pix_fmt);
  3498. struct omap_dss_output *out = &dsi->output;
  3499. u8 data_type;
  3500. u16 word_count;
  3501. int r;
  3502. if (out == NULL || out->manager == NULL) {
  3503. DSSERR("failed to enable display: no output/manager\n");
  3504. return -ENODEV;
  3505. }
  3506. r = dsi_display_init_dispc(dsidev, mgr);
  3507. if (r)
  3508. goto err_init_dispc;
  3509. if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
  3510. switch (dsi->pix_fmt) {
  3511. case OMAP_DSS_DSI_FMT_RGB888:
  3512. data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
  3513. break;
  3514. case OMAP_DSS_DSI_FMT_RGB666:
  3515. data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
  3516. break;
  3517. case OMAP_DSS_DSI_FMT_RGB666_PACKED:
  3518. data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
  3519. break;
  3520. case OMAP_DSS_DSI_FMT_RGB565:
  3521. data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
  3522. break;
  3523. default:
  3524. r = -EINVAL;
  3525. goto err_pix_fmt;
  3526. };
  3527. dsi_if_enable(dsidev, false);
  3528. dsi_vc_enable(dsidev, channel, false);
  3529. /* MODE, 1 = video mode */
  3530. REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
  3531. word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
  3532. dsi_vc_write_long_header(dsidev, channel, data_type,
  3533. word_count, 0);
  3534. dsi_vc_enable(dsidev, channel, true);
  3535. dsi_if_enable(dsidev, true);
  3536. }
  3537. r = dss_mgr_enable(mgr);
  3538. if (r)
  3539. goto err_mgr_enable;
  3540. return 0;
  3541. err_mgr_enable:
  3542. if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
  3543. dsi_if_enable(dsidev, false);
  3544. dsi_vc_enable(dsidev, channel, false);
  3545. }
  3546. err_pix_fmt:
  3547. dsi_display_uninit_dispc(dsidev, mgr);
  3548. err_init_dispc:
  3549. return r;
  3550. }
  3551. EXPORT_SYMBOL(dsi_enable_video_output);
  3552. void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
  3553. {
  3554. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3555. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3556. struct omap_overlay_manager *mgr = dsi->output.manager;
  3557. if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
  3558. dsi_if_enable(dsidev, false);
  3559. dsi_vc_enable(dsidev, channel, false);
  3560. /* MODE, 0 = command mode */
  3561. REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
  3562. dsi_vc_enable(dsidev, channel, true);
  3563. dsi_if_enable(dsidev, true);
  3564. }
  3565. dss_mgr_disable(mgr);
  3566. dsi_display_uninit_dispc(dsidev, mgr);
  3567. }
  3568. EXPORT_SYMBOL(dsi_disable_video_output);
  3569. static void dsi_update_screen_dispc(struct platform_device *dsidev)
  3570. {
  3571. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3572. struct omap_overlay_manager *mgr = dsi->output.manager;
  3573. unsigned bytespp;
  3574. unsigned bytespl;
  3575. unsigned bytespf;
  3576. unsigned total_len;
  3577. unsigned packet_payload;
  3578. unsigned packet_len;
  3579. u32 l;
  3580. int r;
  3581. const unsigned channel = dsi->update_channel;
  3582. const unsigned line_buf_size = dsi->line_buffer_size;
  3583. u16 w = dsi->timings.x_res;
  3584. u16 h = dsi->timings.y_res;
  3585. DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
  3586. dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
  3587. bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
  3588. bytespl = w * bytespp;
  3589. bytespf = bytespl * h;
  3590. /* NOTE: packet_payload has to be equal to N * bytespl, where N is
  3591. * number of lines in a packet. See errata about VP_CLK_RATIO */
  3592. if (bytespf < line_buf_size)
  3593. packet_payload = bytespf;
  3594. else
  3595. packet_payload = (line_buf_size) / bytespl * bytespl;
  3596. packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
  3597. total_len = (bytespf / packet_payload) * packet_len;
  3598. if (bytespf % packet_payload)
  3599. total_len += (bytespf % packet_payload) + 1;
  3600. l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
  3601. dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
  3602. dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
  3603. packet_len, 0);
  3604. if (dsi->te_enabled)
  3605. l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
  3606. else
  3607. l = FLD_MOD(l, 1, 31, 31); /* TE_START */
  3608. dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
  3609. /* We put SIDLEMODE to no-idle for the duration of the transfer,
  3610. * because DSS interrupts are not capable of waking up the CPU and the
  3611. * framedone interrupt could be delayed for quite a long time. I think
  3612. * the same goes for any DSS interrupts, but for some reason I have not
  3613. * seen the problem anywhere else than here.
  3614. */
  3615. dispc_disable_sidle();
  3616. dsi_perf_mark_start(dsidev);
  3617. r = schedule_delayed_work(&dsi->framedone_timeout_work,
  3618. msecs_to_jiffies(250));
  3619. BUG_ON(r == 0);
  3620. dss_mgr_set_timings(mgr, &dsi->timings);
  3621. dss_mgr_start_update(mgr);
  3622. if (dsi->te_enabled) {
  3623. /* disable LP_RX_TO, so that we can receive TE. Time to wait
  3624. * for TE is longer than the timer allows */
  3625. REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
  3626. dsi_vc_send_bta(dsidev, channel);
  3627. #ifdef DSI_CATCH_MISSING_TE
  3628. mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
  3629. #endif
  3630. }
  3631. }
  3632. #ifdef DSI_CATCH_MISSING_TE
  3633. static void dsi_te_timeout(unsigned long arg)
  3634. {
  3635. DSSERR("TE not received for 250ms!\n");
  3636. }
  3637. #endif
  3638. static void dsi_handle_framedone(struct platform_device *dsidev, int error)
  3639. {
  3640. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3641. /* SIDLEMODE back to smart-idle */
  3642. dispc_enable_sidle();
  3643. if (dsi->te_enabled) {
  3644. /* enable LP_RX_TO again after the TE */
  3645. REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
  3646. }
  3647. dsi->framedone_callback(error, dsi->framedone_data);
  3648. if (!error)
  3649. dsi_perf_show(dsidev, "DISPC");
  3650. }
  3651. static void dsi_framedone_timeout_work_callback(struct work_struct *work)
  3652. {
  3653. struct dsi_data *dsi = container_of(work, struct dsi_data,
  3654. framedone_timeout_work.work);
  3655. /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
  3656. * 250ms which would conflict with this timeout work. What should be
  3657. * done is first cancel the transfer on the HW, and then cancel the
  3658. * possibly scheduled framedone work. However, cancelling the transfer
  3659. * on the HW is buggy, and would probably require resetting the whole
  3660. * DSI */
  3661. DSSERR("Framedone not received for 250ms!\n");
  3662. dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
  3663. }
  3664. static void dsi_framedone_irq_callback(void *data)
  3665. {
  3666. struct platform_device *dsidev = (struct platform_device *) data;
  3667. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3668. /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
  3669. * turns itself off. However, DSI still has the pixels in its buffers,
  3670. * and is sending the data.
  3671. */
  3672. cancel_delayed_work(&dsi->framedone_timeout_work);
  3673. dsi_handle_framedone(dsidev, 0);
  3674. }
  3675. int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
  3676. void (*callback)(int, void *), void *data)
  3677. {
  3678. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3679. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3680. u16 dw, dh;
  3681. dsi_perf_mark_setup(dsidev);
  3682. dsi->update_channel = channel;
  3683. dsi->framedone_callback = callback;
  3684. dsi->framedone_data = data;
  3685. dw = dsi->timings.x_res;
  3686. dh = dsi->timings.y_res;
  3687. #ifdef DEBUG
  3688. dsi->update_bytes = dw * dh *
  3689. dsi_get_pixel_size(dsi->pix_fmt) / 8;
  3690. #endif
  3691. dsi_update_screen_dispc(dsidev);
  3692. return 0;
  3693. }
  3694. EXPORT_SYMBOL(omap_dsi_update);
  3695. /* Display funcs */
  3696. static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
  3697. {
  3698. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3699. struct dispc_clock_info dispc_cinfo;
  3700. int r;
  3701. unsigned long fck;
  3702. fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
  3703. dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
  3704. dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
  3705. r = dispc_calc_clock_rates(fck, &dispc_cinfo);
  3706. if (r) {
  3707. DSSERR("Failed to calc dispc clocks\n");
  3708. return r;
  3709. }
  3710. dsi->mgr_config.clock_info = dispc_cinfo;
  3711. return 0;
  3712. }
  3713. static int dsi_display_init_dispc(struct platform_device *dsidev,
  3714. struct omap_overlay_manager *mgr)
  3715. {
  3716. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3717. int r;
  3718. dss_select_lcd_clk_source(mgr->id, dsi->user_lcd_clk_src);
  3719. if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
  3720. dsi->timings.hsw = 1;
  3721. dsi->timings.hfp = 1;
  3722. dsi->timings.hbp = 1;
  3723. dsi->timings.vsw = 1;
  3724. dsi->timings.vfp = 0;
  3725. dsi->timings.vbp = 0;
  3726. r = dss_mgr_register_framedone_handler(mgr,
  3727. dsi_framedone_irq_callback, dsidev);
  3728. if (r) {
  3729. DSSERR("can't register FRAMEDONE handler\n");
  3730. goto err;
  3731. }
  3732. dsi->mgr_config.stallmode = true;
  3733. dsi->mgr_config.fifohandcheck = true;
  3734. } else {
  3735. dsi->mgr_config.stallmode = false;
  3736. dsi->mgr_config.fifohandcheck = false;
  3737. }
  3738. /*
  3739. * override interlace, logic level and edge related parameters in
  3740. * omap_video_timings with default values
  3741. */
  3742. dsi->timings.interlace = false;
  3743. dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
  3744. dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
  3745. dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
  3746. dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
  3747. dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
  3748. dss_mgr_set_timings(mgr, &dsi->timings);
  3749. r = dsi_configure_dispc_clocks(dsidev);
  3750. if (r)
  3751. goto err1;
  3752. dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
  3753. dsi->mgr_config.video_port_width =
  3754. dsi_get_pixel_size(dsi->pix_fmt);
  3755. dsi->mgr_config.lcden_sig_polarity = 0;
  3756. dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
  3757. return 0;
  3758. err1:
  3759. if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
  3760. dss_mgr_unregister_framedone_handler(mgr,
  3761. dsi_framedone_irq_callback, dsidev);
  3762. err:
  3763. dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
  3764. return r;
  3765. }
  3766. static void dsi_display_uninit_dispc(struct platform_device *dsidev,
  3767. struct omap_overlay_manager *mgr)
  3768. {
  3769. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3770. if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
  3771. dss_mgr_unregister_framedone_handler(mgr,
  3772. dsi_framedone_irq_callback, dsidev);
  3773. dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
  3774. }
  3775. static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
  3776. {
  3777. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3778. struct dsi_clock_info cinfo;
  3779. int r;
  3780. cinfo = dsi->user_dsi_cinfo;
  3781. r = dsi_calc_clock_rates(dsidev, &cinfo);
  3782. if (r) {
  3783. DSSERR("Failed to calc dsi clocks\n");
  3784. return r;
  3785. }
  3786. r = dsi_pll_set_clock_div(dsidev, &cinfo);
  3787. if (r) {
  3788. DSSERR("Failed to set dsi clocks\n");
  3789. return r;
  3790. }
  3791. return 0;
  3792. }
  3793. static int dsi_display_init_dsi(struct platform_device *dsidev)
  3794. {
  3795. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3796. int r;
  3797. r = dsi_pll_init(dsidev, true, true);
  3798. if (r)
  3799. goto err0;
  3800. r = dsi_configure_dsi_clocks(dsidev);
  3801. if (r)
  3802. goto err1;
  3803. dss_select_dsi_clk_source(dsi->module_id, dsi->user_dsi_fclk_src);
  3804. DSSDBG("PLL OK\n");
  3805. r = dsi_cio_init(dsidev);
  3806. if (r)
  3807. goto err2;
  3808. _dsi_print_reset_status(dsidev);
  3809. dsi_proto_timings(dsidev);
  3810. dsi_set_lp_clk_divisor(dsidev);
  3811. if (1)
  3812. _dsi_print_reset_status(dsidev);
  3813. r = dsi_proto_config(dsidev);
  3814. if (r)
  3815. goto err3;
  3816. /* enable interface */
  3817. dsi_vc_enable(dsidev, 0, 1);
  3818. dsi_vc_enable(dsidev, 1, 1);
  3819. dsi_vc_enable(dsidev, 2, 1);
  3820. dsi_vc_enable(dsidev, 3, 1);
  3821. dsi_if_enable(dsidev, 1);
  3822. dsi_force_tx_stop_mode_io(dsidev);
  3823. return 0;
  3824. err3:
  3825. dsi_cio_uninit(dsidev);
  3826. err2:
  3827. dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
  3828. err1:
  3829. dsi_pll_uninit(dsidev, true);
  3830. err0:
  3831. return r;
  3832. }
  3833. static void dsi_display_uninit_dsi(struct platform_device *dsidev,
  3834. bool disconnect_lanes, bool enter_ulps)
  3835. {
  3836. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3837. if (enter_ulps && !dsi->ulps_enabled)
  3838. dsi_enter_ulps(dsidev);
  3839. /* disable interface */
  3840. dsi_if_enable(dsidev, 0);
  3841. dsi_vc_enable(dsidev, 0, 0);
  3842. dsi_vc_enable(dsidev, 1, 0);
  3843. dsi_vc_enable(dsidev, 2, 0);
  3844. dsi_vc_enable(dsidev, 3, 0);
  3845. dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
  3846. dsi_cio_uninit(dsidev);
  3847. dsi_pll_uninit(dsidev, disconnect_lanes);
  3848. }
  3849. int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
  3850. {
  3851. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3852. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3853. int r = 0;
  3854. DSSDBG("dsi_display_enable\n");
  3855. WARN_ON(!dsi_bus_is_locked(dsidev));
  3856. mutex_lock(&dsi->lock);
  3857. r = omap_dss_start_device(dssdev);
  3858. if (r) {
  3859. DSSERR("failed to start device\n");
  3860. goto err_start_dev;
  3861. }
  3862. r = dsi_runtime_get(dsidev);
  3863. if (r)
  3864. goto err_get_dsi;
  3865. dsi_enable_pll_clock(dsidev, 1);
  3866. _dsi_initialize_irq(dsidev);
  3867. r = dsi_display_init_dsi(dsidev);
  3868. if (r)
  3869. goto err_init_dsi;
  3870. mutex_unlock(&dsi->lock);
  3871. return 0;
  3872. err_init_dsi:
  3873. dsi_enable_pll_clock(dsidev, 0);
  3874. dsi_runtime_put(dsidev);
  3875. err_get_dsi:
  3876. omap_dss_stop_device(dssdev);
  3877. err_start_dev:
  3878. mutex_unlock(&dsi->lock);
  3879. DSSDBG("dsi_display_enable FAILED\n");
  3880. return r;
  3881. }
  3882. EXPORT_SYMBOL(omapdss_dsi_display_enable);
  3883. void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
  3884. bool disconnect_lanes, bool enter_ulps)
  3885. {
  3886. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3887. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3888. DSSDBG("dsi_display_disable\n");
  3889. WARN_ON(!dsi_bus_is_locked(dsidev));
  3890. mutex_lock(&dsi->lock);
  3891. dsi_sync_vc(dsidev, 0);
  3892. dsi_sync_vc(dsidev, 1);
  3893. dsi_sync_vc(dsidev, 2);
  3894. dsi_sync_vc(dsidev, 3);
  3895. dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
  3896. dsi_runtime_put(dsidev);
  3897. dsi_enable_pll_clock(dsidev, 0);
  3898. omap_dss_stop_device(dssdev);
  3899. mutex_unlock(&dsi->lock);
  3900. }
  3901. EXPORT_SYMBOL(omapdss_dsi_display_disable);
  3902. int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
  3903. {
  3904. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3905. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3906. dsi->te_enabled = enable;
  3907. return 0;
  3908. }
  3909. EXPORT_SYMBOL(omapdss_dsi_enable_te);
  3910. int omapdss_dsi_set_config(struct omap_dss_device *dssdev,
  3911. const struct omap_dss_dsi_config *config)
  3912. {
  3913. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3914. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3915. mutex_lock(&dsi->lock);
  3916. dsi->timings = *config->timings;
  3917. dsi->vm_timings = *config->vm_timings;
  3918. dsi->pix_fmt = config->pixel_format;
  3919. dsi->mode = config->mode;
  3920. dsi_set_clocks(dssdev, config->hs_clk, config->lp_clk);
  3921. mutex_unlock(&dsi->lock);
  3922. return 0;
  3923. }
  3924. EXPORT_SYMBOL(omapdss_dsi_set_config);
  3925. /*
  3926. * Return a hardcoded channel for the DSI output. This should work for
  3927. * current use cases, but this can be later expanded to either resolve
  3928. * the channel in some more dynamic manner, or get the channel as a user
  3929. * parameter.
  3930. */
  3931. static enum omap_channel dsi_get_channel(int module_id)
  3932. {
  3933. switch (omapdss_get_version()) {
  3934. case OMAPDSS_VER_OMAP24xx:
  3935. DSSWARN("DSI not supported\n");
  3936. return OMAP_DSS_CHANNEL_LCD;
  3937. case OMAPDSS_VER_OMAP34xx_ES1:
  3938. case OMAPDSS_VER_OMAP34xx_ES3:
  3939. case OMAPDSS_VER_OMAP3630:
  3940. case OMAPDSS_VER_AM35xx:
  3941. return OMAP_DSS_CHANNEL_LCD;
  3942. case OMAPDSS_VER_OMAP4430_ES1:
  3943. case OMAPDSS_VER_OMAP4430_ES2:
  3944. case OMAPDSS_VER_OMAP4:
  3945. switch (module_id) {
  3946. case 0:
  3947. return OMAP_DSS_CHANNEL_LCD;
  3948. case 1:
  3949. return OMAP_DSS_CHANNEL_LCD2;
  3950. default:
  3951. DSSWARN("unsupported module id\n");
  3952. return OMAP_DSS_CHANNEL_LCD;
  3953. }
  3954. case OMAPDSS_VER_OMAP5:
  3955. switch (module_id) {
  3956. case 0:
  3957. return OMAP_DSS_CHANNEL_LCD;
  3958. case 1:
  3959. return OMAP_DSS_CHANNEL_LCD3;
  3960. default:
  3961. DSSWARN("unsupported module id\n");
  3962. return OMAP_DSS_CHANNEL_LCD;
  3963. }
  3964. default:
  3965. DSSWARN("unsupported DSS version\n");
  3966. return OMAP_DSS_CHANNEL_LCD;
  3967. }
  3968. }
  3969. static int __init dsi_init_display(struct omap_dss_device *dssdev)
  3970. {
  3971. struct platform_device *dsidev =
  3972. dsi_get_dsidev_from_id(dssdev->phy.dsi.module);
  3973. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3974. DSSDBG("DSI init\n");
  3975. if (dsi->vdds_dsi_reg == NULL) {
  3976. struct regulator *vdds_dsi;
  3977. vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
  3978. /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
  3979. if (IS_ERR(vdds_dsi))
  3980. vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
  3981. if (IS_ERR(vdds_dsi)) {
  3982. DSSERR("can't get VDDS_DSI regulator\n");
  3983. return PTR_ERR(vdds_dsi);
  3984. }
  3985. dsi->vdds_dsi_reg = vdds_dsi;
  3986. }
  3987. return 0;
  3988. }
  3989. int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
  3990. {
  3991. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  3992. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  3993. int i;
  3994. for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
  3995. if (!dsi->vc[i].dssdev) {
  3996. dsi->vc[i].dssdev = dssdev;
  3997. *channel = i;
  3998. return 0;
  3999. }
  4000. }
  4001. DSSERR("cannot get VC for display %s", dssdev->name);
  4002. return -ENOSPC;
  4003. }
  4004. EXPORT_SYMBOL(omap_dsi_request_vc);
  4005. int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
  4006. {
  4007. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  4008. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4009. if (vc_id < 0 || vc_id > 3) {
  4010. DSSERR("VC ID out of range\n");
  4011. return -EINVAL;
  4012. }
  4013. if (channel < 0 || channel > 3) {
  4014. DSSERR("Virtual Channel out of range\n");
  4015. return -EINVAL;
  4016. }
  4017. if (dsi->vc[channel].dssdev != dssdev) {
  4018. DSSERR("Virtual Channel not allocated to display %s\n",
  4019. dssdev->name);
  4020. return -EINVAL;
  4021. }
  4022. dsi->vc[channel].vc_id = vc_id;
  4023. return 0;
  4024. }
  4025. EXPORT_SYMBOL(omap_dsi_set_vc_id);
  4026. void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
  4027. {
  4028. struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
  4029. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4030. if ((channel >= 0 && channel <= 3) &&
  4031. dsi->vc[channel].dssdev == dssdev) {
  4032. dsi->vc[channel].dssdev = NULL;
  4033. dsi->vc[channel].vc_id = 0;
  4034. }
  4035. }
  4036. EXPORT_SYMBOL(omap_dsi_release_vc);
  4037. void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
  4038. {
  4039. if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
  4040. DSSERR("%s (%s) not active\n",
  4041. dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
  4042. dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
  4043. }
  4044. void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
  4045. {
  4046. if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
  4047. DSSERR("%s (%s) not active\n",
  4048. dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
  4049. dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
  4050. }
  4051. static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
  4052. {
  4053. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4054. dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
  4055. dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
  4056. dsi->regm_dispc_max =
  4057. dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
  4058. dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
  4059. dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
  4060. dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
  4061. dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
  4062. }
  4063. static int dsi_get_clocks(struct platform_device *dsidev)
  4064. {
  4065. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4066. struct clk *clk;
  4067. clk = clk_get(&dsidev->dev, "fck");
  4068. if (IS_ERR(clk)) {
  4069. DSSERR("can't get fck\n");
  4070. return PTR_ERR(clk);
  4071. }
  4072. dsi->dss_clk = clk;
  4073. clk = clk_get(&dsidev->dev, "sys_clk");
  4074. if (IS_ERR(clk)) {
  4075. DSSERR("can't get sys_clk\n");
  4076. clk_put(dsi->dss_clk);
  4077. dsi->dss_clk = NULL;
  4078. return PTR_ERR(clk);
  4079. }
  4080. dsi->sys_clk = clk;
  4081. return 0;
  4082. }
  4083. static void dsi_put_clocks(struct platform_device *dsidev)
  4084. {
  4085. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4086. if (dsi->dss_clk)
  4087. clk_put(dsi->dss_clk);
  4088. if (dsi->sys_clk)
  4089. clk_put(dsi->sys_clk);
  4090. }
  4091. static struct omap_dss_device * __init dsi_find_dssdev(struct platform_device *pdev)
  4092. {
  4093. struct omap_dss_board_info *pdata = pdev->dev.platform_data;
  4094. struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
  4095. const char *def_disp_name = omapdss_get_default_display_name();
  4096. struct omap_dss_device *def_dssdev;
  4097. int i;
  4098. def_dssdev = NULL;
  4099. for (i = 0; i < pdata->num_devices; ++i) {
  4100. struct omap_dss_device *dssdev = pdata->devices[i];
  4101. if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
  4102. continue;
  4103. if (dssdev->phy.dsi.module != dsi->module_id)
  4104. continue;
  4105. if (def_dssdev == NULL)
  4106. def_dssdev = dssdev;
  4107. if (def_disp_name != NULL &&
  4108. strcmp(dssdev->name, def_disp_name) == 0) {
  4109. def_dssdev = dssdev;
  4110. break;
  4111. }
  4112. }
  4113. return def_dssdev;
  4114. }
  4115. static void __init dsi_probe_pdata(struct platform_device *dsidev)
  4116. {
  4117. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4118. struct omap_dss_device *plat_dssdev;
  4119. struct omap_dss_device *dssdev;
  4120. int r;
  4121. plat_dssdev = dsi_find_dssdev(dsidev);
  4122. if (!plat_dssdev)
  4123. return;
  4124. dssdev = dss_alloc_and_init_device(&dsidev->dev);
  4125. if (!dssdev)
  4126. return;
  4127. dss_copy_device_pdata(dssdev, plat_dssdev);
  4128. r = dsi_init_display(dssdev);
  4129. if (r) {
  4130. DSSERR("device %s init failed: %d\n", dssdev->name, r);
  4131. dss_put_device(dssdev);
  4132. return;
  4133. }
  4134. r = omapdss_output_set_device(&dsi->output, dssdev);
  4135. if (r) {
  4136. DSSERR("failed to connect output to new device: %s\n",
  4137. dssdev->name);
  4138. dss_put_device(dssdev);
  4139. return;
  4140. }
  4141. r = dss_add_device(dssdev);
  4142. if (r) {
  4143. DSSERR("device %s register failed: %d\n", dssdev->name, r);
  4144. omapdss_output_unset_device(&dsi->output);
  4145. dss_put_device(dssdev);
  4146. return;
  4147. }
  4148. }
  4149. static void __init dsi_init_output(struct platform_device *dsidev)
  4150. {
  4151. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4152. struct omap_dss_output *out = &dsi->output;
  4153. out->pdev = dsidev;
  4154. out->id = dsi->module_id == 0 ?
  4155. OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
  4156. out->type = OMAP_DISPLAY_TYPE_DSI;
  4157. out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
  4158. out->dispc_channel = dsi_get_channel(dsi->module_id);
  4159. dss_register_output(out);
  4160. }
  4161. static void __exit dsi_uninit_output(struct platform_device *dsidev)
  4162. {
  4163. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4164. struct omap_dss_output *out = &dsi->output;
  4165. dss_unregister_output(out);
  4166. }
  4167. /* DSI1 HW IP initialisation */
  4168. static int __init omap_dsihw_probe(struct platform_device *dsidev)
  4169. {
  4170. u32 rev;
  4171. int r, i;
  4172. struct resource *dsi_mem;
  4173. struct dsi_data *dsi;
  4174. dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
  4175. if (!dsi)
  4176. return -ENOMEM;
  4177. dsi->module_id = dsidev->id;
  4178. dsi->pdev = dsidev;
  4179. dev_set_drvdata(&dsidev->dev, dsi);
  4180. spin_lock_init(&dsi->irq_lock);
  4181. spin_lock_init(&dsi->errors_lock);
  4182. dsi->errors = 0;
  4183. #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
  4184. spin_lock_init(&dsi->irq_stats_lock);
  4185. dsi->irq_stats.last_reset = jiffies;
  4186. #endif
  4187. mutex_init(&dsi->lock);
  4188. sema_init(&dsi->bus_lock, 1);
  4189. INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
  4190. dsi_framedone_timeout_work_callback);
  4191. #ifdef DSI_CATCH_MISSING_TE
  4192. init_timer(&dsi->te_timer);
  4193. dsi->te_timer.function = dsi_te_timeout;
  4194. dsi->te_timer.data = 0;
  4195. #endif
  4196. dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
  4197. if (!dsi_mem) {
  4198. DSSERR("can't get IORESOURCE_MEM DSI\n");
  4199. return -EINVAL;
  4200. }
  4201. dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
  4202. resource_size(dsi_mem));
  4203. if (!dsi->base) {
  4204. DSSERR("can't ioremap DSI\n");
  4205. return -ENOMEM;
  4206. }
  4207. dsi->irq = platform_get_irq(dsi->pdev, 0);
  4208. if (dsi->irq < 0) {
  4209. DSSERR("platform_get_irq failed\n");
  4210. return -ENODEV;
  4211. }
  4212. r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
  4213. IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
  4214. if (r < 0) {
  4215. DSSERR("request_irq failed\n");
  4216. return r;
  4217. }
  4218. /* DSI VCs initialization */
  4219. for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
  4220. dsi->vc[i].source = DSI_VC_SOURCE_L4;
  4221. dsi->vc[i].dssdev = NULL;
  4222. dsi->vc[i].vc_id = 0;
  4223. }
  4224. dsi_calc_clock_param_ranges(dsidev);
  4225. r = dsi_get_clocks(dsidev);
  4226. if (r)
  4227. return r;
  4228. pm_runtime_enable(&dsidev->dev);
  4229. r = dsi_runtime_get(dsidev);
  4230. if (r)
  4231. goto err_runtime_get;
  4232. rev = dsi_read_reg(dsidev, DSI_REVISION);
  4233. dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
  4234. FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
  4235. /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
  4236. * of data to 3 by default */
  4237. if (dss_has_feature(FEAT_DSI_GNQ))
  4238. /* NB_DATA_LANES */
  4239. dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
  4240. else
  4241. dsi->num_lanes_supported = 3;
  4242. dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
  4243. dsi_init_output(dsidev);
  4244. dsi_probe_pdata(dsidev);
  4245. dsi_runtime_put(dsidev);
  4246. if (dsi->module_id == 0)
  4247. dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
  4248. else if (dsi->module_id == 1)
  4249. dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
  4250. #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
  4251. if (dsi->module_id == 0)
  4252. dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
  4253. else if (dsi->module_id == 1)
  4254. dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
  4255. #endif
  4256. return 0;
  4257. err_runtime_get:
  4258. pm_runtime_disable(&dsidev->dev);
  4259. dsi_put_clocks(dsidev);
  4260. return r;
  4261. }
  4262. static int __exit omap_dsihw_remove(struct platform_device *dsidev)
  4263. {
  4264. struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
  4265. WARN_ON(dsi->scp_clk_refcount > 0);
  4266. dss_unregister_child_devices(&dsidev->dev);
  4267. dsi_uninit_output(dsidev);
  4268. pm_runtime_disable(&dsidev->dev);
  4269. dsi_put_clocks(dsidev);
  4270. if (dsi->vdds_dsi_reg != NULL) {
  4271. if (dsi->vdds_dsi_enabled) {
  4272. regulator_disable(dsi->vdds_dsi_reg);
  4273. dsi->vdds_dsi_enabled = false;
  4274. }
  4275. regulator_put(dsi->vdds_dsi_reg);
  4276. dsi->vdds_dsi_reg = NULL;
  4277. }
  4278. return 0;
  4279. }
  4280. static int dsi_runtime_suspend(struct device *dev)
  4281. {
  4282. dispc_runtime_put();
  4283. return 0;
  4284. }
  4285. static int dsi_runtime_resume(struct device *dev)
  4286. {
  4287. int r;
  4288. r = dispc_runtime_get();
  4289. if (r)
  4290. return r;
  4291. return 0;
  4292. }
  4293. static const struct dev_pm_ops dsi_pm_ops = {
  4294. .runtime_suspend = dsi_runtime_suspend,
  4295. .runtime_resume = dsi_runtime_resume,
  4296. };
  4297. static struct platform_driver omap_dsihw_driver = {
  4298. .remove = __exit_p(omap_dsihw_remove),
  4299. .driver = {
  4300. .name = "omapdss_dsi",
  4301. .owner = THIS_MODULE,
  4302. .pm = &dsi_pm_ops,
  4303. },
  4304. };
  4305. int __init dsi_init_platform_driver(void)
  4306. {
  4307. return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe);
  4308. }
  4309. void __exit dsi_uninit_platform_driver(void)
  4310. {
  4311. platform_driver_unregister(&omap_dsihw_driver);
  4312. }