rts5249.c 6.6 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. * No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
  21. */
  22. #include <linux/module.h>
  23. #include <linux/delay.h>
  24. #include <linux/mfd/rtsx_pci.h>
  25. #include "rtsx_pcr.h"
  26. static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
  27. {
  28. u8 val;
  29. rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  30. return val & 0x0F;
  31. }
  32. static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
  33. {
  34. rtsx_pci_init_cmd(pcr);
  35. /* Configure GPIO as output */
  36. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
  37. /* Switch LDO3318 source from DV33 to card_3v3 */
  38. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
  39. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
  40. /* LED shine disabled, set initial shine cycle period */
  41. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
  42. /* Correct driving */
  43. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  44. SD30_CLK_DRIVE_SEL, 0xFF, 0x99);
  45. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  46. SD30_CMD_DRIVE_SEL, 0xFF, 0x99);
  47. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
  48. SD30_DAT_DRIVE_SEL, 0xFF, 0x92);
  49. return rtsx_pci_send_cmd(pcr, 100);
  50. }
  51. static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
  52. {
  53. int err;
  54. err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
  55. if (err < 0)
  56. return err;
  57. msleep(1);
  58. return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
  59. }
  60. static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
  61. {
  62. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
  63. }
  64. static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
  65. {
  66. return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
  67. }
  68. static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
  69. {
  70. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
  71. }
  72. static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
  73. {
  74. return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
  75. }
  76. static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
  77. {
  78. int err;
  79. rtsx_pci_init_cmd(pcr);
  80. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  81. SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
  82. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  83. LDO3318_PWR_MASK, 0x02);
  84. err = rtsx_pci_send_cmd(pcr, 100);
  85. if (err < 0)
  86. return err;
  87. msleep(5);
  88. rtsx_pci_init_cmd(pcr);
  89. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  90. SD_POWER_MASK, SD_VCC_POWER_ON);
  91. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  92. LDO3318_PWR_MASK, 0x06);
  93. err = rtsx_pci_send_cmd(pcr, 100);
  94. if (err < 0)
  95. return err;
  96. return 0;
  97. }
  98. static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
  99. {
  100. rtsx_pci_init_cmd(pcr);
  101. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  102. SD_POWER_MASK, SD_POWER_OFF);
  103. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
  104. LDO3318_PWR_MASK, 0x00);
  105. return rtsx_pci_send_cmd(pcr, 100);
  106. }
  107. static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  108. {
  109. int err;
  110. u8 clk_drive, cmd_drive, dat_drive;
  111. if (voltage == OUTPUT_3V3) {
  112. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
  113. if (err < 0)
  114. return err;
  115. clk_drive = 0x99;
  116. cmd_drive = 0x99;
  117. dat_drive = 0x92;
  118. } else if (voltage == OUTPUT_1V8) {
  119. err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
  120. if (err < 0)
  121. return err;
  122. err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
  123. if (err < 0)
  124. return err;
  125. clk_drive = 0xb3;
  126. cmd_drive = 0xb3;
  127. dat_drive = 0xb3;
  128. } else {
  129. return -EINVAL;
  130. }
  131. /* set pad drive */
  132. rtsx_pci_init_cmd(pcr);
  133. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  134. 0xFF, clk_drive);
  135. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  136. 0xFF, cmd_drive);
  137. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  138. 0xFF, dat_drive);
  139. return rtsx_pci_send_cmd(pcr, 100);
  140. }
  141. static const struct pcr_ops rts5249_pcr_ops = {
  142. .extra_init_hw = rts5249_extra_init_hw,
  143. .optimize_phy = rts5249_optimize_phy,
  144. .turn_on_led = rts5249_turn_on_led,
  145. .turn_off_led = rts5249_turn_off_led,
  146. .enable_auto_blink = rts5249_enable_auto_blink,
  147. .disable_auto_blink = rts5249_disable_auto_blink,
  148. .card_power_on = rts5249_card_power_on,
  149. .card_power_off = rts5249_card_power_off,
  150. .switch_output_voltage = rts5249_switch_output_voltage,
  151. };
  152. /* SD Pull Control Enable:
  153. * SD_DAT[3:0] ==> pull up
  154. * SD_CD ==> pull up
  155. * SD_WP ==> pull up
  156. * SD_CMD ==> pull up
  157. * SD_CLK ==> pull down
  158. */
  159. static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
  160. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  161. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  162. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
  163. RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
  164. 0,
  165. };
  166. /* SD Pull Control Disable:
  167. * SD_DAT[3:0] ==> pull down
  168. * SD_CD ==> pull up
  169. * SD_WP ==> pull down
  170. * SD_CMD ==> pull down
  171. * SD_CLK ==> pull down
  172. */
  173. static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
  174. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
  175. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  176. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
  177. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  178. 0,
  179. };
  180. /* MS Pull Control Enable:
  181. * MS CD ==> pull up
  182. * others ==> pull down
  183. */
  184. static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
  185. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  186. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  187. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  188. 0,
  189. };
  190. /* MS Pull Control Disable:
  191. * MS CD ==> pull up
  192. * others ==> pull down
  193. */
  194. static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
  195. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
  196. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
  197. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
  198. 0,
  199. };
  200. void rts5249_init_params(struct rtsx_pcr *pcr)
  201. {
  202. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  203. pcr->num_slots = 2;
  204. pcr->ops = &rts5249_pcr_ops;
  205. pcr->ic_version = rts5249_get_ic_version(pcr);
  206. pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
  207. pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
  208. pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
  209. pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
  210. }