rtl8411.c 11 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG <wei_wang@realsil.com.cn>
  20. * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21. */
  22. #include <linux/module.h>
  23. #include <linux/bitops.h>
  24. #include <linux/delay.h>
  25. #include <linux/mfd/rtsx_pci.h>
  26. #include "rtsx_pcr.h"
  27. static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr)
  28. {
  29. u8 val;
  30. rtsx_pci_read_register(pcr, SYS_VER, &val);
  31. return val & 0x0F;
  32. }
  33. static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr)
  34. {
  35. u8 val = 0;
  36. rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val);
  37. if (val & 0x2)
  38. return 1;
  39. else
  40. return 0;
  41. }
  42. static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr)
  43. {
  44. return rtsx_pci_write_register(pcr, CD_PAD_CTL,
  45. CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
  46. }
  47. static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr)
  48. {
  49. if (rtl8411b_is_qfn48(pcr))
  50. rtsx_pci_write_register(pcr, CARD_PULL_CTL3, 0xFF, 0xF5);
  51. return rtsx_pci_write_register(pcr, CD_PAD_CTL,
  52. CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
  53. }
  54. static int rtl8411_turn_on_led(struct rtsx_pcr *pcr)
  55. {
  56. return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
  57. }
  58. static int rtl8411_turn_off_led(struct rtsx_pcr *pcr)
  59. {
  60. return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
  61. }
  62. static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr)
  63. {
  64. return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
  65. }
  66. static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr)
  67. {
  68. return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
  69. }
  70. static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card)
  71. {
  72. int err;
  73. rtsx_pci_init_cmd(pcr);
  74. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
  75. BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
  76. rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL,
  77. BPP_LDO_POWB, BPP_LDO_SUSPEND);
  78. err = rtsx_pci_send_cmd(pcr, 100);
  79. if (err < 0)
  80. return err;
  81. /* To avoid too large in-rush current */
  82. udelay(150);
  83. err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  84. BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON);
  85. if (err < 0)
  86. return err;
  87. udelay(150);
  88. err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  89. BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON);
  90. if (err < 0)
  91. return err;
  92. udelay(150);
  93. err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  94. BPP_POWER_MASK, BPP_POWER_ON);
  95. if (err < 0)
  96. return err;
  97. return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON);
  98. }
  99. static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card)
  100. {
  101. int err;
  102. err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  103. BPP_POWER_MASK, BPP_POWER_OFF);
  104. if (err < 0)
  105. return err;
  106. return rtsx_pci_write_register(pcr, LDO_CTL,
  107. BPP_LDO_POWB, BPP_LDO_SUSPEND);
  108. }
  109. static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
  110. {
  111. u8 mask, val;
  112. int err;
  113. mask = (BPP_REG_TUNED18 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_MASK;
  114. if (voltage == OUTPUT_3V3) {
  115. err = rtsx_pci_write_register(pcr,
  116. SD30_DRIVE_SEL, 0x07, DRIVER_TYPE_D);
  117. if (err < 0)
  118. return err;
  119. val = (BPP_ASIC_3V3 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_3V3;
  120. } else if (voltage == OUTPUT_1V8) {
  121. err = rtsx_pci_write_register(pcr,
  122. SD30_DRIVE_SEL, 0x07, DRIVER_TYPE_B);
  123. if (err < 0)
  124. return err;
  125. val = (BPP_ASIC_1V8 << BPP_TUNED18_SHIFT_8411) | BPP_PAD_1V8;
  126. } else {
  127. return -EINVAL;
  128. }
  129. return rtsx_pci_write_register(pcr, LDO_CTL, mask, val);
  130. }
  131. static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr)
  132. {
  133. unsigned int card_exist;
  134. card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
  135. card_exist &= CARD_EXIST;
  136. if (!card_exist) {
  137. /* Enable card CD */
  138. rtsx_pci_write_register(pcr, CD_PAD_CTL,
  139. CD_DISABLE_MASK, CD_ENABLE);
  140. /* Enable card interrupt */
  141. rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00);
  142. return 0;
  143. }
  144. if (hweight32(card_exist) > 1) {
  145. rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  146. BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
  147. msleep(100);
  148. card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
  149. if (card_exist & MS_EXIST)
  150. card_exist = MS_EXIST;
  151. else if (card_exist & SD_EXIST)
  152. card_exist = SD_EXIST;
  153. else
  154. card_exist = 0;
  155. rtsx_pci_write_register(pcr, CARD_PWR_CTL,
  156. BPP_POWER_MASK, BPP_POWER_OFF);
  157. dev_dbg(&(pcr->pci->dev),
  158. "After CD deglitch, card_exist = 0x%x\n",
  159. card_exist);
  160. }
  161. if (card_exist & MS_EXIST) {
  162. /* Disable SD interrupt */
  163. rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40);
  164. rtsx_pci_write_register(pcr, CD_PAD_CTL,
  165. CD_DISABLE_MASK, MS_CD_EN_ONLY);
  166. } else if (card_exist & SD_EXIST) {
  167. /* Disable MS interrupt */
  168. rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80);
  169. rtsx_pci_write_register(pcr, CD_PAD_CTL,
  170. CD_DISABLE_MASK, SD_CD_EN_ONLY);
  171. }
  172. return card_exist;
  173. }
  174. static int rtl8411_conv_clk_and_div_n(int input, int dir)
  175. {
  176. int output;
  177. if (dir == CLK_TO_DIV_N)
  178. output = input * 4 / 5 - 2;
  179. else
  180. output = (input + 2) * 5 / 4;
  181. return output;
  182. }
  183. static const struct pcr_ops rtl8411_pcr_ops = {
  184. .extra_init_hw = rtl8411_extra_init_hw,
  185. .optimize_phy = NULL,
  186. .turn_on_led = rtl8411_turn_on_led,
  187. .turn_off_led = rtl8411_turn_off_led,
  188. .enable_auto_blink = rtl8411_enable_auto_blink,
  189. .disable_auto_blink = rtl8411_disable_auto_blink,
  190. .card_power_on = rtl8411_card_power_on,
  191. .card_power_off = rtl8411_card_power_off,
  192. .switch_output_voltage = rtl8411_switch_output_voltage,
  193. .cd_deglitch = rtl8411_cd_deglitch,
  194. .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
  195. };
  196. static const struct pcr_ops rtl8411b_pcr_ops = {
  197. .extra_init_hw = rtl8411b_extra_init_hw,
  198. .optimize_phy = NULL,
  199. .turn_on_led = rtl8411_turn_on_led,
  200. .turn_off_led = rtl8411_turn_off_led,
  201. .enable_auto_blink = rtl8411_enable_auto_blink,
  202. .disable_auto_blink = rtl8411_disable_auto_blink,
  203. .card_power_on = rtl8411_card_power_on,
  204. .card_power_off = rtl8411_card_power_off,
  205. .switch_output_voltage = rtl8411_switch_output_voltage,
  206. .cd_deglitch = rtl8411_cd_deglitch,
  207. .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
  208. };
  209. /* SD Pull Control Enable:
  210. * SD_DAT[3:0] ==> pull up
  211. * SD_CD ==> pull up
  212. * SD_WP ==> pull up
  213. * SD_CMD ==> pull up
  214. * SD_CLK ==> pull down
  215. */
  216. static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = {
  217. RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
  218. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  219. RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9),
  220. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
  221. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09),
  222. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
  223. 0,
  224. };
  225. /* SD Pull Control Disable:
  226. * SD_DAT[3:0] ==> pull down
  227. * SD_CD ==> pull up
  228. * SD_WP ==> pull down
  229. * SD_CMD ==> pull down
  230. * SD_CLK ==> pull down
  231. */
  232. static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = {
  233. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  234. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  235. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
  236. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
  237. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
  238. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
  239. 0,
  240. };
  241. /* MS Pull Control Enable:
  242. * MS CD ==> pull up
  243. * others ==> pull down
  244. */
  245. static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = {
  246. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  247. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  248. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
  249. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05),
  250. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
  251. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
  252. 0,
  253. };
  254. /* MS Pull Control Disable:
  255. * MS CD ==> pull up
  256. * others ==> pull down
  257. */
  258. static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = {
  259. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  260. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  261. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
  262. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
  263. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
  264. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
  265. 0,
  266. };
  267. static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = {
  268. RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
  269. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  270. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0),
  271. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
  272. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
  273. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  274. 0,
  275. };
  276. static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = {
  277. RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
  278. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90),
  279. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11),
  280. 0,
  281. };
  282. static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = {
  283. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  284. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  285. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
  286. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
  287. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
  288. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  289. 0,
  290. };
  291. static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = {
  292. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  293. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
  294. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  295. 0,
  296. };
  297. static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = {
  298. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  299. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  300. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
  301. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50),
  302. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
  303. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  304. 0,
  305. };
  306. static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = {
  307. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  308. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
  309. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  310. 0,
  311. };
  312. static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = {
  313. RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
  314. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  315. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
  316. RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
  317. RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
  318. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  319. 0,
  320. };
  321. static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = {
  322. RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
  323. RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
  324. RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
  325. 0,
  326. };
  327. void rtl8411_init_params(struct rtsx_pcr *pcr)
  328. {
  329. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  330. pcr->num_slots = 2;
  331. pcr->ops = &rtl8411_pcr_ops;
  332. pcr->ic_version = rtl8411_get_ic_version(pcr);
  333. pcr->sd_pull_ctl_enable_tbl = rtl8411_sd_pull_ctl_enable_tbl;
  334. pcr->sd_pull_ctl_disable_tbl = rtl8411_sd_pull_ctl_disable_tbl;
  335. pcr->ms_pull_ctl_enable_tbl = rtl8411_ms_pull_ctl_enable_tbl;
  336. pcr->ms_pull_ctl_disable_tbl = rtl8411_ms_pull_ctl_disable_tbl;
  337. }
  338. void rtl8411b_init_params(struct rtsx_pcr *pcr)
  339. {
  340. pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
  341. pcr->num_slots = 2;
  342. pcr->ops = &rtl8411b_pcr_ops;
  343. pcr->ic_version = rtl8411_get_ic_version(pcr);
  344. if (rtl8411b_is_qfn48(pcr)) {
  345. pcr->sd_pull_ctl_enable_tbl =
  346. rtl8411b_qfn48_sd_pull_ctl_enable_tbl;
  347. pcr->sd_pull_ctl_disable_tbl =
  348. rtl8411b_qfn48_sd_pull_ctl_disable_tbl;
  349. pcr->ms_pull_ctl_enable_tbl =
  350. rtl8411b_qfn48_ms_pull_ctl_enable_tbl;
  351. pcr->ms_pull_ctl_disable_tbl =
  352. rtl8411b_qfn48_ms_pull_ctl_disable_tbl;
  353. } else {
  354. pcr->sd_pull_ctl_enable_tbl =
  355. rtl8411b_qfn64_sd_pull_ctl_enable_tbl;
  356. pcr->sd_pull_ctl_disable_tbl =
  357. rtl8411b_qfn64_sd_pull_ctl_disable_tbl;
  358. pcr->ms_pull_ctl_enable_tbl =
  359. rtl8411b_qfn64_ms_pull_ctl_enable_tbl;
  360. pcr->ms_pull_ctl_disable_tbl =
  361. rtl8411b_qfn64_ms_pull_ctl_disable_tbl;
  362. }
  363. }