cros_ec_spi.c 9.6 KB

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  1. /*
  2. * ChromeOS EC multi-function device (SPI)
  3. *
  4. * Copyright (C) 2012 Google, Inc
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/mfd/cros_ec.h>
  19. #include <linux/mfd/cros_ec_commands.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/slab.h>
  22. #include <linux/spi/spi.h>
  23. /* The header byte, which follows the preamble */
  24. #define EC_MSG_HEADER 0xec
  25. /*
  26. * Number of EC preamble bytes we read at a time. Since it takes
  27. * about 400-500us for the EC to respond there is not a lot of
  28. * point in tuning this. If the EC could respond faster then
  29. * we could increase this so that might expect the preamble and
  30. * message to occur in a single transaction. However, the maximum
  31. * SPI transfer size is 256 bytes, so at 5MHz we need a response
  32. * time of perhaps <320us (200 bytes / 1600 bits).
  33. */
  34. #define EC_MSG_PREAMBLE_COUNT 32
  35. /*
  36. * We must get a response from the EC in 5ms. This is a very long
  37. * time, but the flash write command can take 2-3ms. The EC command
  38. * processing is currently not very fast (about 500us). We could
  39. * look at speeding this up and making the flash write command a
  40. * 'slow' command, requiring a GET_STATUS wait loop, like flash
  41. * erase.
  42. */
  43. #define EC_MSG_DEADLINE_MS 5
  44. /*
  45. * Time between raising the SPI chip select (for the end of a
  46. * transaction) and dropping it again (for the next transaction).
  47. * If we go too fast, the EC will miss the transaction. It seems
  48. * that 50us is enough with the 16MHz STM32 EC.
  49. */
  50. #define EC_SPI_RECOVERY_TIME_NS (50 * 1000)
  51. /**
  52. * struct cros_ec_spi - information about a SPI-connected EC
  53. *
  54. * @spi: SPI device we are connected to
  55. * @last_transfer_ns: time that we last finished a transfer, or 0 if there
  56. * if no record
  57. */
  58. struct cros_ec_spi {
  59. struct spi_device *spi;
  60. s64 last_transfer_ns;
  61. };
  62. static void debug_packet(struct device *dev, const char *name, u8 *ptr,
  63. int len)
  64. {
  65. #ifdef DEBUG
  66. int i;
  67. dev_dbg(dev, "%s: ", name);
  68. for (i = 0; i < len; i++)
  69. dev_cont(dev, " %02x", ptr[i]);
  70. #endif
  71. }
  72. /**
  73. * cros_ec_spi_receive_response - Receive a response from the EC.
  74. *
  75. * This function has two phases: reading the preamble bytes (since if we read
  76. * data from the EC before it is ready to send, we just get preamble) and
  77. * reading the actual message.
  78. *
  79. * The received data is placed into ec_dev->din.
  80. *
  81. * @ec_dev: ChromeOS EC device
  82. * @need_len: Number of message bytes we need to read
  83. */
  84. static int cros_ec_spi_receive_response(struct cros_ec_device *ec_dev,
  85. int need_len)
  86. {
  87. struct cros_ec_spi *ec_spi = ec_dev->priv;
  88. struct spi_transfer trans;
  89. struct spi_message msg;
  90. u8 *ptr, *end;
  91. int ret;
  92. unsigned long deadline;
  93. int todo;
  94. /* Receive data until we see the header byte */
  95. deadline = jiffies + msecs_to_jiffies(EC_MSG_DEADLINE_MS);
  96. do {
  97. memset(&trans, '\0', sizeof(trans));
  98. trans.cs_change = 1;
  99. trans.rx_buf = ptr = ec_dev->din;
  100. trans.len = EC_MSG_PREAMBLE_COUNT;
  101. spi_message_init(&msg);
  102. spi_message_add_tail(&trans, &msg);
  103. ret = spi_sync(ec_spi->spi, &msg);
  104. if (ret < 0) {
  105. dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
  106. return ret;
  107. }
  108. for (end = ptr + EC_MSG_PREAMBLE_COUNT; ptr != end; ptr++) {
  109. if (*ptr == EC_MSG_HEADER) {
  110. dev_dbg(ec_dev->dev, "msg found at %zd\n",
  111. ptr - ec_dev->din);
  112. break;
  113. }
  114. }
  115. if (time_after(jiffies, deadline)) {
  116. dev_warn(ec_dev->dev, "EC failed to respond in time\n");
  117. return -ETIMEDOUT;
  118. }
  119. } while (ptr == end);
  120. /*
  121. * ptr now points to the header byte. Copy any valid data to the
  122. * start of our buffer
  123. */
  124. todo = end - ++ptr;
  125. BUG_ON(todo < 0 || todo > ec_dev->din_size);
  126. todo = min(todo, need_len);
  127. memmove(ec_dev->din, ptr, todo);
  128. ptr = ec_dev->din + todo;
  129. dev_dbg(ec_dev->dev, "need %d, got %d bytes from preamble\n",
  130. need_len, todo);
  131. need_len -= todo;
  132. /* Receive data until we have it all */
  133. while (need_len > 0) {
  134. /*
  135. * We can't support transfers larger than the SPI FIFO size
  136. * unless we have DMA. We don't have DMA on the ISP SPI ports
  137. * for Exynos. We need a way of asking SPI driver for
  138. * maximum-supported transfer size.
  139. */
  140. todo = min(need_len, 256);
  141. dev_dbg(ec_dev->dev, "loop, todo=%d, need_len=%d, ptr=%zd\n",
  142. todo, need_len, ptr - ec_dev->din);
  143. memset(&trans, '\0', sizeof(trans));
  144. trans.cs_change = 1;
  145. trans.rx_buf = ptr;
  146. trans.len = todo;
  147. spi_message_init(&msg);
  148. spi_message_add_tail(&trans, &msg);
  149. /* send command to EC and read answer */
  150. BUG_ON((u8 *)trans.rx_buf - ec_dev->din + todo >
  151. ec_dev->din_size);
  152. ret = spi_sync(ec_spi->spi, &msg);
  153. if (ret < 0) {
  154. dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
  155. return ret;
  156. }
  157. debug_packet(ec_dev->dev, "interim", ptr, todo);
  158. ptr += todo;
  159. need_len -= todo;
  160. }
  161. dev_dbg(ec_dev->dev, "loop done, ptr=%zd\n", ptr - ec_dev->din);
  162. return 0;
  163. }
  164. /**
  165. * cros_ec_command_spi_xfer - Transfer a message over SPI and receive the reply
  166. *
  167. * @ec_dev: ChromeOS EC device
  168. * @ec_msg: Message to transfer
  169. */
  170. static int cros_ec_command_spi_xfer(struct cros_ec_device *ec_dev,
  171. struct cros_ec_msg *ec_msg)
  172. {
  173. struct cros_ec_spi *ec_spi = ec_dev->priv;
  174. struct spi_transfer trans;
  175. struct spi_message msg;
  176. int i, len;
  177. u8 *ptr;
  178. int sum;
  179. int ret = 0, final_ret;
  180. struct timespec ts;
  181. len = cros_ec_prepare_tx(ec_dev, ec_msg);
  182. dev_dbg(ec_dev->dev, "prepared, len=%d\n", len);
  183. /* If it's too soon to do another transaction, wait */
  184. if (ec_spi->last_transfer_ns) {
  185. struct timespec ts;
  186. unsigned long delay; /* The delay completed so far */
  187. ktime_get_ts(&ts);
  188. delay = timespec_to_ns(&ts) - ec_spi->last_transfer_ns;
  189. if (delay < EC_SPI_RECOVERY_TIME_NS)
  190. ndelay(delay);
  191. }
  192. /* Transmit phase - send our message */
  193. debug_packet(ec_dev->dev, "out", ec_dev->dout, len);
  194. memset(&trans, '\0', sizeof(trans));
  195. trans.tx_buf = ec_dev->dout;
  196. trans.len = len;
  197. trans.cs_change = 1;
  198. spi_message_init(&msg);
  199. spi_message_add_tail(&trans, &msg);
  200. ret = spi_sync(ec_spi->spi, &msg);
  201. /* Get the response */
  202. if (!ret) {
  203. ret = cros_ec_spi_receive_response(ec_dev,
  204. ec_msg->in_len + EC_MSG_TX_PROTO_BYTES);
  205. } else {
  206. dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
  207. }
  208. /* turn off CS */
  209. spi_message_init(&msg);
  210. final_ret = spi_sync(ec_spi->spi, &msg);
  211. ktime_get_ts(&ts);
  212. ec_spi->last_transfer_ns = timespec_to_ns(&ts);
  213. if (!ret)
  214. ret = final_ret;
  215. if (ret < 0) {
  216. dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
  217. return ret;
  218. }
  219. /* check response error code */
  220. ptr = ec_dev->din;
  221. if (ptr[0]) {
  222. dev_warn(ec_dev->dev, "command 0x%02x returned an error %d\n",
  223. ec_msg->cmd, ptr[0]);
  224. debug_packet(ec_dev->dev, "in_err", ptr, len);
  225. return -EINVAL;
  226. }
  227. len = ptr[1];
  228. sum = ptr[0] + ptr[1];
  229. if (len > ec_msg->in_len) {
  230. dev_err(ec_dev->dev, "packet too long (%d bytes, expected %d)",
  231. len, ec_msg->in_len);
  232. return -ENOSPC;
  233. }
  234. /* copy response packet payload and compute checksum */
  235. for (i = 0; i < len; i++) {
  236. sum += ptr[i + 2];
  237. if (ec_msg->in_len)
  238. ec_msg->in_buf[i] = ptr[i + 2];
  239. }
  240. sum &= 0xff;
  241. debug_packet(ec_dev->dev, "in", ptr, len + 3);
  242. if (sum != ptr[len + 2]) {
  243. dev_err(ec_dev->dev,
  244. "bad packet checksum, expected %02x, got %02x\n",
  245. sum, ptr[len + 2]);
  246. return -EBADMSG;
  247. }
  248. return 0;
  249. }
  250. static int cros_ec_probe_spi(struct spi_device *spi)
  251. {
  252. struct device *dev = &spi->dev;
  253. struct cros_ec_device *ec_dev;
  254. struct cros_ec_spi *ec_spi;
  255. int err;
  256. spi->bits_per_word = 8;
  257. spi->mode = SPI_MODE_0;
  258. err = spi_setup(spi);
  259. if (err < 0)
  260. return err;
  261. ec_spi = devm_kzalloc(dev, sizeof(*ec_spi), GFP_KERNEL);
  262. if (ec_spi == NULL)
  263. return -ENOMEM;
  264. ec_spi->spi = spi;
  265. ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL);
  266. if (!ec_dev)
  267. return -ENOMEM;
  268. spi_set_drvdata(spi, ec_dev);
  269. ec_dev->name = "SPI";
  270. ec_dev->dev = dev;
  271. ec_dev->priv = ec_spi;
  272. ec_dev->irq = spi->irq;
  273. ec_dev->command_xfer = cros_ec_command_spi_xfer;
  274. ec_dev->ec_name = ec_spi->spi->modalias;
  275. ec_dev->phys_name = dev_name(&ec_spi->spi->dev);
  276. ec_dev->parent = &ec_spi->spi->dev;
  277. ec_dev->din_size = EC_MSG_BYTES + EC_MSG_PREAMBLE_COUNT;
  278. ec_dev->dout_size = EC_MSG_BYTES;
  279. err = cros_ec_register(ec_dev);
  280. if (err) {
  281. dev_err(dev, "cannot register EC\n");
  282. return err;
  283. }
  284. return 0;
  285. }
  286. static int cros_ec_remove_spi(struct spi_device *spi)
  287. {
  288. struct cros_ec_device *ec_dev;
  289. ec_dev = spi_get_drvdata(spi);
  290. cros_ec_remove(ec_dev);
  291. return 0;
  292. }
  293. #ifdef CONFIG_PM_SLEEP
  294. static int cros_ec_spi_suspend(struct device *dev)
  295. {
  296. struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
  297. return cros_ec_suspend(ec_dev);
  298. }
  299. static int cros_ec_spi_resume(struct device *dev)
  300. {
  301. struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
  302. return cros_ec_resume(ec_dev);
  303. }
  304. #endif
  305. static SIMPLE_DEV_PM_OPS(cros_ec_spi_pm_ops, cros_ec_spi_suspend,
  306. cros_ec_spi_resume);
  307. static const struct spi_device_id cros_ec_spi_id[] = {
  308. { "cros-ec-spi", 0 },
  309. { }
  310. };
  311. MODULE_DEVICE_TABLE(spi, cros_ec_spi_id);
  312. static struct spi_driver cros_ec_driver_spi = {
  313. .driver = {
  314. .name = "cros-ec-spi",
  315. .owner = THIS_MODULE,
  316. .pm = &cros_ec_spi_pm_ops,
  317. },
  318. .probe = cros_ec_probe_spi,
  319. .remove = cros_ec_remove_spi,
  320. .id_table = cros_ec_spi_id,
  321. };
  322. module_spi_driver(cros_ec_driver_spi);
  323. MODULE_LICENSE("GPL");
  324. MODULE_DESCRIPTION("ChromeOS EC multi function device (SPI)");