ixgb_main.c 59 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238
  1. /*******************************************************************************
  2. Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  3. This program is free software; you can redistribute it and/or modify it
  4. under the terms of the GNU General Public License as published by the Free
  5. Software Foundation; either version 2 of the License, or (at your option)
  6. any later version.
  7. This program is distributed in the hope that it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc., 59
  13. Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. The full GNU General Public License is included in this distribution in the
  15. file called LICENSE.
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  19. *******************************************************************************/
  20. #include "ixgb.h"
  21. /* Change Log
  22. * 1.0.96 04/19/05
  23. * - Make needlessly global code static -- bunk@stusta.de
  24. * - ethtool cleanup -- shemminger@osdl.org
  25. * - Support for MODULE_VERSION -- linville@tuxdriver.com
  26. * - add skb_header_cloned check to the tso path -- herbert@apana.org.au
  27. * 1.0.88 01/05/05
  28. * - include fix to the condition that determines when to quit NAPI - Robert Olsson
  29. * - use netif_poll_{disable/enable} to synchronize between NAPI and i/f up/down
  30. * 1.0.84 10/26/04
  31. * - reset buffer_info->dma in Tx resource cleanup logic
  32. * 1.0.83 10/12/04
  33. * - sparse cleanup - shemminger@osdl.org
  34. * - fix tx resource cleanup logic
  35. */
  36. char ixgb_driver_name[] = "ixgb";
  37. static char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver";
  38. #ifndef CONFIG_IXGB_NAPI
  39. #define DRIVERNAPI
  40. #else
  41. #define DRIVERNAPI "-NAPI"
  42. #endif
  43. #define DRV_VERSION "1.0.104-k4"DRIVERNAPI
  44. char ixgb_driver_version[] = DRV_VERSION;
  45. static char ixgb_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
  46. /* ixgb_pci_tbl - PCI Device ID Table
  47. *
  48. * Wildcard entries (PCI_ANY_ID) should come last
  49. * Last entry must be all 0s
  50. *
  51. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  52. * Class, Class Mask, private data (not used) }
  53. */
  54. static struct pci_device_id ixgb_pci_tbl[] = {
  55. {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX,
  56. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  57. {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_CX4,
  58. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  59. {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_SR,
  60. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  61. {INTEL_VENDOR_ID, IXGB_DEVICE_ID_82597EX_LR,
  62. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  63. /* required last entry */
  64. {0,}
  65. };
  66. MODULE_DEVICE_TABLE(pci, ixgb_pci_tbl);
  67. /* Local Function Prototypes */
  68. int ixgb_up(struct ixgb_adapter *adapter);
  69. void ixgb_down(struct ixgb_adapter *adapter, boolean_t kill_watchdog);
  70. void ixgb_reset(struct ixgb_adapter *adapter);
  71. int ixgb_setup_tx_resources(struct ixgb_adapter *adapter);
  72. int ixgb_setup_rx_resources(struct ixgb_adapter *adapter);
  73. void ixgb_free_tx_resources(struct ixgb_adapter *adapter);
  74. void ixgb_free_rx_resources(struct ixgb_adapter *adapter);
  75. void ixgb_update_stats(struct ixgb_adapter *adapter);
  76. static int ixgb_init_module(void);
  77. static void ixgb_exit_module(void);
  78. static int ixgb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  79. static void __devexit ixgb_remove(struct pci_dev *pdev);
  80. static int ixgb_sw_init(struct ixgb_adapter *adapter);
  81. static int ixgb_open(struct net_device *netdev);
  82. static int ixgb_close(struct net_device *netdev);
  83. static void ixgb_configure_tx(struct ixgb_adapter *adapter);
  84. static void ixgb_configure_rx(struct ixgb_adapter *adapter);
  85. static void ixgb_setup_rctl(struct ixgb_adapter *adapter);
  86. static void ixgb_clean_tx_ring(struct ixgb_adapter *adapter);
  87. static void ixgb_clean_rx_ring(struct ixgb_adapter *adapter);
  88. static void ixgb_set_multi(struct net_device *netdev);
  89. static void ixgb_watchdog(unsigned long data);
  90. static int ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  91. static struct net_device_stats *ixgb_get_stats(struct net_device *netdev);
  92. static int ixgb_change_mtu(struct net_device *netdev, int new_mtu);
  93. static int ixgb_set_mac(struct net_device *netdev, void *p);
  94. static irqreturn_t ixgb_intr(int irq, void *data, struct pt_regs *regs);
  95. static boolean_t ixgb_clean_tx_irq(struct ixgb_adapter *adapter);
  96. #ifdef CONFIG_IXGB_NAPI
  97. static int ixgb_clean(struct net_device *netdev, int *budget);
  98. static boolean_t ixgb_clean_rx_irq(struct ixgb_adapter *adapter,
  99. int *work_done, int work_to_do);
  100. #else
  101. static boolean_t ixgb_clean_rx_irq(struct ixgb_adapter *adapter);
  102. #endif
  103. static void ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter);
  104. void ixgb_set_ethtool_ops(struct net_device *netdev);
  105. static void ixgb_tx_timeout(struct net_device *dev);
  106. static void ixgb_tx_timeout_task(struct net_device *dev);
  107. static void ixgb_vlan_rx_register(struct net_device *netdev,
  108. struct vlan_group *grp);
  109. static void ixgb_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
  110. static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
  111. static void ixgb_restore_vlan(struct ixgb_adapter *adapter);
  112. #ifdef CONFIG_NET_POLL_CONTROLLER
  113. /* for netdump / net console */
  114. static void ixgb_netpoll(struct net_device *dev);
  115. #endif
  116. /* Exported from other modules */
  117. extern void ixgb_check_options(struct ixgb_adapter *adapter);
  118. static struct pci_driver ixgb_driver = {
  119. .name = ixgb_driver_name,
  120. .id_table = ixgb_pci_tbl,
  121. .probe = ixgb_probe,
  122. .remove = __devexit_p(ixgb_remove),
  123. };
  124. MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
  125. MODULE_DESCRIPTION("Intel(R) PRO/10GbE Network Driver");
  126. MODULE_LICENSE("GPL");
  127. MODULE_VERSION(DRV_VERSION);
  128. #define DEFAULT_DEBUG_LEVEL_SHIFT 3
  129. static int debug = DEFAULT_DEBUG_LEVEL_SHIFT;
  130. module_param(debug, int, 0);
  131. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  132. /* some defines for controlling descriptor fetches in h/w */
  133. #define RXDCTL_WTHRESH_DEFAULT 16 /* chip writes back at this many or RXT0 */
  134. #define RXDCTL_PTHRESH_DEFAULT 0 /* chip considers prefech below
  135. * this */
  136. #define RXDCTL_HTHRESH_DEFAULT 0 /* chip will only prefetch if tail
  137. * is pushed this many descriptors
  138. * from head */
  139. /**
  140. * ixgb_init_module - Driver Registration Routine
  141. *
  142. * ixgb_init_module is the first routine called when the driver is
  143. * loaded. All it does is register with the PCI subsystem.
  144. **/
  145. static int __init
  146. ixgb_init_module(void)
  147. {
  148. printk(KERN_INFO "%s - version %s\n",
  149. ixgb_driver_string, ixgb_driver_version);
  150. printk(KERN_INFO "%s\n", ixgb_copyright);
  151. return pci_module_init(&ixgb_driver);
  152. }
  153. module_init(ixgb_init_module);
  154. /**
  155. * ixgb_exit_module - Driver Exit Cleanup Routine
  156. *
  157. * ixgb_exit_module is called just before the driver is removed
  158. * from memory.
  159. **/
  160. static void __exit
  161. ixgb_exit_module(void)
  162. {
  163. pci_unregister_driver(&ixgb_driver);
  164. }
  165. module_exit(ixgb_exit_module);
  166. /**
  167. * ixgb_irq_disable - Mask off interrupt generation on the NIC
  168. * @adapter: board private structure
  169. **/
  170. static inline void
  171. ixgb_irq_disable(struct ixgb_adapter *adapter)
  172. {
  173. atomic_inc(&adapter->irq_sem);
  174. IXGB_WRITE_REG(&adapter->hw, IMC, ~0);
  175. IXGB_WRITE_FLUSH(&adapter->hw);
  176. synchronize_irq(adapter->pdev->irq);
  177. }
  178. /**
  179. * ixgb_irq_enable - Enable default interrupt generation settings
  180. * @adapter: board private structure
  181. **/
  182. static inline void
  183. ixgb_irq_enable(struct ixgb_adapter *adapter)
  184. {
  185. if(atomic_dec_and_test(&adapter->irq_sem)) {
  186. IXGB_WRITE_REG(&adapter->hw, IMS,
  187. IXGB_INT_RXT0 | IXGB_INT_RXDMT0 | IXGB_INT_TXDW |
  188. IXGB_INT_LSC);
  189. IXGB_WRITE_FLUSH(&adapter->hw);
  190. }
  191. }
  192. int
  193. ixgb_up(struct ixgb_adapter *adapter)
  194. {
  195. struct net_device *netdev = adapter->netdev;
  196. int err;
  197. int max_frame = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
  198. struct ixgb_hw *hw = &adapter->hw;
  199. /* hardware has been reset, we need to reload some things */
  200. ixgb_rar_set(hw, netdev->dev_addr, 0);
  201. ixgb_set_multi(netdev);
  202. ixgb_restore_vlan(adapter);
  203. ixgb_configure_tx(adapter);
  204. ixgb_setup_rctl(adapter);
  205. ixgb_configure_rx(adapter);
  206. ixgb_alloc_rx_buffers(adapter);
  207. /* disable interrupts and get the hardware into a known state */
  208. IXGB_WRITE_REG(&adapter->hw, IMC, 0xffffffff);
  209. #ifdef CONFIG_PCI_MSI
  210. {
  211. boolean_t pcix = (IXGB_READ_REG(&adapter->hw, STATUS) &
  212. IXGB_STATUS_PCIX_MODE) ? TRUE : FALSE;
  213. adapter->have_msi = TRUE;
  214. if (!pcix)
  215. adapter->have_msi = FALSE;
  216. else if((err = pci_enable_msi(adapter->pdev))) {
  217. DPRINTK(PROBE, ERR,
  218. "Unable to allocate MSI interrupt Error: %d\n", err);
  219. adapter->have_msi = FALSE;
  220. /* proceed to try to request regular interrupt */
  221. }
  222. }
  223. #endif
  224. if((err = request_irq(adapter->pdev->irq, &ixgb_intr,
  225. SA_SHIRQ | SA_SAMPLE_RANDOM,
  226. netdev->name, netdev))) {
  227. DPRINTK(PROBE, ERR,
  228. "Unable to allocate interrupt Error: %d\n", err);
  229. return err;
  230. }
  231. if((hw->max_frame_size != max_frame) ||
  232. (hw->max_frame_size !=
  233. (IXGB_READ_REG(hw, MFS) >> IXGB_MFS_SHIFT))) {
  234. hw->max_frame_size = max_frame;
  235. IXGB_WRITE_REG(hw, MFS, hw->max_frame_size << IXGB_MFS_SHIFT);
  236. if(hw->max_frame_size >
  237. IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH) {
  238. uint32_t ctrl0 = IXGB_READ_REG(hw, CTRL0);
  239. if(!(ctrl0 & IXGB_CTRL0_JFE)) {
  240. ctrl0 |= IXGB_CTRL0_JFE;
  241. IXGB_WRITE_REG(hw, CTRL0, ctrl0);
  242. }
  243. }
  244. }
  245. mod_timer(&adapter->watchdog_timer, jiffies);
  246. #ifdef CONFIG_IXGB_NAPI
  247. netif_poll_enable(netdev);
  248. #endif
  249. ixgb_irq_enable(adapter);
  250. return 0;
  251. }
  252. void
  253. ixgb_down(struct ixgb_adapter *adapter, boolean_t kill_watchdog)
  254. {
  255. struct net_device *netdev = adapter->netdev;
  256. ixgb_irq_disable(adapter);
  257. free_irq(adapter->pdev->irq, netdev);
  258. #ifdef CONFIG_PCI_MSI
  259. if(adapter->have_msi == TRUE)
  260. pci_disable_msi(adapter->pdev);
  261. #endif
  262. if(kill_watchdog)
  263. del_timer_sync(&adapter->watchdog_timer);
  264. #ifdef CONFIG_IXGB_NAPI
  265. netif_poll_disable(netdev);
  266. #endif
  267. adapter->link_speed = 0;
  268. adapter->link_duplex = 0;
  269. netif_carrier_off(netdev);
  270. netif_stop_queue(netdev);
  271. ixgb_reset(adapter);
  272. ixgb_clean_tx_ring(adapter);
  273. ixgb_clean_rx_ring(adapter);
  274. }
  275. void
  276. ixgb_reset(struct ixgb_adapter *adapter)
  277. {
  278. ixgb_adapter_stop(&adapter->hw);
  279. if(!ixgb_init_hw(&adapter->hw))
  280. DPRINTK(PROBE, ERR, "ixgb_init_hw failed.\n");
  281. }
  282. /**
  283. * ixgb_probe - Device Initialization Routine
  284. * @pdev: PCI device information struct
  285. * @ent: entry in ixgb_pci_tbl
  286. *
  287. * Returns 0 on success, negative on failure
  288. *
  289. * ixgb_probe initializes an adapter identified by a pci_dev structure.
  290. * The OS initialization, configuring of the adapter private structure,
  291. * and a hardware reset occur.
  292. **/
  293. static int __devinit
  294. ixgb_probe(struct pci_dev *pdev,
  295. const struct pci_device_id *ent)
  296. {
  297. struct net_device *netdev = NULL;
  298. struct ixgb_adapter *adapter;
  299. static int cards_found = 0;
  300. unsigned long mmio_start;
  301. int mmio_len;
  302. int pci_using_dac;
  303. int i;
  304. int err;
  305. if((err = pci_enable_device(pdev)))
  306. return err;
  307. if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
  308. !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
  309. pci_using_dac = 1;
  310. } else {
  311. if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
  312. (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
  313. printk(KERN_ERR
  314. "ixgb: No usable DMA configuration, aborting\n");
  315. goto err_dma_mask;
  316. }
  317. pci_using_dac = 0;
  318. }
  319. if((err = pci_request_regions(pdev, ixgb_driver_name)))
  320. goto err_request_regions;
  321. pci_set_master(pdev);
  322. netdev = alloc_etherdev(sizeof(struct ixgb_adapter));
  323. if(!netdev) {
  324. err = -ENOMEM;
  325. goto err_alloc_etherdev;
  326. }
  327. SET_MODULE_OWNER(netdev);
  328. SET_NETDEV_DEV(netdev, &pdev->dev);
  329. pci_set_drvdata(pdev, netdev);
  330. adapter = netdev_priv(netdev);
  331. adapter->netdev = netdev;
  332. adapter->pdev = pdev;
  333. adapter->hw.back = adapter;
  334. adapter->msg_enable = netif_msg_init(debug, DEFAULT_DEBUG_LEVEL_SHIFT);
  335. mmio_start = pci_resource_start(pdev, BAR_0);
  336. mmio_len = pci_resource_len(pdev, BAR_0);
  337. adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
  338. if(!adapter->hw.hw_addr) {
  339. err = -EIO;
  340. goto err_ioremap;
  341. }
  342. for(i = BAR_1; i <= BAR_5; i++) {
  343. if(pci_resource_len(pdev, i) == 0)
  344. continue;
  345. if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  346. adapter->hw.io_base = pci_resource_start(pdev, i);
  347. break;
  348. }
  349. }
  350. netdev->open = &ixgb_open;
  351. netdev->stop = &ixgb_close;
  352. netdev->hard_start_xmit = &ixgb_xmit_frame;
  353. netdev->get_stats = &ixgb_get_stats;
  354. netdev->set_multicast_list = &ixgb_set_multi;
  355. netdev->set_mac_address = &ixgb_set_mac;
  356. netdev->change_mtu = &ixgb_change_mtu;
  357. ixgb_set_ethtool_ops(netdev);
  358. netdev->tx_timeout = &ixgb_tx_timeout;
  359. netdev->watchdog_timeo = 5 * HZ;
  360. #ifdef CONFIG_IXGB_NAPI
  361. netdev->poll = &ixgb_clean;
  362. netdev->weight = 64;
  363. #endif
  364. netdev->vlan_rx_register = ixgb_vlan_rx_register;
  365. netdev->vlan_rx_add_vid = ixgb_vlan_rx_add_vid;
  366. netdev->vlan_rx_kill_vid = ixgb_vlan_rx_kill_vid;
  367. #ifdef CONFIG_NET_POLL_CONTROLLER
  368. netdev->poll_controller = ixgb_netpoll;
  369. #endif
  370. strcpy(netdev->name, pci_name(pdev));
  371. netdev->mem_start = mmio_start;
  372. netdev->mem_end = mmio_start + mmio_len;
  373. netdev->base_addr = adapter->hw.io_base;
  374. adapter->bd_number = cards_found;
  375. adapter->link_speed = 0;
  376. adapter->link_duplex = 0;
  377. /* setup the private structure */
  378. if((err = ixgb_sw_init(adapter)))
  379. goto err_sw_init;
  380. netdev->features = NETIF_F_SG |
  381. NETIF_F_HW_CSUM |
  382. NETIF_F_HW_VLAN_TX |
  383. NETIF_F_HW_VLAN_RX |
  384. NETIF_F_HW_VLAN_FILTER;
  385. #ifdef NETIF_F_TSO
  386. netdev->features |= NETIF_F_TSO;
  387. #endif
  388. #ifdef NETIF_F_LLTX
  389. netdev->features |= NETIF_F_LLTX;
  390. #endif
  391. if(pci_using_dac)
  392. netdev->features |= NETIF_F_HIGHDMA;
  393. /* make sure the EEPROM is good */
  394. if(!ixgb_validate_eeprom_checksum(&adapter->hw)) {
  395. DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
  396. err = -EIO;
  397. goto err_eeprom;
  398. }
  399. ixgb_get_ee_mac_addr(&adapter->hw, netdev->dev_addr);
  400. memcpy(netdev->perm_addr, netdev->dev_addr, netdev->addr_len);
  401. if(!is_valid_ether_addr(netdev->perm_addr)) {
  402. DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
  403. err = -EIO;
  404. goto err_eeprom;
  405. }
  406. adapter->part_num = ixgb_get_ee_pba_number(&adapter->hw);
  407. init_timer(&adapter->watchdog_timer);
  408. adapter->watchdog_timer.function = &ixgb_watchdog;
  409. adapter->watchdog_timer.data = (unsigned long)adapter;
  410. INIT_WORK(&adapter->tx_timeout_task,
  411. (void (*)(void *))ixgb_tx_timeout_task, netdev);
  412. strcpy(netdev->name, "eth%d");
  413. if((err = register_netdev(netdev)))
  414. goto err_register;
  415. /* we're going to reset, so assume we have no link for now */
  416. netif_carrier_off(netdev);
  417. netif_stop_queue(netdev);
  418. DPRINTK(PROBE, INFO, "Intel(R) PRO/10GbE Network Connection\n");
  419. ixgb_check_options(adapter);
  420. /* reset the hardware with the new settings */
  421. ixgb_reset(adapter);
  422. cards_found++;
  423. return 0;
  424. err_register:
  425. err_sw_init:
  426. err_eeprom:
  427. iounmap(adapter->hw.hw_addr);
  428. err_ioremap:
  429. free_netdev(netdev);
  430. err_alloc_etherdev:
  431. pci_release_regions(pdev);
  432. err_request_regions:
  433. err_dma_mask:
  434. pci_disable_device(pdev);
  435. return err;
  436. }
  437. /**
  438. * ixgb_remove - Device Removal Routine
  439. * @pdev: PCI device information struct
  440. *
  441. * ixgb_remove is called by the PCI subsystem to alert the driver
  442. * that it should release a PCI device. The could be caused by a
  443. * Hot-Plug event, or because the driver is going to be removed from
  444. * memory.
  445. **/
  446. static void __devexit
  447. ixgb_remove(struct pci_dev *pdev)
  448. {
  449. struct net_device *netdev = pci_get_drvdata(pdev);
  450. struct ixgb_adapter *adapter = netdev_priv(netdev);
  451. unregister_netdev(netdev);
  452. iounmap(adapter->hw.hw_addr);
  453. pci_release_regions(pdev);
  454. free_netdev(netdev);
  455. }
  456. /**
  457. * ixgb_sw_init - Initialize general software structures (struct ixgb_adapter)
  458. * @adapter: board private structure to initialize
  459. *
  460. * ixgb_sw_init initializes the Adapter private data structure.
  461. * Fields are initialized based on PCI device information and
  462. * OS network device settings (MTU size).
  463. **/
  464. static int __devinit
  465. ixgb_sw_init(struct ixgb_adapter *adapter)
  466. {
  467. struct ixgb_hw *hw = &adapter->hw;
  468. struct net_device *netdev = adapter->netdev;
  469. struct pci_dev *pdev = adapter->pdev;
  470. /* PCI config space info */
  471. hw->vendor_id = pdev->vendor;
  472. hw->device_id = pdev->device;
  473. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  474. hw->subsystem_id = pdev->subsystem_device;
  475. adapter->rx_buffer_len = IXGB_RXBUFFER_2048;
  476. hw->max_frame_size = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
  477. if((hw->device_id == IXGB_DEVICE_ID_82597EX)
  478. || (hw->device_id == IXGB_DEVICE_ID_82597EX_CX4)
  479. || (hw->device_id == IXGB_DEVICE_ID_82597EX_LR)
  480. || (hw->device_id == IXGB_DEVICE_ID_82597EX_SR))
  481. hw->mac_type = ixgb_82597;
  482. else {
  483. /* should never have loaded on this device */
  484. DPRINTK(PROBE, ERR, "unsupported device id\n");
  485. }
  486. /* enable flow control to be programmed */
  487. hw->fc.send_xon = 1;
  488. atomic_set(&adapter->irq_sem, 1);
  489. spin_lock_init(&adapter->tx_lock);
  490. return 0;
  491. }
  492. /**
  493. * ixgb_open - Called when a network interface is made active
  494. * @netdev: network interface device structure
  495. *
  496. * Returns 0 on success, negative value on failure
  497. *
  498. * The open entry point is called when a network interface is made
  499. * active by the system (IFF_UP). At this point all resources needed
  500. * for transmit and receive operations are allocated, the interrupt
  501. * handler is registered with the OS, the watchdog timer is started,
  502. * and the stack is notified that the interface is ready.
  503. **/
  504. static int
  505. ixgb_open(struct net_device *netdev)
  506. {
  507. struct ixgb_adapter *adapter = netdev_priv(netdev);
  508. int err;
  509. /* allocate transmit descriptors */
  510. if((err = ixgb_setup_tx_resources(adapter)))
  511. goto err_setup_tx;
  512. /* allocate receive descriptors */
  513. if((err = ixgb_setup_rx_resources(adapter)))
  514. goto err_setup_rx;
  515. if((err = ixgb_up(adapter)))
  516. goto err_up;
  517. return 0;
  518. err_up:
  519. ixgb_free_rx_resources(adapter);
  520. err_setup_rx:
  521. ixgb_free_tx_resources(adapter);
  522. err_setup_tx:
  523. ixgb_reset(adapter);
  524. return err;
  525. }
  526. /**
  527. * ixgb_close - Disables a network interface
  528. * @netdev: network interface device structure
  529. *
  530. * Returns 0, this is not allowed to fail
  531. *
  532. * The close entry point is called when an interface is de-activated
  533. * by the OS. The hardware is still under the drivers control, but
  534. * needs to be disabled. A global MAC reset is issued to stop the
  535. * hardware, and all transmit and receive resources are freed.
  536. **/
  537. static int
  538. ixgb_close(struct net_device *netdev)
  539. {
  540. struct ixgb_adapter *adapter = netdev_priv(netdev);
  541. ixgb_down(adapter, TRUE);
  542. ixgb_free_tx_resources(adapter);
  543. ixgb_free_rx_resources(adapter);
  544. return 0;
  545. }
  546. /**
  547. * ixgb_setup_tx_resources - allocate Tx resources (Descriptors)
  548. * @adapter: board private structure
  549. *
  550. * Return 0 on success, negative on failure
  551. **/
  552. int
  553. ixgb_setup_tx_resources(struct ixgb_adapter *adapter)
  554. {
  555. struct ixgb_desc_ring *txdr = &adapter->tx_ring;
  556. struct pci_dev *pdev = adapter->pdev;
  557. int size;
  558. size = sizeof(struct ixgb_buffer) * txdr->count;
  559. txdr->buffer_info = vmalloc(size);
  560. if(!txdr->buffer_info) {
  561. DPRINTK(PROBE, ERR,
  562. "Unable to allocate transmit descriptor ring memory\n");
  563. return -ENOMEM;
  564. }
  565. memset(txdr->buffer_info, 0, size);
  566. /* round up to nearest 4K */
  567. txdr->size = txdr->count * sizeof(struct ixgb_tx_desc);
  568. IXGB_ROUNDUP(txdr->size, 4096);
  569. txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
  570. if(!txdr->desc) {
  571. vfree(txdr->buffer_info);
  572. DPRINTK(PROBE, ERR,
  573. "Unable to allocate transmit descriptor memory\n");
  574. return -ENOMEM;
  575. }
  576. memset(txdr->desc, 0, txdr->size);
  577. txdr->next_to_use = 0;
  578. txdr->next_to_clean = 0;
  579. return 0;
  580. }
  581. /**
  582. * ixgb_configure_tx - Configure 82597 Transmit Unit after Reset.
  583. * @adapter: board private structure
  584. *
  585. * Configure the Tx unit of the MAC after a reset.
  586. **/
  587. static void
  588. ixgb_configure_tx(struct ixgb_adapter *adapter)
  589. {
  590. uint64_t tdba = adapter->tx_ring.dma;
  591. uint32_t tdlen = adapter->tx_ring.count * sizeof(struct ixgb_tx_desc);
  592. uint32_t tctl;
  593. struct ixgb_hw *hw = &adapter->hw;
  594. /* Setup the Base and Length of the Tx Descriptor Ring
  595. * tx_ring.dma can be either a 32 or 64 bit value
  596. */
  597. IXGB_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
  598. IXGB_WRITE_REG(hw, TDBAH, (tdba >> 32));
  599. IXGB_WRITE_REG(hw, TDLEN, tdlen);
  600. /* Setup the HW Tx Head and Tail descriptor pointers */
  601. IXGB_WRITE_REG(hw, TDH, 0);
  602. IXGB_WRITE_REG(hw, TDT, 0);
  603. /* don't set up txdctl, it induces performance problems if configured
  604. * incorrectly */
  605. /* Set the Tx Interrupt Delay register */
  606. IXGB_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
  607. /* Program the Transmit Control Register */
  608. tctl = IXGB_TCTL_TCE | IXGB_TCTL_TXEN | IXGB_TCTL_TPDE;
  609. IXGB_WRITE_REG(hw, TCTL, tctl);
  610. /* Setup Transmit Descriptor Settings for this adapter */
  611. adapter->tx_cmd_type =
  612. IXGB_TX_DESC_TYPE
  613. | (adapter->tx_int_delay_enable ? IXGB_TX_DESC_CMD_IDE : 0);
  614. }
  615. /**
  616. * ixgb_setup_rx_resources - allocate Rx resources (Descriptors)
  617. * @adapter: board private structure
  618. *
  619. * Returns 0 on success, negative on failure
  620. **/
  621. int
  622. ixgb_setup_rx_resources(struct ixgb_adapter *adapter)
  623. {
  624. struct ixgb_desc_ring *rxdr = &adapter->rx_ring;
  625. struct pci_dev *pdev = adapter->pdev;
  626. int size;
  627. size = sizeof(struct ixgb_buffer) * rxdr->count;
  628. rxdr->buffer_info = vmalloc(size);
  629. if(!rxdr->buffer_info) {
  630. DPRINTK(PROBE, ERR,
  631. "Unable to allocate receive descriptor ring\n");
  632. return -ENOMEM;
  633. }
  634. memset(rxdr->buffer_info, 0, size);
  635. /* Round up to nearest 4K */
  636. rxdr->size = rxdr->count * sizeof(struct ixgb_rx_desc);
  637. IXGB_ROUNDUP(rxdr->size, 4096);
  638. rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
  639. if(!rxdr->desc) {
  640. vfree(rxdr->buffer_info);
  641. DPRINTK(PROBE, ERR,
  642. "Unable to allocate receive descriptors\n");
  643. return -ENOMEM;
  644. }
  645. memset(rxdr->desc, 0, rxdr->size);
  646. rxdr->next_to_clean = 0;
  647. rxdr->next_to_use = 0;
  648. return 0;
  649. }
  650. /**
  651. * ixgb_setup_rctl - configure the receive control register
  652. * @adapter: Board private structure
  653. **/
  654. static void
  655. ixgb_setup_rctl(struct ixgb_adapter *adapter)
  656. {
  657. uint32_t rctl;
  658. rctl = IXGB_READ_REG(&adapter->hw, RCTL);
  659. rctl &= ~(3 << IXGB_RCTL_MO_SHIFT);
  660. rctl |=
  661. IXGB_RCTL_BAM | IXGB_RCTL_RDMTS_1_2 |
  662. IXGB_RCTL_RXEN | IXGB_RCTL_CFF |
  663. (adapter->hw.mc_filter_type << IXGB_RCTL_MO_SHIFT);
  664. rctl |= IXGB_RCTL_SECRC;
  665. switch (adapter->rx_buffer_len) {
  666. case IXGB_RXBUFFER_2048:
  667. default:
  668. rctl |= IXGB_RCTL_BSIZE_2048;
  669. break;
  670. case IXGB_RXBUFFER_4096:
  671. rctl |= IXGB_RCTL_BSIZE_4096;
  672. break;
  673. case IXGB_RXBUFFER_8192:
  674. rctl |= IXGB_RCTL_BSIZE_8192;
  675. break;
  676. case IXGB_RXBUFFER_16384:
  677. rctl |= IXGB_RCTL_BSIZE_16384;
  678. break;
  679. }
  680. IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
  681. }
  682. /**
  683. * ixgb_configure_rx - Configure 82597 Receive Unit after Reset.
  684. * @adapter: board private structure
  685. *
  686. * Configure the Rx unit of the MAC after a reset.
  687. **/
  688. static void
  689. ixgb_configure_rx(struct ixgb_adapter *adapter)
  690. {
  691. uint64_t rdba = adapter->rx_ring.dma;
  692. uint32_t rdlen = adapter->rx_ring.count * sizeof(struct ixgb_rx_desc);
  693. struct ixgb_hw *hw = &adapter->hw;
  694. uint32_t rctl;
  695. uint32_t rxcsum;
  696. uint32_t rxdctl;
  697. /* make sure receives are disabled while setting up the descriptors */
  698. rctl = IXGB_READ_REG(hw, RCTL);
  699. IXGB_WRITE_REG(hw, RCTL, rctl & ~IXGB_RCTL_RXEN);
  700. /* set the Receive Delay Timer Register */
  701. IXGB_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
  702. /* Setup the Base and Length of the Rx Descriptor Ring */
  703. IXGB_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
  704. IXGB_WRITE_REG(hw, RDBAH, (rdba >> 32));
  705. IXGB_WRITE_REG(hw, RDLEN, rdlen);
  706. /* Setup the HW Rx Head and Tail Descriptor Pointers */
  707. IXGB_WRITE_REG(hw, RDH, 0);
  708. IXGB_WRITE_REG(hw, RDT, 0);
  709. /* set up pre-fetching of receive buffers so we get some before we
  710. * run out (default hardware behavior is to run out before fetching
  711. * more). This sets up to fetch if HTHRESH rx descriptors are avail
  712. * and the descriptors in hw cache are below PTHRESH. This avoids
  713. * the hardware behavior of fetching <=512 descriptors in a single
  714. * burst that pre-empts all other activity, usually causing fifo
  715. * overflows. */
  716. /* use WTHRESH to burst write 16 descriptors or burst when RXT0 */
  717. rxdctl = RXDCTL_WTHRESH_DEFAULT << IXGB_RXDCTL_WTHRESH_SHIFT |
  718. RXDCTL_HTHRESH_DEFAULT << IXGB_RXDCTL_HTHRESH_SHIFT |
  719. RXDCTL_PTHRESH_DEFAULT << IXGB_RXDCTL_PTHRESH_SHIFT;
  720. IXGB_WRITE_REG(hw, RXDCTL, rxdctl);
  721. /* Enable Receive Checksum Offload for TCP and UDP */
  722. if(adapter->rx_csum == TRUE) {
  723. rxcsum = IXGB_READ_REG(hw, RXCSUM);
  724. rxcsum |= IXGB_RXCSUM_TUOFL;
  725. IXGB_WRITE_REG(hw, RXCSUM, rxcsum);
  726. }
  727. /* Enable Receives */
  728. IXGB_WRITE_REG(hw, RCTL, rctl);
  729. }
  730. /**
  731. * ixgb_free_tx_resources - Free Tx Resources
  732. * @adapter: board private structure
  733. *
  734. * Free all transmit software resources
  735. **/
  736. void
  737. ixgb_free_tx_resources(struct ixgb_adapter *adapter)
  738. {
  739. struct pci_dev *pdev = adapter->pdev;
  740. ixgb_clean_tx_ring(adapter);
  741. vfree(adapter->tx_ring.buffer_info);
  742. adapter->tx_ring.buffer_info = NULL;
  743. pci_free_consistent(pdev, adapter->tx_ring.size,
  744. adapter->tx_ring.desc, adapter->tx_ring.dma);
  745. adapter->tx_ring.desc = NULL;
  746. }
  747. static inline void
  748. ixgb_unmap_and_free_tx_resource(struct ixgb_adapter *adapter,
  749. struct ixgb_buffer *buffer_info)
  750. {
  751. struct pci_dev *pdev = adapter->pdev;
  752. if (buffer_info->dma)
  753. pci_unmap_page(pdev, buffer_info->dma, buffer_info->length,
  754. PCI_DMA_TODEVICE);
  755. if (buffer_info->skb)
  756. dev_kfree_skb_any(buffer_info->skb);
  757. buffer_info->skb = NULL;
  758. buffer_info->dma = 0;
  759. buffer_info->time_stamp = 0;
  760. /* these fields must always be initialized in tx
  761. * buffer_info->length = 0;
  762. * buffer_info->next_to_watch = 0; */
  763. }
  764. /**
  765. * ixgb_clean_tx_ring - Free Tx Buffers
  766. * @adapter: board private structure
  767. **/
  768. static void
  769. ixgb_clean_tx_ring(struct ixgb_adapter *adapter)
  770. {
  771. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  772. struct ixgb_buffer *buffer_info;
  773. unsigned long size;
  774. unsigned int i;
  775. /* Free all the Tx ring sk_buffs */
  776. for(i = 0; i < tx_ring->count; i++) {
  777. buffer_info = &tx_ring->buffer_info[i];
  778. ixgb_unmap_and_free_tx_resource(adapter, buffer_info);
  779. }
  780. size = sizeof(struct ixgb_buffer) * tx_ring->count;
  781. memset(tx_ring->buffer_info, 0, size);
  782. /* Zero out the descriptor ring */
  783. memset(tx_ring->desc, 0, tx_ring->size);
  784. tx_ring->next_to_use = 0;
  785. tx_ring->next_to_clean = 0;
  786. IXGB_WRITE_REG(&adapter->hw, TDH, 0);
  787. IXGB_WRITE_REG(&adapter->hw, TDT, 0);
  788. }
  789. /**
  790. * ixgb_free_rx_resources - Free Rx Resources
  791. * @adapter: board private structure
  792. *
  793. * Free all receive software resources
  794. **/
  795. void
  796. ixgb_free_rx_resources(struct ixgb_adapter *adapter)
  797. {
  798. struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
  799. struct pci_dev *pdev = adapter->pdev;
  800. ixgb_clean_rx_ring(adapter);
  801. vfree(rx_ring->buffer_info);
  802. rx_ring->buffer_info = NULL;
  803. pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
  804. rx_ring->desc = NULL;
  805. }
  806. /**
  807. * ixgb_clean_rx_ring - Free Rx Buffers
  808. * @adapter: board private structure
  809. **/
  810. static void
  811. ixgb_clean_rx_ring(struct ixgb_adapter *adapter)
  812. {
  813. struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
  814. struct ixgb_buffer *buffer_info;
  815. struct pci_dev *pdev = adapter->pdev;
  816. unsigned long size;
  817. unsigned int i;
  818. /* Free all the Rx ring sk_buffs */
  819. for(i = 0; i < rx_ring->count; i++) {
  820. buffer_info = &rx_ring->buffer_info[i];
  821. if(buffer_info->skb) {
  822. pci_unmap_single(pdev,
  823. buffer_info->dma,
  824. buffer_info->length,
  825. PCI_DMA_FROMDEVICE);
  826. dev_kfree_skb(buffer_info->skb);
  827. buffer_info->skb = NULL;
  828. }
  829. }
  830. size = sizeof(struct ixgb_buffer) * rx_ring->count;
  831. memset(rx_ring->buffer_info, 0, size);
  832. /* Zero out the descriptor ring */
  833. memset(rx_ring->desc, 0, rx_ring->size);
  834. rx_ring->next_to_clean = 0;
  835. rx_ring->next_to_use = 0;
  836. IXGB_WRITE_REG(&adapter->hw, RDH, 0);
  837. IXGB_WRITE_REG(&adapter->hw, RDT, 0);
  838. }
  839. /**
  840. * ixgb_set_mac - Change the Ethernet Address of the NIC
  841. * @netdev: network interface device structure
  842. * @p: pointer to an address structure
  843. *
  844. * Returns 0 on success, negative on failure
  845. **/
  846. static int
  847. ixgb_set_mac(struct net_device *netdev, void *p)
  848. {
  849. struct ixgb_adapter *adapter = netdev_priv(netdev);
  850. struct sockaddr *addr = p;
  851. if(!is_valid_ether_addr(addr->sa_data))
  852. return -EADDRNOTAVAIL;
  853. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  854. ixgb_rar_set(&adapter->hw, addr->sa_data, 0);
  855. return 0;
  856. }
  857. /**
  858. * ixgb_set_multi - Multicast and Promiscuous mode set
  859. * @netdev: network interface device structure
  860. *
  861. * The set_multi entry point is called whenever the multicast address
  862. * list or the network interface flags are updated. This routine is
  863. * responsible for configuring the hardware for proper multicast,
  864. * promiscuous mode, and all-multi behavior.
  865. **/
  866. static void
  867. ixgb_set_multi(struct net_device *netdev)
  868. {
  869. struct ixgb_adapter *adapter = netdev_priv(netdev);
  870. struct ixgb_hw *hw = &adapter->hw;
  871. struct dev_mc_list *mc_ptr;
  872. uint32_t rctl;
  873. int i;
  874. /* Check for Promiscuous and All Multicast modes */
  875. rctl = IXGB_READ_REG(hw, RCTL);
  876. if(netdev->flags & IFF_PROMISC) {
  877. rctl |= (IXGB_RCTL_UPE | IXGB_RCTL_MPE);
  878. } else if(netdev->flags & IFF_ALLMULTI) {
  879. rctl |= IXGB_RCTL_MPE;
  880. rctl &= ~IXGB_RCTL_UPE;
  881. } else {
  882. rctl &= ~(IXGB_RCTL_UPE | IXGB_RCTL_MPE);
  883. }
  884. if(netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES) {
  885. rctl |= IXGB_RCTL_MPE;
  886. IXGB_WRITE_REG(hw, RCTL, rctl);
  887. } else {
  888. uint8_t mta[netdev->mc_count * IXGB_ETH_LENGTH_OF_ADDRESS];
  889. IXGB_WRITE_REG(hw, RCTL, rctl);
  890. for(i = 0, mc_ptr = netdev->mc_list; mc_ptr;
  891. i++, mc_ptr = mc_ptr->next)
  892. memcpy(&mta[i * IXGB_ETH_LENGTH_OF_ADDRESS],
  893. mc_ptr->dmi_addr, IXGB_ETH_LENGTH_OF_ADDRESS);
  894. ixgb_mc_addr_list_update(hw, mta, netdev->mc_count, 0);
  895. }
  896. }
  897. /**
  898. * ixgb_watchdog - Timer Call-back
  899. * @data: pointer to netdev cast into an unsigned long
  900. **/
  901. static void
  902. ixgb_watchdog(unsigned long data)
  903. {
  904. struct ixgb_adapter *adapter = (struct ixgb_adapter *)data;
  905. struct net_device *netdev = adapter->netdev;
  906. struct ixgb_desc_ring *txdr = &adapter->tx_ring;
  907. ixgb_check_for_link(&adapter->hw);
  908. if (ixgb_check_for_bad_link(&adapter->hw)) {
  909. /* force the reset path */
  910. netif_stop_queue(netdev);
  911. }
  912. if(adapter->hw.link_up) {
  913. if(!netif_carrier_ok(netdev)) {
  914. DPRINTK(LINK, INFO,
  915. "NIC Link is Up 10000 Mbps Full Duplex\n");
  916. adapter->link_speed = 10000;
  917. adapter->link_duplex = FULL_DUPLEX;
  918. netif_carrier_on(netdev);
  919. netif_wake_queue(netdev);
  920. }
  921. } else {
  922. if(netif_carrier_ok(netdev)) {
  923. adapter->link_speed = 0;
  924. adapter->link_duplex = 0;
  925. DPRINTK(LINK, INFO, "NIC Link is Down\n");
  926. netif_carrier_off(netdev);
  927. netif_stop_queue(netdev);
  928. }
  929. }
  930. ixgb_update_stats(adapter);
  931. if(!netif_carrier_ok(netdev)) {
  932. if(IXGB_DESC_UNUSED(txdr) + 1 < txdr->count) {
  933. /* We've lost link, so the controller stops DMA,
  934. * but we've got queued Tx work that's never going
  935. * to get done, so reset controller to flush Tx.
  936. * (Do the reset outside of interrupt context). */
  937. schedule_work(&adapter->tx_timeout_task);
  938. }
  939. }
  940. /* Force detection of hung controller every watchdog period */
  941. adapter->detect_tx_hung = TRUE;
  942. /* generate an interrupt to force clean up of any stragglers */
  943. IXGB_WRITE_REG(&adapter->hw, ICS, IXGB_INT_TXDW);
  944. /* Reset the timer */
  945. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  946. }
  947. #define IXGB_TX_FLAGS_CSUM 0x00000001
  948. #define IXGB_TX_FLAGS_VLAN 0x00000002
  949. #define IXGB_TX_FLAGS_TSO 0x00000004
  950. static inline int
  951. ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
  952. {
  953. #ifdef NETIF_F_TSO
  954. struct ixgb_context_desc *context_desc;
  955. unsigned int i;
  956. uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
  957. uint16_t ipcse, tucse, mss;
  958. int err;
  959. if(likely(skb_shinfo(skb)->tso_size)) {
  960. if (skb_header_cloned(skb)) {
  961. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  962. if (err)
  963. return err;
  964. }
  965. hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
  966. mss = skb_shinfo(skb)->tso_size;
  967. skb->nh.iph->tot_len = 0;
  968. skb->nh.iph->check = 0;
  969. skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr,
  970. skb->nh.iph->daddr,
  971. 0, IPPROTO_TCP, 0);
  972. ipcss = skb->nh.raw - skb->data;
  973. ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
  974. ipcse = skb->h.raw - skb->data - 1;
  975. tucss = skb->h.raw - skb->data;
  976. tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
  977. tucse = 0;
  978. i = adapter->tx_ring.next_to_use;
  979. context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
  980. context_desc->ipcss = ipcss;
  981. context_desc->ipcso = ipcso;
  982. context_desc->ipcse = cpu_to_le16(ipcse);
  983. context_desc->tucss = tucss;
  984. context_desc->tucso = tucso;
  985. context_desc->tucse = cpu_to_le16(tucse);
  986. context_desc->mss = cpu_to_le16(mss);
  987. context_desc->hdr_len = hdr_len;
  988. context_desc->status = 0;
  989. context_desc->cmd_type_len = cpu_to_le32(
  990. IXGB_CONTEXT_DESC_TYPE
  991. | IXGB_CONTEXT_DESC_CMD_TSE
  992. | IXGB_CONTEXT_DESC_CMD_IP
  993. | IXGB_CONTEXT_DESC_CMD_TCP
  994. | IXGB_CONTEXT_DESC_CMD_IDE
  995. | (skb->len - (hdr_len)));
  996. if(++i == adapter->tx_ring.count) i = 0;
  997. adapter->tx_ring.next_to_use = i;
  998. return 1;
  999. }
  1000. #endif
  1001. return 0;
  1002. }
  1003. static inline boolean_t
  1004. ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
  1005. {
  1006. struct ixgb_context_desc *context_desc;
  1007. unsigned int i;
  1008. uint8_t css, cso;
  1009. if(likely(skb->ip_summed == CHECKSUM_HW)) {
  1010. css = skb->h.raw - skb->data;
  1011. cso = (skb->h.raw + skb->csum) - skb->data;
  1012. i = adapter->tx_ring.next_to_use;
  1013. context_desc = IXGB_CONTEXT_DESC(adapter->tx_ring, i);
  1014. context_desc->tucss = css;
  1015. context_desc->tucso = cso;
  1016. context_desc->tucse = 0;
  1017. /* zero out any previously existing data in one instruction */
  1018. *(uint32_t *)&(context_desc->ipcss) = 0;
  1019. context_desc->status = 0;
  1020. context_desc->hdr_len = 0;
  1021. context_desc->mss = 0;
  1022. context_desc->cmd_type_len =
  1023. cpu_to_le32(IXGB_CONTEXT_DESC_TYPE
  1024. | IXGB_TX_DESC_CMD_IDE);
  1025. if(++i == adapter->tx_ring.count) i = 0;
  1026. adapter->tx_ring.next_to_use = i;
  1027. return TRUE;
  1028. }
  1029. return FALSE;
  1030. }
  1031. #define IXGB_MAX_TXD_PWR 14
  1032. #define IXGB_MAX_DATA_PER_TXD (1<<IXGB_MAX_TXD_PWR)
  1033. static inline int
  1034. ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
  1035. unsigned int first)
  1036. {
  1037. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  1038. struct ixgb_buffer *buffer_info;
  1039. int len = skb->len;
  1040. unsigned int offset = 0, size, count = 0, i;
  1041. unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
  1042. unsigned int f;
  1043. len -= skb->data_len;
  1044. i = tx_ring->next_to_use;
  1045. while(len) {
  1046. buffer_info = &tx_ring->buffer_info[i];
  1047. size = min(len, IXGB_MAX_JUMBO_FRAME_SIZE);
  1048. buffer_info->length = size;
  1049. buffer_info->dma =
  1050. pci_map_single(adapter->pdev,
  1051. skb->data + offset,
  1052. size,
  1053. PCI_DMA_TODEVICE);
  1054. buffer_info->time_stamp = jiffies;
  1055. buffer_info->next_to_watch = 0;
  1056. len -= size;
  1057. offset += size;
  1058. count++;
  1059. if(++i == tx_ring->count) i = 0;
  1060. }
  1061. for(f = 0; f < nr_frags; f++) {
  1062. struct skb_frag_struct *frag;
  1063. frag = &skb_shinfo(skb)->frags[f];
  1064. len = frag->size;
  1065. offset = 0;
  1066. while(len) {
  1067. buffer_info = &tx_ring->buffer_info[i];
  1068. size = min(len, IXGB_MAX_JUMBO_FRAME_SIZE);
  1069. buffer_info->length = size;
  1070. buffer_info->dma =
  1071. pci_map_page(adapter->pdev,
  1072. frag->page,
  1073. frag->page_offset + offset,
  1074. size,
  1075. PCI_DMA_TODEVICE);
  1076. buffer_info->time_stamp = jiffies;
  1077. buffer_info->next_to_watch = 0;
  1078. len -= size;
  1079. offset += size;
  1080. count++;
  1081. if(++i == tx_ring->count) i = 0;
  1082. }
  1083. }
  1084. i = (i == 0) ? tx_ring->count - 1 : i - 1;
  1085. tx_ring->buffer_info[i].skb = skb;
  1086. tx_ring->buffer_info[first].next_to_watch = i;
  1087. return count;
  1088. }
  1089. static inline void
  1090. ixgb_tx_queue(struct ixgb_adapter *adapter, int count, int vlan_id,int tx_flags)
  1091. {
  1092. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  1093. struct ixgb_tx_desc *tx_desc = NULL;
  1094. struct ixgb_buffer *buffer_info;
  1095. uint32_t cmd_type_len = adapter->tx_cmd_type;
  1096. uint8_t status = 0;
  1097. uint8_t popts = 0;
  1098. unsigned int i;
  1099. if(tx_flags & IXGB_TX_FLAGS_TSO) {
  1100. cmd_type_len |= IXGB_TX_DESC_CMD_TSE;
  1101. popts |= (IXGB_TX_DESC_POPTS_IXSM | IXGB_TX_DESC_POPTS_TXSM);
  1102. }
  1103. if(tx_flags & IXGB_TX_FLAGS_CSUM)
  1104. popts |= IXGB_TX_DESC_POPTS_TXSM;
  1105. if(tx_flags & IXGB_TX_FLAGS_VLAN) {
  1106. cmd_type_len |= IXGB_TX_DESC_CMD_VLE;
  1107. }
  1108. i = tx_ring->next_to_use;
  1109. while(count--) {
  1110. buffer_info = &tx_ring->buffer_info[i];
  1111. tx_desc = IXGB_TX_DESC(*tx_ring, i);
  1112. tx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
  1113. tx_desc->cmd_type_len =
  1114. cpu_to_le32(cmd_type_len | buffer_info->length);
  1115. tx_desc->status = status;
  1116. tx_desc->popts = popts;
  1117. tx_desc->vlan = cpu_to_le16(vlan_id);
  1118. if(++i == tx_ring->count) i = 0;
  1119. }
  1120. tx_desc->cmd_type_len |= cpu_to_le32(IXGB_TX_DESC_CMD_EOP
  1121. | IXGB_TX_DESC_CMD_RS );
  1122. /* Force memory writes to complete before letting h/w
  1123. * know there are new descriptors to fetch. (Only
  1124. * applicable for weak-ordered memory model archs,
  1125. * such as IA-64). */
  1126. wmb();
  1127. tx_ring->next_to_use = i;
  1128. IXGB_WRITE_REG(&adapter->hw, TDT, i);
  1129. }
  1130. /* Tx Descriptors needed, worst case */
  1131. #define TXD_USE_COUNT(S) (((S) >> IXGB_MAX_TXD_PWR) + \
  1132. (((S) & (IXGB_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
  1133. #define DESC_NEEDED TXD_USE_COUNT(IXGB_MAX_DATA_PER_TXD) + \
  1134. MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1
  1135. static int
  1136. ixgb_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  1137. {
  1138. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1139. unsigned int first;
  1140. unsigned int tx_flags = 0;
  1141. unsigned long flags;
  1142. int vlan_id = 0;
  1143. int tso;
  1144. if(skb->len <= 0) {
  1145. dev_kfree_skb_any(skb);
  1146. return 0;
  1147. }
  1148. #ifdef NETIF_F_LLTX
  1149. local_irq_save(flags);
  1150. if (!spin_trylock(&adapter->tx_lock)) {
  1151. /* Collision - tell upper layer to requeue */
  1152. local_irq_restore(flags);
  1153. return NETDEV_TX_LOCKED;
  1154. }
  1155. #else
  1156. spin_lock_irqsave(&adapter->tx_lock, flags);
  1157. #endif
  1158. if(unlikely(IXGB_DESC_UNUSED(&adapter->tx_ring) < DESC_NEEDED)) {
  1159. netif_stop_queue(netdev);
  1160. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1161. return NETDEV_TX_BUSY;
  1162. }
  1163. #ifndef NETIF_F_LLTX
  1164. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1165. #endif
  1166. if(adapter->vlgrp && vlan_tx_tag_present(skb)) {
  1167. tx_flags |= IXGB_TX_FLAGS_VLAN;
  1168. vlan_id = vlan_tx_tag_get(skb);
  1169. }
  1170. first = adapter->tx_ring.next_to_use;
  1171. tso = ixgb_tso(adapter, skb);
  1172. if (tso < 0) {
  1173. dev_kfree_skb_any(skb);
  1174. #ifdef NETIF_F_LLTX
  1175. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1176. #endif
  1177. return NETDEV_TX_OK;
  1178. }
  1179. if (likely(tso))
  1180. tx_flags |= IXGB_TX_FLAGS_TSO;
  1181. else if(ixgb_tx_csum(adapter, skb))
  1182. tx_flags |= IXGB_TX_FLAGS_CSUM;
  1183. ixgb_tx_queue(adapter, ixgb_tx_map(adapter, skb, first), vlan_id,
  1184. tx_flags);
  1185. netdev->trans_start = jiffies;
  1186. #ifdef NETIF_F_LLTX
  1187. /* Make sure there is space in the ring for the next send. */
  1188. if(unlikely(IXGB_DESC_UNUSED(&adapter->tx_ring) < DESC_NEEDED))
  1189. netif_stop_queue(netdev);
  1190. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1191. #endif
  1192. return NETDEV_TX_OK;
  1193. }
  1194. /**
  1195. * ixgb_tx_timeout - Respond to a Tx Hang
  1196. * @netdev: network interface device structure
  1197. **/
  1198. static void
  1199. ixgb_tx_timeout(struct net_device *netdev)
  1200. {
  1201. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1202. /* Do the reset outside of interrupt context */
  1203. schedule_work(&adapter->tx_timeout_task);
  1204. }
  1205. static void
  1206. ixgb_tx_timeout_task(struct net_device *netdev)
  1207. {
  1208. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1209. adapter->tx_timeout_count++;
  1210. ixgb_down(adapter, TRUE);
  1211. ixgb_up(adapter);
  1212. }
  1213. /**
  1214. * ixgb_get_stats - Get System Network Statistics
  1215. * @netdev: network interface device structure
  1216. *
  1217. * Returns the address of the device statistics structure.
  1218. * The statistics are actually updated from the timer callback.
  1219. **/
  1220. static struct net_device_stats *
  1221. ixgb_get_stats(struct net_device *netdev)
  1222. {
  1223. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1224. return &adapter->net_stats;
  1225. }
  1226. /**
  1227. * ixgb_change_mtu - Change the Maximum Transfer Unit
  1228. * @netdev: network interface device structure
  1229. * @new_mtu: new value for maximum frame size
  1230. *
  1231. * Returns 0 on success, negative on failure
  1232. **/
  1233. static int
  1234. ixgb_change_mtu(struct net_device *netdev, int new_mtu)
  1235. {
  1236. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1237. int max_frame = new_mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
  1238. int old_max_frame = netdev->mtu + ENET_HEADER_SIZE + ENET_FCS_LENGTH;
  1239. if((max_frame < IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH)
  1240. || (max_frame > IXGB_MAX_JUMBO_FRAME_SIZE + ENET_FCS_LENGTH)) {
  1241. DPRINTK(PROBE, ERR, "Invalid MTU setting %d\n", new_mtu);
  1242. return -EINVAL;
  1243. }
  1244. if((max_frame <= IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS + ENET_FCS_LENGTH)
  1245. || (max_frame <= IXGB_RXBUFFER_2048)) {
  1246. adapter->rx_buffer_len = IXGB_RXBUFFER_2048;
  1247. } else if(max_frame <= IXGB_RXBUFFER_4096) {
  1248. adapter->rx_buffer_len = IXGB_RXBUFFER_4096;
  1249. } else if(max_frame <= IXGB_RXBUFFER_8192) {
  1250. adapter->rx_buffer_len = IXGB_RXBUFFER_8192;
  1251. } else {
  1252. adapter->rx_buffer_len = IXGB_RXBUFFER_16384;
  1253. }
  1254. netdev->mtu = new_mtu;
  1255. if(old_max_frame != max_frame && netif_running(netdev)) {
  1256. ixgb_down(adapter, TRUE);
  1257. ixgb_up(adapter);
  1258. }
  1259. return 0;
  1260. }
  1261. /**
  1262. * ixgb_update_stats - Update the board statistics counters.
  1263. * @adapter: board private structure
  1264. **/
  1265. void
  1266. ixgb_update_stats(struct ixgb_adapter *adapter)
  1267. {
  1268. struct net_device *netdev = adapter->netdev;
  1269. if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) ||
  1270. (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) {
  1271. u64 multi = IXGB_READ_REG(&adapter->hw, MPRCL);
  1272. u32 bcast_l = IXGB_READ_REG(&adapter->hw, BPRCL);
  1273. u32 bcast_h = IXGB_READ_REG(&adapter->hw, BPRCH);
  1274. u64 bcast = ((u64)bcast_h << 32) | bcast_l;
  1275. multi |= ((u64)IXGB_READ_REG(&adapter->hw, MPRCH) << 32);
  1276. /* fix up multicast stats by removing broadcasts */
  1277. if(multi >= bcast)
  1278. multi -= bcast;
  1279. adapter->stats.mprcl += (multi & 0xFFFFFFFF);
  1280. adapter->stats.mprch += (multi >> 32);
  1281. adapter->stats.bprcl += bcast_l;
  1282. adapter->stats.bprch += bcast_h;
  1283. } else {
  1284. adapter->stats.mprcl += IXGB_READ_REG(&adapter->hw, MPRCL);
  1285. adapter->stats.mprch += IXGB_READ_REG(&adapter->hw, MPRCH);
  1286. adapter->stats.bprcl += IXGB_READ_REG(&adapter->hw, BPRCL);
  1287. adapter->stats.bprch += IXGB_READ_REG(&adapter->hw, BPRCH);
  1288. }
  1289. adapter->stats.tprl += IXGB_READ_REG(&adapter->hw, TPRL);
  1290. adapter->stats.tprh += IXGB_READ_REG(&adapter->hw, TPRH);
  1291. adapter->stats.gprcl += IXGB_READ_REG(&adapter->hw, GPRCL);
  1292. adapter->stats.gprch += IXGB_READ_REG(&adapter->hw, GPRCH);
  1293. adapter->stats.uprcl += IXGB_READ_REG(&adapter->hw, UPRCL);
  1294. adapter->stats.uprch += IXGB_READ_REG(&adapter->hw, UPRCH);
  1295. adapter->stats.vprcl += IXGB_READ_REG(&adapter->hw, VPRCL);
  1296. adapter->stats.vprch += IXGB_READ_REG(&adapter->hw, VPRCH);
  1297. adapter->stats.jprcl += IXGB_READ_REG(&adapter->hw, JPRCL);
  1298. adapter->stats.jprch += IXGB_READ_REG(&adapter->hw, JPRCH);
  1299. adapter->stats.gorcl += IXGB_READ_REG(&adapter->hw, GORCL);
  1300. adapter->stats.gorch += IXGB_READ_REG(&adapter->hw, GORCH);
  1301. adapter->stats.torl += IXGB_READ_REG(&adapter->hw, TORL);
  1302. adapter->stats.torh += IXGB_READ_REG(&adapter->hw, TORH);
  1303. adapter->stats.rnbc += IXGB_READ_REG(&adapter->hw, RNBC);
  1304. adapter->stats.ruc += IXGB_READ_REG(&adapter->hw, RUC);
  1305. adapter->stats.roc += IXGB_READ_REG(&adapter->hw, ROC);
  1306. adapter->stats.rlec += IXGB_READ_REG(&adapter->hw, RLEC);
  1307. adapter->stats.crcerrs += IXGB_READ_REG(&adapter->hw, CRCERRS);
  1308. adapter->stats.icbc += IXGB_READ_REG(&adapter->hw, ICBC);
  1309. adapter->stats.ecbc += IXGB_READ_REG(&adapter->hw, ECBC);
  1310. adapter->stats.mpc += IXGB_READ_REG(&adapter->hw, MPC);
  1311. adapter->stats.tptl += IXGB_READ_REG(&adapter->hw, TPTL);
  1312. adapter->stats.tpth += IXGB_READ_REG(&adapter->hw, TPTH);
  1313. adapter->stats.gptcl += IXGB_READ_REG(&adapter->hw, GPTCL);
  1314. adapter->stats.gptch += IXGB_READ_REG(&adapter->hw, GPTCH);
  1315. adapter->stats.bptcl += IXGB_READ_REG(&adapter->hw, BPTCL);
  1316. adapter->stats.bptch += IXGB_READ_REG(&adapter->hw, BPTCH);
  1317. adapter->stats.mptcl += IXGB_READ_REG(&adapter->hw, MPTCL);
  1318. adapter->stats.mptch += IXGB_READ_REG(&adapter->hw, MPTCH);
  1319. adapter->stats.uptcl += IXGB_READ_REG(&adapter->hw, UPTCL);
  1320. adapter->stats.uptch += IXGB_READ_REG(&adapter->hw, UPTCH);
  1321. adapter->stats.vptcl += IXGB_READ_REG(&adapter->hw, VPTCL);
  1322. adapter->stats.vptch += IXGB_READ_REG(&adapter->hw, VPTCH);
  1323. adapter->stats.jptcl += IXGB_READ_REG(&adapter->hw, JPTCL);
  1324. adapter->stats.jptch += IXGB_READ_REG(&adapter->hw, JPTCH);
  1325. adapter->stats.gotcl += IXGB_READ_REG(&adapter->hw, GOTCL);
  1326. adapter->stats.gotch += IXGB_READ_REG(&adapter->hw, GOTCH);
  1327. adapter->stats.totl += IXGB_READ_REG(&adapter->hw, TOTL);
  1328. adapter->stats.toth += IXGB_READ_REG(&adapter->hw, TOTH);
  1329. adapter->stats.dc += IXGB_READ_REG(&adapter->hw, DC);
  1330. adapter->stats.plt64c += IXGB_READ_REG(&adapter->hw, PLT64C);
  1331. adapter->stats.tsctc += IXGB_READ_REG(&adapter->hw, TSCTC);
  1332. adapter->stats.tsctfc += IXGB_READ_REG(&adapter->hw, TSCTFC);
  1333. adapter->stats.ibic += IXGB_READ_REG(&adapter->hw, IBIC);
  1334. adapter->stats.rfc += IXGB_READ_REG(&adapter->hw, RFC);
  1335. adapter->stats.lfc += IXGB_READ_REG(&adapter->hw, LFC);
  1336. adapter->stats.pfrc += IXGB_READ_REG(&adapter->hw, PFRC);
  1337. adapter->stats.pftc += IXGB_READ_REG(&adapter->hw, PFTC);
  1338. adapter->stats.mcfrc += IXGB_READ_REG(&adapter->hw, MCFRC);
  1339. adapter->stats.mcftc += IXGB_READ_REG(&adapter->hw, MCFTC);
  1340. adapter->stats.xonrxc += IXGB_READ_REG(&adapter->hw, XONRXC);
  1341. adapter->stats.xontxc += IXGB_READ_REG(&adapter->hw, XONTXC);
  1342. adapter->stats.xoffrxc += IXGB_READ_REG(&adapter->hw, XOFFRXC);
  1343. adapter->stats.xofftxc += IXGB_READ_REG(&adapter->hw, XOFFTXC);
  1344. adapter->stats.rjc += IXGB_READ_REG(&adapter->hw, RJC);
  1345. /* Fill out the OS statistics structure */
  1346. adapter->net_stats.rx_packets = adapter->stats.gprcl;
  1347. adapter->net_stats.tx_packets = adapter->stats.gptcl;
  1348. adapter->net_stats.rx_bytes = adapter->stats.gorcl;
  1349. adapter->net_stats.tx_bytes = adapter->stats.gotcl;
  1350. adapter->net_stats.multicast = adapter->stats.mprcl;
  1351. adapter->net_stats.collisions = 0;
  1352. /* ignore RLEC as it reports errors for padded (<64bytes) frames
  1353. * with a length in the type/len field */
  1354. adapter->net_stats.rx_errors =
  1355. /* adapter->stats.rnbc + */ adapter->stats.crcerrs +
  1356. adapter->stats.ruc +
  1357. adapter->stats.roc /*+ adapter->stats.rlec */ +
  1358. adapter->stats.icbc +
  1359. adapter->stats.ecbc + adapter->stats.mpc;
  1360. /* see above
  1361. * adapter->net_stats.rx_length_errors = adapter->stats.rlec;
  1362. */
  1363. adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
  1364. adapter->net_stats.rx_fifo_errors = adapter->stats.mpc;
  1365. adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
  1366. adapter->net_stats.rx_over_errors = adapter->stats.mpc;
  1367. adapter->net_stats.tx_errors = 0;
  1368. adapter->net_stats.rx_frame_errors = 0;
  1369. adapter->net_stats.tx_aborted_errors = 0;
  1370. adapter->net_stats.tx_carrier_errors = 0;
  1371. adapter->net_stats.tx_fifo_errors = 0;
  1372. adapter->net_stats.tx_heartbeat_errors = 0;
  1373. adapter->net_stats.tx_window_errors = 0;
  1374. }
  1375. #define IXGB_MAX_INTR 10
  1376. /**
  1377. * ixgb_intr - Interrupt Handler
  1378. * @irq: interrupt number
  1379. * @data: pointer to a network interface device structure
  1380. * @pt_regs: CPU registers structure
  1381. **/
  1382. static irqreturn_t
  1383. ixgb_intr(int irq, void *data, struct pt_regs *regs)
  1384. {
  1385. struct net_device *netdev = data;
  1386. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1387. struct ixgb_hw *hw = &adapter->hw;
  1388. uint32_t icr = IXGB_READ_REG(hw, ICR);
  1389. #ifndef CONFIG_IXGB_NAPI
  1390. unsigned int i;
  1391. #endif
  1392. if(unlikely(!icr))
  1393. return IRQ_NONE; /* Not our interrupt */
  1394. if(unlikely(icr & (IXGB_INT_RXSEQ | IXGB_INT_LSC))) {
  1395. mod_timer(&adapter->watchdog_timer, jiffies);
  1396. }
  1397. #ifdef CONFIG_IXGB_NAPI
  1398. if(netif_rx_schedule_prep(netdev)) {
  1399. /* Disable interrupts and register for poll. The flush
  1400. of the posted write is intentionally left out.
  1401. */
  1402. atomic_inc(&adapter->irq_sem);
  1403. IXGB_WRITE_REG(&adapter->hw, IMC, ~0);
  1404. __netif_rx_schedule(netdev);
  1405. }
  1406. #else
  1407. /* yes, that is actually a & and it is meant to make sure that
  1408. * every pass through this for loop checks both receive and
  1409. * transmit queues for completed descriptors, intended to
  1410. * avoid starvation issues and assist tx/rx fairness. */
  1411. for(i = 0; i < IXGB_MAX_INTR; i++)
  1412. if(!ixgb_clean_rx_irq(adapter) &
  1413. !ixgb_clean_tx_irq(adapter))
  1414. break;
  1415. #endif
  1416. return IRQ_HANDLED;
  1417. }
  1418. #ifdef CONFIG_IXGB_NAPI
  1419. /**
  1420. * ixgb_clean - NAPI Rx polling callback
  1421. * @adapter: board private structure
  1422. **/
  1423. static int
  1424. ixgb_clean(struct net_device *netdev, int *budget)
  1425. {
  1426. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1427. int work_to_do = min(*budget, netdev->quota);
  1428. int tx_cleaned;
  1429. int work_done = 0;
  1430. tx_cleaned = ixgb_clean_tx_irq(adapter);
  1431. ixgb_clean_rx_irq(adapter, &work_done, work_to_do);
  1432. *budget -= work_done;
  1433. netdev->quota -= work_done;
  1434. /* if no Tx and not enough Rx work done, exit the polling mode */
  1435. if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
  1436. netif_rx_complete(netdev);
  1437. ixgb_irq_enable(adapter);
  1438. return 0;
  1439. }
  1440. return 1;
  1441. }
  1442. #endif
  1443. /**
  1444. * ixgb_clean_tx_irq - Reclaim resources after transmit completes
  1445. * @adapter: board private structure
  1446. **/
  1447. static boolean_t
  1448. ixgb_clean_tx_irq(struct ixgb_adapter *adapter)
  1449. {
  1450. struct ixgb_desc_ring *tx_ring = &adapter->tx_ring;
  1451. struct net_device *netdev = adapter->netdev;
  1452. struct ixgb_tx_desc *tx_desc, *eop_desc;
  1453. struct ixgb_buffer *buffer_info;
  1454. unsigned int i, eop;
  1455. boolean_t cleaned = FALSE;
  1456. i = tx_ring->next_to_clean;
  1457. eop = tx_ring->buffer_info[i].next_to_watch;
  1458. eop_desc = IXGB_TX_DESC(*tx_ring, eop);
  1459. while(eop_desc->status & IXGB_TX_DESC_STATUS_DD) {
  1460. for(cleaned = FALSE; !cleaned; ) {
  1461. tx_desc = IXGB_TX_DESC(*tx_ring, i);
  1462. buffer_info = &tx_ring->buffer_info[i];
  1463. if (tx_desc->popts
  1464. & (IXGB_TX_DESC_POPTS_TXSM |
  1465. IXGB_TX_DESC_POPTS_IXSM))
  1466. adapter->hw_csum_tx_good++;
  1467. ixgb_unmap_and_free_tx_resource(adapter, buffer_info);
  1468. *(uint32_t *)&(tx_desc->status) = 0;
  1469. cleaned = (i == eop);
  1470. if(++i == tx_ring->count) i = 0;
  1471. }
  1472. eop = tx_ring->buffer_info[i].next_to_watch;
  1473. eop_desc = IXGB_TX_DESC(*tx_ring, eop);
  1474. }
  1475. tx_ring->next_to_clean = i;
  1476. spin_lock(&adapter->tx_lock);
  1477. if(cleaned && netif_queue_stopped(netdev) && netif_carrier_ok(netdev) &&
  1478. (IXGB_DESC_UNUSED(tx_ring) > IXGB_TX_QUEUE_WAKE)) {
  1479. netif_wake_queue(netdev);
  1480. }
  1481. spin_unlock(&adapter->tx_lock);
  1482. if(adapter->detect_tx_hung) {
  1483. /* detect a transmit hang in hardware, this serializes the
  1484. * check with the clearing of time_stamp and movement of i */
  1485. adapter->detect_tx_hung = FALSE;
  1486. if (tx_ring->buffer_info[eop].dma &&
  1487. time_after(jiffies, tx_ring->buffer_info[eop].time_stamp + HZ)
  1488. && !(IXGB_READ_REG(&adapter->hw, STATUS) &
  1489. IXGB_STATUS_TXOFF)) {
  1490. /* detected Tx unit hang */
  1491. DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
  1492. " TDH <%x>\n"
  1493. " TDT <%x>\n"
  1494. " next_to_use <%x>\n"
  1495. " next_to_clean <%x>\n"
  1496. "buffer_info[next_to_clean]\n"
  1497. " time_stamp <%lx>\n"
  1498. " next_to_watch <%x>\n"
  1499. " jiffies <%lx>\n"
  1500. " next_to_watch.status <%x>\n",
  1501. IXGB_READ_REG(&adapter->hw, TDH),
  1502. IXGB_READ_REG(&adapter->hw, TDT),
  1503. tx_ring->next_to_use,
  1504. tx_ring->next_to_clean,
  1505. tx_ring->buffer_info[eop].time_stamp,
  1506. eop,
  1507. jiffies,
  1508. eop_desc->status);
  1509. netif_stop_queue(netdev);
  1510. }
  1511. }
  1512. return cleaned;
  1513. }
  1514. /**
  1515. * ixgb_rx_checksum - Receive Checksum Offload for 82597.
  1516. * @adapter: board private structure
  1517. * @rx_desc: receive descriptor
  1518. * @sk_buff: socket buffer with received data
  1519. **/
  1520. static inline void
  1521. ixgb_rx_checksum(struct ixgb_adapter *adapter,
  1522. struct ixgb_rx_desc *rx_desc,
  1523. struct sk_buff *skb)
  1524. {
  1525. /* Ignore Checksum bit is set OR
  1526. * TCP Checksum has not been calculated
  1527. */
  1528. if((rx_desc->status & IXGB_RX_DESC_STATUS_IXSM) ||
  1529. (!(rx_desc->status & IXGB_RX_DESC_STATUS_TCPCS))) {
  1530. skb->ip_summed = CHECKSUM_NONE;
  1531. return;
  1532. }
  1533. /* At this point we know the hardware did the TCP checksum */
  1534. /* now look at the TCP checksum error bit */
  1535. if(rx_desc->errors & IXGB_RX_DESC_ERRORS_TCPE) {
  1536. /* let the stack verify checksum errors */
  1537. skb->ip_summed = CHECKSUM_NONE;
  1538. adapter->hw_csum_rx_error++;
  1539. } else {
  1540. /* TCP checksum is good */
  1541. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1542. adapter->hw_csum_rx_good++;
  1543. }
  1544. }
  1545. /**
  1546. * ixgb_clean_rx_irq - Send received data up the network stack,
  1547. * @adapter: board private structure
  1548. **/
  1549. static boolean_t
  1550. #ifdef CONFIG_IXGB_NAPI
  1551. ixgb_clean_rx_irq(struct ixgb_adapter *adapter, int *work_done, int work_to_do)
  1552. #else
  1553. ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
  1554. #endif
  1555. {
  1556. struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
  1557. struct net_device *netdev = adapter->netdev;
  1558. struct pci_dev *pdev = adapter->pdev;
  1559. struct ixgb_rx_desc *rx_desc, *next_rxd;
  1560. struct ixgb_buffer *buffer_info, *next_buffer, *next2_buffer;
  1561. uint32_t length;
  1562. unsigned int i, j;
  1563. boolean_t cleaned = FALSE;
  1564. i = rx_ring->next_to_clean;
  1565. rx_desc = IXGB_RX_DESC(*rx_ring, i);
  1566. buffer_info = &rx_ring->buffer_info[i];
  1567. while(rx_desc->status & IXGB_RX_DESC_STATUS_DD) {
  1568. struct sk_buff *skb, *next_skb;
  1569. u8 status;
  1570. #ifdef CONFIG_IXGB_NAPI
  1571. if(*work_done >= work_to_do)
  1572. break;
  1573. (*work_done)++;
  1574. #endif
  1575. status = rx_desc->status;
  1576. skb = buffer_info->skb;
  1577. buffer_info->skb = NULL;
  1578. prefetch(skb->data);
  1579. if(++i == rx_ring->count) i = 0;
  1580. next_rxd = IXGB_RX_DESC(*rx_ring, i);
  1581. prefetch(next_rxd);
  1582. if((j = i + 1) == rx_ring->count) j = 0;
  1583. next2_buffer = &rx_ring->buffer_info[j];
  1584. prefetch(next2_buffer);
  1585. next_buffer = &rx_ring->buffer_info[i];
  1586. next_skb = next_buffer->skb;
  1587. prefetch(next_skb);
  1588. cleaned = TRUE;
  1589. pci_unmap_single(pdev,
  1590. buffer_info->dma,
  1591. buffer_info->length,
  1592. PCI_DMA_FROMDEVICE);
  1593. length = le16_to_cpu(rx_desc->length);
  1594. if(unlikely(!(status & IXGB_RX_DESC_STATUS_EOP))) {
  1595. /* All receives must fit into a single buffer */
  1596. IXGB_DBG("Receive packet consumed multiple buffers "
  1597. "length<%x>\n", length);
  1598. dev_kfree_skb_irq(skb);
  1599. goto rxdesc_done;
  1600. }
  1601. if (unlikely(rx_desc->errors
  1602. & (IXGB_RX_DESC_ERRORS_CE | IXGB_RX_DESC_ERRORS_SE
  1603. | IXGB_RX_DESC_ERRORS_P |
  1604. IXGB_RX_DESC_ERRORS_RXE))) {
  1605. dev_kfree_skb_irq(skb);
  1606. goto rxdesc_done;
  1607. }
  1608. /* code added for copybreak, this should improve
  1609. * performance for small packets with large amounts
  1610. * of reassembly being done in the stack */
  1611. #define IXGB_CB_LENGTH 256
  1612. if (length < IXGB_CB_LENGTH) {
  1613. struct sk_buff *new_skb =
  1614. dev_alloc_skb(length + NET_IP_ALIGN);
  1615. if (new_skb) {
  1616. skb_reserve(new_skb, NET_IP_ALIGN);
  1617. new_skb->dev = netdev;
  1618. memcpy(new_skb->data - NET_IP_ALIGN,
  1619. skb->data - NET_IP_ALIGN,
  1620. length + NET_IP_ALIGN);
  1621. /* save the skb in buffer_info as good */
  1622. buffer_info->skb = skb;
  1623. skb = new_skb;
  1624. }
  1625. }
  1626. /* end copybreak code */
  1627. /* Good Receive */
  1628. skb_put(skb, length);
  1629. /* Receive Checksum Offload */
  1630. ixgb_rx_checksum(adapter, rx_desc, skb);
  1631. skb->protocol = eth_type_trans(skb, netdev);
  1632. #ifdef CONFIG_IXGB_NAPI
  1633. if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
  1634. vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
  1635. le16_to_cpu(rx_desc->special) &
  1636. IXGB_RX_DESC_SPECIAL_VLAN_MASK);
  1637. } else {
  1638. netif_receive_skb(skb);
  1639. }
  1640. #else /* CONFIG_IXGB_NAPI */
  1641. if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
  1642. vlan_hwaccel_rx(skb, adapter->vlgrp,
  1643. le16_to_cpu(rx_desc->special) &
  1644. IXGB_RX_DESC_SPECIAL_VLAN_MASK);
  1645. } else {
  1646. netif_rx(skb);
  1647. }
  1648. #endif /* CONFIG_IXGB_NAPI */
  1649. netdev->last_rx = jiffies;
  1650. rxdesc_done:
  1651. /* clean up descriptor, might be written over by hw */
  1652. rx_desc->status = 0;
  1653. /* use prefetched values */
  1654. rx_desc = next_rxd;
  1655. buffer_info = next_buffer;
  1656. }
  1657. rx_ring->next_to_clean = i;
  1658. ixgb_alloc_rx_buffers(adapter);
  1659. return cleaned;
  1660. }
  1661. /**
  1662. * ixgb_alloc_rx_buffers - Replace used receive buffers
  1663. * @adapter: address of board private structure
  1664. **/
  1665. static void
  1666. ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
  1667. {
  1668. struct ixgb_desc_ring *rx_ring = &adapter->rx_ring;
  1669. struct net_device *netdev = adapter->netdev;
  1670. struct pci_dev *pdev = adapter->pdev;
  1671. struct ixgb_rx_desc *rx_desc;
  1672. struct ixgb_buffer *buffer_info;
  1673. struct sk_buff *skb;
  1674. unsigned int i;
  1675. int num_group_tail_writes;
  1676. long cleancount;
  1677. i = rx_ring->next_to_use;
  1678. buffer_info = &rx_ring->buffer_info[i];
  1679. cleancount = IXGB_DESC_UNUSED(rx_ring);
  1680. num_group_tail_writes = IXGB_RX_BUFFER_WRITE;
  1681. /* leave three descriptors unused */
  1682. while(--cleancount > 2) {
  1683. /* recycle! its good for you */
  1684. if (!(skb = buffer_info->skb))
  1685. skb = dev_alloc_skb(adapter->rx_buffer_len
  1686. + NET_IP_ALIGN);
  1687. else {
  1688. skb_trim(skb, 0);
  1689. goto map_skb;
  1690. }
  1691. if (unlikely(!skb)) {
  1692. /* Better luck next round */
  1693. adapter->alloc_rx_buff_failed++;
  1694. break;
  1695. }
  1696. /* Make buffer alignment 2 beyond a 16 byte boundary
  1697. * this will result in a 16 byte aligned IP header after
  1698. * the 14 byte MAC header is removed
  1699. */
  1700. skb_reserve(skb, NET_IP_ALIGN);
  1701. skb->dev = netdev;
  1702. buffer_info->skb = skb;
  1703. buffer_info->length = adapter->rx_buffer_len;
  1704. map_skb:
  1705. buffer_info->dma = pci_map_single(pdev,
  1706. skb->data,
  1707. adapter->rx_buffer_len,
  1708. PCI_DMA_FROMDEVICE);
  1709. rx_desc = IXGB_RX_DESC(*rx_ring, i);
  1710. rx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
  1711. /* guarantee DD bit not set now before h/w gets descriptor
  1712. * this is the rest of the workaround for h/w double
  1713. * writeback. */
  1714. rx_desc->status = 0;
  1715. if(++i == rx_ring->count) i = 0;
  1716. buffer_info = &rx_ring->buffer_info[i];
  1717. }
  1718. if (likely(rx_ring->next_to_use != i)) {
  1719. rx_ring->next_to_use = i;
  1720. if (unlikely(i-- == 0))
  1721. i = (rx_ring->count - 1);
  1722. /* Force memory writes to complete before letting h/w
  1723. * know there are new descriptors to fetch. (Only
  1724. * applicable for weak-ordered memory model archs, such
  1725. * as IA-64). */
  1726. wmb();
  1727. IXGB_WRITE_REG(&adapter->hw, RDT, i);
  1728. }
  1729. }
  1730. /**
  1731. * ixgb_vlan_rx_register - enables or disables vlan tagging/stripping.
  1732. *
  1733. * @param netdev network interface device structure
  1734. * @param grp indicates to enable or disable tagging/stripping
  1735. **/
  1736. static void
  1737. ixgb_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
  1738. {
  1739. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1740. uint32_t ctrl, rctl;
  1741. ixgb_irq_disable(adapter);
  1742. adapter->vlgrp = grp;
  1743. if(grp) {
  1744. /* enable VLAN tag insert/strip */
  1745. ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
  1746. ctrl |= IXGB_CTRL0_VME;
  1747. IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
  1748. /* enable VLAN receive filtering */
  1749. rctl = IXGB_READ_REG(&adapter->hw, RCTL);
  1750. rctl |= IXGB_RCTL_VFE;
  1751. rctl &= ~IXGB_RCTL_CFIEN;
  1752. IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
  1753. } else {
  1754. /* disable VLAN tag insert/strip */
  1755. ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
  1756. ctrl &= ~IXGB_CTRL0_VME;
  1757. IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
  1758. /* disable VLAN filtering */
  1759. rctl = IXGB_READ_REG(&adapter->hw, RCTL);
  1760. rctl &= ~IXGB_RCTL_VFE;
  1761. IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
  1762. }
  1763. ixgb_irq_enable(adapter);
  1764. }
  1765. static void
  1766. ixgb_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
  1767. {
  1768. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1769. uint32_t vfta, index;
  1770. /* add VID to filter table */
  1771. index = (vid >> 5) & 0x7F;
  1772. vfta = IXGB_READ_REG_ARRAY(&adapter->hw, VFTA, index);
  1773. vfta |= (1 << (vid & 0x1F));
  1774. ixgb_write_vfta(&adapter->hw, index, vfta);
  1775. }
  1776. static void
  1777. ixgb_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
  1778. {
  1779. struct ixgb_adapter *adapter = netdev_priv(netdev);
  1780. uint32_t vfta, index;
  1781. ixgb_irq_disable(adapter);
  1782. if(adapter->vlgrp)
  1783. adapter->vlgrp->vlan_devices[vid] = NULL;
  1784. ixgb_irq_enable(adapter);
  1785. /* remove VID from filter table*/
  1786. index = (vid >> 5) & 0x7F;
  1787. vfta = IXGB_READ_REG_ARRAY(&adapter->hw, VFTA, index);
  1788. vfta &= ~(1 << (vid & 0x1F));
  1789. ixgb_write_vfta(&adapter->hw, index, vfta);
  1790. }
  1791. static void
  1792. ixgb_restore_vlan(struct ixgb_adapter *adapter)
  1793. {
  1794. ixgb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
  1795. if(adapter->vlgrp) {
  1796. uint16_t vid;
  1797. for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
  1798. if(!adapter->vlgrp->vlan_devices[vid])
  1799. continue;
  1800. ixgb_vlan_rx_add_vid(adapter->netdev, vid);
  1801. }
  1802. }
  1803. }
  1804. #ifdef CONFIG_NET_POLL_CONTROLLER
  1805. /*
  1806. * Polling 'interrupt' - used by things like netconsole to send skbs
  1807. * without having to re-enable interrupts. It's not called while
  1808. * the interrupt routine is executing.
  1809. */
  1810. static void ixgb_netpoll(struct net_device *dev)
  1811. {
  1812. struct ixgb_adapter *adapter = dev->priv;
  1813. disable_irq(adapter->pdev->irq);
  1814. ixgb_intr(adapter->pdev->irq, dev, NULL);
  1815. enable_irq(adapter->pdev->irq);
  1816. }
  1817. #endif
  1818. /* ixgb_main.c */