twl4030.c 74 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl.h>
  29. #include <linux/slab.h>
  30. #include <sound/core.h>
  31. #include <sound/pcm.h>
  32. #include <sound/pcm_params.h>
  33. #include <sound/soc.h>
  34. #include <sound/soc-dapm.h>
  35. #include <sound/initval.h>
  36. #include <sound/tlv.h>
  37. #include "twl4030.h"
  38. /*
  39. * twl4030 register cache & default register settings
  40. */
  41. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  42. 0x00, /* this register not used */
  43. 0x00, /* REG_CODEC_MODE (0x1) */
  44. 0x00, /* REG_OPTION (0x2) */
  45. 0x00, /* REG_UNKNOWN (0x3) */
  46. 0x00, /* REG_MICBIAS_CTL (0x4) */
  47. 0x00, /* REG_ANAMICL (0x5) */
  48. 0x00, /* REG_ANAMICR (0x6) */
  49. 0x00, /* REG_AVADC_CTL (0x7) */
  50. 0x00, /* REG_ADCMICSEL (0x8) */
  51. 0x00, /* REG_DIGMIXING (0x9) */
  52. 0x0f, /* REG_ATXL1PGA (0xA) */
  53. 0x0f, /* REG_ATXR1PGA (0xB) */
  54. 0x0f, /* REG_AVTXL2PGA (0xC) */
  55. 0x0f, /* REG_AVTXR2PGA (0xD) */
  56. 0x00, /* REG_AUDIO_IF (0xE) */
  57. 0x00, /* REG_VOICE_IF (0xF) */
  58. 0x3f, /* REG_ARXR1PGA (0x10) */
  59. 0x3f, /* REG_ARXL1PGA (0x11) */
  60. 0x3f, /* REG_ARXR2PGA (0x12) */
  61. 0x3f, /* REG_ARXL2PGA (0x13) */
  62. 0x25, /* REG_VRXPGA (0x14) */
  63. 0x00, /* REG_VSTPGA (0x15) */
  64. 0x00, /* REG_VRX2ARXPGA (0x16) */
  65. 0x00, /* REG_AVDAC_CTL (0x17) */
  66. 0x00, /* REG_ARX2VTXPGA (0x18) */
  67. 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
  68. 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
  69. 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
  70. 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
  71. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  72. 0x00, /* REG_BT_IF (0x1E) */
  73. 0x55, /* REG_BTPGA (0x1F) */
  74. 0x00, /* REG_BTSTPGA (0x20) */
  75. 0x00, /* REG_EAR_CTL (0x21) */
  76. 0x00, /* REG_HS_SEL (0x22) */
  77. 0x00, /* REG_HS_GAIN_SET (0x23) */
  78. 0x00, /* REG_HS_POPN_SET (0x24) */
  79. 0x00, /* REG_PREDL_CTL (0x25) */
  80. 0x00, /* REG_PREDR_CTL (0x26) */
  81. 0x00, /* REG_PRECKL_CTL (0x27) */
  82. 0x00, /* REG_PRECKR_CTL (0x28) */
  83. 0x00, /* REG_HFL_CTL (0x29) */
  84. 0x00, /* REG_HFR_CTL (0x2A) */
  85. 0x05, /* REG_ALC_CTL (0x2B) */
  86. 0x00, /* REG_ALC_SET1 (0x2C) */
  87. 0x00, /* REG_ALC_SET2 (0x2D) */
  88. 0x00, /* REG_BOOST_CTL (0x2E) */
  89. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  90. 0x13, /* REG_DTMF_FREQSEL (0x30) */
  91. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  92. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  93. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  94. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  95. 0x79, /* REG_DTMF_TONOFF (0x35) */
  96. 0x11, /* REG_DTMF_WANONOFF (0x36) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  99. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  100. 0x06, /* REG_APLL_CTL (0x3A) */
  101. 0x00, /* REG_DTMF_CTL (0x3B) */
  102. 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
  103. 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
  104. 0x00, /* REG_MISC_SET_1 (0x3E) */
  105. 0x00, /* REG_PCMBTMUX (0x3F) */
  106. 0x00, /* not used (0x40) */
  107. 0x00, /* not used (0x41) */
  108. 0x00, /* not used (0x42) */
  109. 0x00, /* REG_RX_PATH_SEL (0x43) */
  110. 0x32, /* REG_VDL_APGA_CTL (0x44) */
  111. 0x00, /* REG_VIBRA_CTL (0x45) */
  112. 0x00, /* REG_VIBRA_SET (0x46) */
  113. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  114. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  115. 0x00, /* REG_MISC_SET_2 (0x49) */
  116. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  117. };
  118. /* codec private data */
  119. struct twl4030_priv {
  120. struct snd_soc_codec codec;
  121. unsigned int codec_powered;
  122. /* reference counts of AIF/APLL users */
  123. unsigned int apll_enabled;
  124. struct snd_pcm_substream *master_substream;
  125. struct snd_pcm_substream *slave_substream;
  126. unsigned int configured;
  127. unsigned int rate;
  128. unsigned int sample_bits;
  129. unsigned int channels;
  130. unsigned int sysclk;
  131. /* Output (with associated amp) states */
  132. u8 hsl_enabled, hsr_enabled;
  133. u8 earpiece_enabled;
  134. u8 predrivel_enabled, predriver_enabled;
  135. u8 carkitl_enabled, carkitr_enabled;
  136. /* Delay needed after enabling the digimic interface */
  137. unsigned int digimic_delay;
  138. };
  139. /*
  140. * read twl4030 register cache
  141. */
  142. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  143. unsigned int reg)
  144. {
  145. u8 *cache = codec->reg_cache;
  146. if (reg >= TWL4030_CACHEREGNUM)
  147. return -EIO;
  148. return cache[reg];
  149. }
  150. /*
  151. * write twl4030 register cache
  152. */
  153. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  154. u8 reg, u8 value)
  155. {
  156. u8 *cache = codec->reg_cache;
  157. if (reg >= TWL4030_CACHEREGNUM)
  158. return;
  159. cache[reg] = value;
  160. }
  161. /*
  162. * write to the twl4030 register space
  163. */
  164. static int twl4030_write(struct snd_soc_codec *codec,
  165. unsigned int reg, unsigned int value)
  166. {
  167. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  168. int write_to_reg = 0;
  169. twl4030_write_reg_cache(codec, reg, value);
  170. if (likely(reg < TWL4030_REG_SW_SHADOW)) {
  171. /* Decide if the given register can be written */
  172. switch (reg) {
  173. case TWL4030_REG_EAR_CTL:
  174. if (twl4030->earpiece_enabled)
  175. write_to_reg = 1;
  176. break;
  177. case TWL4030_REG_PREDL_CTL:
  178. if (twl4030->predrivel_enabled)
  179. write_to_reg = 1;
  180. break;
  181. case TWL4030_REG_PREDR_CTL:
  182. if (twl4030->predriver_enabled)
  183. write_to_reg = 1;
  184. break;
  185. case TWL4030_REG_PRECKL_CTL:
  186. if (twl4030->carkitl_enabled)
  187. write_to_reg = 1;
  188. break;
  189. case TWL4030_REG_PRECKR_CTL:
  190. if (twl4030->carkitr_enabled)
  191. write_to_reg = 1;
  192. break;
  193. case TWL4030_REG_HS_GAIN_SET:
  194. if (twl4030->hsl_enabled || twl4030->hsr_enabled)
  195. write_to_reg = 1;
  196. break;
  197. default:
  198. /* All other register can be written */
  199. write_to_reg = 1;
  200. break;
  201. }
  202. if (write_to_reg)
  203. return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  204. value, reg);
  205. }
  206. return 0;
  207. }
  208. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  209. {
  210. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  211. int mode;
  212. if (enable == twl4030->codec_powered)
  213. return;
  214. if (enable)
  215. mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
  216. else
  217. mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
  218. if (mode >= 0) {
  219. twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
  220. twl4030->codec_powered = enable;
  221. }
  222. /* REVISIT: this delay is present in TI sample drivers */
  223. /* but there seems to be no TRM requirement for it */
  224. udelay(10);
  225. }
  226. static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
  227. {
  228. int i, difference = 0;
  229. u8 val;
  230. dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
  231. for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
  232. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
  233. if (val != twl4030_reg[i]) {
  234. difference++;
  235. dev_dbg(codec->dev,
  236. "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
  237. i, val, twl4030_reg[i]);
  238. }
  239. }
  240. dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
  241. difference, difference ? "Not OK" : "OK");
  242. }
  243. static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
  244. {
  245. int i;
  246. /* set all audio section registers to reasonable defaults */
  247. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  248. if (i != TWL4030_REG_APLL_CTL)
  249. twl4030_write(codec, i, twl4030_reg[i]);
  250. }
  251. static void twl4030_init_chip(struct platform_device *pdev)
  252. {
  253. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  254. struct twl4030_setup_data *setup = socdev->codec_data;
  255. struct snd_soc_codec *codec = socdev->card->codec;
  256. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  257. u8 reg, byte;
  258. int i = 0;
  259. /* Check defaults, if instructed before anything else */
  260. if (setup && setup->check_defaults)
  261. twl4030_check_defaults(codec);
  262. /* Reset registers, if no setup data or if instructed to do so */
  263. if (!setup || (setup && setup->reset_registers))
  264. twl4030_reset_registers(codec);
  265. /* Refresh APLL_CTL register from HW */
  266. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  267. TWL4030_REG_APLL_CTL);
  268. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
  269. /* anti-pop when changing analog gain */
  270. reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  271. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  272. reg | TWL4030_SMOOTH_ANAVOL_EN);
  273. twl4030_write(codec, TWL4030_REG_OPTION,
  274. TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
  275. TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
  276. /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
  277. twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
  278. /* Machine dependent setup */
  279. if (!setup)
  280. return;
  281. twl4030->digimic_delay = setup->digimic_delay;
  282. /* Configuration for headset ramp delay from setup data */
  283. if (setup->sysclk != twl4030->sysclk)
  284. dev_warn(codec->dev,
  285. "Mismatch in APLL mclk: %u (configured: %u)\n",
  286. setup->sysclk, twl4030->sysclk);
  287. reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  288. reg &= ~TWL4030_RAMP_DELAY;
  289. reg |= (setup->ramp_delay_value << 2);
  290. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
  291. /* initiate offset cancellation */
  292. twl4030_codec_enable(codec, 1);
  293. reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  294. reg &= ~TWL4030_OFFSET_CNCL_SEL;
  295. reg |= setup->offset_cncl_path;
  296. twl4030_write(codec, TWL4030_REG_ANAMICL,
  297. reg | TWL4030_CNCL_OFFSET_START);
  298. /* wait for offset cancellation to complete */
  299. do {
  300. /* this takes a little while, so don't slam i2c */
  301. udelay(2000);
  302. twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  303. TWL4030_REG_ANAMICL);
  304. } while ((i++ < 100) &&
  305. ((byte & TWL4030_CNCL_OFFSET_START) ==
  306. TWL4030_CNCL_OFFSET_START));
  307. /* Make sure that the reg_cache has the same value as the HW */
  308. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  309. twl4030_codec_enable(codec, 0);
  310. }
  311. static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
  312. {
  313. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  314. int status = -1;
  315. if (enable) {
  316. twl4030->apll_enabled++;
  317. if (twl4030->apll_enabled == 1)
  318. status = twl4030_codec_enable_resource(
  319. TWL4030_CODEC_RES_APLL);
  320. } else {
  321. twl4030->apll_enabled--;
  322. if (!twl4030->apll_enabled)
  323. status = twl4030_codec_disable_resource(
  324. TWL4030_CODEC_RES_APLL);
  325. }
  326. if (status >= 0)
  327. twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
  328. }
  329. /* Earpiece */
  330. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  331. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  332. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  333. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  334. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  335. };
  336. /* PreDrive Left */
  337. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  338. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  339. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  340. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  341. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  342. };
  343. /* PreDrive Right */
  344. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  345. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  346. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  347. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  348. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  349. };
  350. /* Headset Left */
  351. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  352. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  353. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  354. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  355. };
  356. /* Headset Right */
  357. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  358. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  359. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  360. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  361. };
  362. /* Carkit Left */
  363. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  364. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  365. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  366. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  367. };
  368. /* Carkit Right */
  369. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  370. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  371. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  372. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  373. };
  374. /* Handsfree Left */
  375. static const char *twl4030_handsfreel_texts[] =
  376. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  377. static const struct soc_enum twl4030_handsfreel_enum =
  378. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  379. ARRAY_SIZE(twl4030_handsfreel_texts),
  380. twl4030_handsfreel_texts);
  381. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  382. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  383. /* Handsfree Left virtual mute */
  384. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  385. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  386. /* Handsfree Right */
  387. static const char *twl4030_handsfreer_texts[] =
  388. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  389. static const struct soc_enum twl4030_handsfreer_enum =
  390. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  391. ARRAY_SIZE(twl4030_handsfreer_texts),
  392. twl4030_handsfreer_texts);
  393. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  394. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  395. /* Handsfree Right virtual mute */
  396. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  397. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  398. /* Vibra */
  399. /* Vibra audio path selection */
  400. static const char *twl4030_vibra_texts[] =
  401. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  402. static const struct soc_enum twl4030_vibra_enum =
  403. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  404. ARRAY_SIZE(twl4030_vibra_texts),
  405. twl4030_vibra_texts);
  406. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  407. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  408. /* Vibra path selection: local vibrator (PWM) or audio driven */
  409. static const char *twl4030_vibrapath_texts[] =
  410. {"Local vibrator", "Audio"};
  411. static const struct soc_enum twl4030_vibrapath_enum =
  412. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  413. ARRAY_SIZE(twl4030_vibrapath_texts),
  414. twl4030_vibrapath_texts);
  415. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  416. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  417. /* Left analog microphone selection */
  418. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  419. SOC_DAPM_SINGLE("Main Mic Capture Switch",
  420. TWL4030_REG_ANAMICL, 0, 1, 0),
  421. SOC_DAPM_SINGLE("Headset Mic Capture Switch",
  422. TWL4030_REG_ANAMICL, 1, 1, 0),
  423. SOC_DAPM_SINGLE("AUXL Capture Switch",
  424. TWL4030_REG_ANAMICL, 2, 1, 0),
  425. SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
  426. TWL4030_REG_ANAMICL, 3, 1, 0),
  427. };
  428. /* Right analog microphone selection */
  429. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  430. SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
  431. SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
  432. };
  433. /* TX1 L/R Analog/Digital microphone selection */
  434. static const char *twl4030_micpathtx1_texts[] =
  435. {"Analog", "Digimic0"};
  436. static const struct soc_enum twl4030_micpathtx1_enum =
  437. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  438. ARRAY_SIZE(twl4030_micpathtx1_texts),
  439. twl4030_micpathtx1_texts);
  440. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  441. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  442. /* TX2 L/R Analog/Digital microphone selection */
  443. static const char *twl4030_micpathtx2_texts[] =
  444. {"Analog", "Digimic1"};
  445. static const struct soc_enum twl4030_micpathtx2_enum =
  446. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  447. ARRAY_SIZE(twl4030_micpathtx2_texts),
  448. twl4030_micpathtx2_texts);
  449. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  450. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  451. /* Analog bypass for AudioR1 */
  452. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  453. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  454. /* Analog bypass for AudioL1 */
  455. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  456. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  457. /* Analog bypass for AudioR2 */
  458. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  459. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  460. /* Analog bypass for AudioL2 */
  461. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  462. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  463. /* Analog bypass for Voice */
  464. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  465. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  466. /* Digital bypass gain, mute instead of -30dB */
  467. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  468. TLV_DB_RANGE_HEAD(3),
  469. 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
  470. 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
  471. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  472. };
  473. /* Digital bypass left (TX1L -> RX2L) */
  474. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  475. SOC_DAPM_SINGLE_TLV("Volume",
  476. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  477. twl4030_dapm_dbypass_tlv);
  478. /* Digital bypass right (TX1R -> RX2R) */
  479. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  480. SOC_DAPM_SINGLE_TLV("Volume",
  481. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  482. twl4030_dapm_dbypass_tlv);
  483. /*
  484. * Voice Sidetone GAIN volume control:
  485. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  486. */
  487. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  488. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  489. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  490. SOC_DAPM_SINGLE_TLV("Volume",
  491. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  492. twl4030_dapm_dbypassv_tlv);
  493. static int micpath_event(struct snd_soc_dapm_widget *w,
  494. struct snd_kcontrol *kcontrol, int event)
  495. {
  496. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  497. unsigned char adcmicsel, micbias_ctl;
  498. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  499. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  500. /* Prepare the bits for the given TX path:
  501. * shift_l == 0: TX1 microphone path
  502. * shift_l == 2: TX2 microphone path */
  503. if (e->shift_l) {
  504. /* TX2 microphone path */
  505. if (adcmicsel & TWL4030_TX2IN_SEL)
  506. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  507. else
  508. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  509. } else {
  510. /* TX1 microphone path */
  511. if (adcmicsel & TWL4030_TX1IN_SEL)
  512. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  513. else
  514. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  515. }
  516. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  517. return 0;
  518. }
  519. /*
  520. * Output PGA builder:
  521. * Handle the muting and unmuting of the given output (turning off the
  522. * amplifier associated with the output pin)
  523. * On mute bypass the reg_cache and write 0 to the register
  524. * On unmute: restore the register content from the reg_cache
  525. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  526. */
  527. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  528. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  529. struct snd_kcontrol *kcontrol, int event) \
  530. { \
  531. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
  532. \
  533. switch (event) { \
  534. case SND_SOC_DAPM_POST_PMU: \
  535. twl4030->pin_name##_enabled = 1; \
  536. twl4030_write(w->codec, reg, \
  537. twl4030_read_reg_cache(w->codec, reg)); \
  538. break; \
  539. case SND_SOC_DAPM_POST_PMD: \
  540. twl4030->pin_name##_enabled = 0; \
  541. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  542. 0, reg); \
  543. break; \
  544. } \
  545. return 0; \
  546. }
  547. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  548. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  549. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  550. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  551. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  552. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  553. {
  554. unsigned char hs_ctl;
  555. hs_ctl = twl4030_read_reg_cache(codec, reg);
  556. if (ramp) {
  557. /* HF ramp-up */
  558. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  559. twl4030_write(codec, reg, hs_ctl);
  560. udelay(10);
  561. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  562. twl4030_write(codec, reg, hs_ctl);
  563. udelay(40);
  564. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  565. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  566. twl4030_write(codec, reg, hs_ctl);
  567. } else {
  568. /* HF ramp-down */
  569. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  570. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  571. twl4030_write(codec, reg, hs_ctl);
  572. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  573. twl4030_write(codec, reg, hs_ctl);
  574. udelay(40);
  575. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  576. twl4030_write(codec, reg, hs_ctl);
  577. }
  578. }
  579. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  580. struct snd_kcontrol *kcontrol, int event)
  581. {
  582. switch (event) {
  583. case SND_SOC_DAPM_POST_PMU:
  584. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  585. break;
  586. case SND_SOC_DAPM_POST_PMD:
  587. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  588. break;
  589. }
  590. return 0;
  591. }
  592. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  593. struct snd_kcontrol *kcontrol, int event)
  594. {
  595. switch (event) {
  596. case SND_SOC_DAPM_POST_PMU:
  597. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  598. break;
  599. case SND_SOC_DAPM_POST_PMD:
  600. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  601. break;
  602. }
  603. return 0;
  604. }
  605. static int vibramux_event(struct snd_soc_dapm_widget *w,
  606. struct snd_kcontrol *kcontrol, int event)
  607. {
  608. twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
  609. return 0;
  610. }
  611. static int apll_event(struct snd_soc_dapm_widget *w,
  612. struct snd_kcontrol *kcontrol, int event)
  613. {
  614. switch (event) {
  615. case SND_SOC_DAPM_PRE_PMU:
  616. twl4030_apll_enable(w->codec, 1);
  617. break;
  618. case SND_SOC_DAPM_POST_PMD:
  619. twl4030_apll_enable(w->codec, 0);
  620. break;
  621. }
  622. return 0;
  623. }
  624. static int aif_event(struct snd_soc_dapm_widget *w,
  625. struct snd_kcontrol *kcontrol, int event)
  626. {
  627. u8 audio_if;
  628. audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
  629. switch (event) {
  630. case SND_SOC_DAPM_PRE_PMU:
  631. /* Enable AIF */
  632. /* enable the PLL before we use it to clock the DAI */
  633. twl4030_apll_enable(w->codec, 1);
  634. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  635. audio_if | TWL4030_AIF_EN);
  636. break;
  637. case SND_SOC_DAPM_POST_PMD:
  638. /* disable the DAI before we stop it's source PLL */
  639. twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
  640. audio_if & ~TWL4030_AIF_EN);
  641. twl4030_apll_enable(w->codec, 0);
  642. break;
  643. }
  644. return 0;
  645. }
  646. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  647. {
  648. struct snd_soc_device *socdev = codec->socdev;
  649. struct twl4030_setup_data *setup = socdev->codec_data;
  650. unsigned char hs_gain, hs_pop;
  651. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  652. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  653. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  654. 8388608, 16777216, 33554432, 67108864};
  655. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  656. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  657. /* Enable external mute control, this dramatically reduces
  658. * the pop-noise */
  659. if (setup && setup->hs_extmute) {
  660. if (setup->set_hs_extmute) {
  661. setup->set_hs_extmute(1);
  662. } else {
  663. hs_pop |= TWL4030_EXTMUTE;
  664. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  665. }
  666. }
  667. if (ramp) {
  668. /* Headset ramp-up according to the TRM */
  669. hs_pop |= TWL4030_VMID_EN;
  670. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  671. /* Actually write to the register */
  672. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  673. hs_gain,
  674. TWL4030_REG_HS_GAIN_SET);
  675. hs_pop |= TWL4030_RAMP_EN;
  676. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  677. /* Wait ramp delay time + 1, so the VMID can settle */
  678. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  679. twl4030->sysclk) + 1);
  680. } else {
  681. /* Headset ramp-down _not_ according to
  682. * the TRM, but in a way that it is working */
  683. hs_pop &= ~TWL4030_RAMP_EN;
  684. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  685. /* Wait ramp delay time + 1, so the VMID can settle */
  686. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  687. twl4030->sysclk) + 1);
  688. /* Bypass the reg_cache to mute the headset */
  689. twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  690. hs_gain & (~0x0f),
  691. TWL4030_REG_HS_GAIN_SET);
  692. hs_pop &= ~TWL4030_VMID_EN;
  693. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  694. }
  695. /* Disable external mute */
  696. if (setup && setup->hs_extmute) {
  697. if (setup->set_hs_extmute) {
  698. setup->set_hs_extmute(0);
  699. } else {
  700. hs_pop &= ~TWL4030_EXTMUTE;
  701. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  702. }
  703. }
  704. }
  705. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  706. struct snd_kcontrol *kcontrol, int event)
  707. {
  708. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  709. switch (event) {
  710. case SND_SOC_DAPM_POST_PMU:
  711. /* Do the ramp-up only once */
  712. if (!twl4030->hsr_enabled)
  713. headset_ramp(w->codec, 1);
  714. twl4030->hsl_enabled = 1;
  715. break;
  716. case SND_SOC_DAPM_POST_PMD:
  717. /* Do the ramp-down only if both headsetL/R is disabled */
  718. if (!twl4030->hsr_enabled)
  719. headset_ramp(w->codec, 0);
  720. twl4030->hsl_enabled = 0;
  721. break;
  722. }
  723. return 0;
  724. }
  725. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  726. struct snd_kcontrol *kcontrol, int event)
  727. {
  728. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  729. switch (event) {
  730. case SND_SOC_DAPM_POST_PMU:
  731. /* Do the ramp-up only once */
  732. if (!twl4030->hsl_enabled)
  733. headset_ramp(w->codec, 1);
  734. twl4030->hsr_enabled = 1;
  735. break;
  736. case SND_SOC_DAPM_POST_PMD:
  737. /* Do the ramp-down only if both headsetL/R is disabled */
  738. if (!twl4030->hsl_enabled)
  739. headset_ramp(w->codec, 0);
  740. twl4030->hsr_enabled = 0;
  741. break;
  742. }
  743. return 0;
  744. }
  745. static int digimic_event(struct snd_soc_dapm_widget *w,
  746. struct snd_kcontrol *kcontrol, int event)
  747. {
  748. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
  749. if (twl4030->digimic_delay)
  750. mdelay(twl4030->digimic_delay);
  751. return 0;
  752. }
  753. /*
  754. * Some of the gain controls in TWL (mostly those which are associated with
  755. * the outputs) are implemented in an interesting way:
  756. * 0x0 : Power down (mute)
  757. * 0x1 : 6dB
  758. * 0x2 : 0 dB
  759. * 0x3 : -6 dB
  760. * Inverting not going to help with these.
  761. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  762. */
  763. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  764. xinvert, tlv_array) \
  765. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  766. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  767. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  768. .tlv.p = (tlv_array), \
  769. .info = snd_soc_info_volsw, \
  770. .get = snd_soc_get_volsw_twl4030, \
  771. .put = snd_soc_put_volsw_twl4030, \
  772. .private_value = (unsigned long)&(struct soc_mixer_control) \
  773. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  774. .max = xmax, .invert = xinvert} }
  775. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  776. xinvert, tlv_array) \
  777. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  778. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  779. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  780. .tlv.p = (tlv_array), \
  781. .info = snd_soc_info_volsw_2r, \
  782. .get = snd_soc_get_volsw_r2_twl4030,\
  783. .put = snd_soc_put_volsw_r2_twl4030, \
  784. .private_value = (unsigned long)&(struct soc_mixer_control) \
  785. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  786. .rshift = xshift, .max = xmax, .invert = xinvert} }
  787. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  788. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  789. xinvert, tlv_array)
  790. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  791. struct snd_ctl_elem_value *ucontrol)
  792. {
  793. struct soc_mixer_control *mc =
  794. (struct soc_mixer_control *)kcontrol->private_value;
  795. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  796. unsigned int reg = mc->reg;
  797. unsigned int shift = mc->shift;
  798. unsigned int rshift = mc->rshift;
  799. int max = mc->max;
  800. int mask = (1 << fls(max)) - 1;
  801. ucontrol->value.integer.value[0] =
  802. (snd_soc_read(codec, reg) >> shift) & mask;
  803. if (ucontrol->value.integer.value[0])
  804. ucontrol->value.integer.value[0] =
  805. max + 1 - ucontrol->value.integer.value[0];
  806. if (shift != rshift) {
  807. ucontrol->value.integer.value[1] =
  808. (snd_soc_read(codec, reg) >> rshift) & mask;
  809. if (ucontrol->value.integer.value[1])
  810. ucontrol->value.integer.value[1] =
  811. max + 1 - ucontrol->value.integer.value[1];
  812. }
  813. return 0;
  814. }
  815. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  816. struct snd_ctl_elem_value *ucontrol)
  817. {
  818. struct soc_mixer_control *mc =
  819. (struct soc_mixer_control *)kcontrol->private_value;
  820. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  821. unsigned int reg = mc->reg;
  822. unsigned int shift = mc->shift;
  823. unsigned int rshift = mc->rshift;
  824. int max = mc->max;
  825. int mask = (1 << fls(max)) - 1;
  826. unsigned short val, val2, val_mask;
  827. val = (ucontrol->value.integer.value[0] & mask);
  828. val_mask = mask << shift;
  829. if (val)
  830. val = max + 1 - val;
  831. val = val << shift;
  832. if (shift != rshift) {
  833. val2 = (ucontrol->value.integer.value[1] & mask);
  834. val_mask |= mask << rshift;
  835. if (val2)
  836. val2 = max + 1 - val2;
  837. val |= val2 << rshift;
  838. }
  839. return snd_soc_update_bits(codec, reg, val_mask, val);
  840. }
  841. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  842. struct snd_ctl_elem_value *ucontrol)
  843. {
  844. struct soc_mixer_control *mc =
  845. (struct soc_mixer_control *)kcontrol->private_value;
  846. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  847. unsigned int reg = mc->reg;
  848. unsigned int reg2 = mc->rreg;
  849. unsigned int shift = mc->shift;
  850. int max = mc->max;
  851. int mask = (1<<fls(max))-1;
  852. ucontrol->value.integer.value[0] =
  853. (snd_soc_read(codec, reg) >> shift) & mask;
  854. ucontrol->value.integer.value[1] =
  855. (snd_soc_read(codec, reg2) >> shift) & mask;
  856. if (ucontrol->value.integer.value[0])
  857. ucontrol->value.integer.value[0] =
  858. max + 1 - ucontrol->value.integer.value[0];
  859. if (ucontrol->value.integer.value[1])
  860. ucontrol->value.integer.value[1] =
  861. max + 1 - ucontrol->value.integer.value[1];
  862. return 0;
  863. }
  864. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  865. struct snd_ctl_elem_value *ucontrol)
  866. {
  867. struct soc_mixer_control *mc =
  868. (struct soc_mixer_control *)kcontrol->private_value;
  869. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  870. unsigned int reg = mc->reg;
  871. unsigned int reg2 = mc->rreg;
  872. unsigned int shift = mc->shift;
  873. int max = mc->max;
  874. int mask = (1 << fls(max)) - 1;
  875. int err;
  876. unsigned short val, val2, val_mask;
  877. val_mask = mask << shift;
  878. val = (ucontrol->value.integer.value[0] & mask);
  879. val2 = (ucontrol->value.integer.value[1] & mask);
  880. if (val)
  881. val = max + 1 - val;
  882. if (val2)
  883. val2 = max + 1 - val2;
  884. val = val << shift;
  885. val2 = val2 << shift;
  886. err = snd_soc_update_bits(codec, reg, val_mask, val);
  887. if (err < 0)
  888. return err;
  889. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  890. return err;
  891. }
  892. /* Codec operation modes */
  893. static const char *twl4030_op_modes_texts[] = {
  894. "Option 2 (voice/audio)", "Option 1 (audio)"
  895. };
  896. static const struct soc_enum twl4030_op_modes_enum =
  897. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  898. ARRAY_SIZE(twl4030_op_modes_texts),
  899. twl4030_op_modes_texts);
  900. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  901. struct snd_ctl_elem_value *ucontrol)
  902. {
  903. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  904. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  905. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  906. unsigned short val;
  907. unsigned short mask, bitmask;
  908. if (twl4030->configured) {
  909. printk(KERN_ERR "twl4030 operation mode cannot be "
  910. "changed on-the-fly\n");
  911. return -EBUSY;
  912. }
  913. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  914. ;
  915. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  916. return -EINVAL;
  917. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  918. mask = (bitmask - 1) << e->shift_l;
  919. if (e->shift_l != e->shift_r) {
  920. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  921. return -EINVAL;
  922. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  923. mask |= (bitmask - 1) << e->shift_r;
  924. }
  925. return snd_soc_update_bits(codec, e->reg, mask, val);
  926. }
  927. /*
  928. * FGAIN volume control:
  929. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  930. */
  931. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  932. /*
  933. * CGAIN volume control:
  934. * 0 dB to 12 dB in 6 dB steps
  935. * value 2 and 3 means 12 dB
  936. */
  937. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  938. /*
  939. * Voice Downlink GAIN volume control:
  940. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  941. */
  942. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  943. /*
  944. * Analog playback gain
  945. * -24 dB to 12 dB in 2 dB steps
  946. */
  947. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  948. /*
  949. * Gain controls tied to outputs
  950. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  951. */
  952. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  953. /*
  954. * Gain control for earpiece amplifier
  955. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  956. */
  957. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  958. /*
  959. * Capture gain after the ADCs
  960. * from 0 dB to 31 dB in 1 dB steps
  961. */
  962. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  963. /*
  964. * Gain control for input amplifiers
  965. * 0 dB to 30 dB in 6 dB steps
  966. */
  967. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  968. /* AVADC clock priority */
  969. static const char *twl4030_avadc_clk_priority_texts[] = {
  970. "Voice high priority", "HiFi high priority"
  971. };
  972. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  973. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  974. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  975. twl4030_avadc_clk_priority_texts);
  976. static const char *twl4030_rampdelay_texts[] = {
  977. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  978. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  979. "3495/2581/1748 ms"
  980. };
  981. static const struct soc_enum twl4030_rampdelay_enum =
  982. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  983. ARRAY_SIZE(twl4030_rampdelay_texts),
  984. twl4030_rampdelay_texts);
  985. /* Vibra H-bridge direction mode */
  986. static const char *twl4030_vibradirmode_texts[] = {
  987. "Vibra H-bridge direction", "Audio data MSB",
  988. };
  989. static const struct soc_enum twl4030_vibradirmode_enum =
  990. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  991. ARRAY_SIZE(twl4030_vibradirmode_texts),
  992. twl4030_vibradirmode_texts);
  993. /* Vibra H-bridge direction */
  994. static const char *twl4030_vibradir_texts[] = {
  995. "Positive polarity", "Negative polarity",
  996. };
  997. static const struct soc_enum twl4030_vibradir_enum =
  998. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  999. ARRAY_SIZE(twl4030_vibradir_texts),
  1000. twl4030_vibradir_texts);
  1001. /* Digimic Left and right swapping */
  1002. static const char *twl4030_digimicswap_texts[] = {
  1003. "Not swapped", "Swapped",
  1004. };
  1005. static const struct soc_enum twl4030_digimicswap_enum =
  1006. SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
  1007. ARRAY_SIZE(twl4030_digimicswap_texts),
  1008. twl4030_digimicswap_texts);
  1009. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  1010. /* Codec operation mode control */
  1011. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  1012. snd_soc_get_enum_double,
  1013. snd_soc_put_twl4030_opmode_enum_double),
  1014. /* Common playback gain controls */
  1015. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  1016. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  1017. 0, 0x3f, 0, digital_fine_tlv),
  1018. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  1019. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1020. 0, 0x3f, 0, digital_fine_tlv),
  1021. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  1022. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  1023. 6, 0x2, 0, digital_coarse_tlv),
  1024. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  1025. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  1026. 6, 0x2, 0, digital_coarse_tlv),
  1027. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  1028. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1029. 3, 0x12, 1, analog_tlv),
  1030. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  1031. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1032. 3, 0x12, 1, analog_tlv),
  1033. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  1034. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  1035. 1, 1, 0),
  1036. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  1037. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  1038. 1, 1, 0),
  1039. /* Common voice downlink gain controls */
  1040. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  1041. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  1042. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  1043. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  1044. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  1045. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  1046. /* Separate output gain controls */
  1047. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  1048. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  1049. 4, 3, 0, output_tvl),
  1050. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  1051. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  1052. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  1053. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  1054. 4, 3, 0, output_tvl),
  1055. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  1056. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  1057. /* Common capture gain controls */
  1058. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  1059. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  1060. 0, 0x1f, 0, digital_capture_tlv),
  1061. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  1062. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  1063. 0, 0x1f, 0, digital_capture_tlv),
  1064. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  1065. 0, 3, 5, 0, input_gain_tlv),
  1066. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  1067. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  1068. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  1069. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  1070. SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
  1071. };
  1072. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  1073. /* Left channel inputs */
  1074. SND_SOC_DAPM_INPUT("MAINMIC"),
  1075. SND_SOC_DAPM_INPUT("HSMIC"),
  1076. SND_SOC_DAPM_INPUT("AUXL"),
  1077. SND_SOC_DAPM_INPUT("CARKITMIC"),
  1078. /* Right channel inputs */
  1079. SND_SOC_DAPM_INPUT("SUBMIC"),
  1080. SND_SOC_DAPM_INPUT("AUXR"),
  1081. /* Digital microphones (Stereo) */
  1082. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  1083. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  1084. /* Outputs */
  1085. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1086. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1087. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1088. SND_SOC_DAPM_OUTPUT("HSOL"),
  1089. SND_SOC_DAPM_OUTPUT("HSOR"),
  1090. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1091. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1092. SND_SOC_DAPM_OUTPUT("HFL"),
  1093. SND_SOC_DAPM_OUTPUT("HFR"),
  1094. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1095. /* AIF and APLL clocks for running DAIs (including loopback) */
  1096. SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
  1097. SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
  1098. SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
  1099. /* DACs */
  1100. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1101. SND_SOC_NOPM, 0, 0),
  1102. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1103. SND_SOC_NOPM, 0, 0),
  1104. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1105. SND_SOC_NOPM, 0, 0),
  1106. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1107. SND_SOC_NOPM, 0, 0),
  1108. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1109. SND_SOC_NOPM, 0, 0),
  1110. /* Analog bypasses */
  1111. SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1112. &twl4030_dapm_abypassr1_control),
  1113. SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1114. &twl4030_dapm_abypassl1_control),
  1115. SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1116. &twl4030_dapm_abypassr2_control),
  1117. SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1118. &twl4030_dapm_abypassl2_control),
  1119. SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1120. &twl4030_dapm_abypassv_control),
  1121. /* Master analog loopback switch */
  1122. SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
  1123. NULL, 0),
  1124. /* Digital bypasses */
  1125. SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1126. &twl4030_dapm_dbypassl_control),
  1127. SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1128. &twl4030_dapm_dbypassr_control),
  1129. SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1130. &twl4030_dapm_dbypassv_control),
  1131. /* Digital mixers, power control for the physical DACs */
  1132. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1133. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1134. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1135. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1136. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1137. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1138. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1139. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1140. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1141. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1142. /* Analog mixers, power control for the physical PGAs */
  1143. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1144. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1145. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1146. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1147. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1148. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1149. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1150. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1151. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1152. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1153. SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
  1154. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1155. SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
  1156. SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
  1157. /* Output MIXER controls */
  1158. /* Earpiece */
  1159. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1160. &twl4030_dapm_earpiece_controls[0],
  1161. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1162. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1163. 0, 0, NULL, 0, earpiecepga_event,
  1164. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1165. /* PreDrivL/R */
  1166. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1167. &twl4030_dapm_predrivel_controls[0],
  1168. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1169. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1170. 0, 0, NULL, 0, predrivelpga_event,
  1171. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1172. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1173. &twl4030_dapm_predriver_controls[0],
  1174. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1175. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1176. 0, 0, NULL, 0, predriverpga_event,
  1177. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1178. /* HeadsetL/R */
  1179. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1180. &twl4030_dapm_hsol_controls[0],
  1181. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1182. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1183. 0, 0, NULL, 0, headsetlpga_event,
  1184. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1185. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1186. &twl4030_dapm_hsor_controls[0],
  1187. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1188. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1189. 0, 0, NULL, 0, headsetrpga_event,
  1190. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1191. /* CarkitL/R */
  1192. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1193. &twl4030_dapm_carkitl_controls[0],
  1194. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1195. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1196. 0, 0, NULL, 0, carkitlpga_event,
  1197. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1198. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1199. &twl4030_dapm_carkitr_controls[0],
  1200. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1201. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1202. 0, 0, NULL, 0, carkitrpga_event,
  1203. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1204. /* Output MUX controls */
  1205. /* HandsfreeL/R */
  1206. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1207. &twl4030_dapm_handsfreel_control),
  1208. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1209. &twl4030_dapm_handsfreelmute_control),
  1210. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1211. 0, 0, NULL, 0, handsfreelpga_event,
  1212. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1213. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1214. &twl4030_dapm_handsfreer_control),
  1215. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1216. &twl4030_dapm_handsfreermute_control),
  1217. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1218. 0, 0, NULL, 0, handsfreerpga_event,
  1219. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1220. /* Vibra */
  1221. SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1222. &twl4030_dapm_vibra_control, vibramux_event,
  1223. SND_SOC_DAPM_PRE_PMU),
  1224. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1225. &twl4030_dapm_vibrapath_control),
  1226. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1227. capture */
  1228. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1229. SND_SOC_NOPM, 0, 0),
  1230. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1231. SND_SOC_NOPM, 0, 0),
  1232. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1233. SND_SOC_NOPM, 0, 0),
  1234. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1235. SND_SOC_NOPM, 0, 0),
  1236. /* Analog/Digital mic path selection.
  1237. TX1 Left/Right: either analog Left/Right or Digimic0
  1238. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1239. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1240. &twl4030_dapm_micpathtx1_control, micpath_event,
  1241. SND_SOC_DAPM_POST_REG),
  1242. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1243. &twl4030_dapm_micpathtx2_control, micpath_event,
  1244. SND_SOC_DAPM_POST_REG),
  1245. /* Analog input mixers for the capture amplifiers */
  1246. SND_SOC_DAPM_MIXER("Analog Left",
  1247. TWL4030_REG_ANAMICL, 4, 0,
  1248. &twl4030_dapm_analoglmic_controls[0],
  1249. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1250. SND_SOC_DAPM_MIXER("Analog Right",
  1251. TWL4030_REG_ANAMICR, 4, 0,
  1252. &twl4030_dapm_analogrmic_controls[0],
  1253. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1254. SND_SOC_DAPM_PGA("ADC Physical Left",
  1255. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1256. SND_SOC_DAPM_PGA("ADC Physical Right",
  1257. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1258. SND_SOC_DAPM_PGA_E("Digimic0 Enable",
  1259. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
  1260. digimic_event, SND_SOC_DAPM_POST_PMU),
  1261. SND_SOC_DAPM_PGA_E("Digimic1 Enable",
  1262. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
  1263. digimic_event, SND_SOC_DAPM_POST_PMU),
  1264. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1265. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1266. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1267. };
  1268. static const struct snd_soc_dapm_route intercon[] = {
  1269. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1270. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1271. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1272. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1273. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1274. /* Supply for the digital part (APLL) */
  1275. {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
  1276. {"DAC Left1", NULL, "AIF Enable"},
  1277. {"DAC Right1", NULL, "AIF Enable"},
  1278. {"DAC Left2", NULL, "AIF Enable"},
  1279. {"DAC Right1", NULL, "AIF Enable"},
  1280. {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
  1281. {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
  1282. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1283. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1284. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1285. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1286. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1287. /* Internal playback routings */
  1288. /* Earpiece */
  1289. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1290. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1291. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1292. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1293. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1294. /* PreDrivL */
  1295. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1296. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1297. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1298. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1299. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1300. /* PreDrivR */
  1301. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1302. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1303. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1304. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1305. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1306. /* HeadsetL */
  1307. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1308. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1309. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1310. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1311. /* HeadsetR */
  1312. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1313. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1314. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1315. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1316. /* CarkitL */
  1317. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1318. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1319. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1320. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1321. /* CarkitR */
  1322. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1323. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1324. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1325. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1326. /* HandsfreeL */
  1327. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1328. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1329. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1330. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1331. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1332. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1333. /* HandsfreeR */
  1334. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1335. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1336. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1337. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1338. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1339. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1340. /* Vibra */
  1341. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1342. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1343. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1344. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1345. /* outputs */
  1346. /* Must be always connected (for AIF and APLL) */
  1347. {"Virtual HiFi OUT", NULL, "DAC Left1"},
  1348. {"Virtual HiFi OUT", NULL, "DAC Right1"},
  1349. {"Virtual HiFi OUT", NULL, "DAC Left2"},
  1350. {"Virtual HiFi OUT", NULL, "DAC Right2"},
  1351. /* Must be always connected (for APLL) */
  1352. {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
  1353. /* Physical outputs */
  1354. {"EARPIECE", NULL, "Earpiece PGA"},
  1355. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1356. {"PREDRIVER", NULL, "PredriveR PGA"},
  1357. {"HSOL", NULL, "HeadsetL PGA"},
  1358. {"HSOR", NULL, "HeadsetR PGA"},
  1359. {"CARKITL", NULL, "CarkitL PGA"},
  1360. {"CARKITR", NULL, "CarkitR PGA"},
  1361. {"HFL", NULL, "HandsfreeL PGA"},
  1362. {"HFR", NULL, "HandsfreeR PGA"},
  1363. {"Vibra Route", "Audio", "Vibra Mux"},
  1364. {"VIBRA", NULL, "Vibra Route"},
  1365. /* Capture path */
  1366. /* Must be always connected (for AIF and APLL) */
  1367. {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
  1368. {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
  1369. {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
  1370. {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
  1371. /* Physical inputs */
  1372. {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
  1373. {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
  1374. {"Analog Left", "AUXL Capture Switch", "AUXL"},
  1375. {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
  1376. {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
  1377. {"Analog Right", "AUXR Capture Switch", "AUXR"},
  1378. {"ADC Physical Left", NULL, "Analog Left"},
  1379. {"ADC Physical Right", NULL, "Analog Right"},
  1380. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1381. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1382. /* TX1 Left capture path */
  1383. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1384. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1385. /* TX1 Right capture path */
  1386. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1387. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1388. /* TX2 Left capture path */
  1389. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1390. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1391. /* TX2 Right capture path */
  1392. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1393. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1394. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1395. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1396. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1397. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1398. {"ADC Virtual Left1", NULL, "AIF Enable"},
  1399. {"ADC Virtual Right1", NULL, "AIF Enable"},
  1400. {"ADC Virtual Left2", NULL, "AIF Enable"},
  1401. {"ADC Virtual Right2", NULL, "AIF Enable"},
  1402. /* Analog bypass routes */
  1403. {"Right1 Analog Loopback", "Switch", "Analog Right"},
  1404. {"Left1 Analog Loopback", "Switch", "Analog Left"},
  1405. {"Right2 Analog Loopback", "Switch", "Analog Right"},
  1406. {"Left2 Analog Loopback", "Switch", "Analog Left"},
  1407. {"Voice Analog Loopback", "Switch", "Analog Left"},
  1408. /* Supply for the Analog loopbacks */
  1409. {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
  1410. {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
  1411. {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
  1412. {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
  1413. {"Voice Analog Loopback", NULL, "FM Loop Enable"},
  1414. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1415. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1416. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1417. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1418. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1419. /* Digital bypass routes */
  1420. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1421. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1422. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1423. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1424. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1425. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1426. };
  1427. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1428. {
  1429. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1430. ARRAY_SIZE(twl4030_dapm_widgets));
  1431. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1432. return 0;
  1433. }
  1434. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1435. enum snd_soc_bias_level level)
  1436. {
  1437. switch (level) {
  1438. case SND_SOC_BIAS_ON:
  1439. break;
  1440. case SND_SOC_BIAS_PREPARE:
  1441. break;
  1442. case SND_SOC_BIAS_STANDBY:
  1443. if (codec->bias_level == SND_SOC_BIAS_OFF)
  1444. twl4030_codec_enable(codec, 1);
  1445. break;
  1446. case SND_SOC_BIAS_OFF:
  1447. twl4030_codec_enable(codec, 0);
  1448. break;
  1449. }
  1450. codec->bias_level = level;
  1451. return 0;
  1452. }
  1453. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1454. struct snd_pcm_substream *mst_substream)
  1455. {
  1456. struct snd_pcm_substream *slv_substream;
  1457. /* Pick the stream, which need to be constrained */
  1458. if (mst_substream == twl4030->master_substream)
  1459. slv_substream = twl4030->slave_substream;
  1460. else if (mst_substream == twl4030->slave_substream)
  1461. slv_substream = twl4030->master_substream;
  1462. else /* This should not happen.. */
  1463. return;
  1464. /* Set the constraints according to the already configured stream */
  1465. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1466. SNDRV_PCM_HW_PARAM_RATE,
  1467. twl4030->rate,
  1468. twl4030->rate);
  1469. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1470. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1471. twl4030->sample_bits,
  1472. twl4030->sample_bits);
  1473. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1474. SNDRV_PCM_HW_PARAM_CHANNELS,
  1475. twl4030->channels,
  1476. twl4030->channels);
  1477. }
  1478. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1479. * capture has to be enabled/disabled. */
  1480. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1481. int enable)
  1482. {
  1483. u8 reg, mask;
  1484. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1485. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1486. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1487. else
  1488. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1489. if (enable)
  1490. reg |= mask;
  1491. else
  1492. reg &= ~mask;
  1493. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1494. }
  1495. static int twl4030_startup(struct snd_pcm_substream *substream,
  1496. struct snd_soc_dai *dai)
  1497. {
  1498. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1499. struct snd_soc_device *socdev = rtd->socdev;
  1500. struct snd_soc_codec *codec = socdev->card->codec;
  1501. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1502. if (twl4030->master_substream) {
  1503. twl4030->slave_substream = substream;
  1504. /* The DAI has one configuration for playback and capture, so
  1505. * if the DAI has been already configured then constrain this
  1506. * substream to match it. */
  1507. if (twl4030->configured)
  1508. twl4030_constraints(twl4030, twl4030->master_substream);
  1509. } else {
  1510. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1511. TWL4030_OPTION_1)) {
  1512. /* In option2 4 channel is not supported, set the
  1513. * constraint for the first stream for channels, the
  1514. * second stream will 'inherit' this cosntraint */
  1515. snd_pcm_hw_constraint_minmax(substream->runtime,
  1516. SNDRV_PCM_HW_PARAM_CHANNELS,
  1517. 2, 2);
  1518. }
  1519. twl4030->master_substream = substream;
  1520. }
  1521. return 0;
  1522. }
  1523. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1524. struct snd_soc_dai *dai)
  1525. {
  1526. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1527. struct snd_soc_device *socdev = rtd->socdev;
  1528. struct snd_soc_codec *codec = socdev->card->codec;
  1529. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1530. if (twl4030->master_substream == substream)
  1531. twl4030->master_substream = twl4030->slave_substream;
  1532. twl4030->slave_substream = NULL;
  1533. /* If all streams are closed, or the remaining stream has not yet
  1534. * been configured than set the DAI as not configured. */
  1535. if (!twl4030->master_substream)
  1536. twl4030->configured = 0;
  1537. else if (!twl4030->master_substream->runtime->channels)
  1538. twl4030->configured = 0;
  1539. /* If the closing substream had 4 channel, do the necessary cleanup */
  1540. if (substream->runtime->channels == 4)
  1541. twl4030_tdm_enable(codec, substream->stream, 0);
  1542. }
  1543. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1544. struct snd_pcm_hw_params *params,
  1545. struct snd_soc_dai *dai)
  1546. {
  1547. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1548. struct snd_soc_device *socdev = rtd->socdev;
  1549. struct snd_soc_codec *codec = socdev->card->codec;
  1550. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1551. u8 mode, old_mode, format, old_format;
  1552. /* If the substream has 4 channel, do the necessary setup */
  1553. if (params_channels(params) == 4) {
  1554. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1555. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1556. /* Safety check: are we in the correct operating mode and
  1557. * the interface is in TDM mode? */
  1558. if ((mode & TWL4030_OPTION_1) &&
  1559. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1560. twl4030_tdm_enable(codec, substream->stream, 1);
  1561. else
  1562. return -EINVAL;
  1563. }
  1564. if (twl4030->configured)
  1565. /* Ignoring hw_params for already configured DAI */
  1566. return 0;
  1567. /* bit rate */
  1568. old_mode = twl4030_read_reg_cache(codec,
  1569. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1570. mode = old_mode & ~TWL4030_APLL_RATE;
  1571. switch (params_rate(params)) {
  1572. case 8000:
  1573. mode |= TWL4030_APLL_RATE_8000;
  1574. break;
  1575. case 11025:
  1576. mode |= TWL4030_APLL_RATE_11025;
  1577. break;
  1578. case 12000:
  1579. mode |= TWL4030_APLL_RATE_12000;
  1580. break;
  1581. case 16000:
  1582. mode |= TWL4030_APLL_RATE_16000;
  1583. break;
  1584. case 22050:
  1585. mode |= TWL4030_APLL_RATE_22050;
  1586. break;
  1587. case 24000:
  1588. mode |= TWL4030_APLL_RATE_24000;
  1589. break;
  1590. case 32000:
  1591. mode |= TWL4030_APLL_RATE_32000;
  1592. break;
  1593. case 44100:
  1594. mode |= TWL4030_APLL_RATE_44100;
  1595. break;
  1596. case 48000:
  1597. mode |= TWL4030_APLL_RATE_48000;
  1598. break;
  1599. case 96000:
  1600. mode |= TWL4030_APLL_RATE_96000;
  1601. break;
  1602. default:
  1603. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1604. params_rate(params));
  1605. return -EINVAL;
  1606. }
  1607. /* sample size */
  1608. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1609. format = old_format;
  1610. format &= ~TWL4030_DATA_WIDTH;
  1611. switch (params_format(params)) {
  1612. case SNDRV_PCM_FORMAT_S16_LE:
  1613. format |= TWL4030_DATA_WIDTH_16S_16W;
  1614. break;
  1615. case SNDRV_PCM_FORMAT_S24_LE:
  1616. format |= TWL4030_DATA_WIDTH_32S_24W;
  1617. break;
  1618. default:
  1619. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1620. params_format(params));
  1621. return -EINVAL;
  1622. }
  1623. if (format != old_format || mode != old_mode) {
  1624. if (twl4030->codec_powered) {
  1625. /*
  1626. * If the codec is powered, than we need to toggle the
  1627. * codec power.
  1628. */
  1629. twl4030_codec_enable(codec, 0);
  1630. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1631. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1632. twl4030_codec_enable(codec, 1);
  1633. } else {
  1634. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1635. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1636. }
  1637. }
  1638. /* Store the important parameters for the DAI configuration and set
  1639. * the DAI as configured */
  1640. twl4030->configured = 1;
  1641. twl4030->rate = params_rate(params);
  1642. twl4030->sample_bits = hw_param_interval(params,
  1643. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1644. twl4030->channels = params_channels(params);
  1645. /* If both playback and capture streams are open, and one of them
  1646. * is setting the hw parameters right now (since we are here), set
  1647. * constraints to the other stream to match the current one. */
  1648. if (twl4030->slave_substream)
  1649. twl4030_constraints(twl4030, substream);
  1650. return 0;
  1651. }
  1652. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1653. int clk_id, unsigned int freq, int dir)
  1654. {
  1655. struct snd_soc_codec *codec = codec_dai->codec;
  1656. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1657. switch (freq) {
  1658. case 19200000:
  1659. case 26000000:
  1660. case 38400000:
  1661. break;
  1662. default:
  1663. dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
  1664. return -EINVAL;
  1665. }
  1666. if ((freq / 1000) != twl4030->sysclk) {
  1667. dev_err(codec->dev,
  1668. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1669. freq, twl4030->sysclk * 1000);
  1670. return -EINVAL;
  1671. }
  1672. return 0;
  1673. }
  1674. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1675. unsigned int fmt)
  1676. {
  1677. struct snd_soc_codec *codec = codec_dai->codec;
  1678. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1679. u8 old_format, format;
  1680. /* get format */
  1681. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1682. format = old_format;
  1683. /* set master/slave audio interface */
  1684. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1685. case SND_SOC_DAIFMT_CBM_CFM:
  1686. format &= ~(TWL4030_AIF_SLAVE_EN);
  1687. format &= ~(TWL4030_CLK256FS_EN);
  1688. break;
  1689. case SND_SOC_DAIFMT_CBS_CFS:
  1690. format |= TWL4030_AIF_SLAVE_EN;
  1691. format |= TWL4030_CLK256FS_EN;
  1692. break;
  1693. default:
  1694. return -EINVAL;
  1695. }
  1696. /* interface format */
  1697. format &= ~TWL4030_AIF_FORMAT;
  1698. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1699. case SND_SOC_DAIFMT_I2S:
  1700. format |= TWL4030_AIF_FORMAT_CODEC;
  1701. break;
  1702. case SND_SOC_DAIFMT_DSP_A:
  1703. format |= TWL4030_AIF_FORMAT_TDM;
  1704. break;
  1705. default:
  1706. return -EINVAL;
  1707. }
  1708. if (format != old_format) {
  1709. if (twl4030->codec_powered) {
  1710. /*
  1711. * If the codec is powered, than we need to toggle the
  1712. * codec power.
  1713. */
  1714. twl4030_codec_enable(codec, 0);
  1715. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1716. twl4030_codec_enable(codec, 1);
  1717. } else {
  1718. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1719. }
  1720. }
  1721. return 0;
  1722. }
  1723. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1724. {
  1725. struct snd_soc_codec *codec = dai->codec;
  1726. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1727. if (tristate)
  1728. reg |= TWL4030_AIF_TRI_EN;
  1729. else
  1730. reg &= ~TWL4030_AIF_TRI_EN;
  1731. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1732. }
  1733. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1734. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1735. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1736. int enable)
  1737. {
  1738. u8 reg, mask;
  1739. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1740. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1741. mask = TWL4030_ARXL1_VRX_EN;
  1742. else
  1743. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1744. if (enable)
  1745. reg |= mask;
  1746. else
  1747. reg &= ~mask;
  1748. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1749. }
  1750. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1751. struct snd_soc_dai *dai)
  1752. {
  1753. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1754. struct snd_soc_device *socdev = rtd->socdev;
  1755. struct snd_soc_codec *codec = socdev->card->codec;
  1756. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1757. u8 mode;
  1758. /* If the system master clock is not 26MHz, the voice PCM interface is
  1759. * not avilable.
  1760. */
  1761. if (twl4030->sysclk != 26000) {
  1762. dev_err(codec->dev, "The board is configured for %u Hz, while"
  1763. "the Voice interface needs 26MHz APLL mclk\n",
  1764. twl4030->sysclk * 1000);
  1765. return -EINVAL;
  1766. }
  1767. /* If the codec mode is not option2, the voice PCM interface is not
  1768. * avilable.
  1769. */
  1770. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1771. & TWL4030_OPT_MODE;
  1772. if (mode != TWL4030_OPTION_2) {
  1773. printk(KERN_ERR "TWL4030 voice startup: "
  1774. "the codec mode is not option2\n");
  1775. return -EINVAL;
  1776. }
  1777. return 0;
  1778. }
  1779. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1780. struct snd_soc_dai *dai)
  1781. {
  1782. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1783. struct snd_soc_device *socdev = rtd->socdev;
  1784. struct snd_soc_codec *codec = socdev->card->codec;
  1785. /* Enable voice digital filters */
  1786. twl4030_voice_enable(codec, substream->stream, 0);
  1787. }
  1788. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1789. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1790. {
  1791. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1792. struct snd_soc_device *socdev = rtd->socdev;
  1793. struct snd_soc_codec *codec = socdev->card->codec;
  1794. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1795. u8 old_mode, mode;
  1796. /* Enable voice digital filters */
  1797. twl4030_voice_enable(codec, substream->stream, 1);
  1798. /* bit rate */
  1799. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1800. & ~(TWL4030_CODECPDZ);
  1801. mode = old_mode;
  1802. switch (params_rate(params)) {
  1803. case 8000:
  1804. mode &= ~(TWL4030_SEL_16K);
  1805. break;
  1806. case 16000:
  1807. mode |= TWL4030_SEL_16K;
  1808. break;
  1809. default:
  1810. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1811. params_rate(params));
  1812. return -EINVAL;
  1813. }
  1814. if (mode != old_mode) {
  1815. if (twl4030->codec_powered) {
  1816. /*
  1817. * If the codec is powered, than we need to toggle the
  1818. * codec power.
  1819. */
  1820. twl4030_codec_enable(codec, 0);
  1821. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1822. twl4030_codec_enable(codec, 1);
  1823. } else {
  1824. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1825. }
  1826. }
  1827. return 0;
  1828. }
  1829. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1830. int clk_id, unsigned int freq, int dir)
  1831. {
  1832. struct snd_soc_codec *codec = codec_dai->codec;
  1833. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1834. if (freq != 26000000) {
  1835. dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
  1836. "interface needs 26MHz APLL mclk\n", freq);
  1837. return -EINVAL;
  1838. }
  1839. if ((freq / 1000) != twl4030->sysclk) {
  1840. dev_err(codec->dev,
  1841. "Mismatch in APLL mclk: %u (configured: %u)\n",
  1842. freq, twl4030->sysclk * 1000);
  1843. return -EINVAL;
  1844. }
  1845. return 0;
  1846. }
  1847. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1848. unsigned int fmt)
  1849. {
  1850. struct snd_soc_codec *codec = codec_dai->codec;
  1851. struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
  1852. u8 old_format, format;
  1853. /* get format */
  1854. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1855. format = old_format;
  1856. /* set master/slave audio interface */
  1857. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1858. case SND_SOC_DAIFMT_CBM_CFM:
  1859. format &= ~(TWL4030_VIF_SLAVE_EN);
  1860. break;
  1861. case SND_SOC_DAIFMT_CBS_CFS:
  1862. format |= TWL4030_VIF_SLAVE_EN;
  1863. break;
  1864. default:
  1865. return -EINVAL;
  1866. }
  1867. /* clock inversion */
  1868. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1869. case SND_SOC_DAIFMT_IB_NF:
  1870. format &= ~(TWL4030_VIF_FORMAT);
  1871. break;
  1872. case SND_SOC_DAIFMT_NB_IF:
  1873. format |= TWL4030_VIF_FORMAT;
  1874. break;
  1875. default:
  1876. return -EINVAL;
  1877. }
  1878. if (format != old_format) {
  1879. if (twl4030->codec_powered) {
  1880. /*
  1881. * If the codec is powered, than we need to toggle the
  1882. * codec power.
  1883. */
  1884. twl4030_codec_enable(codec, 0);
  1885. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1886. twl4030_codec_enable(codec, 1);
  1887. } else {
  1888. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1889. }
  1890. }
  1891. return 0;
  1892. }
  1893. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1894. {
  1895. struct snd_soc_codec *codec = dai->codec;
  1896. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1897. if (tristate)
  1898. reg |= TWL4030_VIF_TRI_EN;
  1899. else
  1900. reg &= ~TWL4030_VIF_TRI_EN;
  1901. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1902. }
  1903. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1904. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1905. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1906. .startup = twl4030_startup,
  1907. .shutdown = twl4030_shutdown,
  1908. .hw_params = twl4030_hw_params,
  1909. .set_sysclk = twl4030_set_dai_sysclk,
  1910. .set_fmt = twl4030_set_dai_fmt,
  1911. .set_tristate = twl4030_set_tristate,
  1912. };
  1913. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1914. .startup = twl4030_voice_startup,
  1915. .shutdown = twl4030_voice_shutdown,
  1916. .hw_params = twl4030_voice_hw_params,
  1917. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1918. .set_fmt = twl4030_voice_set_dai_fmt,
  1919. .set_tristate = twl4030_voice_set_tristate,
  1920. };
  1921. struct snd_soc_dai twl4030_dai[] = {
  1922. {
  1923. .name = "twl4030",
  1924. .playback = {
  1925. .stream_name = "HiFi Playback",
  1926. .channels_min = 2,
  1927. .channels_max = 4,
  1928. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1929. .formats = TWL4030_FORMATS,},
  1930. .capture = {
  1931. .stream_name = "Capture",
  1932. .channels_min = 2,
  1933. .channels_max = 4,
  1934. .rates = TWL4030_RATES,
  1935. .formats = TWL4030_FORMATS,},
  1936. .ops = &twl4030_dai_ops,
  1937. },
  1938. {
  1939. .name = "twl4030 Voice",
  1940. .playback = {
  1941. .stream_name = "Voice Playback",
  1942. .channels_min = 1,
  1943. .channels_max = 1,
  1944. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1945. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1946. .capture = {
  1947. .stream_name = "Capture",
  1948. .channels_min = 1,
  1949. .channels_max = 2,
  1950. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1951. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1952. .ops = &twl4030_dai_voice_ops,
  1953. },
  1954. };
  1955. EXPORT_SYMBOL_GPL(twl4030_dai);
  1956. static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state)
  1957. {
  1958. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1959. struct snd_soc_codec *codec = socdev->card->codec;
  1960. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1961. return 0;
  1962. }
  1963. static int twl4030_soc_resume(struct platform_device *pdev)
  1964. {
  1965. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1966. struct snd_soc_codec *codec = socdev->card->codec;
  1967. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1968. return 0;
  1969. }
  1970. static struct snd_soc_codec *twl4030_codec;
  1971. static int twl4030_soc_probe(struct platform_device *pdev)
  1972. {
  1973. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1974. struct snd_soc_codec *codec;
  1975. int ret;
  1976. BUG_ON(!twl4030_codec);
  1977. codec = twl4030_codec;
  1978. socdev->card->codec = codec;
  1979. twl4030_init_chip(pdev);
  1980. /* register pcms */
  1981. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1982. if (ret < 0) {
  1983. dev_err(&pdev->dev, "failed to create pcms\n");
  1984. return ret;
  1985. }
  1986. snd_soc_add_controls(codec, twl4030_snd_controls,
  1987. ARRAY_SIZE(twl4030_snd_controls));
  1988. twl4030_add_widgets(codec);
  1989. return 0;
  1990. }
  1991. static int twl4030_soc_remove(struct platform_device *pdev)
  1992. {
  1993. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1994. struct snd_soc_codec *codec = socdev->card->codec;
  1995. /* Reset registers to their chip default before leaving */
  1996. twl4030_reset_registers(codec);
  1997. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1998. snd_soc_free_pcms(socdev);
  1999. snd_soc_dapm_free(socdev);
  2000. return 0;
  2001. }
  2002. static int __devinit twl4030_codec_probe(struct platform_device *pdev)
  2003. {
  2004. struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
  2005. struct snd_soc_codec *codec;
  2006. struct twl4030_priv *twl4030;
  2007. int ret;
  2008. if (!pdata) {
  2009. dev_err(&pdev->dev, "platform_data is missing\n");
  2010. return -EINVAL;
  2011. }
  2012. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  2013. if (twl4030 == NULL) {
  2014. dev_err(&pdev->dev, "Can not allocate memroy\n");
  2015. return -ENOMEM;
  2016. }
  2017. codec = &twl4030->codec;
  2018. snd_soc_codec_set_drvdata(codec, twl4030);
  2019. codec->dev = &pdev->dev;
  2020. twl4030_dai[0].dev = &pdev->dev;
  2021. twl4030_dai[1].dev = &pdev->dev;
  2022. mutex_init(&codec->mutex);
  2023. INIT_LIST_HEAD(&codec->dapm_widgets);
  2024. INIT_LIST_HEAD(&codec->dapm_paths);
  2025. codec->name = "twl4030";
  2026. codec->owner = THIS_MODULE;
  2027. codec->read = twl4030_read_reg_cache;
  2028. codec->write = twl4030_write;
  2029. codec->set_bias_level = twl4030_set_bias_level;
  2030. codec->idle_bias_off = 1;
  2031. codec->dai = twl4030_dai;
  2032. codec->num_dai = ARRAY_SIZE(twl4030_dai);
  2033. codec->reg_cache_size = sizeof(twl4030_reg);
  2034. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  2035. GFP_KERNEL);
  2036. if (codec->reg_cache == NULL) {
  2037. ret = -ENOMEM;
  2038. goto error_cache;
  2039. }
  2040. platform_set_drvdata(pdev, twl4030);
  2041. twl4030_codec = codec;
  2042. /* Set the defaults, and power up the codec */
  2043. twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
  2044. codec->bias_level = SND_SOC_BIAS_OFF;
  2045. ret = snd_soc_register_codec(codec);
  2046. if (ret != 0) {
  2047. dev_err(codec->dev, "Failed to register codec: %d\n", ret);
  2048. goto error_codec;
  2049. }
  2050. ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2051. if (ret != 0) {
  2052. dev_err(codec->dev, "Failed to register DAIs: %d\n", ret);
  2053. snd_soc_unregister_codec(codec);
  2054. goto error_codec;
  2055. }
  2056. return 0;
  2057. error_codec:
  2058. twl4030_codec_enable(codec, 0);
  2059. kfree(codec->reg_cache);
  2060. error_cache:
  2061. kfree(twl4030);
  2062. return ret;
  2063. }
  2064. static int __devexit twl4030_codec_remove(struct platform_device *pdev)
  2065. {
  2066. struct twl4030_priv *twl4030 = platform_get_drvdata(pdev);
  2067. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  2068. snd_soc_unregister_codec(&twl4030->codec);
  2069. kfree(twl4030->codec.reg_cache);
  2070. kfree(twl4030);
  2071. twl4030_codec = NULL;
  2072. return 0;
  2073. }
  2074. MODULE_ALIAS("platform:twl4030_codec_audio");
  2075. static struct platform_driver twl4030_codec_driver = {
  2076. .probe = twl4030_codec_probe,
  2077. .remove = __devexit_p(twl4030_codec_remove),
  2078. .driver = {
  2079. .name = "twl4030_codec_audio",
  2080. .owner = THIS_MODULE,
  2081. },
  2082. };
  2083. static int __init twl4030_modinit(void)
  2084. {
  2085. return platform_driver_register(&twl4030_codec_driver);
  2086. }
  2087. module_init(twl4030_modinit);
  2088. static void __exit twl4030_exit(void)
  2089. {
  2090. platform_driver_unregister(&twl4030_codec_driver);
  2091. }
  2092. module_exit(twl4030_exit);
  2093. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  2094. .probe = twl4030_soc_probe,
  2095. .remove = twl4030_soc_remove,
  2096. .suspend = twl4030_soc_suspend,
  2097. .resume = twl4030_soc_resume,
  2098. };
  2099. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  2100. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  2101. MODULE_AUTHOR("Steve Sakoman");
  2102. MODULE_LICENSE("GPL");