at91sam9263.dtsi 8.5 KB

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  1. /*
  2. * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. /include/ "skeleton.dtsi"
  9. / {
  10. model = "Atmel AT91SAM9263 family SoC";
  11. compatible = "atmel,at91sam9263";
  12. interrupt-parent = <&aic>;
  13. aliases {
  14. serial0 = &dbgu;
  15. serial1 = &usart0;
  16. serial2 = &usart1;
  17. serial3 = &usart2;
  18. gpio0 = &pioA;
  19. gpio1 = &pioB;
  20. gpio2 = &pioC;
  21. gpio3 = &pioD;
  22. gpio4 = &pioE;
  23. tcb0 = &tcb0;
  24. i2c0 = &i2c0;
  25. };
  26. cpus {
  27. cpu@0 {
  28. compatible = "arm,arm926ejs";
  29. };
  30. };
  31. memory {
  32. reg = <0x20000000 0x08000000>;
  33. };
  34. ahb {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. ranges;
  39. apb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. aic: interrupt-controller@fffff000 {
  45. #interrupt-cells = <3>;
  46. compatible = "atmel,at91rm9200-aic";
  47. interrupt-controller;
  48. reg = <0xfffff000 0x200>;
  49. atmel,external-irqs = <30 31>;
  50. };
  51. pmc: pmc@fffffc00 {
  52. compatible = "atmel,at91rm9200-pmc";
  53. reg = <0xfffffc00 0x100>;
  54. };
  55. ramc: ramc@ffffe200 {
  56. compatible = "atmel,at91sam9260-sdramc";
  57. reg = <0xffffe200 0x200
  58. 0xffffe800 0x200>;
  59. };
  60. pit: timer@fffffd30 {
  61. compatible = "atmel,at91sam9260-pit";
  62. reg = <0xfffffd30 0xf>;
  63. interrupts = <1 4 7>;
  64. };
  65. tcb0: timer@fff7c000 {
  66. compatible = "atmel,at91rm9200-tcb";
  67. reg = <0xfff7c000 0x100>;
  68. interrupts = <19 4 0>;
  69. };
  70. rstc@fffffd00 {
  71. compatible = "atmel,at91sam9260-rstc";
  72. reg = <0xfffffd00 0x10>;
  73. };
  74. shdwc@fffffd10 {
  75. compatible = "atmel,at91sam9260-shdwc";
  76. reg = <0xfffffd10 0x10>;
  77. };
  78. pinctrl@fffff200 {
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  82. ranges = <0xfffff200 0xfffff200 0xa00>;
  83. atmel,mux-mask = <
  84. /* A B */
  85. 0xfffffffb 0xffffe07f /* pioA */
  86. 0x0007ffff 0x39072fff /* pioB */
  87. 0xffffffff 0x3ffffff8 /* pioC */
  88. 0xfffffbff 0xffffffff /* pioD */
  89. 0xffe00fff 0xfbfcff00 /* pioE */
  90. >;
  91. /* shared pinctrl settings */
  92. dbgu {
  93. pinctrl_dbgu: dbgu-0 {
  94. atmel,pins =
  95. <2 30 0x1 0x0 /* PC30 periph A */
  96. 2 31 0x1 0x1>; /* PC31 periph with pullup */
  97. };
  98. };
  99. usart0 {
  100. pinctrl_usart0: usart0-0 {
  101. atmel,pins =
  102. <0 26 0x1 0x1 /* PA26 periph A with pullup */
  103. 0 27 0x1 0x0>; /* PA27 periph A */
  104. };
  105. pinctrl_usart0_rts: usart0_rts-0 {
  106. atmel,pins =
  107. <0 28 0x1 0x0>; /* PA28 periph A */
  108. };
  109. pinctrl_usart0_cts: usart0_cts-0 {
  110. atmel,pins =
  111. <0 29 0x1 0x0>; /* PA29 periph A */
  112. };
  113. };
  114. usart1 {
  115. pinctrl_usart1: usart1-0 {
  116. atmel,pins =
  117. <3 0 0x1 0x1 /* PD0 periph A with pullup */
  118. 3 1 0x1 0x0>; /* PD1 periph A */
  119. };
  120. pinctrl_usart1_rts: usart1_rts-0 {
  121. atmel,pins =
  122. <3 7 0x2 0x0>; /* PD7 periph B */
  123. };
  124. pinctrl_usart1_cts: usart1_cts-0 {
  125. atmel,pins =
  126. <3 8 0x2 0x0>; /* PD8 periph B */
  127. };
  128. };
  129. usart2 {
  130. pinctrl_usart2: usart2-0 {
  131. atmel,pins =
  132. <3 2 0x1 0x1 /* PD2 periph A with pullup */
  133. 3 3 0x1 0x0>; /* PD3 periph A */
  134. };
  135. pinctrl_usart2_rts: usart2_rts-0 {
  136. atmel,pins =
  137. <3 5 0x2 0x0>; /* PD5 periph B */
  138. };
  139. pinctrl_usart2_cts: usart2_cts-0 {
  140. atmel,pins =
  141. <4 6 0x2 0x0>; /* PD6 periph B */
  142. };
  143. };
  144. nand {
  145. pinctrl_nand: nand-0 {
  146. atmel,pins =
  147. <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
  148. 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
  149. };
  150. };
  151. macb {
  152. pinctrl_macb_rmii: macb_rmii-0 {
  153. atmel,pins =
  154. <2 25 0x2 0x0 /* PC25 periph B */
  155. 4 21 0x1 0x0 /* PE21 periph A */
  156. 4 23 0x1 0x0 /* PE23 periph A */
  157. 4 24 0x1 0x0 /* PE24 periph A */
  158. 4 25 0x1 0x0 /* PE25 periph A */
  159. 4 26 0x1 0x0 /* PE26 periph A */
  160. 4 27 0x1 0x0 /* PE27 periph A */
  161. 4 28 0x1 0x0 /* PE28 periph A */
  162. 4 29 0x1 0x0 /* PE29 periph A */
  163. 4 30 0x1 0x0>; /* PE30 periph A */
  164. };
  165. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  166. atmel,pins =
  167. <2 20 0x2 0x0 /* PC20 periph B */
  168. 2 21 0x2 0x0 /* PC21 periph B */
  169. 2 22 0x2 0x0 /* PC22 periph B */
  170. 2 23 0x2 0x0 /* PC23 periph B */
  171. 2 24 0x2 0x0 /* PC24 periph B */
  172. 2 25 0x2 0x0 /* PC25 periph B */
  173. 2 27 0x2 0x0 /* PC27 periph B */
  174. 4 22 0x2 0x0>; /* PE22 periph B */
  175. };
  176. };
  177. pioA: gpio@fffff200 {
  178. compatible = "atmel,at91rm9200-gpio";
  179. reg = <0xfffff200 0x200>;
  180. interrupts = <2 4 1>;
  181. #gpio-cells = <2>;
  182. gpio-controller;
  183. interrupt-controller;
  184. #interrupt-cells = <2>;
  185. };
  186. pioB: gpio@fffff400 {
  187. compatible = "atmel,at91rm9200-gpio";
  188. reg = <0xfffff400 0x200>;
  189. interrupts = <3 4 1>;
  190. #gpio-cells = <2>;
  191. gpio-controller;
  192. interrupt-controller;
  193. #interrupt-cells = <2>;
  194. };
  195. pioC: gpio@fffff600 {
  196. compatible = "atmel,at91rm9200-gpio";
  197. reg = <0xfffff600 0x200>;
  198. interrupts = <4 4 1>;
  199. #gpio-cells = <2>;
  200. gpio-controller;
  201. interrupt-controller;
  202. #interrupt-cells = <2>;
  203. };
  204. pioD: gpio@fffff800 {
  205. compatible = "atmel,at91rm9200-gpio";
  206. reg = <0xfffff800 0x200>;
  207. interrupts = <4 4 1>;
  208. #gpio-cells = <2>;
  209. gpio-controller;
  210. interrupt-controller;
  211. #interrupt-cells = <2>;
  212. };
  213. pioE: gpio@fffffa00 {
  214. compatible = "atmel,at91rm9200-gpio";
  215. reg = <0xfffffa00 0x200>;
  216. interrupts = <4 4 1>;
  217. #gpio-cells = <2>;
  218. gpio-controller;
  219. interrupt-controller;
  220. #interrupt-cells = <2>;
  221. };
  222. };
  223. dbgu: serial@ffffee00 {
  224. compatible = "atmel,at91sam9260-usart";
  225. reg = <0xffffee00 0x200>;
  226. interrupts = <1 4 7>;
  227. pinctrl-names = "default";
  228. pinctrl-0 = <&pinctrl_dbgu>;
  229. status = "disabled";
  230. };
  231. usart0: serial@fff8c000 {
  232. compatible = "atmel,at91sam9260-usart";
  233. reg = <0xfff8c000 0x200>;
  234. interrupts = <7 4 5>;
  235. atmel,use-dma-rx;
  236. atmel,use-dma-tx;
  237. pinctrl-names = "default";
  238. pinctrl-0 = <&pinctrl_usart0>;
  239. status = "disabled";
  240. };
  241. usart1: serial@fff90000 {
  242. compatible = "atmel,at91sam9260-usart";
  243. reg = <0xfff90000 0x200>;
  244. interrupts = <8 4 5>;
  245. atmel,use-dma-rx;
  246. atmel,use-dma-tx;
  247. pinctrl-names = "default";
  248. pinctrl-0 = <&pinctrl_usart1>;
  249. status = "disabled";
  250. };
  251. usart2: serial@fff94000 {
  252. compatible = "atmel,at91sam9260-usart";
  253. reg = <0xfff94000 0x200>;
  254. interrupts = <9 4 5>;
  255. atmel,use-dma-rx;
  256. atmel,use-dma-tx;
  257. pinctrl-names = "default";
  258. pinctrl-0 = <&pinctrl_usart2>;
  259. status = "disabled";
  260. };
  261. macb0: ethernet@fffbc000 {
  262. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  263. reg = <0xfffbc000 0x100>;
  264. interrupts = <21 4 3>;
  265. pinctrl-names = "default";
  266. pinctrl-0 = <&pinctrl_macb_rmii>;
  267. status = "disabled";
  268. };
  269. usb1: gadget@fff78000 {
  270. compatible = "atmel,at91rm9200-udc";
  271. reg = <0xfff78000 0x4000>;
  272. interrupts = <24 4 2>;
  273. status = "disabled";
  274. };
  275. i2c0: i2c@fff88000 {
  276. compatible = "atmel,at91sam9263-i2c";
  277. reg = <0xfff88000 0x100>;
  278. interrupts = <13 4 6>;
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. status = "disabled";
  282. };
  283. mmc0: mmc@fff80000 {
  284. compatible = "atmel,hsmci";
  285. reg = <0xfff80000 0x600>;
  286. interrupts = <10 4 0>;
  287. #address-cells = <1>;
  288. #size-cells = <0>;
  289. status = "disabled";
  290. };
  291. mmc1: mmc@fff84000 {
  292. compatible = "atmel,hsmci";
  293. reg = <0xfff84000 0x600>;
  294. interrupts = <11 4 0>;
  295. #address-cells = <1>;
  296. #size-cells = <0>;
  297. status = "disabled";
  298. };
  299. };
  300. nand0: nand@40000000 {
  301. compatible = "atmel,at91rm9200-nand";
  302. #address-cells = <1>;
  303. #size-cells = <1>;
  304. reg = <0x40000000 0x10000000
  305. 0xffffe000 0x200
  306. >;
  307. atmel,nand-addr-offset = <21>;
  308. atmel,nand-cmd-offset = <22>;
  309. pinctrl-names = "default";
  310. pinctrl-0 = <&pinctrl_nand>;
  311. gpios = <&pioA 22 0
  312. &pioD 15 0
  313. 0
  314. >;
  315. status = "disabled";
  316. };
  317. usb0: ohci@00a00000 {
  318. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  319. reg = <0x00a00000 0x100000>;
  320. interrupts = <29 4 2>;
  321. status = "disabled";
  322. };
  323. };
  324. i2c@0 {
  325. compatible = "i2c-gpio";
  326. gpios = <&pioB 4 0 /* sda */
  327. &pioB 5 0 /* scl */
  328. >;
  329. i2c-gpio,sda-open-drain;
  330. i2c-gpio,scl-open-drain;
  331. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  332. #address-cells = <1>;
  333. #size-cells = <0>;
  334. status = "disabled";
  335. };
  336. };