sdhci.c 36 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/highmem.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mmc/protocol.h>
  16. #include <asm/scatterlist.h>
  17. #include "sdhci.h"
  18. #define DRIVER_NAME "sdhci"
  19. #define DRIVER_VERSION "0.12"
  20. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  21. #define DBG(f, x...) \
  22. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  23. static unsigned int debug_nodma = 0;
  24. static unsigned int debug_forcedma = 0;
  25. static unsigned int debug_quirks = 0;
  26. #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
  27. #define SDHCI_QUIRK_FORCE_DMA (1<<1)
  28. static const struct pci_device_id pci_ids[] __devinitdata = {
  29. {
  30. .vendor = PCI_VENDOR_ID_RICOH,
  31. .device = PCI_DEVICE_ID_RICOH_R5C822,
  32. .subvendor = PCI_VENDOR_ID_IBM,
  33. .subdevice = PCI_ANY_ID,
  34. .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  35. SDHCI_QUIRK_FORCE_DMA,
  36. },
  37. {
  38. .vendor = PCI_VENDOR_ID_RICOH,
  39. .device = PCI_DEVICE_ID_RICOH_R5C822,
  40. .subvendor = PCI_ANY_ID,
  41. .subdevice = PCI_ANY_ID,
  42. .driver_data = SDHCI_QUIRK_FORCE_DMA,
  43. },
  44. {
  45. .vendor = PCI_VENDOR_ID_TI,
  46. .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  47. .subvendor = PCI_ANY_ID,
  48. .subdevice = PCI_ANY_ID,
  49. .driver_data = SDHCI_QUIRK_FORCE_DMA,
  50. },
  51. { /* Generic SD host controller */
  52. PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
  53. },
  54. { /* end: all zeroes */ },
  55. };
  56. MODULE_DEVICE_TABLE(pci, pci_ids);
  57. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  58. static void sdhci_finish_data(struct sdhci_host *);
  59. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  60. static void sdhci_finish_command(struct sdhci_host *);
  61. static void sdhci_dumpregs(struct sdhci_host *host)
  62. {
  63. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  64. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  65. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  66. readw(host->ioaddr + SDHCI_HOST_VERSION));
  67. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  68. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  69. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  70. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  71. readl(host->ioaddr + SDHCI_ARGUMENT),
  72. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  73. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  74. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  75. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  76. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  77. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  78. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  79. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  80. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  81. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  82. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  83. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  84. readl(host->ioaddr + SDHCI_INT_STATUS));
  85. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  86. readl(host->ioaddr + SDHCI_INT_ENABLE),
  87. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  88. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  89. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  90. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  91. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  92. readl(host->ioaddr + SDHCI_CAPABILITIES),
  93. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  94. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  95. }
  96. /*****************************************************************************\
  97. * *
  98. * Low level functions *
  99. * *
  100. \*****************************************************************************/
  101. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  102. {
  103. unsigned long timeout;
  104. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  105. if (mask & SDHCI_RESET_ALL)
  106. host->clock = 0;
  107. /* Wait max 100 ms */
  108. timeout = 100;
  109. /* hw clears the bit when it's done */
  110. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  111. if (timeout == 0) {
  112. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  113. "Please report this to " BUGMAIL ".\n",
  114. mmc_hostname(host->mmc), (int)mask);
  115. sdhci_dumpregs(host);
  116. return;
  117. }
  118. timeout--;
  119. mdelay(1);
  120. }
  121. }
  122. static void sdhci_init(struct sdhci_host *host)
  123. {
  124. u32 intmask;
  125. sdhci_reset(host, SDHCI_RESET_ALL);
  126. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  127. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  128. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  129. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  130. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
  131. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  132. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  133. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  134. }
  135. static void sdhci_activate_led(struct sdhci_host *host)
  136. {
  137. u8 ctrl;
  138. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  139. ctrl |= SDHCI_CTRL_LED;
  140. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  141. }
  142. static void sdhci_deactivate_led(struct sdhci_host *host)
  143. {
  144. u8 ctrl;
  145. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  146. ctrl &= ~SDHCI_CTRL_LED;
  147. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  148. }
  149. /*****************************************************************************\
  150. * *
  151. * Core functions *
  152. * *
  153. \*****************************************************************************/
  154. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  155. {
  156. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  157. return host->mapped_sg + host->cur_sg->offset;
  158. }
  159. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  160. {
  161. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  162. }
  163. static inline int sdhci_next_sg(struct sdhci_host* host)
  164. {
  165. /*
  166. * Skip to next SG entry.
  167. */
  168. host->cur_sg++;
  169. host->num_sg--;
  170. /*
  171. * Any entries left?
  172. */
  173. if (host->num_sg > 0) {
  174. host->offset = 0;
  175. host->remain = host->cur_sg->length;
  176. }
  177. return host->num_sg;
  178. }
  179. static void sdhci_read_block_pio(struct sdhci_host *host)
  180. {
  181. int blksize, chunk_remain;
  182. u32 data;
  183. char *buffer;
  184. int size;
  185. DBG("PIO reading\n");
  186. blksize = host->data->blksz;
  187. chunk_remain = 0;
  188. data = 0;
  189. buffer = sdhci_kmap_sg(host) + host->offset;
  190. while (blksize) {
  191. if (chunk_remain == 0) {
  192. data = readl(host->ioaddr + SDHCI_BUFFER);
  193. chunk_remain = min(blksize, 4);
  194. }
  195. size = min(host->size, host->remain);
  196. size = min(size, chunk_remain);
  197. chunk_remain -= size;
  198. blksize -= size;
  199. host->offset += size;
  200. host->remain -= size;
  201. host->size -= size;
  202. while (size) {
  203. *buffer = data & 0xFF;
  204. buffer++;
  205. data >>= 8;
  206. size--;
  207. }
  208. if (host->remain == 0) {
  209. sdhci_kunmap_sg(host);
  210. if (sdhci_next_sg(host) == 0) {
  211. BUG_ON(blksize != 0);
  212. return;
  213. }
  214. buffer = sdhci_kmap_sg(host);
  215. }
  216. }
  217. sdhci_kunmap_sg(host);
  218. }
  219. static void sdhci_write_block_pio(struct sdhci_host *host)
  220. {
  221. int blksize, chunk_remain;
  222. u32 data;
  223. char *buffer;
  224. int bytes, size;
  225. DBG("PIO writing\n");
  226. blksize = host->data->blksz;
  227. chunk_remain = 4;
  228. data = 0;
  229. bytes = 0;
  230. buffer = sdhci_kmap_sg(host) + host->offset;
  231. while (blksize) {
  232. size = min(host->size, host->remain);
  233. size = min(size, chunk_remain);
  234. chunk_remain -= size;
  235. blksize -= size;
  236. host->offset += size;
  237. host->remain -= size;
  238. host->size -= size;
  239. while (size) {
  240. data >>= 8;
  241. data |= (u32)*buffer << 24;
  242. buffer++;
  243. size--;
  244. }
  245. if (chunk_remain == 0) {
  246. writel(data, host->ioaddr + SDHCI_BUFFER);
  247. chunk_remain = min(blksize, 4);
  248. }
  249. if (host->remain == 0) {
  250. sdhci_kunmap_sg(host);
  251. if (sdhci_next_sg(host) == 0) {
  252. BUG_ON(blksize != 0);
  253. return;
  254. }
  255. buffer = sdhci_kmap_sg(host);
  256. }
  257. }
  258. sdhci_kunmap_sg(host);
  259. }
  260. static void sdhci_transfer_pio(struct sdhci_host *host)
  261. {
  262. u32 mask;
  263. BUG_ON(!host->data);
  264. if (host->size == 0)
  265. return;
  266. if (host->data->flags & MMC_DATA_READ)
  267. mask = SDHCI_DATA_AVAILABLE;
  268. else
  269. mask = SDHCI_SPACE_AVAILABLE;
  270. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  271. if (host->data->flags & MMC_DATA_READ)
  272. sdhci_read_block_pio(host);
  273. else
  274. sdhci_write_block_pio(host);
  275. if (host->size == 0)
  276. break;
  277. BUG_ON(host->num_sg == 0);
  278. }
  279. DBG("PIO transfer complete.\n");
  280. }
  281. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  282. {
  283. u8 count;
  284. unsigned target_timeout, current_timeout;
  285. WARN_ON(host->data);
  286. if (data == NULL)
  287. return;
  288. DBG("blksz %04x blks %04x flags %08x\n",
  289. data->blksz, data->blocks, data->flags);
  290. DBG("tsac %d ms nsac %d clk\n",
  291. data->timeout_ns / 1000000, data->timeout_clks);
  292. /* Sanity checks */
  293. BUG_ON(data->blksz * data->blocks > 524288);
  294. BUG_ON(data->blksz > host->max_block);
  295. BUG_ON(data->blocks > 65535);
  296. /* timeout in us */
  297. target_timeout = data->timeout_ns / 1000 +
  298. data->timeout_clks / host->clock;
  299. /*
  300. * Figure out needed cycles.
  301. * We do this in steps in order to fit inside a 32 bit int.
  302. * The first step is the minimum timeout, which will have a
  303. * minimum resolution of 6 bits:
  304. * (1) 2^13*1000 > 2^22,
  305. * (2) host->timeout_clk < 2^16
  306. * =>
  307. * (1) / (2) > 2^6
  308. */
  309. count = 0;
  310. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  311. while (current_timeout < target_timeout) {
  312. count++;
  313. current_timeout <<= 1;
  314. if (count >= 0xF)
  315. break;
  316. }
  317. if (count >= 0xF) {
  318. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  319. mmc_hostname(host->mmc));
  320. count = 0xE;
  321. }
  322. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  323. if (host->flags & SDHCI_USE_DMA) {
  324. int count;
  325. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  326. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  327. BUG_ON(count != 1);
  328. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  329. } else {
  330. host->size = data->blksz * data->blocks;
  331. host->cur_sg = data->sg;
  332. host->num_sg = data->sg_len;
  333. host->offset = 0;
  334. host->remain = host->cur_sg->length;
  335. }
  336. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  337. writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
  338. host->ioaddr + SDHCI_BLOCK_SIZE);
  339. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  340. }
  341. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  342. struct mmc_data *data)
  343. {
  344. u16 mode;
  345. WARN_ON(host->data);
  346. if (data == NULL)
  347. return;
  348. mode = SDHCI_TRNS_BLK_CNT_EN;
  349. if (data->blocks > 1)
  350. mode |= SDHCI_TRNS_MULTI;
  351. if (data->flags & MMC_DATA_READ)
  352. mode |= SDHCI_TRNS_READ;
  353. if (host->flags & SDHCI_USE_DMA)
  354. mode |= SDHCI_TRNS_DMA;
  355. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  356. }
  357. static void sdhci_finish_data(struct sdhci_host *host)
  358. {
  359. struct mmc_data *data;
  360. u16 blocks;
  361. BUG_ON(!host->data);
  362. data = host->data;
  363. host->data = NULL;
  364. if (host->flags & SDHCI_USE_DMA) {
  365. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  366. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  367. }
  368. /*
  369. * Controller doesn't count down when in single block mode.
  370. */
  371. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  372. blocks = 0;
  373. else
  374. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  375. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  376. if ((data->error == MMC_ERR_NONE) && blocks) {
  377. printk(KERN_ERR "%s: Controller signalled completion even "
  378. "though there were blocks left. Please report this "
  379. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  380. data->error = MMC_ERR_FAILED;
  381. }
  382. if (host->size != 0) {
  383. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  384. "Please report this to " BUGMAIL ".\n",
  385. mmc_hostname(host->mmc), host->size);
  386. data->error = MMC_ERR_FAILED;
  387. }
  388. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  389. if (data->stop) {
  390. /*
  391. * The controller needs a reset of internal state machines
  392. * upon error conditions.
  393. */
  394. if (data->error != MMC_ERR_NONE) {
  395. sdhci_reset(host, SDHCI_RESET_CMD);
  396. sdhci_reset(host, SDHCI_RESET_DATA);
  397. }
  398. sdhci_send_command(host, data->stop);
  399. } else
  400. tasklet_schedule(&host->finish_tasklet);
  401. }
  402. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  403. {
  404. int flags;
  405. u32 mask;
  406. unsigned long timeout;
  407. WARN_ON(host->cmd);
  408. DBG("Sending cmd (%x)\n", cmd->opcode);
  409. /* Wait max 10 ms */
  410. timeout = 10;
  411. mask = SDHCI_CMD_INHIBIT;
  412. if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
  413. mask |= SDHCI_DATA_INHIBIT;
  414. /* We shouldn't wait for data inihibit for stop commands, even
  415. though they might use busy signaling */
  416. if (host->mrq->data && (cmd == host->mrq->data->stop))
  417. mask &= ~SDHCI_DATA_INHIBIT;
  418. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  419. if (timeout == 0) {
  420. printk(KERN_ERR "%s: Controller never released "
  421. "inhibit bit(s). Please report this to "
  422. BUGMAIL ".\n", mmc_hostname(host->mmc));
  423. sdhci_dumpregs(host);
  424. cmd->error = MMC_ERR_FAILED;
  425. tasklet_schedule(&host->finish_tasklet);
  426. return;
  427. }
  428. timeout--;
  429. mdelay(1);
  430. }
  431. mod_timer(&host->timer, jiffies + 10 * HZ);
  432. host->cmd = cmd;
  433. sdhci_prepare_data(host, cmd->data);
  434. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  435. sdhci_set_transfer_mode(host, cmd->data);
  436. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  437. printk(KERN_ERR "%s: Unsupported response type! "
  438. "Please report this to " BUGMAIL ".\n",
  439. mmc_hostname(host->mmc));
  440. cmd->error = MMC_ERR_INVALID;
  441. tasklet_schedule(&host->finish_tasklet);
  442. return;
  443. }
  444. if (!(cmd->flags & MMC_RSP_PRESENT))
  445. flags = SDHCI_CMD_RESP_NONE;
  446. else if (cmd->flags & MMC_RSP_136)
  447. flags = SDHCI_CMD_RESP_LONG;
  448. else if (cmd->flags & MMC_RSP_BUSY)
  449. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  450. else
  451. flags = SDHCI_CMD_RESP_SHORT;
  452. if (cmd->flags & MMC_RSP_CRC)
  453. flags |= SDHCI_CMD_CRC;
  454. if (cmd->flags & MMC_RSP_OPCODE)
  455. flags |= SDHCI_CMD_INDEX;
  456. if (cmd->data)
  457. flags |= SDHCI_CMD_DATA;
  458. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  459. host->ioaddr + SDHCI_COMMAND);
  460. }
  461. static void sdhci_finish_command(struct sdhci_host *host)
  462. {
  463. int i;
  464. BUG_ON(host->cmd == NULL);
  465. if (host->cmd->flags & MMC_RSP_PRESENT) {
  466. if (host->cmd->flags & MMC_RSP_136) {
  467. /* CRC is stripped so we need to do some shifting. */
  468. for (i = 0;i < 4;i++) {
  469. host->cmd->resp[i] = readl(host->ioaddr +
  470. SDHCI_RESPONSE + (3-i)*4) << 8;
  471. if (i != 3)
  472. host->cmd->resp[i] |=
  473. readb(host->ioaddr +
  474. SDHCI_RESPONSE + (3-i)*4-1);
  475. }
  476. } else {
  477. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  478. }
  479. }
  480. host->cmd->error = MMC_ERR_NONE;
  481. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  482. if (host->cmd->data)
  483. host->data = host->cmd->data;
  484. else
  485. tasklet_schedule(&host->finish_tasklet);
  486. host->cmd = NULL;
  487. }
  488. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  489. {
  490. int div;
  491. u16 clk;
  492. unsigned long timeout;
  493. if (clock == host->clock)
  494. return;
  495. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  496. if (clock == 0)
  497. goto out;
  498. for (div = 1;div < 256;div *= 2) {
  499. if ((host->max_clk / div) <= clock)
  500. break;
  501. }
  502. div >>= 1;
  503. clk = div << SDHCI_DIVIDER_SHIFT;
  504. clk |= SDHCI_CLOCK_INT_EN;
  505. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  506. /* Wait max 10 ms */
  507. timeout = 10;
  508. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  509. & SDHCI_CLOCK_INT_STABLE)) {
  510. if (timeout == 0) {
  511. printk(KERN_ERR "%s: Internal clock never stabilised. "
  512. "Please report this to " BUGMAIL ".\n",
  513. mmc_hostname(host->mmc));
  514. sdhci_dumpregs(host);
  515. return;
  516. }
  517. timeout--;
  518. mdelay(1);
  519. }
  520. clk |= SDHCI_CLOCK_CARD_EN;
  521. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  522. out:
  523. host->clock = clock;
  524. }
  525. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  526. {
  527. u8 pwr;
  528. if (host->power == power)
  529. return;
  530. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  531. if (power == (unsigned short)-1)
  532. goto out;
  533. pwr = SDHCI_POWER_ON;
  534. switch (power) {
  535. case MMC_VDD_170:
  536. case MMC_VDD_180:
  537. case MMC_VDD_190:
  538. pwr |= SDHCI_POWER_180;
  539. break;
  540. case MMC_VDD_290:
  541. case MMC_VDD_300:
  542. case MMC_VDD_310:
  543. pwr |= SDHCI_POWER_300;
  544. break;
  545. case MMC_VDD_320:
  546. case MMC_VDD_330:
  547. case MMC_VDD_340:
  548. pwr |= SDHCI_POWER_330;
  549. break;
  550. default:
  551. BUG();
  552. }
  553. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  554. out:
  555. host->power = power;
  556. }
  557. /*****************************************************************************\
  558. * *
  559. * MMC callbacks *
  560. * *
  561. \*****************************************************************************/
  562. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  563. {
  564. struct sdhci_host *host;
  565. unsigned long flags;
  566. host = mmc_priv(mmc);
  567. spin_lock_irqsave(&host->lock, flags);
  568. WARN_ON(host->mrq != NULL);
  569. sdhci_activate_led(host);
  570. host->mrq = mrq;
  571. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  572. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  573. tasklet_schedule(&host->finish_tasklet);
  574. } else
  575. sdhci_send_command(host, mrq->cmd);
  576. spin_unlock_irqrestore(&host->lock, flags);
  577. }
  578. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  579. {
  580. struct sdhci_host *host;
  581. unsigned long flags;
  582. u8 ctrl;
  583. host = mmc_priv(mmc);
  584. spin_lock_irqsave(&host->lock, flags);
  585. /*
  586. * Reset the chip on each power off.
  587. * Should clear out any weird states.
  588. */
  589. if (ios->power_mode == MMC_POWER_OFF) {
  590. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  591. sdhci_init(host);
  592. }
  593. sdhci_set_clock(host, ios->clock);
  594. if (ios->power_mode == MMC_POWER_OFF)
  595. sdhci_set_power(host, -1);
  596. else
  597. sdhci_set_power(host, ios->vdd);
  598. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  599. if (ios->bus_width == MMC_BUS_WIDTH_4)
  600. ctrl |= SDHCI_CTRL_4BITBUS;
  601. else
  602. ctrl &= ~SDHCI_CTRL_4BITBUS;
  603. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  604. spin_unlock_irqrestore(&host->lock, flags);
  605. }
  606. static int sdhci_get_ro(struct mmc_host *mmc)
  607. {
  608. struct sdhci_host *host;
  609. unsigned long flags;
  610. int present;
  611. host = mmc_priv(mmc);
  612. spin_lock_irqsave(&host->lock, flags);
  613. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  614. spin_unlock_irqrestore(&host->lock, flags);
  615. return !(present & SDHCI_WRITE_PROTECT);
  616. }
  617. static struct mmc_host_ops sdhci_ops = {
  618. .request = sdhci_request,
  619. .set_ios = sdhci_set_ios,
  620. .get_ro = sdhci_get_ro,
  621. };
  622. /*****************************************************************************\
  623. * *
  624. * Tasklets *
  625. * *
  626. \*****************************************************************************/
  627. static void sdhci_tasklet_card(unsigned long param)
  628. {
  629. struct sdhci_host *host;
  630. unsigned long flags;
  631. host = (struct sdhci_host*)param;
  632. spin_lock_irqsave(&host->lock, flags);
  633. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  634. if (host->mrq) {
  635. printk(KERN_ERR "%s: Card removed during transfer!\n",
  636. mmc_hostname(host->mmc));
  637. printk(KERN_ERR "%s: Resetting controller.\n",
  638. mmc_hostname(host->mmc));
  639. sdhci_reset(host, SDHCI_RESET_CMD);
  640. sdhci_reset(host, SDHCI_RESET_DATA);
  641. host->mrq->cmd->error = MMC_ERR_FAILED;
  642. tasklet_schedule(&host->finish_tasklet);
  643. }
  644. }
  645. spin_unlock_irqrestore(&host->lock, flags);
  646. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  647. }
  648. static void sdhci_tasklet_finish(unsigned long param)
  649. {
  650. struct sdhci_host *host;
  651. unsigned long flags;
  652. struct mmc_request *mrq;
  653. host = (struct sdhci_host*)param;
  654. spin_lock_irqsave(&host->lock, flags);
  655. del_timer(&host->timer);
  656. mrq = host->mrq;
  657. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  658. /*
  659. * The controller needs a reset of internal state machines
  660. * upon error conditions.
  661. */
  662. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  663. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  664. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  665. /* Some controllers need this kick or reset won't work here */
  666. if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
  667. unsigned int clock;
  668. /* This is to force an update */
  669. clock = host->clock;
  670. host->clock = 0;
  671. sdhci_set_clock(host, clock);
  672. }
  673. /* Spec says we should do both at the same time, but Ricoh
  674. controllers do not like that. */
  675. sdhci_reset(host, SDHCI_RESET_CMD);
  676. sdhci_reset(host, SDHCI_RESET_DATA);
  677. }
  678. host->mrq = NULL;
  679. host->cmd = NULL;
  680. host->data = NULL;
  681. sdhci_deactivate_led(host);
  682. spin_unlock_irqrestore(&host->lock, flags);
  683. mmc_request_done(host->mmc, mrq);
  684. }
  685. static void sdhci_timeout_timer(unsigned long data)
  686. {
  687. struct sdhci_host *host;
  688. unsigned long flags;
  689. host = (struct sdhci_host*)data;
  690. spin_lock_irqsave(&host->lock, flags);
  691. if (host->mrq) {
  692. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  693. "Please report this to " BUGMAIL ".\n",
  694. mmc_hostname(host->mmc));
  695. sdhci_dumpregs(host);
  696. if (host->data) {
  697. host->data->error = MMC_ERR_TIMEOUT;
  698. sdhci_finish_data(host);
  699. } else {
  700. if (host->cmd)
  701. host->cmd->error = MMC_ERR_TIMEOUT;
  702. else
  703. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  704. tasklet_schedule(&host->finish_tasklet);
  705. }
  706. }
  707. spin_unlock_irqrestore(&host->lock, flags);
  708. }
  709. /*****************************************************************************\
  710. * *
  711. * Interrupt handling *
  712. * *
  713. \*****************************************************************************/
  714. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  715. {
  716. BUG_ON(intmask == 0);
  717. if (!host->cmd) {
  718. printk(KERN_ERR "%s: Got command interrupt even though no "
  719. "command operation was in progress.\n",
  720. mmc_hostname(host->mmc));
  721. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  722. mmc_hostname(host->mmc));
  723. sdhci_dumpregs(host);
  724. return;
  725. }
  726. if (intmask & SDHCI_INT_RESPONSE)
  727. sdhci_finish_command(host);
  728. else {
  729. if (intmask & SDHCI_INT_TIMEOUT)
  730. host->cmd->error = MMC_ERR_TIMEOUT;
  731. else if (intmask & SDHCI_INT_CRC)
  732. host->cmd->error = MMC_ERR_BADCRC;
  733. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  734. host->cmd->error = MMC_ERR_FAILED;
  735. else
  736. host->cmd->error = MMC_ERR_INVALID;
  737. tasklet_schedule(&host->finish_tasklet);
  738. }
  739. }
  740. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  741. {
  742. BUG_ON(intmask == 0);
  743. if (!host->data) {
  744. /*
  745. * A data end interrupt is sent together with the response
  746. * for the stop command.
  747. */
  748. if (intmask & SDHCI_INT_DATA_END)
  749. return;
  750. printk(KERN_ERR "%s: Got data interrupt even though no "
  751. "data operation was in progress.\n",
  752. mmc_hostname(host->mmc));
  753. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  754. mmc_hostname(host->mmc));
  755. sdhci_dumpregs(host);
  756. return;
  757. }
  758. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  759. host->data->error = MMC_ERR_TIMEOUT;
  760. else if (intmask & SDHCI_INT_DATA_CRC)
  761. host->data->error = MMC_ERR_BADCRC;
  762. else if (intmask & SDHCI_INT_DATA_END_BIT)
  763. host->data->error = MMC_ERR_FAILED;
  764. if (host->data->error != MMC_ERR_NONE)
  765. sdhci_finish_data(host);
  766. else {
  767. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  768. sdhci_transfer_pio(host);
  769. if (intmask & SDHCI_INT_DATA_END)
  770. sdhci_finish_data(host);
  771. }
  772. }
  773. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  774. {
  775. irqreturn_t result;
  776. struct sdhci_host* host = dev_id;
  777. u32 intmask;
  778. spin_lock(&host->lock);
  779. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  780. if (!intmask) {
  781. result = IRQ_NONE;
  782. goto out;
  783. }
  784. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  785. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  786. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  787. host->ioaddr + SDHCI_INT_STATUS);
  788. tasklet_schedule(&host->card_tasklet);
  789. }
  790. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  791. if (intmask & SDHCI_INT_CMD_MASK) {
  792. writel(intmask & SDHCI_INT_CMD_MASK,
  793. host->ioaddr + SDHCI_INT_STATUS);
  794. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  795. }
  796. if (intmask & SDHCI_INT_DATA_MASK) {
  797. writel(intmask & SDHCI_INT_DATA_MASK,
  798. host->ioaddr + SDHCI_INT_STATUS);
  799. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  800. }
  801. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  802. if (intmask & SDHCI_INT_BUS_POWER) {
  803. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  804. mmc_hostname(host->mmc));
  805. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  806. }
  807. intmask &= SDHCI_INT_BUS_POWER;
  808. if (intmask) {
  809. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  810. "report this to " BUGMAIL ".\n",
  811. mmc_hostname(host->mmc), intmask);
  812. sdhci_dumpregs(host);
  813. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  814. }
  815. result = IRQ_HANDLED;
  816. out:
  817. spin_unlock(&host->lock);
  818. return result;
  819. }
  820. /*****************************************************************************\
  821. * *
  822. * Suspend/resume *
  823. * *
  824. \*****************************************************************************/
  825. #ifdef CONFIG_PM
  826. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  827. {
  828. struct sdhci_chip *chip;
  829. int i, ret;
  830. chip = pci_get_drvdata(pdev);
  831. if (!chip)
  832. return 0;
  833. DBG("Suspending...\n");
  834. for (i = 0;i < chip->num_slots;i++) {
  835. if (!chip->hosts[i])
  836. continue;
  837. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  838. if (ret) {
  839. for (i--;i >= 0;i--)
  840. mmc_resume_host(chip->hosts[i]->mmc);
  841. return ret;
  842. }
  843. }
  844. pci_save_state(pdev);
  845. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  846. pci_disable_device(pdev);
  847. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  848. return 0;
  849. }
  850. static int sdhci_resume (struct pci_dev *pdev)
  851. {
  852. struct sdhci_chip *chip;
  853. int i, ret;
  854. chip = pci_get_drvdata(pdev);
  855. if (!chip)
  856. return 0;
  857. DBG("Resuming...\n");
  858. pci_set_power_state(pdev, PCI_D0);
  859. pci_restore_state(pdev);
  860. pci_enable_device(pdev);
  861. for (i = 0;i < chip->num_slots;i++) {
  862. if (!chip->hosts[i])
  863. continue;
  864. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  865. pci_set_master(pdev);
  866. sdhci_init(chip->hosts[i]);
  867. ret = mmc_resume_host(chip->hosts[i]->mmc);
  868. if (ret)
  869. return ret;
  870. }
  871. return 0;
  872. }
  873. #else /* CONFIG_PM */
  874. #define sdhci_suspend NULL
  875. #define sdhci_resume NULL
  876. #endif /* CONFIG_PM */
  877. /*****************************************************************************\
  878. * *
  879. * Device probing/removal *
  880. * *
  881. \*****************************************************************************/
  882. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  883. {
  884. int ret;
  885. unsigned int version;
  886. struct sdhci_chip *chip;
  887. struct mmc_host *mmc;
  888. struct sdhci_host *host;
  889. u8 first_bar;
  890. unsigned int caps;
  891. chip = pci_get_drvdata(pdev);
  892. BUG_ON(!chip);
  893. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  894. if (ret)
  895. return ret;
  896. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  897. if (first_bar > 5) {
  898. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  899. return -ENODEV;
  900. }
  901. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  902. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  903. return -ENODEV;
  904. }
  905. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  906. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  907. return -ENODEV;
  908. }
  909. if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  910. printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
  911. return -ENODEV;
  912. }
  913. if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
  914. printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
  915. return -ENODEV;
  916. }
  917. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  918. if (!mmc)
  919. return -ENOMEM;
  920. host = mmc_priv(mmc);
  921. host->mmc = mmc;
  922. host->bar = first_bar + slot;
  923. host->addr = pci_resource_start(pdev, host->bar);
  924. host->irq = pdev->irq;
  925. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  926. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  927. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  928. if (ret)
  929. goto free;
  930. host->ioaddr = ioremap_nocache(host->addr,
  931. pci_resource_len(pdev, host->bar));
  932. if (!host->ioaddr) {
  933. ret = -ENOMEM;
  934. goto release;
  935. }
  936. sdhci_reset(host, SDHCI_RESET_ALL);
  937. version = readw(host->ioaddr + SDHCI_HOST_VERSION);
  938. version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
  939. if (version != 0) {
  940. printk(KERN_ERR "%s: Unknown controller version (%d). "
  941. "Cowardly refusing to continue.\n", host->slot_descr,
  942. version);
  943. ret = -ENODEV;
  944. goto unmap;
  945. }
  946. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  947. if (debug_nodma)
  948. DBG("DMA forced off\n");
  949. else if (debug_forcedma) {
  950. DBG("DMA forced on\n");
  951. host->flags |= SDHCI_USE_DMA;
  952. } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
  953. host->flags |= SDHCI_USE_DMA;
  954. else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
  955. DBG("Controller doesn't have DMA interface\n");
  956. else if (!(caps & SDHCI_CAN_DO_DMA))
  957. DBG("Controller doesn't have DMA capability\n");
  958. else
  959. host->flags |= SDHCI_USE_DMA;
  960. if (host->flags & SDHCI_USE_DMA) {
  961. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  962. printk(KERN_WARNING "%s: No suitable DMA available. "
  963. "Falling back to PIO.\n", host->slot_descr);
  964. host->flags &= ~SDHCI_USE_DMA;
  965. }
  966. }
  967. if (host->flags & SDHCI_USE_DMA)
  968. pci_set_master(pdev);
  969. else /* XXX: Hack to get MMC layer to avoid highmem */
  970. pdev->dma_mask = 0;
  971. host->max_clk =
  972. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  973. if (host->max_clk == 0) {
  974. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  975. "frequency.\n", host->slot_descr);
  976. ret = -ENODEV;
  977. goto unmap;
  978. }
  979. host->max_clk *= 1000000;
  980. host->timeout_clk =
  981. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  982. if (host->timeout_clk == 0) {
  983. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  984. "frequency.\n", host->slot_descr);
  985. ret = -ENODEV;
  986. goto unmap;
  987. }
  988. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  989. host->timeout_clk *= 1000;
  990. host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
  991. if (host->max_block >= 3) {
  992. printk(KERN_ERR "%s: Invalid maximum block size.\n",
  993. host->slot_descr);
  994. ret = -ENODEV;
  995. goto unmap;
  996. }
  997. host->max_block = 512 << host->max_block;
  998. /*
  999. * Set host parameters.
  1000. */
  1001. mmc->ops = &sdhci_ops;
  1002. mmc->f_min = host->max_clk / 256;
  1003. mmc->f_max = host->max_clk;
  1004. mmc->caps = MMC_CAP_4_BIT_DATA;
  1005. mmc->ocr_avail = 0;
  1006. if (caps & SDHCI_CAN_VDD_330)
  1007. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  1008. else if (caps & SDHCI_CAN_VDD_300)
  1009. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  1010. else if (caps & SDHCI_CAN_VDD_180)
  1011. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  1012. if (mmc->ocr_avail == 0) {
  1013. printk(KERN_ERR "%s: Hardware doesn't report any "
  1014. "support voltages.\n", host->slot_descr);
  1015. ret = -ENODEV;
  1016. goto unmap;
  1017. }
  1018. spin_lock_init(&host->lock);
  1019. /*
  1020. * Maximum number of segments. Hardware cannot do scatter lists.
  1021. */
  1022. if (host->flags & SDHCI_USE_DMA)
  1023. mmc->max_hw_segs = 1;
  1024. else
  1025. mmc->max_hw_segs = 16;
  1026. mmc->max_phys_segs = 16;
  1027. /*
  1028. * Maximum number of sectors in one transfer. Limited by DMA boundary
  1029. * size (512KiB), which means (512 KiB/512=) 1024 entries.
  1030. */
  1031. mmc->max_sectors = 1024;
  1032. /*
  1033. * Maximum segment size. Could be one segment with the maximum number
  1034. * of sectors.
  1035. */
  1036. mmc->max_seg_size = mmc->max_sectors * 512;
  1037. /*
  1038. * Init tasklets.
  1039. */
  1040. tasklet_init(&host->card_tasklet,
  1041. sdhci_tasklet_card, (unsigned long)host);
  1042. tasklet_init(&host->finish_tasklet,
  1043. sdhci_tasklet_finish, (unsigned long)host);
  1044. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  1045. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  1046. host->slot_descr, host);
  1047. if (ret)
  1048. goto untasklet;
  1049. sdhci_init(host);
  1050. #ifdef CONFIG_MMC_DEBUG
  1051. sdhci_dumpregs(host);
  1052. #endif
  1053. host->chip = chip;
  1054. chip->hosts[slot] = host;
  1055. mmc_add_host(mmc);
  1056. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  1057. host->addr, host->irq,
  1058. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  1059. return 0;
  1060. untasklet:
  1061. tasklet_kill(&host->card_tasklet);
  1062. tasklet_kill(&host->finish_tasklet);
  1063. unmap:
  1064. iounmap(host->ioaddr);
  1065. release:
  1066. pci_release_region(pdev, host->bar);
  1067. free:
  1068. mmc_free_host(mmc);
  1069. return ret;
  1070. }
  1071. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  1072. {
  1073. struct sdhci_chip *chip;
  1074. struct mmc_host *mmc;
  1075. struct sdhci_host *host;
  1076. chip = pci_get_drvdata(pdev);
  1077. host = chip->hosts[slot];
  1078. mmc = host->mmc;
  1079. chip->hosts[slot] = NULL;
  1080. mmc_remove_host(mmc);
  1081. sdhci_reset(host, SDHCI_RESET_ALL);
  1082. free_irq(host->irq, host);
  1083. del_timer_sync(&host->timer);
  1084. tasklet_kill(&host->card_tasklet);
  1085. tasklet_kill(&host->finish_tasklet);
  1086. iounmap(host->ioaddr);
  1087. pci_release_region(pdev, host->bar);
  1088. mmc_free_host(mmc);
  1089. }
  1090. static int __devinit sdhci_probe(struct pci_dev *pdev,
  1091. const struct pci_device_id *ent)
  1092. {
  1093. int ret, i;
  1094. u8 slots, rev;
  1095. struct sdhci_chip *chip;
  1096. BUG_ON(pdev == NULL);
  1097. BUG_ON(ent == NULL);
  1098. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1099. printk(KERN_INFO DRIVER_NAME
  1100. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1101. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1102. (int)rev);
  1103. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1104. if (ret)
  1105. return ret;
  1106. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1107. DBG("found %d slot(s)\n", slots);
  1108. if (slots == 0)
  1109. return -ENODEV;
  1110. ret = pci_enable_device(pdev);
  1111. if (ret)
  1112. return ret;
  1113. chip = kzalloc(sizeof(struct sdhci_chip) +
  1114. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1115. if (!chip) {
  1116. ret = -ENOMEM;
  1117. goto err;
  1118. }
  1119. chip->pdev = pdev;
  1120. chip->quirks = ent->driver_data;
  1121. if (debug_quirks)
  1122. chip->quirks = debug_quirks;
  1123. chip->num_slots = slots;
  1124. pci_set_drvdata(pdev, chip);
  1125. for (i = 0;i < slots;i++) {
  1126. ret = sdhci_probe_slot(pdev, i);
  1127. if (ret) {
  1128. for (i--;i >= 0;i--)
  1129. sdhci_remove_slot(pdev, i);
  1130. goto free;
  1131. }
  1132. }
  1133. return 0;
  1134. free:
  1135. pci_set_drvdata(pdev, NULL);
  1136. kfree(chip);
  1137. err:
  1138. pci_disable_device(pdev);
  1139. return ret;
  1140. }
  1141. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1142. {
  1143. int i;
  1144. struct sdhci_chip *chip;
  1145. chip = pci_get_drvdata(pdev);
  1146. if (chip) {
  1147. for (i = 0;i < chip->num_slots;i++)
  1148. sdhci_remove_slot(pdev, i);
  1149. pci_set_drvdata(pdev, NULL);
  1150. kfree(chip);
  1151. }
  1152. pci_disable_device(pdev);
  1153. }
  1154. static struct pci_driver sdhci_driver = {
  1155. .name = DRIVER_NAME,
  1156. .id_table = pci_ids,
  1157. .probe = sdhci_probe,
  1158. .remove = __devexit_p(sdhci_remove),
  1159. .suspend = sdhci_suspend,
  1160. .resume = sdhci_resume,
  1161. };
  1162. /*****************************************************************************\
  1163. * *
  1164. * Driver init/exit *
  1165. * *
  1166. \*****************************************************************************/
  1167. static int __init sdhci_drv_init(void)
  1168. {
  1169. printk(KERN_INFO DRIVER_NAME
  1170. ": Secure Digital Host Controller Interface driver, "
  1171. DRIVER_VERSION "\n");
  1172. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1173. return pci_register_driver(&sdhci_driver);
  1174. }
  1175. static void __exit sdhci_drv_exit(void)
  1176. {
  1177. DBG("Exiting\n");
  1178. pci_unregister_driver(&sdhci_driver);
  1179. }
  1180. module_init(sdhci_drv_init);
  1181. module_exit(sdhci_drv_exit);
  1182. module_param(debug_nodma, uint, 0444);
  1183. module_param(debug_forcedma, uint, 0444);
  1184. module_param(debug_quirks, uint, 0444);
  1185. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1186. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1187. MODULE_VERSION(DRIVER_VERSION);
  1188. MODULE_LICENSE("GPL");
  1189. MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
  1190. MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
  1191. MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");