cpuidle44xx.c 6.3 KB

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  1. /*
  2. * OMAP4 CPU idle Routines
  3. *
  4. * Copyright (C) 2011 Texas Instruments, Inc.
  5. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  6. * Rajendra Nayak <rnayak@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/sched.h>
  13. #include <linux/cpuidle.h>
  14. #include <linux/cpu_pm.h>
  15. #include <linux/export.h>
  16. #include <asm/proc-fns.h>
  17. #include "common.h"
  18. #include "pm.h"
  19. #include "prm.h"
  20. #ifdef CONFIG_CPU_IDLE
  21. /* Machine specific information to be recorded in the C-state driver_data */
  22. struct omap4_idle_statedata {
  23. u32 cpu_state;
  24. u32 mpu_logic_state;
  25. u32 mpu_state;
  26. u8 valid;
  27. };
  28. static struct cpuidle_params cpuidle_params_table[] = {
  29. /* C1 - CPU0 ON + CPU1 ON + MPU ON */
  30. {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
  31. /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
  32. {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
  33. /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
  34. {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
  35. };
  36. #define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
  37. struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
  38. static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
  39. /**
  40. * omap4_enter_idle - Programs OMAP4 to enter the specified state
  41. * @dev: cpuidle device
  42. * @drv: cpuidle driver
  43. * @index: the index of state to be entered
  44. *
  45. * Called from the CPUidle framework to program the device to the
  46. * specified low power state selected by the governor.
  47. * Returns the amount of time spent in the low power state.
  48. */
  49. static int omap4_enter_idle(struct cpuidle_device *dev,
  50. struct cpuidle_driver *drv,
  51. int index)
  52. {
  53. struct omap4_idle_statedata *cx =
  54. cpuidle_get_statedata(&dev->states_usage[index]);
  55. struct timespec ts_preidle, ts_postidle, ts_idle;
  56. u32 cpu1_state;
  57. int idle_time;
  58. int new_state_idx;
  59. /* Used to keep track of the total time in idle */
  60. getnstimeofday(&ts_preidle);
  61. local_irq_disable();
  62. local_fiq_disable();
  63. /*
  64. * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
  65. * This is necessary to honour hardware recommondation
  66. * of triggeing all the possible low power modes once CPU1 is
  67. * out of coherency and in OFF mode.
  68. * Update dev->last_state so that governor stats reflects right
  69. * data.
  70. */
  71. cpu1_state = pwrdm_read_pwrst(cpu1_pd);
  72. if (cpu1_state != PWRDM_POWER_OFF) {
  73. new_state_idx = drv->safe_state_index;
  74. cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
  75. }
  76. /*
  77. * Call idle CPU PM enter notifier chain so that
  78. * VFP and per CPU interrupt context is saved.
  79. */
  80. if (cx->cpu_state == PWRDM_POWER_OFF)
  81. cpu_pm_enter();
  82. pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
  83. omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
  84. /*
  85. * Call idle CPU cluster PM enter notifier chain
  86. * to save GIC and wakeupgen context.
  87. */
  88. if ((cx->mpu_state == PWRDM_POWER_RET) &&
  89. (cx->mpu_logic_state == PWRDM_POWER_OFF))
  90. cpu_cluster_pm_enter();
  91. omap4_enter_lowpower(dev->cpu, cx->cpu_state);
  92. /*
  93. * Call idle CPU PM exit notifier chain to restore
  94. * VFP and per CPU IRQ context. Only CPU0 state is
  95. * considered since CPU1 is managed by CPU hotplug.
  96. */
  97. if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
  98. cpu_pm_exit();
  99. /*
  100. * Call idle CPU cluster PM exit notifier chain
  101. * to restore GIC and wakeupgen context.
  102. */
  103. if (omap4_mpuss_read_prev_context_state())
  104. cpu_cluster_pm_exit();
  105. getnstimeofday(&ts_postidle);
  106. ts_idle = timespec_sub(ts_postidle, ts_preidle);
  107. local_irq_enable();
  108. local_fiq_enable();
  109. idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
  110. USEC_PER_SEC;
  111. /* Update cpuidle counters */
  112. dev->last_residency = idle_time;
  113. return index;
  114. }
  115. DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
  116. struct cpuidle_driver omap4_idle_driver = {
  117. .name = "omap4_idle",
  118. .owner = THIS_MODULE,
  119. };
  120. static inline void _fill_cstate(struct cpuidle_driver *drv,
  121. int idx, const char *descr)
  122. {
  123. struct cpuidle_state *state = &drv->states[idx];
  124. state->exit_latency = cpuidle_params_table[idx].exit_latency;
  125. state->target_residency = cpuidle_params_table[idx].target_residency;
  126. state->flags = CPUIDLE_FLAG_TIME_VALID;
  127. state->enter = omap4_enter_idle;
  128. sprintf(state->name, "C%d", idx + 1);
  129. strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
  130. }
  131. static inline struct omap4_idle_statedata *_fill_cstate_usage(
  132. struct cpuidle_device *dev,
  133. int idx)
  134. {
  135. struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
  136. struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
  137. cx->valid = cpuidle_params_table[idx].valid;
  138. cpuidle_set_statedata(state_usage, cx);
  139. return cx;
  140. }
  141. /**
  142. * omap4_idle_init - Init routine for OMAP4 idle
  143. *
  144. * Registers the OMAP4 specific cpuidle driver to the cpuidle
  145. * framework with the valid set of states.
  146. */
  147. int __init omap4_idle_init(void)
  148. {
  149. struct omap4_idle_statedata *cx;
  150. struct cpuidle_device *dev;
  151. struct cpuidle_driver *drv = &omap4_idle_driver;
  152. unsigned int cpu_id = 0;
  153. mpu_pd = pwrdm_lookup("mpu_pwrdm");
  154. cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
  155. cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
  156. if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
  157. return -ENODEV;
  158. drv->safe_state_index = -1;
  159. dev = &per_cpu(omap4_idle_dev, cpu_id);
  160. dev->cpu = cpu_id;
  161. /* C1 - CPU0 ON + CPU1 ON + MPU ON */
  162. _fill_cstate(drv, 0, "MPUSS ON");
  163. drv->safe_state_index = 0;
  164. cx = _fill_cstate_usage(dev, 0);
  165. cx->valid = 1; /* C1 is always valid */
  166. cx->cpu_state = PWRDM_POWER_ON;
  167. cx->mpu_state = PWRDM_POWER_ON;
  168. cx->mpu_logic_state = PWRDM_POWER_RET;
  169. /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
  170. _fill_cstate(drv, 1, "MPUSS CSWR");
  171. cx = _fill_cstate_usage(dev, 1);
  172. cx->cpu_state = PWRDM_POWER_OFF;
  173. cx->mpu_state = PWRDM_POWER_RET;
  174. cx->mpu_logic_state = PWRDM_POWER_RET;
  175. /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
  176. _fill_cstate(drv, 2, "MPUSS OSWR");
  177. cx = _fill_cstate_usage(dev, 2);
  178. cx->cpu_state = PWRDM_POWER_OFF;
  179. cx->mpu_state = PWRDM_POWER_RET;
  180. cx->mpu_logic_state = PWRDM_POWER_OFF;
  181. drv->state_count = OMAP4_NUM_STATES;
  182. cpuidle_register_driver(&omap4_idle_driver);
  183. dev->state_count = OMAP4_NUM_STATES;
  184. if (cpuidle_register_device(dev)) {
  185. pr_err("%s: CPUidle register device failed\n", __func__);
  186. return -EIO;
  187. }
  188. return 0;
  189. }
  190. #else
  191. int __init omap4_idle_init(void)
  192. {
  193. return 0;
  194. }
  195. #endif /* CONFIG_CPU_IDLE */