at91sam9x5.dtsi 14 KB

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  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. i2c0 = &i2c0;
  28. i2c1 = &i2c1;
  29. i2c2 = &i2c2;
  30. ssc0 = &ssc0;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x20000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe800 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe800 0x200>;
  60. };
  61. pmc: pmc@fffffc00 {
  62. compatible = "atmel,at91rm9200-pmc";
  63. reg = <0xfffffc00 0x100>;
  64. };
  65. rstc@fffffe00 {
  66. compatible = "atmel,at91sam9g45-rstc";
  67. reg = <0xfffffe00 0x10>;
  68. };
  69. shdwc@fffffe10 {
  70. compatible = "atmel,at91sam9x5-shdwc";
  71. reg = <0xfffffe10 0x10>;
  72. };
  73. pit: timer@fffffe30 {
  74. compatible = "atmel,at91sam9260-pit";
  75. reg = <0xfffffe30 0xf>;
  76. interrupts = <1 4 7>;
  77. };
  78. tcb0: timer@f8008000 {
  79. compatible = "atmel,at91sam9x5-tcb";
  80. reg = <0xf8008000 0x100>;
  81. interrupts = <17 4 0>;
  82. };
  83. tcb1: timer@f800c000 {
  84. compatible = "atmel,at91sam9x5-tcb";
  85. reg = <0xf800c000 0x100>;
  86. interrupts = <17 4 0>;
  87. };
  88. dma0: dma-controller@ffffec00 {
  89. compatible = "atmel,at91sam9g45-dma";
  90. reg = <0xffffec00 0x200>;
  91. interrupts = <20 4 0>;
  92. #dma-cells = <2>;
  93. };
  94. dma1: dma-controller@ffffee00 {
  95. compatible = "atmel,at91sam9g45-dma";
  96. reg = <0xffffee00 0x200>;
  97. interrupts = <21 4 0>;
  98. #dma-cells = <2>;
  99. };
  100. pinctrl@fffff400 {
  101. #address-cells = <1>;
  102. #size-cells = <1>;
  103. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  104. ranges = <0xfffff400 0xfffff400 0x800>;
  105. /* shared pinctrl settings */
  106. dbgu {
  107. pinctrl_dbgu: dbgu-0 {
  108. atmel,pins =
  109. <0 9 0x1 0x0 /* PA9 periph A */
  110. 0 10 0x1 0x1>; /* PA10 periph A with pullup */
  111. };
  112. };
  113. usart0 {
  114. pinctrl_usart0: usart0-0 {
  115. atmel,pins =
  116. <0 0 0x1 0x1 /* PA0 periph A with pullup */
  117. 0 1 0x1 0x0>; /* PA1 periph A */
  118. };
  119. pinctrl_usart0_rts: usart0_rts-0 {
  120. atmel,pins =
  121. <0 2 0x1 0x0>; /* PA2 periph A */
  122. };
  123. pinctrl_usart0_cts: usart0_cts-0 {
  124. atmel,pins =
  125. <0 3 0x1 0x0>; /* PA3 periph A */
  126. };
  127. pinctrl_usart0_sck: usart0_sck-0 {
  128. atmel,pins =
  129. <0 4 0x1 0x0>; /* PA4 periph A */
  130. };
  131. };
  132. usart1 {
  133. pinctrl_usart1: usart1-0 {
  134. atmel,pins =
  135. <0 5 0x1 0x1 /* PA5 periph A with pullup */
  136. 0 6 0x1 0x0>; /* PA6 periph A */
  137. };
  138. pinctrl_usart1_rts: usart1_rts-0 {
  139. atmel,pins =
  140. <2 27 0x3 0x0>; /* PC27 periph C */
  141. };
  142. pinctrl_usart1_cts: usart1_cts-0 {
  143. atmel,pins =
  144. <2 28 0x3 0x0>; /* PC28 periph C */
  145. };
  146. pinctrl_usart1_sck: usart1_sck-0 {
  147. atmel,pins =
  148. <2 28 0x3 0x0>; /* PC29 periph C */
  149. };
  150. };
  151. usart2 {
  152. pinctrl_usart2: usart2-0 {
  153. atmel,pins =
  154. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  155. 0 8 0x1 0x0>; /* PA8 periph A */
  156. };
  157. pinctrl_uart2_rts: uart2_rts-0 {
  158. atmel,pins =
  159. <1 0 0x2 0x0>; /* PB0 periph B */
  160. };
  161. pinctrl_uart2_cts: uart2_cts-0 {
  162. atmel,pins =
  163. <1 1 0x2 0x0>; /* PB1 periph B */
  164. };
  165. pinctrl_usart2_sck: usart2_sck-0 {
  166. atmel,pins =
  167. <1 2 0x2 0x0>; /* PB2 periph B */
  168. };
  169. };
  170. usart3 {
  171. pinctrl_usart3: usart3-0 {
  172. atmel,pins =
  173. <2 22 0x2 0x1 /* PC22 periph B with pullup */
  174. 2 23 0x2 0x0>; /* PC23 periph B */
  175. };
  176. pinctrl_usart3_rts: usart3_rts-0 {
  177. atmel,pins =
  178. <2 24 0x2 0x0>; /* PC24 periph B */
  179. };
  180. pinctrl_usart3_cts: usart3_cts-0 {
  181. atmel,pins =
  182. <2 25 0x2 0x0>; /* PC25 periph B */
  183. };
  184. pinctrl_usart3_sck: usart3_sck-0 {
  185. atmel,pins =
  186. <2 26 0x2 0x0>; /* PC26 periph B */
  187. };
  188. };
  189. uart0 {
  190. pinctrl_uart0: uart0-0 {
  191. atmel,pins =
  192. <2 8 0x3 0x0 /* PC8 periph C */
  193. 2 9 0x3 0x1>; /* PC9 periph C with pullup */
  194. };
  195. };
  196. uart1 {
  197. pinctrl_uart1: uart1-0 {
  198. atmel,pins =
  199. <2 16 0x3 0x0 /* PC16 periph C */
  200. 2 17 0x3 0x1>; /* PC17 periph C with pullup */
  201. };
  202. };
  203. nand {
  204. pinctrl_nand: nand-0 {
  205. atmel,pins =
  206. <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
  207. 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  208. };
  209. };
  210. macb0 {
  211. pinctrl_macb0_rmii: macb0_rmii-0 {
  212. atmel,pins =
  213. <1 0 0x1 0x0 /* PB0 periph A */
  214. 1 1 0x1 0x0 /* PB1 periph A */
  215. 1 2 0x1 0x0 /* PB2 periph A */
  216. 1 3 0x1 0x0 /* PB3 periph A */
  217. 1 4 0x1 0x0 /* PB4 periph A */
  218. 1 5 0x1 0x0 /* PB5 periph A */
  219. 1 6 0x1 0x0 /* PB6 periph A */
  220. 1 7 0x1 0x0 /* PB7 periph A */
  221. 1 9 0x1 0x0 /* PB9 periph A */
  222. 1 10 0x1 0x0>; /* PB10 periph A */
  223. };
  224. pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
  225. atmel,pins =
  226. <1 8 0x1 0x0 /* PB8 periph A */
  227. 1 11 0x1 0x0 /* PB11 periph A */
  228. 1 12 0x1 0x0 /* PB12 periph A */
  229. 1 13 0x1 0x0 /* PB13 periph A */
  230. 1 14 0x1 0x0 /* PB14 periph A */
  231. 1 15 0x1 0x0 /* PB15 periph A */
  232. 1 16 0x1 0x0 /* PB16 periph A */
  233. 1 17 0x1 0x0>; /* PB17 periph A */
  234. };
  235. };
  236. mmc0 {
  237. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  238. atmel,pins =
  239. <0 17 0x1 0x0 /* PA17 periph A */
  240. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  241. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  242. };
  243. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  244. atmel,pins =
  245. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  246. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  247. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  248. };
  249. };
  250. mmc1 {
  251. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  252. atmel,pins =
  253. <0 13 0x2 0x0 /* PA13 periph B */
  254. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  255. 0 11 0x2 0x1>; /* PA11 periph B with pullup */
  256. };
  257. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  258. atmel,pins =
  259. <0 2 0x2 0x1 /* PA2 periph B with pullup */
  260. 0 3 0x2 0x1 /* PA3 periph B with pullup */
  261. 0 4 0x2 0x1>; /* PA4 periph B with pullup */
  262. };
  263. };
  264. ssc0 {
  265. pinctrl_ssc0_tx: ssc0_tx-0 {
  266. atmel,pins =
  267. <0 24 0x2 0x0 /* PA24 periph B */
  268. 0 25 0x2 0x0 /* PA25 periph B */
  269. 0 26 0x2 0x0>; /* PA26 periph B */
  270. };
  271. pinctrl_ssc0_rx: ssc0_rx-0 {
  272. atmel,pins =
  273. <0 27 0x2 0x0 /* PA27 periph B */
  274. 0 28 0x2 0x0 /* PA28 periph B */
  275. 0 29 0x2 0x0>; /* PA29 periph B */
  276. };
  277. };
  278. pioA: gpio@fffff400 {
  279. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  280. reg = <0xfffff400 0x200>;
  281. interrupts = <2 4 1>;
  282. #gpio-cells = <2>;
  283. gpio-controller;
  284. interrupt-controller;
  285. #interrupt-cells = <2>;
  286. };
  287. pioB: gpio@fffff600 {
  288. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  289. reg = <0xfffff600 0x200>;
  290. interrupts = <2 4 1>;
  291. #gpio-cells = <2>;
  292. gpio-controller;
  293. #gpio-lines = <19>;
  294. interrupt-controller;
  295. #interrupt-cells = <2>;
  296. };
  297. pioC: gpio@fffff800 {
  298. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  299. reg = <0xfffff800 0x200>;
  300. interrupts = <3 4 1>;
  301. #gpio-cells = <2>;
  302. gpio-controller;
  303. interrupt-controller;
  304. #interrupt-cells = <2>;
  305. };
  306. pioD: gpio@fffffa00 {
  307. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  308. reg = <0xfffffa00 0x200>;
  309. interrupts = <3 4 1>;
  310. #gpio-cells = <2>;
  311. gpio-controller;
  312. #gpio-lines = <22>;
  313. interrupt-controller;
  314. #interrupt-cells = <2>;
  315. };
  316. };
  317. ssc0: ssc@f0010000 {
  318. compatible = "atmel,at91sam9g45-ssc";
  319. reg = <0xf0010000 0x4000>;
  320. interrupts = <28 4 5>;
  321. pinctrl-names = "default";
  322. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  323. status = "disabled";
  324. };
  325. mmc0: mmc@f0008000 {
  326. compatible = "atmel,hsmci";
  327. reg = <0xf0008000 0x600>;
  328. interrupts = <12 4 0>;
  329. #address-cells = <1>;
  330. #size-cells = <0>;
  331. status = "disabled";
  332. };
  333. mmc1: mmc@f000c000 {
  334. compatible = "atmel,hsmci";
  335. reg = <0xf000c000 0x600>;
  336. interrupts = <26 4 0>;
  337. #address-cells = <1>;
  338. #size-cells = <0>;
  339. status = "disabled";
  340. };
  341. dbgu: serial@fffff200 {
  342. compatible = "atmel,at91sam9260-usart";
  343. reg = <0xfffff200 0x200>;
  344. interrupts = <1 4 7>;
  345. pinctrl-names = "default";
  346. pinctrl-0 = <&pinctrl_dbgu>;
  347. status = "disabled";
  348. };
  349. usart0: serial@f801c000 {
  350. compatible = "atmel,at91sam9260-usart";
  351. reg = <0xf801c000 0x200>;
  352. interrupts = <5 4 5>;
  353. pinctrl-names = "default";
  354. pinctrl-0 = <&pinctrl_usart0>;
  355. status = "disabled";
  356. };
  357. usart1: serial@f8020000 {
  358. compatible = "atmel,at91sam9260-usart";
  359. reg = <0xf8020000 0x200>;
  360. interrupts = <6 4 5>;
  361. pinctrl-names = "default";
  362. pinctrl-0 = <&pinctrl_usart1>;
  363. status = "disabled";
  364. };
  365. usart2: serial@f8024000 {
  366. compatible = "atmel,at91sam9260-usart";
  367. reg = <0xf8024000 0x200>;
  368. interrupts = <7 4 5>;
  369. pinctrl-names = "default";
  370. pinctrl-0 = <&pinctrl_usart2>;
  371. status = "disabled";
  372. };
  373. macb0: ethernet@f802c000 {
  374. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  375. reg = <0xf802c000 0x100>;
  376. interrupts = <24 4 3>;
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&pinctrl_macb0_rmii>;
  379. status = "disabled";
  380. };
  381. macb1: ethernet@f8030000 {
  382. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  383. reg = <0xf8030000 0x100>;
  384. interrupts = <27 4 3>;
  385. status = "disabled";
  386. };
  387. i2c0: i2c@f8010000 {
  388. compatible = "atmel,at91sam9x5-i2c";
  389. reg = <0xf8010000 0x100>;
  390. interrupts = <9 4 6>;
  391. #address-cells = <1>;
  392. #size-cells = <0>;
  393. status = "disabled";
  394. };
  395. i2c1: i2c@f8014000 {
  396. compatible = "atmel,at91sam9x5-i2c";
  397. reg = <0xf8014000 0x100>;
  398. interrupts = <10 4 6>;
  399. #address-cells = <1>;
  400. #size-cells = <0>;
  401. status = "disabled";
  402. };
  403. i2c2: i2c@f8018000 {
  404. compatible = "atmel,at91sam9x5-i2c";
  405. reg = <0xf8018000 0x100>;
  406. interrupts = <11 4 6>;
  407. #address-cells = <1>;
  408. #size-cells = <0>;
  409. status = "disabled";
  410. };
  411. adc0: adc@f804c000 {
  412. compatible = "atmel,at91sam9260-adc";
  413. reg = <0xf804c000 0x100>;
  414. interrupts = <19 4 0>;
  415. atmel,adc-use-external;
  416. atmel,adc-channels-used = <0xffff>;
  417. atmel,adc-vref = <3300>;
  418. atmel,adc-num-channels = <12>;
  419. atmel,adc-startup-time = <40>;
  420. atmel,adc-channel-base = <0x50>;
  421. atmel,adc-drdy-mask = <0x1000000>;
  422. atmel,adc-status-register = <0x30>;
  423. atmel,adc-trigger-register = <0xc0>;
  424. trigger@0 {
  425. trigger-name = "external-rising";
  426. trigger-value = <0x1>;
  427. trigger-external;
  428. };
  429. trigger@1 {
  430. trigger-name = "external-falling";
  431. trigger-value = <0x2>;
  432. trigger-external;
  433. };
  434. trigger@2 {
  435. trigger-name = "external-any";
  436. trigger-value = <0x3>;
  437. trigger-external;
  438. };
  439. trigger@3 {
  440. trigger-name = "continuous";
  441. trigger-value = <0x6>;
  442. };
  443. };
  444. };
  445. nand0: nand@40000000 {
  446. compatible = "atmel,at91rm9200-nand";
  447. #address-cells = <1>;
  448. #size-cells = <1>;
  449. reg = <0x40000000 0x10000000
  450. 0xffffe000 0x600 /* PMECC Registers */
  451. 0xffffe600 0x200 /* PMECC Error Location Registers */
  452. 0x00108000 0x18000 /* PMECC looup table in ROM code */
  453. >;
  454. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  455. atmel,nand-addr-offset = <21>;
  456. atmel,nand-cmd-offset = <22>;
  457. pinctrl-names = "default";
  458. pinctrl-0 = <&pinctrl_nand>;
  459. gpios = <&pioD 5 0
  460. &pioD 4 0
  461. 0
  462. >;
  463. status = "disabled";
  464. };
  465. usb0: ohci@00600000 {
  466. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  467. reg = <0x00600000 0x100000>;
  468. interrupts = <22 4 2>;
  469. status = "disabled";
  470. };
  471. usb1: ehci@00700000 {
  472. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  473. reg = <0x00700000 0x100000>;
  474. interrupts = <22 4 2>;
  475. status = "disabled";
  476. };
  477. };
  478. i2c@0 {
  479. compatible = "i2c-gpio";
  480. gpios = <&pioA 30 0 /* sda */
  481. &pioA 31 0 /* scl */
  482. >;
  483. i2c-gpio,sda-open-drain;
  484. i2c-gpio,scl-open-drain;
  485. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  486. #address-cells = <1>;
  487. #size-cells = <0>;
  488. status = "disabled";
  489. };
  490. i2c@1 {
  491. compatible = "i2c-gpio";
  492. gpios = <&pioC 0 0 /* sda */
  493. &pioC 1 0 /* scl */
  494. >;
  495. i2c-gpio,sda-open-drain;
  496. i2c-gpio,scl-open-drain;
  497. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  498. #address-cells = <1>;
  499. #size-cells = <0>;
  500. status = "disabled";
  501. };
  502. i2c@2 {
  503. compatible = "i2c-gpio";
  504. gpios = <&pioB 4 0 /* sda */
  505. &pioB 5 0 /* scl */
  506. >;
  507. i2c-gpio,sda-open-drain;
  508. i2c-gpio,scl-open-drain;
  509. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  510. #address-cells = <1>;
  511. #size-cells = <0>;
  512. status = "disabled";
  513. };
  514. };