at91sam9n12.dtsi 9.5 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. /include/ "skeleton.dtsi"
  10. / {
  11. model = "Atmel AT91SAM9N12 SoC";
  12. compatible = "atmel,at91sam9n12";
  13. interrupt-parent = <&aic>;
  14. aliases {
  15. serial0 = &dbgu;
  16. serial1 = &usart0;
  17. serial2 = &usart1;
  18. serial3 = &usart2;
  19. serial4 = &usart3;
  20. gpio0 = &pioA;
  21. gpio1 = &pioB;
  22. gpio2 = &pioC;
  23. gpio3 = &pioD;
  24. tcb0 = &tcb0;
  25. tcb1 = &tcb1;
  26. i2c0 = &i2c0;
  27. i2c1 = &i2c1;
  28. ssc0 = &ssc0;
  29. };
  30. cpus {
  31. cpu@0 {
  32. compatible = "arm,arm926ejs";
  33. };
  34. };
  35. memory {
  36. reg = <0x20000000 0x10000000>;
  37. };
  38. ahb {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. ranges;
  43. apb {
  44. compatible = "simple-bus";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. ranges;
  48. aic: interrupt-controller@fffff000 {
  49. #interrupt-cells = <3>;
  50. compatible = "atmel,at91rm9200-aic";
  51. interrupt-controller;
  52. reg = <0xfffff000 0x200>;
  53. };
  54. ramc0: ramc@ffffe800 {
  55. compatible = "atmel,at91sam9g45-ddramc";
  56. reg = <0xffffe800 0x200>;
  57. };
  58. pmc: pmc@fffffc00 {
  59. compatible = "atmel,at91rm9200-pmc";
  60. reg = <0xfffffc00 0x100>;
  61. };
  62. rstc@fffffe00 {
  63. compatible = "atmel,at91sam9g45-rstc";
  64. reg = <0xfffffe00 0x10>;
  65. };
  66. pit: timer@fffffe30 {
  67. compatible = "atmel,at91sam9260-pit";
  68. reg = <0xfffffe30 0xf>;
  69. interrupts = <1 4 7>;
  70. };
  71. shdwc@fffffe10 {
  72. compatible = "atmel,at91sam9x5-shdwc";
  73. reg = <0xfffffe10 0x10>;
  74. };
  75. mmc0: mmc@f0008000 {
  76. compatible = "atmel,hsmci";
  77. reg = <0xf0008000 0x600>;
  78. interrupts = <12 4 0>;
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. status = "disabled";
  82. };
  83. tcb0: timer@f8008000 {
  84. compatible = "atmel,at91sam9x5-tcb";
  85. reg = <0xf8008000 0x100>;
  86. interrupts = <17 4 0>;
  87. };
  88. tcb1: timer@f800c000 {
  89. compatible = "atmel,at91sam9x5-tcb";
  90. reg = <0xf800c000 0x100>;
  91. interrupts = <17 4 0>;
  92. };
  93. dma: dma-controller@ffffec00 {
  94. compatible = "atmel,at91sam9g45-dma";
  95. reg = <0xffffec00 0x200>;
  96. interrupts = <20 4 0>;
  97. #dma-cells = <2>;
  98. };
  99. pinctrl@fffff400 {
  100. #address-cells = <1>;
  101. #size-cells = <1>;
  102. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  103. ranges = <0xfffff400 0xfffff400 0x800>;
  104. atmel,mux-mask = <
  105. /* A B C */
  106. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  107. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  108. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  109. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  110. >;
  111. /* shared pinctrl settings */
  112. dbgu {
  113. pinctrl_dbgu: dbgu-0 {
  114. atmel,pins =
  115. <0 9 0x1 0x0 /* PA9 periph A */
  116. 0 10 0x1 0x1>; /* PA10 periph with pullup */
  117. };
  118. };
  119. usart0 {
  120. pinctrl_usart0: usart0-0 {
  121. atmel,pins =
  122. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  123. 0 0 0x1 0x0>; /* PA0 periph A */
  124. };
  125. pinctrl_usart0_rts: usart0_rts-0 {
  126. atmel,pins =
  127. <0 2 0x1 0x0>; /* PA2 periph A */
  128. };
  129. pinctrl_usart0_cts: usart0_cts-0 {
  130. atmel,pins =
  131. <0 3 0x1 0x0>; /* PA3 periph A */
  132. };
  133. };
  134. usart1 {
  135. pinctrl_usart1: usart1-0 {
  136. atmel,pins =
  137. <0 6 0x1 0x1 /* PA6 periph A with pullup */
  138. 0 5 0x1 0x0>; /* PA5 periph A */
  139. };
  140. };
  141. usart2 {
  142. pinctrl_usart2: usart2-0 {
  143. atmel,pins =
  144. <0 8 0x1 0x1 /* PA8 periph A with pullup */
  145. 0 7 0x1 0x0>; /* PA7 periph A */
  146. };
  147. pinctrl_usart2_rts: usart2_rts-0 {
  148. atmel,pins =
  149. <1 0 0x2 0x0>; /* PB0 periph B */
  150. };
  151. pinctrl_usart2_cts: usart2_cts-0 {
  152. atmel,pins =
  153. <1 1 0x2 0x0>; /* PB1 periph B */
  154. };
  155. };
  156. usart3 {
  157. pinctrl_usart3: usart3-0 {
  158. atmel,pins =
  159. <2 23 0x2 0x1 /* PC23 periph B with pullup */
  160. 2 22 0x2 0x0>; /* PC22 periph B */
  161. };
  162. pinctrl_usart3_rts: usart3_rts-0 {
  163. atmel,pins =
  164. <2 24 0x2 0x0>; /* PC24 periph B */
  165. };
  166. pinctrl_usart3_cts: usart3_cts-0 {
  167. atmel,pins =
  168. <2 25 0x2 0x0>; /* PC25 periph B */
  169. };
  170. };
  171. uart0 {
  172. pinctrl_uart0: uart0-0 {
  173. atmel,pins =
  174. <2 9 0x3 0x1 /* PC9 periph C with pullup */
  175. 2 8 0x3 0x0>; /* PC8 periph C */
  176. };
  177. };
  178. uart1 {
  179. pinctrl_uart1: uart1-0 {
  180. atmel,pins =
  181. <2 16 0x3 0x1 /* PC17 periph C with pullup */
  182. 2 17 0x3 0x0>; /* PC16 periph C */
  183. };
  184. };
  185. nand {
  186. pinctrl_nand: nand-0 {
  187. atmel,pins =
  188. <3 5 0x0 0x1 /* PD5 gpio RDY pin pull_up*/
  189. 3 4 0x0 0x1>; /* PD4 gpio enable pin pull_up */
  190. };
  191. };
  192. mmc0 {
  193. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  194. atmel,pins =
  195. <0 17 0x1 0x0 /* PA17 periph A */
  196. 0 16 0x1 0x1 /* PA16 periph A with pullup */
  197. 0 15 0x1 0x1>; /* PA15 periph A with pullup */
  198. };
  199. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  200. atmel,pins =
  201. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  202. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  203. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  204. };
  205. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  206. atmel,pins =
  207. <0 11 0x2 0x1 /* PA11 periph B with pullup */
  208. 0 12 0x2 0x1 /* PA12 periph B with pullup */
  209. 0 13 0x2 0x1 /* PA13 periph B with pullup */
  210. 0 14 0x2 0x1>; /* PA14 periph B with pullup */
  211. };
  212. };
  213. ssc0 {
  214. pinctrl_ssc0_tx: ssc0_tx-0 {
  215. atmel,pins =
  216. <0 24 0x2 0x0 /* PA24 periph B */
  217. 0 25 0x2 0x0 /* PA25 periph B */
  218. 0 26 0x2 0x0>; /* PA26 periph B */
  219. };
  220. pinctrl_ssc0_rx: ssc0_rx-0 {
  221. atmel,pins =
  222. <0 27 0x2 0x0 /* PA27 periph B */
  223. 0 28 0x2 0x0 /* PA28 periph B */
  224. 0 29 0x2 0x0>; /* PA29 periph B */
  225. };
  226. };
  227. pioA: gpio@fffff400 {
  228. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  229. reg = <0xfffff400 0x200>;
  230. interrupts = <2 4 1>;
  231. #gpio-cells = <2>;
  232. gpio-controller;
  233. interrupt-controller;
  234. #interrupt-cells = <2>;
  235. };
  236. pioB: gpio@fffff600 {
  237. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  238. reg = <0xfffff600 0x200>;
  239. interrupts = <2 4 1>;
  240. #gpio-cells = <2>;
  241. gpio-controller;
  242. interrupt-controller;
  243. #interrupt-cells = <2>;
  244. };
  245. pioC: gpio@fffff800 {
  246. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  247. reg = <0xfffff800 0x200>;
  248. interrupts = <3 4 1>;
  249. #gpio-cells = <2>;
  250. gpio-controller;
  251. interrupt-controller;
  252. #interrupt-cells = <2>;
  253. };
  254. pioD: gpio@fffffa00 {
  255. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  256. reg = <0xfffffa00 0x200>;
  257. interrupts = <3 4 1>;
  258. #gpio-cells = <2>;
  259. gpio-controller;
  260. interrupt-controller;
  261. #interrupt-cells = <2>;
  262. };
  263. };
  264. dbgu: serial@fffff200 {
  265. compatible = "atmel,at91sam9260-usart";
  266. reg = <0xfffff200 0x200>;
  267. interrupts = <1 4 7>;
  268. pinctrl-names = "default";
  269. pinctrl-0 = <&pinctrl_dbgu>;
  270. status = "disabled";
  271. };
  272. ssc0: ssc@f0010000 {
  273. compatible = "atmel,at91sam9g45-ssc";
  274. reg = <0xf0010000 0x4000>;
  275. interrupts = <28 4 5>;
  276. pinctrl-names = "default";
  277. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  278. status = "disabled";
  279. };
  280. usart0: serial@f801c000 {
  281. compatible = "atmel,at91sam9260-usart";
  282. reg = <0xf801c000 0x4000>;
  283. interrupts = <5 4 5>;
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&pinctrl_usart0>;
  286. status = "disabled";
  287. };
  288. usart1: serial@f8020000 {
  289. compatible = "atmel,at91sam9260-usart";
  290. reg = <0xf8020000 0x4000>;
  291. interrupts = <6 4 5>;
  292. pinctrl-names = "default";
  293. pinctrl-0 = <&pinctrl_usart1>;
  294. status = "disabled";
  295. };
  296. usart2: serial@f8024000 {
  297. compatible = "atmel,at91sam9260-usart";
  298. reg = <0xf8024000 0x4000>;
  299. interrupts = <7 4 5>;
  300. pinctrl-names = "default";
  301. pinctrl-0 = <&pinctrl_usart2>;
  302. status = "disabled";
  303. };
  304. usart3: serial@f8028000 {
  305. compatible = "atmel,at91sam9260-usart";
  306. reg = <0xf8028000 0x4000>;
  307. interrupts = <8 4 5>;
  308. pinctrl-names = "default";
  309. pinctrl-0 = <&pinctrl_usart3>;
  310. status = "disabled";
  311. };
  312. i2c0: i2c@f8010000 {
  313. compatible = "atmel,at91sam9x5-i2c";
  314. reg = <0xf8010000 0x100>;
  315. interrupts = <9 4 6>;
  316. #address-cells = <1>;
  317. #size-cells = <0>;
  318. status = "disabled";
  319. };
  320. i2c1: i2c@f8014000 {
  321. compatible = "atmel,at91sam9x5-i2c";
  322. reg = <0xf8014000 0x100>;
  323. interrupts = <10 4 6>;
  324. #address-cells = <1>;
  325. #size-cells = <0>;
  326. status = "disabled";
  327. };
  328. };
  329. nand0: nand@40000000 {
  330. compatible = "atmel,at91rm9200-nand";
  331. #address-cells = <1>;
  332. #size-cells = <1>;
  333. reg = < 0x40000000 0x10000000
  334. 0xffffe000 0x00000600
  335. 0xffffe600 0x00000200
  336. 0x00108000 0x00018000
  337. >;
  338. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  339. atmel,nand-addr-offset = <21>;
  340. atmel,nand-cmd-offset = <22>;
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&pinctrl_nand>;
  343. gpios = <&pioD 5 0
  344. &pioD 4 0
  345. 0
  346. >;
  347. status = "disabled";
  348. };
  349. usb0: ohci@00500000 {
  350. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  351. reg = <0x00500000 0x00100000>;
  352. interrupts = <22 4 2>;
  353. status = "disabled";
  354. };
  355. };
  356. i2c@0 {
  357. compatible = "i2c-gpio";
  358. gpios = <&pioA 30 0 /* sda */
  359. &pioA 31 0 /* scl */
  360. >;
  361. i2c-gpio,sda-open-drain;
  362. i2c-gpio,scl-open-drain;
  363. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  364. #address-cells = <1>;
  365. #size-cells = <0>;
  366. status = "disabled";
  367. };
  368. };