tegra20-ventana.dts 13 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra20 Ventana evaluation board";
  5. compatible = "nvidia,ventana", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. host1x {
  10. hdmi {
  11. status = "okay";
  12. vdd-supply = <&hdmi_vdd_reg>;
  13. pll-supply = <&hdmi_pll_reg>;
  14. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  15. nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
  16. };
  17. };
  18. pinmux {
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&state_default>;
  21. state_default: pinmux {
  22. ata {
  23. nvidia,pins = "ata";
  24. nvidia,function = "ide";
  25. };
  26. atb {
  27. nvidia,pins = "atb", "gma", "gme";
  28. nvidia,function = "sdio4";
  29. };
  30. atc {
  31. nvidia,pins = "atc";
  32. nvidia,function = "nand";
  33. };
  34. atd {
  35. nvidia,pins = "atd", "ate", "gmb", "spia",
  36. "spib", "spic";
  37. nvidia,function = "gmi";
  38. };
  39. cdev1 {
  40. nvidia,pins = "cdev1";
  41. nvidia,function = "plla_out";
  42. };
  43. cdev2 {
  44. nvidia,pins = "cdev2";
  45. nvidia,function = "pllp_out4";
  46. };
  47. crtp {
  48. nvidia,pins = "crtp", "lm1";
  49. nvidia,function = "crt";
  50. };
  51. csus {
  52. nvidia,pins = "csus";
  53. nvidia,function = "vi_sensor_clk";
  54. };
  55. dap1 {
  56. nvidia,pins = "dap1";
  57. nvidia,function = "dap1";
  58. };
  59. dap2 {
  60. nvidia,pins = "dap2";
  61. nvidia,function = "dap2";
  62. };
  63. dap3 {
  64. nvidia,pins = "dap3";
  65. nvidia,function = "dap3";
  66. };
  67. dap4 {
  68. nvidia,pins = "dap4";
  69. nvidia,function = "dap4";
  70. };
  71. dta {
  72. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  73. nvidia,function = "vi";
  74. };
  75. dtf {
  76. nvidia,pins = "dtf";
  77. nvidia,function = "i2c3";
  78. };
  79. gmc {
  80. nvidia,pins = "gmc";
  81. nvidia,function = "uartd";
  82. };
  83. gmd {
  84. nvidia,pins = "gmd";
  85. nvidia,function = "sflash";
  86. };
  87. gpu {
  88. nvidia,pins = "gpu";
  89. nvidia,function = "pwm";
  90. };
  91. gpu7 {
  92. nvidia,pins = "gpu7";
  93. nvidia,function = "rtck";
  94. };
  95. gpv {
  96. nvidia,pins = "gpv", "slxa", "slxk";
  97. nvidia,function = "pcie";
  98. };
  99. hdint {
  100. nvidia,pins = "hdint";
  101. nvidia,function = "hdmi";
  102. };
  103. i2cp {
  104. nvidia,pins = "i2cp";
  105. nvidia,function = "i2cp";
  106. };
  107. irrx {
  108. nvidia,pins = "irrx", "irtx";
  109. nvidia,function = "uartb";
  110. };
  111. kbca {
  112. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  113. "kbce", "kbcf";
  114. nvidia,function = "kbc";
  115. };
  116. lcsn {
  117. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  118. "lsdi", "lvp0";
  119. nvidia,function = "rsvd4";
  120. };
  121. ld0 {
  122. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  123. "ld5", "ld6", "ld7", "ld8", "ld9",
  124. "ld10", "ld11", "ld12", "ld13", "ld14",
  125. "ld15", "ld16", "ld17", "ldi", "lhp0",
  126. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  127. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  128. "lspi", "lvp1", "lvs";
  129. nvidia,function = "displaya";
  130. };
  131. owc {
  132. nvidia,pins = "owc", "spdi", "spdo", "uac";
  133. nvidia,function = "rsvd2";
  134. };
  135. pmc {
  136. nvidia,pins = "pmc";
  137. nvidia,function = "pwr_on";
  138. };
  139. rm {
  140. nvidia,pins = "rm";
  141. nvidia,function = "i2c1";
  142. };
  143. sdb {
  144. nvidia,pins = "sdb", "sdc", "sdd", "slxc";
  145. nvidia,function = "sdio3";
  146. };
  147. sdio1 {
  148. nvidia,pins = "sdio1";
  149. nvidia,function = "sdio1";
  150. };
  151. slxd {
  152. nvidia,pins = "slxd";
  153. nvidia,function = "spdif";
  154. };
  155. spid {
  156. nvidia,pins = "spid", "spie", "spif";
  157. nvidia,function = "spi1";
  158. };
  159. spig {
  160. nvidia,pins = "spig", "spih";
  161. nvidia,function = "spi2_alt";
  162. };
  163. uaa {
  164. nvidia,pins = "uaa", "uab", "uda";
  165. nvidia,function = "ulpi";
  166. };
  167. uad {
  168. nvidia,pins = "uad";
  169. nvidia,function = "irda";
  170. };
  171. uca {
  172. nvidia,pins = "uca", "ucb";
  173. nvidia,function = "uartc";
  174. };
  175. conf_ata {
  176. nvidia,pins = "ata", "atb", "atc", "atd",
  177. "cdev1", "cdev2", "dap1", "dap2",
  178. "dap4", "ddc", "dtf", "gma", "gmc",
  179. "gme", "gpu", "gpu7", "i2cp", "irrx",
  180. "irtx", "pta", "rm", "sdc", "sdd",
  181. "slxc", "slxd", "slxk", "spdi", "spdo",
  182. "uac", "uad", "uca", "ucb", "uda";
  183. nvidia,pull = <0>;
  184. nvidia,tristate = <0>;
  185. };
  186. conf_ate {
  187. nvidia,pins = "ate", "csus", "dap3", "gmd",
  188. "gpv", "owc", "spia", "spib", "spic",
  189. "spid", "spie", "spig";
  190. nvidia,pull = <0>;
  191. nvidia,tristate = <1>;
  192. };
  193. conf_ck32 {
  194. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  195. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  196. nvidia,pull = <0>;
  197. };
  198. conf_crtp {
  199. nvidia,pins = "crtp", "gmb", "slxa", "spih";
  200. nvidia,pull = <2>;
  201. nvidia,tristate = <1>;
  202. };
  203. conf_dta {
  204. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  205. nvidia,pull = <1>;
  206. nvidia,tristate = <0>;
  207. };
  208. conf_dte {
  209. nvidia,pins = "dte", "spif";
  210. nvidia,pull = <1>;
  211. nvidia,tristate = <1>;
  212. };
  213. conf_hdint {
  214. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  215. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  216. nvidia,tristate = <1>;
  217. };
  218. conf_kbca {
  219. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  220. "kbce", "kbcf", "sdio1", "uaa", "uab";
  221. nvidia,pull = <2>;
  222. nvidia,tristate = <0>;
  223. };
  224. conf_lc {
  225. nvidia,pins = "lc", "ls";
  226. nvidia,pull = <2>;
  227. };
  228. conf_ld0 {
  229. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  230. "ld5", "ld6", "ld7", "ld8", "ld9",
  231. "ld10", "ld11", "ld12", "ld13", "ld14",
  232. "ld15", "ld16", "ld17", "ldi", "lhp0",
  233. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  234. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  235. "lvp1", "lvs", "pmc", "sdb";
  236. nvidia,tristate = <0>;
  237. };
  238. conf_ld17_0 {
  239. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  240. "ld23_22";
  241. nvidia,pull = <1>;
  242. };
  243. drive_sdio1 {
  244. nvidia,pins = "drive_sdio1";
  245. nvidia,high-speed-mode = <0>;
  246. nvidia,schmitt = <1>;
  247. nvidia,low-power-mode = <3>;
  248. nvidia,pull-down-strength = <31>;
  249. nvidia,pull-up-strength = <31>;
  250. nvidia,slew-rate-rising = <3>;
  251. nvidia,slew-rate-falling = <3>;
  252. };
  253. };
  254. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  255. ddc {
  256. nvidia,pins = "ddc";
  257. nvidia,function = "i2c2";
  258. };
  259. pta {
  260. nvidia,pins = "pta";
  261. nvidia,function = "rsvd4";
  262. };
  263. };
  264. state_i2cmux_pta: pinmux_i2cmux_pta {
  265. ddc {
  266. nvidia,pins = "ddc";
  267. nvidia,function = "rsvd4";
  268. };
  269. pta {
  270. nvidia,pins = "pta";
  271. nvidia,function = "i2c2";
  272. };
  273. };
  274. state_i2cmux_idle: pinmux_i2cmux_idle {
  275. ddc {
  276. nvidia,pins = "ddc";
  277. nvidia,function = "rsvd4";
  278. };
  279. pta {
  280. nvidia,pins = "pta";
  281. nvidia,function = "rsvd4";
  282. };
  283. };
  284. };
  285. i2s@70002800 {
  286. status = "okay";
  287. };
  288. serial@70006300 {
  289. status = "okay";
  290. clock-frequency = <216000000>;
  291. };
  292. i2c@7000c000 {
  293. status = "okay";
  294. clock-frequency = <400000>;
  295. wm8903: wm8903@1a {
  296. compatible = "wlf,wm8903";
  297. reg = <0x1a>;
  298. interrupt-parent = <&gpio>;
  299. interrupts = <187 0x04>;
  300. gpio-controller;
  301. #gpio-cells = <2>;
  302. micdet-cfg = <0>;
  303. micdet-delay = <100>;
  304. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  305. };
  306. /* ALS and proximity sensor */
  307. isl29018@44 {
  308. compatible = "isil,isl29018";
  309. reg = <0x44>;
  310. interrupt-parent = <&gpio>;
  311. interrupts = <202 0x04>; /*gpio PZ2 */
  312. };
  313. };
  314. i2c@7000c400 {
  315. status = "okay";
  316. clock-frequency = <100000>;
  317. };
  318. i2cmux {
  319. compatible = "i2c-mux-pinctrl";
  320. #address-cells = <1>;
  321. #size-cells = <0>;
  322. i2c-parent = <&{/i2c@7000c400}>;
  323. pinctrl-names = "ddc", "pta", "idle";
  324. pinctrl-0 = <&state_i2cmux_ddc>;
  325. pinctrl-1 = <&state_i2cmux_pta>;
  326. pinctrl-2 = <&state_i2cmux_idle>;
  327. hdmi_ddc: i2c@0 {
  328. reg = <0>;
  329. #address-cells = <1>;
  330. #size-cells = <0>;
  331. };
  332. i2c@1 {
  333. reg = <1>;
  334. #address-cells = <1>;
  335. #size-cells = <0>;
  336. };
  337. };
  338. i2c@7000c500 {
  339. status = "okay";
  340. clock-frequency = <400000>;
  341. };
  342. i2c@7000d000 {
  343. status = "okay";
  344. clock-frequency = <400000>;
  345. pmic: tps6586x@34 {
  346. compatible = "ti,tps6586x";
  347. reg = <0x34>;
  348. interrupts = <0 86 0x4>;
  349. ti,system-power-controller;
  350. #gpio-cells = <2>;
  351. gpio-controller;
  352. sys-supply = <&vdd_5v0_reg>;
  353. vin-sm0-supply = <&sys_reg>;
  354. vin-sm1-supply = <&sys_reg>;
  355. vin-sm2-supply = <&sys_reg>;
  356. vinldo01-supply = <&sm2_reg>;
  357. vinldo23-supply = <&sm2_reg>;
  358. vinldo4-supply = <&sm2_reg>;
  359. vinldo678-supply = <&sm2_reg>;
  360. vinldo9-supply = <&sm2_reg>;
  361. regulators {
  362. sys_reg: sys {
  363. regulator-name = "vdd_sys";
  364. regulator-always-on;
  365. };
  366. sm0 {
  367. regulator-name = "vdd_sm0,vdd_core";
  368. regulator-min-microvolt = <1200000>;
  369. regulator-max-microvolt = <1200000>;
  370. regulator-always-on;
  371. };
  372. sm1 {
  373. regulator-name = "vdd_sm1,vdd_cpu";
  374. regulator-min-microvolt = <1000000>;
  375. regulator-max-microvolt = <1000000>;
  376. regulator-always-on;
  377. };
  378. sm2_reg: sm2 {
  379. regulator-name = "vdd_sm2,vin_ldo*";
  380. regulator-min-microvolt = <3700000>;
  381. regulator-max-microvolt = <3700000>;
  382. regulator-always-on;
  383. };
  384. /* LDO0 is not connected to anything */
  385. ldo1 {
  386. regulator-name = "vdd_ldo1,avdd_pll*";
  387. regulator-min-microvolt = <1100000>;
  388. regulator-max-microvolt = <1100000>;
  389. regulator-always-on;
  390. };
  391. ldo2 {
  392. regulator-name = "vdd_ldo2,vdd_rtc";
  393. regulator-min-microvolt = <1200000>;
  394. regulator-max-microvolt = <1200000>;
  395. };
  396. ldo3 {
  397. regulator-name = "vdd_ldo3,avdd_usb*";
  398. regulator-min-microvolt = <3300000>;
  399. regulator-max-microvolt = <3300000>;
  400. regulator-always-on;
  401. };
  402. ldo4 {
  403. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  404. regulator-min-microvolt = <1800000>;
  405. regulator-max-microvolt = <1800000>;
  406. regulator-always-on;
  407. };
  408. ldo5 {
  409. regulator-name = "vdd_ldo5,vcore_mmc";
  410. regulator-min-microvolt = <2850000>;
  411. regulator-max-microvolt = <2850000>;
  412. regulator-always-on;
  413. };
  414. ldo6 {
  415. regulator-name = "vdd_ldo6,avdd_vdac";
  416. regulator-min-microvolt = <1800000>;
  417. regulator-max-microvolt = <1800000>;
  418. };
  419. hdmi_vdd_reg: ldo7 {
  420. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  421. regulator-min-microvolt = <3300000>;
  422. regulator-max-microvolt = <3300000>;
  423. };
  424. hdmi_pll_reg: ldo8 {
  425. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  426. regulator-min-microvolt = <1800000>;
  427. regulator-max-microvolt = <1800000>;
  428. };
  429. ldo9 {
  430. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  431. regulator-min-microvolt = <2850000>;
  432. regulator-max-microvolt = <2850000>;
  433. regulator-always-on;
  434. };
  435. ldo_rtc {
  436. regulator-name = "vdd_rtc_out,vdd_cell";
  437. regulator-min-microvolt = <3300000>;
  438. regulator-max-microvolt = <3300000>;
  439. regulator-always-on;
  440. };
  441. };
  442. };
  443. temperature-sensor@4c {
  444. compatible = "onnn,nct1008";
  445. reg = <0x4c>;
  446. };
  447. };
  448. pmc {
  449. nvidia,invert-interrupt;
  450. };
  451. usb@c5000000 {
  452. status = "okay";
  453. };
  454. usb@c5004000 {
  455. status = "okay";
  456. nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
  457. };
  458. usb@c5008000 {
  459. status = "okay";
  460. };
  461. sdhci@c8000000 {
  462. status = "okay";
  463. power-gpios = <&gpio 86 0>; /* gpio PK6 */
  464. bus-width = <4>;
  465. };
  466. sdhci@c8000400 {
  467. status = "okay";
  468. cd-gpios = <&gpio 69 0>; /* gpio PI5 */
  469. wp-gpios = <&gpio 57 0>; /* gpio PH1 */
  470. power-gpios = <&gpio 70 0>; /* gpio PI6 */
  471. bus-width = <4>;
  472. };
  473. sdhci@c8000600 {
  474. status = "okay";
  475. bus-width = <8>;
  476. };
  477. regulators {
  478. compatible = "simple-bus";
  479. #address-cells = <1>;
  480. #size-cells = <0>;
  481. vdd_5v0_reg: regulator@0 {
  482. compatible = "regulator-fixed";
  483. reg = <0>;
  484. regulator-name = "vdd_5v0";
  485. regulator-min-microvolt = <5000000>;
  486. regulator-max-microvolt = <5000000>;
  487. regulator-always-on;
  488. };
  489. regulator@1 {
  490. compatible = "regulator-fixed";
  491. reg = <1>;
  492. regulator-name = "vdd_1v5";
  493. regulator-min-microvolt = <1500000>;
  494. regulator-max-microvolt = <1500000>;
  495. gpio = <&pmic 0 0>;
  496. };
  497. regulator@2 {
  498. compatible = "regulator-fixed";
  499. reg = <2>;
  500. regulator-name = "vdd_1v2";
  501. regulator-min-microvolt = <1200000>;
  502. regulator-max-microvolt = <1200000>;
  503. gpio = <&pmic 1 0>;
  504. enable-active-high;
  505. };
  506. regulator@3 {
  507. compatible = "regulator-fixed";
  508. reg = <3>;
  509. regulator-name = "vdd_pnl";
  510. regulator-min-microvolt = <2800000>;
  511. regulator-max-microvolt = <2800000>;
  512. gpio = <&gpio 22 0>; /* gpio PC6 */
  513. enable-active-high;
  514. };
  515. regulator@4 {
  516. compatible = "regulator-fixed";
  517. reg = <4>;
  518. regulator-name = "vdd_bl";
  519. regulator-min-microvolt = <2800000>;
  520. regulator-max-microvolt = <2800000>;
  521. gpio = <&gpio 176 0>; /* gpio PW0 */
  522. enable-active-high;
  523. };
  524. };
  525. sound {
  526. compatible = "nvidia,tegra-audio-wm8903-ventana",
  527. "nvidia,tegra-audio-wm8903";
  528. nvidia,model = "NVIDIA Tegra Ventana";
  529. nvidia,audio-routing =
  530. "Headphone Jack", "HPOUTR",
  531. "Headphone Jack", "HPOUTL",
  532. "Int Spk", "ROP",
  533. "Int Spk", "RON",
  534. "Int Spk", "LOP",
  535. "Int Spk", "LON",
  536. "Mic Jack", "MICBIAS",
  537. "IN1L", "Mic Jack";
  538. nvidia,i2s-controller = <&tegra_i2s1>;
  539. nvidia,audio-codec = <&wm8903>;
  540. nvidia,spkr-en-gpios = <&wm8903 2 0>;
  541. nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
  542. nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
  543. nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
  544. };
  545. };