netxen_nic_hw.c 28 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to access the Phantom hardware
  31. *
  32. */
  33. #include "netxen_nic.h"
  34. #include "netxen_nic_hw.h"
  35. #include "netxen_nic_phan_reg.h"
  36. /* PCI Windowing for DDR regions. */
  37. #define ADDR_IN_RANGE(addr, low, high) \
  38. (((addr) <= (high)) && ((addr) >= (low)))
  39. #define NETXEN_FLASH_BASE (BOOTLD_START)
  40. #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
  41. #define NETXEN_MAX_MTU 8000
  42. #define NETXEN_MIN_MTU 64
  43. #define NETXEN_ETH_FCS_SIZE 4
  44. #define NETXEN_ENET_HEADER_SIZE 14
  45. #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
  46. #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
  47. #define NETXEN_NIU_HDRSIZE (0x1 << 6)
  48. #define NETXEN_NIU_TLRSIZE (0x1 << 5)
  49. #define lower32(x) ((u32)((x) & 0xffffffff))
  50. #define upper32(x) \
  51. ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
  52. #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
  53. #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
  54. #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
  55. #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
  56. #define NETXEN_NIC_WINDOW_MARGIN 0x100000
  57. unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
  58. unsigned long long addr);
  59. void netxen_free_hw_resources(struct netxen_adapter *adapter);
  60. int netxen_nic_set_mac(struct net_device *netdev, void *p)
  61. {
  62. struct netxen_port *port = netdev_priv(netdev);
  63. struct netxen_adapter *adapter = port->adapter;
  64. struct sockaddr *addr = p;
  65. if (netif_running(netdev))
  66. return -EBUSY;
  67. if (!is_valid_ether_addr(addr->sa_data))
  68. return -EADDRNOTAVAIL;
  69. DPRINTK(INFO, "valid ether addr\n");
  70. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  71. if (adapter->ops->macaddr_set)
  72. adapter->ops->macaddr_set(port, addr->sa_data);
  73. return 0;
  74. }
  75. /*
  76. * netxen_nic_set_multi - Multicast
  77. */
  78. void netxen_nic_set_multi(struct net_device *netdev)
  79. {
  80. struct netxen_port *port = netdev_priv(netdev);
  81. struct netxen_adapter *adapter = port->adapter;
  82. struct dev_mc_list *mc_ptr;
  83. __le32 netxen_mac_addr_cntl_data = 0;
  84. mc_ptr = netdev->mc_list;
  85. if (netdev->flags & IFF_PROMISC) {
  86. if (adapter->ops->set_promisc)
  87. adapter->ops->set_promisc(adapter,
  88. port->portnum,
  89. NETXEN_NIU_PROMISC_MODE);
  90. } else {
  91. if (adapter->ops->unset_promisc &&
  92. adapter->ahw.boardcfg.board_type
  93. != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
  94. adapter->ops->unset_promisc(adapter,
  95. port->portnum,
  96. NETXEN_NIU_NON_PROMISC_MODE);
  97. }
  98. if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
  99. netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
  100. netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
  101. netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00);
  102. netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00);
  103. netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00);
  104. netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data);
  105. netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data);
  106. netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data);
  107. netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data);
  108. } else {
  109. netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00);
  110. netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
  111. netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01);
  112. netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02);
  113. netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03);
  114. }
  115. writel(netxen_mac_addr_cntl_data,
  116. NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG));
  117. if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
  118. writel(netxen_mac_addr_cntl_data,
  119. NETXEN_CRB_NORMALIZE(adapter,
  120. NETXEN_MULTICAST_ADDR_HI_0));
  121. } else {
  122. writel(netxen_mac_addr_cntl_data,
  123. NETXEN_CRB_NORMALIZE(adapter,
  124. NETXEN_MULTICAST_ADDR_HI_1));
  125. }
  126. netxen_mac_addr_cntl_data = 0;
  127. writel(netxen_mac_addr_cntl_data,
  128. NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR));
  129. }
  130. /*
  131. * netxen_nic_change_mtu - Change the Maximum Transfer Unit
  132. * @returns 0 on success, negative on failure
  133. */
  134. int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
  135. {
  136. struct netxen_port *port = netdev_priv(netdev);
  137. struct netxen_adapter *adapter = port->adapter;
  138. int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
  139. if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
  140. printk(KERN_ERR "%s: %s %d is not supported.\n",
  141. netxen_nic_driver_name, netdev->name, mtu);
  142. return -EINVAL;
  143. }
  144. if (adapter->ops->set_mtu)
  145. adapter->ops->set_mtu(port, mtu);
  146. netdev->mtu = mtu;
  147. return 0;
  148. }
  149. /*
  150. * check if the firmware has been downloaded and ready to run and
  151. * setup the address for the descriptors in the adapter
  152. */
  153. int netxen_nic_hw_resources(struct netxen_adapter *adapter)
  154. {
  155. struct netxen_hardware_context *hw = &adapter->ahw;
  156. u32 state = 0;
  157. void *addr;
  158. void *pause_addr;
  159. int loops = 0, err = 0;
  160. int ctx, ring;
  161. u32 card_cmdring = 0;
  162. struct netxen_rcv_desc_crb *rcv_desc_crb = NULL;
  163. struct netxen_recv_context *recv_ctx;
  164. struct netxen_rcv_desc_ctx *rcv_desc;
  165. DPRINTK(INFO, "crb_base: %lx %lx", NETXEN_PCI_CRBSPACE,
  166. PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
  167. DPRINTK(INFO, "cam base: %lx %lx", NETXEN_CRB_CAM,
  168. pci_base_offset(adapter, NETXEN_CRB_CAM));
  169. DPRINTK(INFO, "cam RAM: %lx %lx", NETXEN_CAM_RAM_BASE,
  170. pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
  171. DPRINTK(INFO, "NIC base:%lx %lx\n", NIC_CRB_BASE_PORT1,
  172. pci_base_offset(adapter, NIC_CRB_BASE_PORT1));
  173. /* Window 1 call */
  174. card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
  175. DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n",
  176. card_cmdring);
  177. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  178. DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
  179. loops = 0;
  180. state = 0;
  181. /* Window 1 call */
  182. state = readl(NETXEN_CRB_NORMALIZE(adapter,
  183. recv_crb_registers[ctx].
  184. crb_rcvpeg_state));
  185. while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
  186. udelay(100);
  187. /* Window 1 call */
  188. state = readl(NETXEN_CRB_NORMALIZE(adapter,
  189. recv_crb_registers
  190. [ctx].
  191. crb_rcvpeg_state));
  192. loops++;
  193. }
  194. if (loops >= 20) {
  195. printk(KERN_ERR "Rcv Peg initialization not complete:"
  196. "%x.\n", state);
  197. err = -EIO;
  198. return err;
  199. }
  200. }
  201. DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
  202. addr = netxen_alloc(adapter->ahw.pdev,
  203. sizeof(struct cmd_desc_type0) *
  204. adapter->max_tx_desc_count,
  205. &hw->cmd_desc_phys_addr, &hw->cmd_desc_pdev);
  206. if (addr == NULL) {
  207. DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
  208. return -ENOMEM;
  209. }
  210. pause_addr = netxen_alloc(adapter->ahw.pdev, 512,
  211. (dma_addr_t *) & hw->pause_physaddr,
  212. &hw->pause_pdev);
  213. if (pause_addr == NULL) {
  214. DPRINTK(1, ERR, "bad return from pci_alloc_consistent\n");
  215. return -ENOMEM;
  216. }
  217. hw->pauseaddr = (char *)pause_addr;
  218. {
  219. u64 *ptr = (u64 *) pause_addr;
  220. *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
  221. *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
  222. *ptr++ = NETXEN_NIC_UNIT_PAUSE_ADDR;
  223. *ptr++ = NETXEN_NIC_ZERO_PAUSE_ADDR;
  224. *ptr++ = NETXEN_NIC_EPG_PAUSE_ADDR1;
  225. *ptr++ = NETXEN_NIC_EPG_PAUSE_ADDR2;
  226. }
  227. hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
  228. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  229. recv_ctx = &adapter->recv_ctx[ctx];
  230. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  231. rcv_desc = &recv_ctx->rcv_desc[ring];
  232. addr = netxen_alloc(adapter->ahw.pdev,
  233. RCV_DESC_RINGSIZE,
  234. &rcv_desc->phys_addr,
  235. &rcv_desc->phys_pdev);
  236. if (addr == NULL) {
  237. DPRINTK(ERR, "bad return from "
  238. "pci_alloc_consistent\n");
  239. netxen_free_hw_resources(adapter);
  240. err = -ENOMEM;
  241. return err;
  242. }
  243. rcv_desc->desc_head = (struct rcv_desc *)addr;
  244. }
  245. addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
  246. &recv_ctx->rcv_status_desc_phys_addr,
  247. &recv_ctx->rcv_status_desc_pdev);
  248. if (addr == NULL) {
  249. DPRINTK(ERR, "bad return from"
  250. " pci_alloc_consistent\n");
  251. netxen_free_hw_resources(adapter);
  252. err = -ENOMEM;
  253. return err;
  254. }
  255. recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
  256. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  257. rcv_desc = &recv_ctx->rcv_desc[ring];
  258. rcv_desc_crb =
  259. &recv_crb_registers[ctx].rcv_desc_crb[ring];
  260. DPRINTK(INFO, "ring #%d crb global ring reg 0x%x\n",
  261. ring, rcv_desc_crb->crb_globalrcv_ring);
  262. /* Window = 1 */
  263. writel(lower32(rcv_desc->phys_addr),
  264. NETXEN_CRB_NORMALIZE(adapter,
  265. rcv_desc_crb->
  266. crb_globalrcv_ring));
  267. DPRINTK(INFO, "GLOBAL_RCV_RING ctx %d, addr 0x%x"
  268. " val 0x%llx,"
  269. " virt %p\n", ctx,
  270. rcv_desc_crb->crb_globalrcv_ring,
  271. (unsigned long long)rcv_desc->phys_addr,
  272. +rcv_desc->desc_head);
  273. }
  274. /* Window = 1 */
  275. writel(lower32(recv_ctx->rcv_status_desc_phys_addr),
  276. NETXEN_CRB_NORMALIZE(adapter,
  277. recv_crb_registers[ctx].
  278. crb_rcvstatus_ring));
  279. DPRINTK(INFO, "RCVSTATUS_RING, ctx %d, addr 0x%x,"
  280. " val 0x%x,virt%p\n",
  281. ctx,
  282. recv_crb_registers[ctx].crb_rcvstatus_ring,
  283. (unsigned long long)recv_ctx->rcv_status_desc_phys_addr,
  284. recv_ctx->rcv_status_desc_head);
  285. }
  286. /* Window = 1 */
  287. writel(lower32(hw->pause_physaddr),
  288. NETXEN_CRB_NORMALIZE(adapter, CRB_PAUSE_ADDR_LO));
  289. writel(upper32(hw->pause_physaddr),
  290. NETXEN_CRB_NORMALIZE(adapter, CRB_PAUSE_ADDR_HI));
  291. writel(lower32(hw->cmd_desc_phys_addr),
  292. NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_LO));
  293. writel(upper32(hw->cmd_desc_phys_addr),
  294. NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_CMD_ADDR_HI));
  295. return err;
  296. }
  297. void netxen_free_hw_resources(struct netxen_adapter *adapter)
  298. {
  299. struct netxen_recv_context *recv_ctx;
  300. struct netxen_rcv_desc_ctx *rcv_desc;
  301. int ctx, ring;
  302. if (adapter->ahw.cmd_desc_head != NULL) {
  303. pci_free_consistent(adapter->ahw.cmd_desc_pdev,
  304. sizeof(struct cmd_desc_type0) *
  305. adapter->max_tx_desc_count,
  306. adapter->ahw.cmd_desc_head,
  307. adapter->ahw.cmd_desc_phys_addr);
  308. adapter->ahw.cmd_desc_head = NULL;
  309. }
  310. if (adapter->ahw.pauseaddr != NULL) {
  311. pci_free_consistent(adapter->ahw.pause_pdev, 512,
  312. adapter->ahw.pauseaddr,
  313. adapter->ahw.pause_physaddr);
  314. adapter->ahw.pauseaddr = NULL;
  315. }
  316. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  317. recv_ctx = &adapter->recv_ctx[ctx];
  318. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  319. rcv_desc = &recv_ctx->rcv_desc[ring];
  320. if (rcv_desc->desc_head != NULL) {
  321. pci_free_consistent(rcv_desc->phys_pdev,
  322. RCV_DESC_RINGSIZE,
  323. rcv_desc->desc_head,
  324. rcv_desc->phys_addr);
  325. rcv_desc->desc_head = NULL;
  326. }
  327. }
  328. if (recv_ctx->rcv_status_desc_head != NULL) {
  329. pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
  330. STATUS_DESC_RINGSIZE,
  331. recv_ctx->rcv_status_desc_head,
  332. recv_ctx->
  333. rcv_status_desc_phys_addr);
  334. recv_ctx->rcv_status_desc_head = NULL;
  335. }
  336. }
  337. }
  338. void netxen_tso_check(struct netxen_adapter *adapter,
  339. struct cmd_desc_type0 *desc, struct sk_buff *skb)
  340. {
  341. if (desc->mss) {
  342. desc->total_hdr_length = sizeof(struct ethhdr) +
  343. ((skb->nh.iph)->ihl * sizeof(u32)) +
  344. ((skb->h.th)->doff * sizeof(u32));
  345. desc->opcode = TX_TCP_LSO;
  346. } else if (skb->ip_summed == CHECKSUM_COMPLETE) {
  347. if (skb->nh.iph->protocol == IPPROTO_TCP) {
  348. desc->opcode = TX_TCP_PKT;
  349. } else if (skb->nh.iph->protocol == IPPROTO_UDP) {
  350. desc->opcode = TX_UDP_PKT;
  351. } else {
  352. return;
  353. }
  354. }
  355. adapter->stats.xmitcsummed++;
  356. CMD_DESC_TCP_HDR_OFFSET_WRT(desc, skb->h.raw - skb->data);
  357. desc->length_tcp_hdr = cpu_to_le32(desc->length_tcp_hdr);
  358. desc->ip_hdr_offset = skb->nh.raw - skb->data;
  359. }
  360. int netxen_is_flash_supported(struct netxen_adapter *adapter)
  361. {
  362. const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
  363. int addr, val01, val02, i, j;
  364. /* if the flash size less than 4Mb, make huge war cry and die */
  365. for (j = 1; j < 4; j++) {
  366. addr = j * NETXEN_NIC_WINDOW_MARGIN;
  367. for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
  368. if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
  369. && netxen_rom_fast_read(adapter, (addr + locs[i]),
  370. &val02) == 0) {
  371. if (val01 == val02)
  372. return -1;
  373. } else
  374. return -1;
  375. }
  376. }
  377. return 0;
  378. }
  379. static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
  380. int size, u32 * buf)
  381. {
  382. int i, addr;
  383. u32 *ptr32;
  384. addr = base;
  385. ptr32 = buf;
  386. for (i = 0; i < size / sizeof(u32); i++) {
  387. if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
  388. return -1;
  389. ptr32++;
  390. addr += sizeof(u32);
  391. }
  392. if ((char *)buf + size > (char *)ptr32) {
  393. u32 local;
  394. if (netxen_rom_fast_read(adapter, addr, &local) == -1)
  395. return -1;
  396. memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
  397. }
  398. return 0;
  399. }
  400. int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
  401. {
  402. u32 *pmac = (u32 *) & mac[0];
  403. if (netxen_get_flash_block(adapter,
  404. USER_START +
  405. offsetof(struct netxen_new_user_info,
  406. mac_addr),
  407. FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
  408. return -1;
  409. }
  410. if (*mac == ~0ULL) {
  411. if (netxen_get_flash_block(adapter,
  412. USER_START_OLD +
  413. offsetof(struct netxen_user_old_info,
  414. mac_addr),
  415. FLASH_NUM_PORTS * sizeof(u64),
  416. pmac) == -1)
  417. return -1;
  418. if (*mac == ~0ULL)
  419. return -1;
  420. }
  421. return 0;
  422. }
  423. /*
  424. * Changes the CRB window to the specified window.
  425. */
  426. void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
  427. {
  428. void __iomem *offset;
  429. u32 tmp;
  430. int count = 0;
  431. if (adapter->curr_window == wndw)
  432. return;
  433. /*
  434. * Move the CRB window.
  435. * We need to write to the "direct access" region of PCI
  436. * to avoid a race condition where the window register has
  437. * not been successfully written across CRB before the target
  438. * register address is received by PCI. The direct region bypasses
  439. * the CRB bus.
  440. */
  441. offset =
  442. PCI_OFFSET_SECOND_RANGE(adapter,
  443. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
  444. if (wndw & 0x1)
  445. wndw = NETXEN_WINDOW_ONE;
  446. writel(wndw, offset);
  447. /* MUST make sure window is set before we forge on... */
  448. while ((tmp = readl(offset)) != wndw) {
  449. printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
  450. "registered properly: 0x%08x.\n",
  451. netxen_nic_driver_name, __FUNCTION__, tmp);
  452. mdelay(1);
  453. if (count >= 10)
  454. break;
  455. count++;
  456. }
  457. adapter->curr_window = wndw;
  458. }
  459. void netxen_load_firmware(struct netxen_adapter *adapter)
  460. {
  461. int i;
  462. long data, size = 0;
  463. long flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
  464. u64 off;
  465. void __iomem *addr;
  466. size = NETXEN_FIRMWARE_LEN;
  467. writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
  468. for (i = 0; i < size; i++) {
  469. if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
  470. DPRINTK(ERR,
  471. "Error in netxen_rom_fast_read(). Will skip"
  472. "loading flash image\n");
  473. return;
  474. }
  475. off = netxen_nic_pci_set_window(adapter, memaddr);
  476. addr = pci_base_offset(adapter, off);
  477. writel(data, addr);
  478. flashaddr += 4;
  479. memaddr += 4;
  480. }
  481. udelay(100);
  482. /* make sure Casper is powered on */
  483. writel(0x3fff,
  484. NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
  485. writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
  486. udelay(100);
  487. }
  488. int
  489. netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
  490. int len)
  491. {
  492. void __iomem *addr;
  493. if (ADDR_IN_WINDOW1(off)) {
  494. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  495. } else { /* Window 0 */
  496. addr = pci_base_offset(adapter, off);
  497. netxen_nic_pci_change_crbwindow(adapter, 0);
  498. }
  499. DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
  500. " data %llx len %d\n",
  501. pci_base(adapter, off), off, addr,
  502. *(unsigned long long *)data, len);
  503. if (!addr) {
  504. netxen_nic_pci_change_crbwindow(adapter, 1);
  505. return 1;
  506. }
  507. switch (len) {
  508. case 1:
  509. writeb(*(u8 *) data, addr);
  510. break;
  511. case 2:
  512. writew(*(u16 *) data, addr);
  513. break;
  514. case 4:
  515. writel(*(u32 *) data, addr);
  516. break;
  517. case 8:
  518. writeq(*(u64 *) data, addr);
  519. break;
  520. default:
  521. DPRINTK(INFO,
  522. "writing data %lx to offset %llx, num words=%d\n",
  523. *(unsigned long *)data, off, (len >> 3));
  524. netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
  525. (len >> 3));
  526. break;
  527. }
  528. if (!ADDR_IN_WINDOW1(off))
  529. netxen_nic_pci_change_crbwindow(adapter, 1);
  530. return 0;
  531. }
  532. int
  533. netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
  534. int len)
  535. {
  536. void __iomem *addr;
  537. if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
  538. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  539. } else { /* Window 0 */
  540. addr = pci_base_offset(adapter, off);
  541. netxen_nic_pci_change_crbwindow(adapter, 0);
  542. }
  543. DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
  544. pci_base(adapter, off), off, addr);
  545. if (!addr) {
  546. netxen_nic_pci_change_crbwindow(adapter, 1);
  547. return 1;
  548. }
  549. switch (len) {
  550. case 1:
  551. *(u8 *) data = readb(addr);
  552. break;
  553. case 2:
  554. *(u16 *) data = readw(addr);
  555. break;
  556. case 4:
  557. *(u32 *) data = readl(addr);
  558. break;
  559. case 8:
  560. *(u64 *) data = readq(addr);
  561. break;
  562. default:
  563. netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
  564. (len >> 3));
  565. break;
  566. }
  567. DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
  568. if (!ADDR_IN_WINDOW1(off))
  569. netxen_nic_pci_change_crbwindow(adapter, 1);
  570. return 0;
  571. }
  572. void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
  573. { /* Only for window 1 */
  574. void __iomem *addr;
  575. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  576. DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
  577. pci_base(adapter, off), off, addr);
  578. writel(val, addr);
  579. }
  580. int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
  581. { /* Only for window 1 */
  582. void __iomem *addr;
  583. int val;
  584. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  585. DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
  586. adapter->ahw.pci_base, off, addr);
  587. val = readl(addr);
  588. writel(val, addr);
  589. return val;
  590. }
  591. /* Change the window to 0, write and change back to window 1. */
  592. void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
  593. {
  594. void __iomem *addr;
  595. netxen_nic_pci_change_crbwindow(adapter, 0);
  596. addr = pci_base_offset(adapter, index);
  597. writel(value, addr);
  598. netxen_nic_pci_change_crbwindow(adapter, 1);
  599. }
  600. /* Change the window to 0, read and change back to window 1. */
  601. void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
  602. {
  603. void __iomem *addr;
  604. addr = pci_base_offset(adapter, index);
  605. netxen_nic_pci_change_crbwindow(adapter, 0);
  606. *value = readl(addr);
  607. netxen_nic_pci_change_crbwindow(adapter, 1);
  608. }
  609. int netxen_pci_set_window_warning_count = 0;
  610. unsigned long
  611. netxen_nic_pci_set_window(struct netxen_adapter *adapter,
  612. unsigned long long addr)
  613. {
  614. static int ddr_mn_window = -1;
  615. static int qdr_sn_window = -1;
  616. int window;
  617. if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
  618. /* DDR network side */
  619. addr -= NETXEN_ADDR_DDR_NET;
  620. window = (addr >> 25) & 0x3ff;
  621. if (ddr_mn_window != window) {
  622. ddr_mn_window = window;
  623. writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
  624. NETXEN_PCIX_PH_REG
  625. (PCIX_MN_WINDOW)));
  626. /* MUST make sure window is set before we forge on... */
  627. readl(PCI_OFFSET_SECOND_RANGE(adapter,
  628. NETXEN_PCIX_PH_REG
  629. (PCIX_MN_WINDOW)));
  630. }
  631. addr -= (window * NETXEN_WINDOW_ONE);
  632. addr += NETXEN_PCI_DDR_NET;
  633. } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
  634. addr -= NETXEN_ADDR_OCM0;
  635. addr += NETXEN_PCI_OCM0;
  636. } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
  637. addr -= NETXEN_ADDR_OCM1;
  638. addr += NETXEN_PCI_OCM1;
  639. } else
  640. if (ADDR_IN_RANGE
  641. (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
  642. /* QDR network side */
  643. addr -= NETXEN_ADDR_QDR_NET;
  644. window = (addr >> 22) & 0x3f;
  645. if (qdr_sn_window != window) {
  646. qdr_sn_window = window;
  647. writel((window << 22),
  648. PCI_OFFSET_SECOND_RANGE(adapter,
  649. NETXEN_PCIX_PH_REG
  650. (PCIX_SN_WINDOW)));
  651. /* MUST make sure window is set before we forge on... */
  652. readl(PCI_OFFSET_SECOND_RANGE(adapter,
  653. NETXEN_PCIX_PH_REG
  654. (PCIX_SN_WINDOW)));
  655. }
  656. addr -= (window * 0x400000);
  657. addr += NETXEN_PCI_QDR_NET;
  658. } else {
  659. /*
  660. * peg gdb frequently accesses memory that doesn't exist,
  661. * this limits the chit chat so debugging isn't slowed down.
  662. */
  663. if ((netxen_pci_set_window_warning_count++ < 8)
  664. || (netxen_pci_set_window_warning_count % 64 == 0))
  665. printk("%s: Warning:netxen_nic_pci_set_window()"
  666. " Unknown address range!\n",
  667. netxen_nic_driver_name);
  668. }
  669. return addr;
  670. }
  671. int netxen_nic_get_board_info(struct netxen_adapter *adapter)
  672. {
  673. int rv = 0;
  674. int addr = BRDCFG_START;
  675. struct netxen_board_info *boardinfo;
  676. int index;
  677. u32 *ptr32;
  678. boardinfo = &adapter->ahw.boardcfg;
  679. ptr32 = (u32 *) boardinfo;
  680. for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
  681. index++) {
  682. if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
  683. return -EIO;
  684. }
  685. ptr32++;
  686. addr += sizeof(u32);
  687. }
  688. if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
  689. printk("%s: ERROR reading %s board config."
  690. " Read %x, expected %x\n", netxen_nic_driver_name,
  691. netxen_nic_driver_name,
  692. boardinfo->magic, NETXEN_BDINFO_MAGIC);
  693. rv = -1;
  694. }
  695. if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
  696. printk("%s: Unknown board config version."
  697. " Read %x, expected %x\n", netxen_nic_driver_name,
  698. boardinfo->header_version, NETXEN_BDINFO_VERSION);
  699. rv = -1;
  700. }
  701. DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
  702. switch ((netxen_brdtype_t) boardinfo->board_type) {
  703. case NETXEN_BRDTYPE_P2_SB35_4G:
  704. adapter->ahw.board_type = NETXEN_NIC_GBE;
  705. break;
  706. case NETXEN_BRDTYPE_P2_SB31_10G:
  707. case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
  708. case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
  709. case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
  710. adapter->ahw.board_type = NETXEN_NIC_XGBE;
  711. break;
  712. case NETXEN_BRDTYPE_P1_BD:
  713. case NETXEN_BRDTYPE_P1_SB:
  714. case NETXEN_BRDTYPE_P1_SMAX:
  715. case NETXEN_BRDTYPE_P1_SOCK:
  716. adapter->ahw.board_type = NETXEN_NIC_GBE;
  717. break;
  718. default:
  719. printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
  720. boardinfo->board_type);
  721. break;
  722. }
  723. return rv;
  724. }
  725. /* NIU access sections */
  726. int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu)
  727. {
  728. struct netxen_adapter *adapter = port->adapter;
  729. netxen_nic_write_w0(adapter,
  730. NETXEN_NIU_GB_MAX_FRAME_SIZE(port->portnum),
  731. new_mtu);
  732. return 0;
  733. }
  734. int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu)
  735. {
  736. struct netxen_adapter *adapter = port->adapter;
  737. new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
  738. netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
  739. return 0;
  740. }
  741. void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
  742. {
  743. int portno;
  744. for (portno = 0; portno < NETXEN_NIU_MAX_GBE_PORTS; portno++)
  745. netxen_niu_gbe_init_port(adapter, portno);
  746. }
  747. void netxen_nic_stop_all_ports(struct netxen_adapter *adapter)
  748. {
  749. int port_nr;
  750. struct netxen_port *port;
  751. for (port_nr = 0; port_nr < adapter->ahw.max_ports; port_nr++) {
  752. port = adapter->port[port_nr];
  753. if (adapter->ops->stop_port)
  754. adapter->ops->stop_port(adapter, port->portnum);
  755. }
  756. }
  757. void
  758. netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
  759. int data)
  760. {
  761. void __iomem *addr;
  762. if (ADDR_IN_WINDOW1(off)) {
  763. writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
  764. } else {
  765. netxen_nic_pci_change_crbwindow(adapter, 0);
  766. addr = pci_base_offset(adapter, off);
  767. writel(data, addr);
  768. netxen_nic_pci_change_crbwindow(adapter, 1);
  769. }
  770. }
  771. void netxen_nic_set_link_parameters(struct netxen_port *port)
  772. {
  773. struct netxen_adapter *adapter = port->adapter;
  774. __le32 status;
  775. u16 autoneg;
  776. __le32 mode;
  777. netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
  778. if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
  779. if (adapter->ops->phy_read
  780. && adapter->ops->
  781. phy_read(adapter, port->portnum,
  782. NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
  783. &status) == 0) {
  784. if (netxen_get_phy_link(status)) {
  785. switch (netxen_get_phy_speed(status)) {
  786. case 0:
  787. port->link_speed = SPEED_10;
  788. break;
  789. case 1:
  790. port->link_speed = SPEED_100;
  791. break;
  792. case 2:
  793. port->link_speed = SPEED_1000;
  794. break;
  795. default:
  796. port->link_speed = -1;
  797. break;
  798. }
  799. switch (netxen_get_phy_duplex(status)) {
  800. case 0:
  801. port->link_duplex = DUPLEX_HALF;
  802. break;
  803. case 1:
  804. port->link_duplex = DUPLEX_FULL;
  805. break;
  806. default:
  807. port->link_duplex = -1;
  808. break;
  809. }
  810. if (adapter->ops->phy_read
  811. && adapter->ops->
  812. phy_read(adapter, port->portnum,
  813. NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
  814. (__le32 *) & autoneg) != 0)
  815. port->link_autoneg = autoneg;
  816. } else
  817. goto link_down;
  818. } else {
  819. link_down:
  820. port->link_speed = -1;
  821. port->link_duplex = -1;
  822. }
  823. }
  824. }
  825. void netxen_nic_flash_print(struct netxen_adapter *adapter)
  826. {
  827. int valid = 1;
  828. u32 fw_major = 0;
  829. u32 fw_minor = 0;
  830. u32 fw_build = 0;
  831. char brd_name[NETXEN_MAX_SHORT_NAME];
  832. struct netxen_new_user_info user_info;
  833. int i, addr = USER_START;
  834. u32 *ptr32;
  835. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  836. if (board_info->magic != NETXEN_BDINFO_MAGIC) {
  837. printk
  838. ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
  839. board_info->magic, NETXEN_BDINFO_MAGIC);
  840. valid = 0;
  841. }
  842. if (board_info->header_version != NETXEN_BDINFO_VERSION) {
  843. printk("NetXen Unknown board config version."
  844. " Read %x, expected %x\n",
  845. board_info->header_version, NETXEN_BDINFO_VERSION);
  846. valid = 0;
  847. }
  848. if (valid) {
  849. ptr32 = (u32 *) & user_info;
  850. for (i = 0;
  851. i < sizeof(struct netxen_new_user_info) / sizeof(u32);
  852. i++) {
  853. if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
  854. printk("%s: ERROR reading %s board userarea.\n",
  855. netxen_nic_driver_name,
  856. netxen_nic_driver_name);
  857. return;
  858. }
  859. ptr32++;
  860. addr += sizeof(u32);
  861. }
  862. get_brd_name_by_type(board_info->board_type, brd_name);
  863. printk("NetXen %s Board S/N %s Chip id 0x%x\n",
  864. brd_name, user_info.serial_num, board_info->chip_id);
  865. printk("NetXen %s Board #%d, Chip id 0x%x\n",
  866. board_info->board_type == 0x0b ? "XGB" : "GBE",
  867. board_info->board_num, board_info->chip_id);
  868. fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
  869. NETXEN_FW_VERSION_MAJOR));
  870. fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
  871. NETXEN_FW_VERSION_MINOR));
  872. fw_build =
  873. readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
  874. printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
  875. fw_build);
  876. }
  877. if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
  878. printk(KERN_ERR "The mismatch in driver version and firmware "
  879. "version major number\n"
  880. "Driver version major number = %d \t"
  881. "Firmware version major number = %d \n",
  882. _NETXEN_NIC_LINUX_MAJOR, fw_major);
  883. adapter->driver_mismatch = 1;
  884. }
  885. if (fw_minor != _NETXEN_NIC_LINUX_MINOR) {
  886. printk(KERN_ERR "The mismatch in driver version and firmware "
  887. "version minor number\n"
  888. "Driver version minor number = %d \t"
  889. "Firmware version minor number = %d \n",
  890. _NETXEN_NIC_LINUX_MINOR, fw_minor);
  891. adapter->driver_mismatch = 1;
  892. }
  893. if (adapter->driver_mismatch)
  894. printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
  895. fw_major, fw_minor);
  896. }
  897. int netxen_crb_read_val(struct netxen_adapter *adapter, unsigned long off)
  898. {
  899. int data;
  900. netxen_nic_hw_read_wx(adapter, off, &data, 4);
  901. return data;
  902. }