iwl3945-base.c 230 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-commands.h"
  47. #include "iwl-3945.h"
  48. #include "iwl-3945-fh.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-core.h"
  51. #include "iwl-dev.h"
  52. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  53. struct iwl3945_tx_queue *txq);
  54. /******************************************************************************
  55. *
  56. * module boiler plate
  57. *
  58. ******************************************************************************/
  59. /* module parameters */
  60. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  61. static u32 iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  62. static int iwl3945_param_disable; /* def: 0 = enable radio */
  63. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  64. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  65. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWL39_VERSION "1.2.26k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  83. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  84. #define DRV_VERSION IWL39_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88. MODULE_LICENSE("GPL");
  89. static const struct ieee80211_supported_band *iwl3945_get_band(
  90. struct iwl_priv *priv, enum ieee80211_band band)
  91. {
  92. return priv->hw->wiphy->bands[band];
  93. }
  94. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  95. * DMA services
  96. *
  97. * Theory of operation
  98. *
  99. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  100. * of buffer descriptors, each of which points to one or more data buffers for
  101. * the device to read from or fill. Driver and device exchange status of each
  102. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  103. * entries in each circular buffer, to protect against confusing empty and full
  104. * queue states.
  105. *
  106. * The device reads or writes the data in the queues via the device's several
  107. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  108. *
  109. * For Tx queue, there are low mark and high mark limits. If, after queuing
  110. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  111. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  112. * Tx queue resumed.
  113. *
  114. * The 3945 operates with six queues: One receive queue, one transmit queue
  115. * (#4) for sending commands to the device firmware, and four transmit queues
  116. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  117. ***************************************************/
  118. int iwl3945_x2_queue_used(const struct iwl_queue *q, int i)
  119. {
  120. return q->write_ptr > q->read_ptr ?
  121. (i >= q->read_ptr && i < q->write_ptr) :
  122. !(i < q->read_ptr && i >= q->write_ptr);
  123. }
  124. /**
  125. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  126. */
  127. static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  128. int count, int slots_num, u32 id)
  129. {
  130. q->n_bd = count;
  131. q->n_window = slots_num;
  132. q->id = id;
  133. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  134. * and iwl_queue_dec_wrap are broken. */
  135. BUG_ON(!is_power_of_2(count));
  136. /* slots_num must be power-of-two size, otherwise
  137. * get_cmd_index is broken. */
  138. BUG_ON(!is_power_of_2(slots_num));
  139. q->low_mark = q->n_window / 4;
  140. if (q->low_mark < 4)
  141. q->low_mark = 4;
  142. q->high_mark = q->n_window / 8;
  143. if (q->high_mark < 2)
  144. q->high_mark = 2;
  145. q->write_ptr = q->read_ptr = 0;
  146. return 0;
  147. }
  148. /**
  149. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  150. */
  151. static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
  152. struct iwl3945_tx_queue *txq, u32 id)
  153. {
  154. struct pci_dev *dev = priv->pci_dev;
  155. /* Driver private data, only for Tx (not command) queues,
  156. * not shared with device. */
  157. if (id != IWL_CMD_QUEUE_NUM) {
  158. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  159. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  160. if (!txq->txb) {
  161. IWL_ERROR("kmalloc for auxiliary BD "
  162. "structures failed\n");
  163. goto error;
  164. }
  165. } else
  166. txq->txb = NULL;
  167. /* Circular buffer of transmit frame descriptors (TFDs),
  168. * shared with device */
  169. txq->bd = pci_alloc_consistent(dev,
  170. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  171. &txq->q.dma_addr);
  172. if (!txq->bd) {
  173. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  174. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  175. goto error;
  176. }
  177. txq->q.id = id;
  178. return 0;
  179. error:
  180. kfree(txq->txb);
  181. txq->txb = NULL;
  182. return -ENOMEM;
  183. }
  184. /**
  185. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  186. */
  187. int iwl3945_tx_queue_init(struct iwl_priv *priv,
  188. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  189. {
  190. struct pci_dev *dev = priv->pci_dev;
  191. int len;
  192. int rc = 0;
  193. /*
  194. * Alloc buffer array for commands (Tx or other types of commands).
  195. * For the command queue (#4), allocate command space + one big
  196. * command for scan, since scan command is very huge; the system will
  197. * not have two scans at the same time, so only one is needed.
  198. * For data Tx queues (all other queues), no super-size command
  199. * space is needed.
  200. */
  201. len = sizeof(struct iwl3945_cmd) * slots_num;
  202. if (txq_id == IWL_CMD_QUEUE_NUM)
  203. len += IWL_MAX_SCAN_SIZE;
  204. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  205. if (!txq->cmd)
  206. return -ENOMEM;
  207. /* Alloc driver data array and TFD circular buffer */
  208. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  209. if (rc) {
  210. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  211. return -ENOMEM;
  212. }
  213. txq->need_update = 0;
  214. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  215. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  216. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  217. /* Initialize queue high/low-water, head/tail indexes */
  218. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  219. /* Tell device where to find queue, enable DMA channel. */
  220. iwl3945_hw_tx_queue_init(priv, txq);
  221. return 0;
  222. }
  223. /**
  224. * iwl3945_tx_queue_free - Deallocate DMA queue.
  225. * @txq: Transmit queue to deallocate.
  226. *
  227. * Empty queue by removing and destroying all BD's.
  228. * Free all buffers.
  229. * 0-fill, but do not free "txq" descriptor structure.
  230. */
  231. void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
  232. {
  233. struct iwl_queue *q = &txq->q;
  234. struct pci_dev *dev = priv->pci_dev;
  235. int len;
  236. if (q->n_bd == 0)
  237. return;
  238. /* first, empty all BD's */
  239. for (; q->write_ptr != q->read_ptr;
  240. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  241. iwl3945_hw_txq_free_tfd(priv, txq);
  242. len = sizeof(struct iwl3945_cmd) * q->n_window;
  243. if (q->id == IWL_CMD_QUEUE_NUM)
  244. len += IWL_MAX_SCAN_SIZE;
  245. /* De-alloc array of command/tx buffers */
  246. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  247. /* De-alloc circular buffer of TFDs */
  248. if (txq->q.n_bd)
  249. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  250. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  251. /* De-alloc array of per-TFD driver data */
  252. kfree(txq->txb);
  253. txq->txb = NULL;
  254. /* 0-fill queue descriptor structure */
  255. memset(txq, 0, sizeof(*txq));
  256. }
  257. /*************** STATION TABLE MANAGEMENT ****
  258. * mac80211 should be examined to determine if sta_info is duplicating
  259. * the functionality provided here
  260. */
  261. /**************************************************************/
  262. #if 0 /* temporary disable till we add real remove station */
  263. /**
  264. * iwl3945_remove_station - Remove driver's knowledge of station.
  265. *
  266. * NOTE: This does not remove station from device's station table.
  267. */
  268. static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  269. {
  270. int index = IWL_INVALID_STATION;
  271. int i;
  272. unsigned long flags;
  273. spin_lock_irqsave(&priv->sta_lock, flags);
  274. if (is_ap)
  275. index = IWL_AP_ID;
  276. else if (is_broadcast_ether_addr(addr))
  277. index = priv->hw_params.bcast_sta_id;
  278. else
  279. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
  280. if (priv->stations_39[i].used &&
  281. !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  282. addr)) {
  283. index = i;
  284. break;
  285. }
  286. if (unlikely(index == IWL_INVALID_STATION))
  287. goto out;
  288. if (priv->stations_39[index].used) {
  289. priv->stations_39[index].used = 0;
  290. priv->num_stations--;
  291. }
  292. BUG_ON(priv->num_stations < 0);
  293. out:
  294. spin_unlock_irqrestore(&priv->sta_lock, flags);
  295. return 0;
  296. }
  297. #endif
  298. /**
  299. * iwl3945_clear_stations_table - Clear the driver's station table
  300. *
  301. * NOTE: This does not clear or otherwise alter the device's station table.
  302. */
  303. static void iwl3945_clear_stations_table(struct iwl_priv *priv)
  304. {
  305. unsigned long flags;
  306. spin_lock_irqsave(&priv->sta_lock, flags);
  307. priv->num_stations = 0;
  308. memset(priv->stations_39, 0, sizeof(priv->stations_39));
  309. spin_unlock_irqrestore(&priv->sta_lock, flags);
  310. }
  311. /**
  312. * iwl3945_add_station - Add station to station tables in driver and device
  313. */
  314. u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
  315. {
  316. int i;
  317. int index = IWL_INVALID_STATION;
  318. struct iwl3945_station_entry *station;
  319. unsigned long flags_spin;
  320. u8 rate;
  321. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  322. if (is_ap)
  323. index = IWL_AP_ID;
  324. else if (is_broadcast_ether_addr(addr))
  325. index = priv->hw_params.bcast_sta_id;
  326. else
  327. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
  328. if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  329. addr)) {
  330. index = i;
  331. break;
  332. }
  333. if (!priv->stations_39[i].used &&
  334. index == IWL_INVALID_STATION)
  335. index = i;
  336. }
  337. /* These two conditions has the same outcome but keep them separate
  338. since they have different meaning */
  339. if (unlikely(index == IWL_INVALID_STATION)) {
  340. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  341. return index;
  342. }
  343. if (priv->stations_39[index].used &&
  344. !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
  345. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  346. return index;
  347. }
  348. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  349. station = &priv->stations_39[index];
  350. station->used = 1;
  351. priv->num_stations++;
  352. /* Set up the REPLY_ADD_STA command to send to device */
  353. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  354. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  355. station->sta.mode = 0;
  356. station->sta.sta.sta_id = index;
  357. station->sta.station_flags = 0;
  358. if (priv->band == IEEE80211_BAND_5GHZ)
  359. rate = IWL_RATE_6M_PLCP;
  360. else
  361. rate = IWL_RATE_1M_PLCP;
  362. /* Turn on both antennas for the station... */
  363. station->sta.rate_n_flags =
  364. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  365. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  366. /* Add station to device's station table */
  367. iwl3945_send_add_station(priv, &station->sta, flags);
  368. return index;
  369. }
  370. /*************** DRIVER STATUS FUNCTIONS *****/
  371. static inline int iwl3945_is_ready(struct iwl_priv *priv)
  372. {
  373. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  374. * set but EXIT_PENDING is not */
  375. return test_bit(STATUS_READY, &priv->status) &&
  376. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  377. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  378. }
  379. static inline int iwl3945_is_alive(struct iwl_priv *priv)
  380. {
  381. return test_bit(STATUS_ALIVE, &priv->status);
  382. }
  383. static inline int iwl3945_is_init(struct iwl_priv *priv)
  384. {
  385. return test_bit(STATUS_INIT, &priv->status);
  386. }
  387. static inline int iwl3945_is_rfkill_sw(struct iwl_priv *priv)
  388. {
  389. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  390. }
  391. static inline int iwl3945_is_rfkill_hw(struct iwl_priv *priv)
  392. {
  393. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  394. }
  395. static inline int iwl3945_is_rfkill(struct iwl_priv *priv)
  396. {
  397. return iwl3945_is_rfkill_hw(priv) ||
  398. iwl3945_is_rfkill_sw(priv);
  399. }
  400. static inline int iwl3945_is_ready_rf(struct iwl_priv *priv)
  401. {
  402. if (iwl3945_is_rfkill(priv))
  403. return 0;
  404. return iwl3945_is_ready(priv);
  405. }
  406. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  407. #define IWL_CMD(x) case x: return #x
  408. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  409. /**
  410. * iwl3945_enqueue_hcmd - enqueue a uCode command
  411. * @priv: device private data point
  412. * @cmd: a point to the ucode command structure
  413. *
  414. * The function returns < 0 values to indicate the operation is
  415. * failed. On success, it turns the index (> 0) of command in the
  416. * command queue.
  417. */
  418. static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl3945_host_cmd *cmd)
  419. {
  420. struct iwl3945_tx_queue *txq = &priv->txq39[IWL_CMD_QUEUE_NUM];
  421. struct iwl_queue *q = &txq->q;
  422. struct iwl3945_tfd_frame *tfd;
  423. u32 *control_flags;
  424. struct iwl3945_cmd *out_cmd;
  425. u32 idx;
  426. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  427. dma_addr_t phys_addr;
  428. int pad;
  429. u16 count;
  430. int ret;
  431. unsigned long flags;
  432. /* If any of the command structures end up being larger than
  433. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  434. * we will need to increase the size of the TFD entries */
  435. BUG_ON((fix_size > TFD39_MAX_PAYLOAD_SIZE) &&
  436. !(cmd->meta.flags & CMD_SIZE_HUGE));
  437. if (iwl3945_is_rfkill(priv)) {
  438. IWL_DEBUG_INFO("Not sending command - RF KILL");
  439. return -EIO;
  440. }
  441. if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  442. IWL_ERROR("No space for Tx\n");
  443. return -ENOSPC;
  444. }
  445. spin_lock_irqsave(&priv->hcmd_lock, flags);
  446. tfd = &txq->bd[q->write_ptr];
  447. memset(tfd, 0, sizeof(*tfd));
  448. control_flags = (u32 *) tfd;
  449. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  450. out_cmd = &txq->cmd[idx];
  451. out_cmd->hdr.cmd = cmd->id;
  452. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  453. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  454. /* At this point, the out_cmd now has all of the incoming cmd
  455. * information */
  456. out_cmd->hdr.flags = 0;
  457. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  458. INDEX_TO_SEQ(q->write_ptr));
  459. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  460. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  461. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  462. offsetof(struct iwl3945_cmd, hdr);
  463. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  464. pad = U32_PAD(cmd->len);
  465. count = TFD_CTL_COUNT_GET(*control_flags);
  466. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  467. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  468. "%d bytes at %d[%d]:%d\n",
  469. get_cmd_string(out_cmd->hdr.cmd),
  470. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  471. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  472. txq->need_update = 1;
  473. /* Increment and update queue's write index */
  474. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  475. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  476. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  477. return ret ? ret : idx;
  478. }
  479. static int iwl3945_send_cmd_async(struct iwl_priv *priv, struct iwl3945_host_cmd *cmd)
  480. {
  481. int ret;
  482. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  483. /* An asynchronous command can not expect an SKB to be set. */
  484. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  485. /* An asynchronous command MUST have a callback. */
  486. BUG_ON(!cmd->meta.u.callback);
  487. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  488. return -EBUSY;
  489. ret = iwl3945_enqueue_hcmd(priv, cmd);
  490. if (ret < 0) {
  491. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  492. get_cmd_string(cmd->id), ret);
  493. return ret;
  494. }
  495. return 0;
  496. }
  497. static int iwl3945_send_cmd_sync(struct iwl_priv *priv, struct iwl3945_host_cmd *cmd)
  498. {
  499. int cmd_idx;
  500. int ret;
  501. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  502. /* A synchronous command can not have a callback set. */
  503. BUG_ON(cmd->meta.u.callback != NULL);
  504. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  505. IWL_ERROR("Error sending %s: Already sending a host command\n",
  506. get_cmd_string(cmd->id));
  507. ret = -EBUSY;
  508. goto out;
  509. }
  510. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  511. if (cmd->meta.flags & CMD_WANT_SKB)
  512. cmd->meta.source = &cmd->meta;
  513. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  514. if (cmd_idx < 0) {
  515. ret = cmd_idx;
  516. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  517. get_cmd_string(cmd->id), ret);
  518. goto out;
  519. }
  520. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  521. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  522. HOST_COMPLETE_TIMEOUT);
  523. if (!ret) {
  524. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  525. IWL_ERROR("Error sending %s: time out after %dms.\n",
  526. get_cmd_string(cmd->id),
  527. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  528. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  529. ret = -ETIMEDOUT;
  530. goto cancel;
  531. }
  532. }
  533. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  534. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  535. get_cmd_string(cmd->id));
  536. ret = -ECANCELED;
  537. goto fail;
  538. }
  539. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  540. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  541. get_cmd_string(cmd->id));
  542. ret = -EIO;
  543. goto fail;
  544. }
  545. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  546. IWL_ERROR("Error: Response NULL in '%s'\n",
  547. get_cmd_string(cmd->id));
  548. ret = -EIO;
  549. goto cancel;
  550. }
  551. ret = 0;
  552. goto out;
  553. cancel:
  554. if (cmd->meta.flags & CMD_WANT_SKB) {
  555. struct iwl3945_cmd *qcmd;
  556. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  557. * TX cmd queue. Otherwise in case the cmd comes
  558. * in later, it will possibly set an invalid
  559. * address (cmd->meta.source). */
  560. qcmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  561. qcmd->meta.flags &= ~CMD_WANT_SKB;
  562. }
  563. fail:
  564. if (cmd->meta.u.skb) {
  565. dev_kfree_skb_any(cmd->meta.u.skb);
  566. cmd->meta.u.skb = NULL;
  567. }
  568. out:
  569. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  570. return ret;
  571. }
  572. int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl3945_host_cmd *cmd)
  573. {
  574. if (cmd->meta.flags & CMD_ASYNC)
  575. return iwl3945_send_cmd_async(priv, cmd);
  576. return iwl3945_send_cmd_sync(priv, cmd);
  577. }
  578. int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
  579. {
  580. struct iwl3945_host_cmd cmd = {
  581. .id = id,
  582. .len = len,
  583. .data = data,
  584. };
  585. return iwl3945_send_cmd_sync(priv, &cmd);
  586. }
  587. static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
  588. {
  589. struct iwl3945_host_cmd cmd = {
  590. .id = id,
  591. .len = sizeof(val),
  592. .data = &val,
  593. };
  594. return iwl3945_send_cmd_sync(priv, &cmd);
  595. }
  596. int iwl3945_send_statistics_request(struct iwl_priv *priv)
  597. {
  598. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  599. }
  600. /**
  601. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  602. * @band: 2.4 or 5 GHz band
  603. * @channel: Any channel valid for the requested band
  604. * In addition to setting the staging RXON, priv->band is also set.
  605. *
  606. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  607. * in the staging RXON flag structure based on the band
  608. */
  609. static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
  610. enum ieee80211_band band,
  611. u16 channel)
  612. {
  613. if (!iwl3945_get_channel_info(priv, band, channel)) {
  614. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  615. channel, band);
  616. return -EINVAL;
  617. }
  618. if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
  619. (priv->band == band))
  620. return 0;
  621. priv->staging39_rxon.channel = cpu_to_le16(channel);
  622. if (band == IEEE80211_BAND_5GHZ)
  623. priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  624. else
  625. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  626. priv->band = band;
  627. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  628. return 0;
  629. }
  630. /**
  631. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  632. *
  633. * NOTE: This is really only useful during development and can eventually
  634. * be #ifdef'd out once the driver is stable and folks aren't actively
  635. * making changes
  636. */
  637. static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
  638. {
  639. int error = 0;
  640. int counter = 1;
  641. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  642. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  643. error |= le32_to_cpu(rxon->flags &
  644. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  645. RXON_FLG_RADAR_DETECT_MSK));
  646. if (error)
  647. IWL_WARNING("check 24G fields %d | %d\n",
  648. counter++, error);
  649. } else {
  650. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  651. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  652. if (error)
  653. IWL_WARNING("check 52 fields %d | %d\n",
  654. counter++, error);
  655. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  656. if (error)
  657. IWL_WARNING("check 52 CCK %d | %d\n",
  658. counter++, error);
  659. }
  660. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  661. if (error)
  662. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  663. /* make sure basic rates 6Mbps and 1Mbps are supported */
  664. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  665. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  666. if (error)
  667. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  668. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  669. if (error)
  670. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  671. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  672. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  673. if (error)
  674. IWL_WARNING("check CCK and short slot %d | %d\n",
  675. counter++, error);
  676. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  677. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  678. if (error)
  679. IWL_WARNING("check CCK & auto detect %d | %d\n",
  680. counter++, error);
  681. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  682. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  683. if (error)
  684. IWL_WARNING("check TGG and auto detect %d | %d\n",
  685. counter++, error);
  686. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  687. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  688. RXON_FLG_ANT_A_MSK)) == 0);
  689. if (error)
  690. IWL_WARNING("check antenna %d %d\n", counter++, error);
  691. if (error)
  692. IWL_WARNING("Tuning to channel %d\n",
  693. le16_to_cpu(rxon->channel));
  694. if (error) {
  695. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  696. return -1;
  697. }
  698. return 0;
  699. }
  700. /**
  701. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  702. * @priv: staging_rxon is compared to active_rxon
  703. *
  704. * If the RXON structure is changing enough to require a new tune,
  705. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  706. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  707. */
  708. static int iwl3945_full_rxon_required(struct iwl_priv *priv)
  709. {
  710. /* These items are only settable from the full RXON command */
  711. if (!(iwl3945_is_associated(priv)) ||
  712. compare_ether_addr(priv->staging39_rxon.bssid_addr,
  713. priv->active39_rxon.bssid_addr) ||
  714. compare_ether_addr(priv->staging39_rxon.node_addr,
  715. priv->active39_rxon.node_addr) ||
  716. compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
  717. priv->active39_rxon.wlap_bssid_addr) ||
  718. (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
  719. (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
  720. (priv->staging39_rxon.air_propagation !=
  721. priv->active39_rxon.air_propagation) ||
  722. (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
  723. return 1;
  724. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  725. * be updated with the RXON_ASSOC command -- however only some
  726. * flag transitions are allowed using RXON_ASSOC */
  727. /* Check if we are not switching bands */
  728. if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  729. (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
  730. return 1;
  731. /* Check if we are switching association toggle */
  732. if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  733. (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  734. return 1;
  735. return 0;
  736. }
  737. static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
  738. {
  739. int rc = 0;
  740. struct iwl_rx_packet *res = NULL;
  741. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  742. struct iwl3945_host_cmd cmd = {
  743. .id = REPLY_RXON_ASSOC,
  744. .len = sizeof(rxon_assoc),
  745. .meta.flags = CMD_WANT_SKB,
  746. .data = &rxon_assoc,
  747. };
  748. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
  749. const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
  750. if ((rxon1->flags == rxon2->flags) &&
  751. (rxon1->filter_flags == rxon2->filter_flags) &&
  752. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  753. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  754. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  755. return 0;
  756. }
  757. rxon_assoc.flags = priv->staging39_rxon.flags;
  758. rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
  759. rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
  760. rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
  761. rxon_assoc.reserved = 0;
  762. rc = iwl3945_send_cmd_sync(priv, &cmd);
  763. if (rc)
  764. return rc;
  765. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  766. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  767. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  768. rc = -EIO;
  769. }
  770. priv->alloc_rxb_skb--;
  771. dev_kfree_skb_any(cmd.meta.u.skb);
  772. return rc;
  773. }
  774. /**
  775. * iwl3945_commit_rxon - commit staging_rxon to hardware
  776. *
  777. * The RXON command in staging_rxon is committed to the hardware and
  778. * the active_rxon structure is updated with the new data. This
  779. * function correctly transitions out of the RXON_ASSOC_MSK state if
  780. * a HW tune is required based on the RXON structure changes.
  781. */
  782. static int iwl3945_commit_rxon(struct iwl_priv *priv)
  783. {
  784. /* cast away the const for active_rxon in this function */
  785. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
  786. int rc = 0;
  787. if (!iwl3945_is_alive(priv))
  788. return -1;
  789. /* always get timestamp with Rx frame */
  790. priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  791. /* select antenna */
  792. priv->staging39_rxon.flags &=
  793. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  794. priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
  795. rc = iwl3945_check_rxon_cmd(priv);
  796. if (rc) {
  797. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  798. return -EINVAL;
  799. }
  800. /* If we don't need to send a full RXON, we can use
  801. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  802. * and other flags for the current radio configuration. */
  803. if (!iwl3945_full_rxon_required(priv)) {
  804. rc = iwl3945_send_rxon_assoc(priv);
  805. if (rc) {
  806. IWL_ERROR("Error setting RXON_ASSOC "
  807. "configuration (%d).\n", rc);
  808. return rc;
  809. }
  810. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  811. return 0;
  812. }
  813. /* If we are currently associated and the new config requires
  814. * an RXON_ASSOC and the new config wants the associated mask enabled,
  815. * we must clear the associated from the active configuration
  816. * before we apply the new config */
  817. if (iwl3945_is_associated(priv) &&
  818. (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  819. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  820. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  821. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  822. sizeof(struct iwl3945_rxon_cmd),
  823. &priv->active39_rxon);
  824. /* If the mask clearing failed then we set
  825. * active_rxon back to what it was previously */
  826. if (rc) {
  827. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  828. IWL_ERROR("Error clearing ASSOC_MSK on current "
  829. "configuration (%d).\n", rc);
  830. return rc;
  831. }
  832. }
  833. IWL_DEBUG_INFO("Sending RXON\n"
  834. "* with%s RXON_FILTER_ASSOC_MSK\n"
  835. "* channel = %d\n"
  836. "* bssid = %pM\n",
  837. ((priv->staging39_rxon.filter_flags &
  838. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  839. le16_to_cpu(priv->staging39_rxon.channel),
  840. priv->staging_rxon.bssid_addr);
  841. /* Apply the new configuration */
  842. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  843. sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
  844. if (rc) {
  845. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  846. return rc;
  847. }
  848. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  849. iwl3945_clear_stations_table(priv);
  850. /* If we issue a new RXON command which required a tune then we must
  851. * send a new TXPOWER command or we won't be able to Tx any frames */
  852. rc = iwl3945_hw_reg_send_txpower(priv);
  853. if (rc) {
  854. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  855. return rc;
  856. }
  857. /* Add the broadcast address so we can send broadcast frames */
  858. if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
  859. IWL_INVALID_STATION) {
  860. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  861. return -EIO;
  862. }
  863. /* If we have set the ASSOC_MSK and we are in BSS mode then
  864. * add the IWL_AP_ID to the station rate table */
  865. if (iwl3945_is_associated(priv) &&
  866. (priv->iw_mode == NL80211_IFTYPE_STATION))
  867. if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
  868. == IWL_INVALID_STATION) {
  869. IWL_ERROR("Error adding AP address for transmit.\n");
  870. return -EIO;
  871. }
  872. /* Init the hardware's rate fallback order based on the band */
  873. rc = iwl3945_init_hw_rate_table(priv);
  874. if (rc) {
  875. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  876. return -EIO;
  877. }
  878. return 0;
  879. }
  880. static int iwl3945_send_bt_config(struct iwl_priv *priv)
  881. {
  882. struct iwl_bt_cmd bt_cmd = {
  883. .flags = 3,
  884. .lead_time = 0xAA,
  885. .max_kill = 1,
  886. .kill_ack_mask = 0,
  887. .kill_cts_mask = 0,
  888. };
  889. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  890. sizeof(bt_cmd), &bt_cmd);
  891. }
  892. static int iwl3945_send_scan_abort(struct iwl_priv *priv)
  893. {
  894. int rc = 0;
  895. struct iwl_rx_packet *res;
  896. struct iwl3945_host_cmd cmd = {
  897. .id = REPLY_SCAN_ABORT_CMD,
  898. .meta.flags = CMD_WANT_SKB,
  899. };
  900. /* If there isn't a scan actively going on in the hardware
  901. * then we are in between scan bands and not actually
  902. * actively scanning, so don't send the abort command */
  903. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  904. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  905. return 0;
  906. }
  907. rc = iwl3945_send_cmd_sync(priv, &cmd);
  908. if (rc) {
  909. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  910. return rc;
  911. }
  912. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  913. if (res->u.status != CAN_ABORT_STATUS) {
  914. /* The scan abort will return 1 for success or
  915. * 2 for "failure". A failure condition can be
  916. * due to simply not being in an active scan which
  917. * can occur if we send the scan abort before we
  918. * the microcode has notified us that a scan is
  919. * completed. */
  920. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  921. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  922. clear_bit(STATUS_SCAN_HW, &priv->status);
  923. }
  924. dev_kfree_skb_any(cmd.meta.u.skb);
  925. return rc;
  926. }
  927. static int iwl3945_card_state_sync_callback(struct iwl_priv *priv,
  928. struct iwl3945_cmd *cmd,
  929. struct sk_buff *skb)
  930. {
  931. return 1;
  932. }
  933. /*
  934. * CARD_STATE_CMD
  935. *
  936. * Use: Sets the device's internal card state to enable, disable, or halt
  937. *
  938. * When in the 'enable' state the card operates as normal.
  939. * When in the 'disable' state, the card enters into a low power mode.
  940. * When in the 'halt' state, the card is shut down and must be fully
  941. * restarted to come back on.
  942. */
  943. static int iwl3945_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  944. {
  945. struct iwl3945_host_cmd cmd = {
  946. .id = REPLY_CARD_STATE_CMD,
  947. .len = sizeof(u32),
  948. .data = &flags,
  949. .meta.flags = meta_flag,
  950. };
  951. if (meta_flag & CMD_ASYNC)
  952. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  953. return iwl3945_send_cmd(priv, &cmd);
  954. }
  955. static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
  956. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  957. {
  958. struct iwl_rx_packet *res = NULL;
  959. if (!skb) {
  960. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  961. return 1;
  962. }
  963. res = (struct iwl_rx_packet *)skb->data;
  964. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  965. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  966. res->hdr.flags);
  967. return 1;
  968. }
  969. switch (res->u.add_sta.status) {
  970. case ADD_STA_SUCCESS_MSK:
  971. break;
  972. default:
  973. break;
  974. }
  975. /* We didn't cache the SKB; let the caller free it */
  976. return 1;
  977. }
  978. int iwl3945_send_add_station(struct iwl_priv *priv,
  979. struct iwl3945_addsta_cmd *sta, u8 flags)
  980. {
  981. struct iwl_rx_packet *res = NULL;
  982. int rc = 0;
  983. struct iwl3945_host_cmd cmd = {
  984. .id = REPLY_ADD_STA,
  985. .len = sizeof(struct iwl3945_addsta_cmd),
  986. .meta.flags = flags,
  987. .data = sta,
  988. };
  989. if (flags & CMD_ASYNC)
  990. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  991. else
  992. cmd.meta.flags |= CMD_WANT_SKB;
  993. rc = iwl3945_send_cmd(priv, &cmd);
  994. if (rc || (flags & CMD_ASYNC))
  995. return rc;
  996. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  997. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  998. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  999. res->hdr.flags);
  1000. rc = -EIO;
  1001. }
  1002. if (rc == 0) {
  1003. switch (res->u.add_sta.status) {
  1004. case ADD_STA_SUCCESS_MSK:
  1005. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1006. break;
  1007. default:
  1008. rc = -EIO;
  1009. IWL_WARNING("REPLY_ADD_STA failed\n");
  1010. break;
  1011. }
  1012. }
  1013. priv->alloc_rxb_skb--;
  1014. dev_kfree_skb_any(cmd.meta.u.skb);
  1015. return rc;
  1016. }
  1017. static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
  1018. struct ieee80211_key_conf *keyconf,
  1019. u8 sta_id)
  1020. {
  1021. unsigned long flags;
  1022. __le16 key_flags = 0;
  1023. switch (keyconf->alg) {
  1024. case ALG_CCMP:
  1025. key_flags |= STA_KEY_FLG_CCMP;
  1026. key_flags |= cpu_to_le16(
  1027. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1028. key_flags &= ~STA_KEY_FLG_INVALID;
  1029. break;
  1030. case ALG_TKIP:
  1031. case ALG_WEP:
  1032. default:
  1033. return -EINVAL;
  1034. }
  1035. spin_lock_irqsave(&priv->sta_lock, flags);
  1036. priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
  1037. priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
  1038. memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
  1039. keyconf->keylen);
  1040. memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
  1041. keyconf->keylen);
  1042. priv->stations_39[sta_id].sta.key.key_flags = key_flags;
  1043. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1044. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1045. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1046. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1047. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1048. return 0;
  1049. }
  1050. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  1051. {
  1052. unsigned long flags;
  1053. spin_lock_irqsave(&priv->sta_lock, flags);
  1054. memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1055. memset(&priv->stations_39[sta_id].sta.key, 0,
  1056. sizeof(struct iwl4965_keyinfo));
  1057. priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1058. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1059. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1060. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1061. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1062. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1063. return 0;
  1064. }
  1065. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  1066. {
  1067. struct list_head *element;
  1068. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1069. priv->frames_count);
  1070. while (!list_empty(&priv->free_frames)) {
  1071. element = priv->free_frames.next;
  1072. list_del(element);
  1073. kfree(list_entry(element, struct iwl3945_frame, list));
  1074. priv->frames_count--;
  1075. }
  1076. if (priv->frames_count) {
  1077. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1078. priv->frames_count);
  1079. priv->frames_count = 0;
  1080. }
  1081. }
  1082. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  1083. {
  1084. struct iwl3945_frame *frame;
  1085. struct list_head *element;
  1086. if (list_empty(&priv->free_frames)) {
  1087. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1088. if (!frame) {
  1089. IWL_ERROR("Could not allocate frame!\n");
  1090. return NULL;
  1091. }
  1092. priv->frames_count++;
  1093. return frame;
  1094. }
  1095. element = priv->free_frames.next;
  1096. list_del(element);
  1097. return list_entry(element, struct iwl3945_frame, list);
  1098. }
  1099. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  1100. {
  1101. memset(frame, 0, sizeof(*frame));
  1102. list_add(&frame->list, &priv->free_frames);
  1103. }
  1104. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  1105. struct ieee80211_hdr *hdr,
  1106. int left)
  1107. {
  1108. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1109. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1110. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1111. return 0;
  1112. if (priv->ibss_beacon->len > left)
  1113. return 0;
  1114. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1115. return priv->ibss_beacon->len;
  1116. }
  1117. static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
  1118. {
  1119. u8 i;
  1120. int rate_mask;
  1121. /* Set rate mask*/
  1122. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1123. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1124. else
  1125. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1126. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1127. i = iwl3945_rates[i].next_ieee) {
  1128. if (rate_mask & (1 << i))
  1129. return iwl3945_rates[i].plcp;
  1130. }
  1131. /* No valid rate was found. Assign the lowest one */
  1132. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1133. return IWL_RATE_1M_PLCP;
  1134. else
  1135. return IWL_RATE_6M_PLCP;
  1136. }
  1137. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  1138. {
  1139. struct iwl3945_frame *frame;
  1140. unsigned int frame_size;
  1141. int rc;
  1142. u8 rate;
  1143. frame = iwl3945_get_free_frame(priv);
  1144. if (!frame) {
  1145. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1146. "command.\n");
  1147. return -ENOMEM;
  1148. }
  1149. rate = iwl3945_rate_get_lowest_plcp(priv);
  1150. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1151. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1152. &frame->u.cmd[0]);
  1153. iwl3945_free_frame(priv, frame);
  1154. return rc;
  1155. }
  1156. /******************************************************************************
  1157. *
  1158. * EEPROM related functions
  1159. *
  1160. ******************************************************************************/
  1161. static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
  1162. {
  1163. memcpy(mac, priv->eeprom39.mac_address, 6);
  1164. }
  1165. /*
  1166. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1167. * embedded controller) as EEPROM reader; each read is a series of pulses
  1168. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1169. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1170. * simply claims ownership, which should be safe when this function is called
  1171. * (i.e. before loading uCode!).
  1172. */
  1173. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
  1174. {
  1175. _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1176. return 0;
  1177. }
  1178. /**
  1179. * iwl3945_eeprom_init - read EEPROM contents
  1180. *
  1181. * Load the EEPROM contents from adapter into priv->eeprom39
  1182. *
  1183. * NOTE: This routine uses the non-debug IO access functions.
  1184. */
  1185. int iwl3945_eeprom_init(struct iwl_priv *priv)
  1186. {
  1187. u16 *e = (u16 *)&priv->eeprom39;
  1188. u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
  1189. int sz = sizeof(priv->eeprom39);
  1190. int ret;
  1191. u16 addr;
  1192. /* The EEPROM structure has several padding buffers within it
  1193. * and when adding new EEPROM maps is subject to programmer errors
  1194. * which may be very difficult to identify without explicitly
  1195. * checking the resulting size of the eeprom map. */
  1196. BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
  1197. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1198. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1199. return -ENOENT;
  1200. }
  1201. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1202. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1203. if (ret < 0) {
  1204. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1205. return -ENOENT;
  1206. }
  1207. /* eeprom is an array of 16bit values */
  1208. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1209. u32 r;
  1210. _iwl_write32(priv, CSR_EEPROM_REG,
  1211. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1212. _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1213. ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
  1214. CSR_EEPROM_REG_READ_VALID_MSK,
  1215. IWL_EEPROM_ACCESS_TIMEOUT);
  1216. if (ret < 0) {
  1217. IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
  1218. return ret;
  1219. }
  1220. r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
  1221. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1222. }
  1223. return 0;
  1224. }
  1225. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  1226. {
  1227. if (priv->shared_virt)
  1228. pci_free_consistent(priv->pci_dev,
  1229. sizeof(struct iwl3945_shared),
  1230. priv->shared_virt,
  1231. priv->shared_phys);
  1232. }
  1233. /**
  1234. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1235. *
  1236. * return : set the bit for each supported rate insert in ie
  1237. */
  1238. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1239. u16 basic_rate, int *left)
  1240. {
  1241. u16 ret_rates = 0, bit;
  1242. int i;
  1243. u8 *cnt = ie;
  1244. u8 *rates = ie + 1;
  1245. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1246. if (bit & supported_rate) {
  1247. ret_rates |= bit;
  1248. rates[*cnt] = iwl3945_rates[i].ieee |
  1249. ((bit & basic_rate) ? 0x80 : 0x00);
  1250. (*cnt)++;
  1251. (*left)--;
  1252. if ((*left <= 0) ||
  1253. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1254. break;
  1255. }
  1256. }
  1257. return ret_rates;
  1258. }
  1259. /**
  1260. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1261. */
  1262. static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
  1263. struct ieee80211_mgmt *frame,
  1264. int left)
  1265. {
  1266. int len = 0;
  1267. u8 *pos = NULL;
  1268. u16 active_rates, ret_rates, cck_rates;
  1269. /* Make sure there is enough space for the probe request,
  1270. * two mandatory IEs and the data */
  1271. left -= 24;
  1272. if (left < 0)
  1273. return 0;
  1274. len += 24;
  1275. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1276. memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
  1277. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1278. memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
  1279. frame->seq_ctrl = 0;
  1280. /* fill in our indirect SSID IE */
  1281. /* ...next IE... */
  1282. left -= 2;
  1283. if (left < 0)
  1284. return 0;
  1285. len += 2;
  1286. pos = &(frame->u.probe_req.variable[0]);
  1287. *pos++ = WLAN_EID_SSID;
  1288. *pos++ = 0;
  1289. /* fill in supported rate */
  1290. /* ...next IE... */
  1291. left -= 2;
  1292. if (left < 0)
  1293. return 0;
  1294. /* ... fill it in... */
  1295. *pos++ = WLAN_EID_SUPP_RATES;
  1296. *pos = 0;
  1297. priv->active_rate = priv->rates_mask;
  1298. active_rates = priv->active_rate;
  1299. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1300. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1301. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1302. priv->active_rate_basic, &left);
  1303. active_rates &= ~ret_rates;
  1304. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1305. priv->active_rate_basic, &left);
  1306. active_rates &= ~ret_rates;
  1307. len += 2 + *pos;
  1308. pos += (*pos) + 1;
  1309. if (active_rates == 0)
  1310. goto fill_end;
  1311. /* fill in supported extended rate */
  1312. /* ...next IE... */
  1313. left -= 2;
  1314. if (left < 0)
  1315. return 0;
  1316. /* ... fill it in... */
  1317. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1318. *pos = 0;
  1319. iwl3945_supported_rate_to_ie(pos, active_rates,
  1320. priv->active_rate_basic, &left);
  1321. if (*pos > 0)
  1322. len += 2 + *pos;
  1323. fill_end:
  1324. return (u16)len;
  1325. }
  1326. /*
  1327. * QoS support
  1328. */
  1329. static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
  1330. struct iwl_qosparam_cmd *qos)
  1331. {
  1332. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1333. sizeof(struct iwl_qosparam_cmd), qos);
  1334. }
  1335. static void iwl3945_reset_qos(struct iwl_priv *priv)
  1336. {
  1337. u16 cw_min = 15;
  1338. u16 cw_max = 1023;
  1339. u8 aifs = 2;
  1340. u8 is_legacy = 0;
  1341. unsigned long flags;
  1342. int i;
  1343. spin_lock_irqsave(&priv->lock, flags);
  1344. priv->qos_data.qos_active = 0;
  1345. /* QoS always active in AP and ADHOC mode
  1346. * In STA mode wait for association
  1347. */
  1348. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  1349. priv->iw_mode == NL80211_IFTYPE_AP)
  1350. priv->qos_data.qos_active = 1;
  1351. else
  1352. priv->qos_data.qos_active = 0;
  1353. /* check for legacy mode */
  1354. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  1355. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  1356. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  1357. (priv->staging39_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  1358. cw_min = 31;
  1359. is_legacy = 1;
  1360. }
  1361. if (priv->qos_data.qos_active)
  1362. aifs = 3;
  1363. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1364. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1365. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1366. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1367. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1368. if (priv->qos_data.qos_active) {
  1369. i = 1;
  1370. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1371. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1372. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1373. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1374. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1375. i = 2;
  1376. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1377. cpu_to_le16((cw_min + 1) / 2 - 1);
  1378. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1379. cpu_to_le16(cw_max);
  1380. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1381. if (is_legacy)
  1382. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1383. cpu_to_le16(6016);
  1384. else
  1385. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1386. cpu_to_le16(3008);
  1387. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1388. i = 3;
  1389. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1390. cpu_to_le16((cw_min + 1) / 4 - 1);
  1391. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1392. cpu_to_le16((cw_max + 1) / 2 - 1);
  1393. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1394. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1395. if (is_legacy)
  1396. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1397. cpu_to_le16(3264);
  1398. else
  1399. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1400. cpu_to_le16(1504);
  1401. } else {
  1402. for (i = 1; i < 4; i++) {
  1403. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1404. cpu_to_le16(cw_min);
  1405. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1406. cpu_to_le16(cw_max);
  1407. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1408. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1409. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1410. }
  1411. }
  1412. IWL_DEBUG_QOS("set QoS to default \n");
  1413. spin_unlock_irqrestore(&priv->lock, flags);
  1414. }
  1415. static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
  1416. {
  1417. unsigned long flags;
  1418. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1419. return;
  1420. spin_lock_irqsave(&priv->lock, flags);
  1421. priv->qos_data.def_qos_parm.qos_flags = 0;
  1422. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1423. !priv->qos_data.qos_cap.q_AP.txop_request)
  1424. priv->qos_data.def_qos_parm.qos_flags |=
  1425. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1426. if (priv->qos_data.qos_active)
  1427. priv->qos_data.def_qos_parm.qos_flags |=
  1428. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1429. spin_unlock_irqrestore(&priv->lock, flags);
  1430. if (force || iwl3945_is_associated(priv)) {
  1431. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1432. priv->qos_data.qos_active);
  1433. iwl3945_send_qos_params_command(priv,
  1434. &(priv->qos_data.def_qos_parm));
  1435. }
  1436. }
  1437. /*
  1438. * Power management (not Tx power!) functions
  1439. */
  1440. #define MSEC_TO_USEC 1024
  1441. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1442. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1443. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1444. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1445. __constant_cpu_to_le32(X1), \
  1446. __constant_cpu_to_le32(X2), \
  1447. __constant_cpu_to_le32(X3), \
  1448. __constant_cpu_to_le32(X4)}
  1449. /* default power management (not Tx power) table values */
  1450. /* for TIM 0-10 */
  1451. static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
  1452. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1453. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1454. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1455. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1456. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1457. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1458. };
  1459. /* for TIM > 10 */
  1460. static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
  1461. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1462. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1463. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1464. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1465. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1466. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1467. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1468. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1469. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1470. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1471. };
  1472. int iwl3945_power_init_handle(struct iwl_priv *priv)
  1473. {
  1474. int rc = 0, i;
  1475. struct iwl3945_power_mgr *pow_data;
  1476. int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
  1477. u16 pci_pm;
  1478. IWL_DEBUG_POWER("Initialize power \n");
  1479. pow_data = &(priv->power_data_39);
  1480. memset(pow_data, 0, sizeof(*pow_data));
  1481. pow_data->active_index = IWL_POWER_RANGE_0;
  1482. pow_data->dtim_val = 0xffff;
  1483. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1484. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1485. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1486. if (rc != 0)
  1487. return 0;
  1488. else {
  1489. struct iwl_powertable_cmd *cmd;
  1490. IWL_DEBUG_POWER("adjust power command flags\n");
  1491. for (i = 0; i < IWL39_POWER_AC; i++) {
  1492. cmd = &pow_data->pwr_range_0[i].cmd;
  1493. if (pci_pm & 0x1)
  1494. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1495. else
  1496. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1497. }
  1498. }
  1499. return rc;
  1500. }
  1501. static int iwl3945_update_power_cmd(struct iwl_priv *priv,
  1502. struct iwl_powertable_cmd *cmd, u32 mode)
  1503. {
  1504. int rc = 0, i;
  1505. u8 skip;
  1506. u32 max_sleep = 0;
  1507. struct iwl_power_vec_entry *range;
  1508. u8 period = 0;
  1509. struct iwl3945_power_mgr *pow_data;
  1510. if (mode > IWL_POWER_INDEX_5) {
  1511. IWL_DEBUG_POWER("Error invalid power mode \n");
  1512. return -1;
  1513. }
  1514. pow_data = &(priv->power_data_39);
  1515. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1516. range = &pow_data->pwr_range_0[0];
  1517. else
  1518. range = &pow_data->pwr_range_1[1];
  1519. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1520. #ifdef IWL_MAC80211_DISABLE
  1521. if (priv->assoc_network != NULL) {
  1522. unsigned long flags;
  1523. period = priv->assoc_network->tim.tim_period;
  1524. }
  1525. #endif /*IWL_MAC80211_DISABLE */
  1526. skip = range[mode].no_dtim;
  1527. if (period == 0) {
  1528. period = 1;
  1529. skip = 0;
  1530. }
  1531. if (skip == 0) {
  1532. max_sleep = period;
  1533. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1534. } else {
  1535. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1536. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1537. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1538. }
  1539. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1540. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1541. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1542. }
  1543. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1544. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1545. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1546. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1547. le32_to_cpu(cmd->sleep_interval[0]),
  1548. le32_to_cpu(cmd->sleep_interval[1]),
  1549. le32_to_cpu(cmd->sleep_interval[2]),
  1550. le32_to_cpu(cmd->sleep_interval[3]),
  1551. le32_to_cpu(cmd->sleep_interval[4]));
  1552. return rc;
  1553. }
  1554. static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
  1555. {
  1556. u32 uninitialized_var(final_mode);
  1557. int rc;
  1558. struct iwl_powertable_cmd cmd;
  1559. /* If on battery, set to 3,
  1560. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1561. * else user level */
  1562. switch (mode) {
  1563. case IWL39_POWER_BATTERY:
  1564. final_mode = IWL_POWER_INDEX_3;
  1565. break;
  1566. case IWL39_POWER_AC:
  1567. final_mode = IWL_POWER_MODE_CAM;
  1568. break;
  1569. default:
  1570. final_mode = mode;
  1571. break;
  1572. }
  1573. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1574. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1575. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1576. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1577. if (final_mode == IWL_POWER_MODE_CAM)
  1578. clear_bit(STATUS_POWER_PMI, &priv->status);
  1579. else
  1580. set_bit(STATUS_POWER_PMI, &priv->status);
  1581. return rc;
  1582. }
  1583. /**
  1584. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1585. *
  1586. * NOTE: priv->mutex is not required before calling this function
  1587. */
  1588. static int iwl3945_scan_cancel(struct iwl_priv *priv)
  1589. {
  1590. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1591. clear_bit(STATUS_SCANNING, &priv->status);
  1592. return 0;
  1593. }
  1594. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1595. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1596. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1597. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1598. queue_work(priv->workqueue, &priv->abort_scan);
  1599. } else
  1600. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1601. return test_bit(STATUS_SCANNING, &priv->status);
  1602. }
  1603. return 0;
  1604. }
  1605. /**
  1606. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1607. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1608. *
  1609. * NOTE: priv->mutex must be held before calling this function
  1610. */
  1611. static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
  1612. {
  1613. unsigned long now = jiffies;
  1614. int ret;
  1615. ret = iwl3945_scan_cancel(priv);
  1616. if (ret && ms) {
  1617. mutex_unlock(&priv->mutex);
  1618. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1619. test_bit(STATUS_SCANNING, &priv->status))
  1620. msleep(1);
  1621. mutex_lock(&priv->mutex);
  1622. return test_bit(STATUS_SCANNING, &priv->status);
  1623. }
  1624. return ret;
  1625. }
  1626. #define MAX_UCODE_BEACON_INTERVAL 1024
  1627. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1628. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1629. {
  1630. u16 new_val = 0;
  1631. u16 beacon_factor = 0;
  1632. beacon_factor =
  1633. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1634. / MAX_UCODE_BEACON_INTERVAL;
  1635. new_val = beacon_val / beacon_factor;
  1636. return cpu_to_le16(new_val);
  1637. }
  1638. static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
  1639. {
  1640. u64 interval_tm_unit;
  1641. u64 tsf, result;
  1642. unsigned long flags;
  1643. struct ieee80211_conf *conf = NULL;
  1644. u16 beacon_int = 0;
  1645. conf = ieee80211_get_hw_conf(priv->hw);
  1646. spin_lock_irqsave(&priv->lock, flags);
  1647. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1648. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1649. tsf = priv->timestamp;
  1650. beacon_int = priv->beacon_int;
  1651. spin_unlock_irqrestore(&priv->lock, flags);
  1652. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1653. if (beacon_int == 0) {
  1654. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1655. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1656. } else {
  1657. priv->rxon_timing.beacon_interval =
  1658. cpu_to_le16(beacon_int);
  1659. priv->rxon_timing.beacon_interval =
  1660. iwl3945_adjust_beacon_interval(
  1661. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1662. }
  1663. priv->rxon_timing.atim_window = 0;
  1664. } else {
  1665. priv->rxon_timing.beacon_interval =
  1666. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1667. /* TODO: we need to get atim_window from upper stack
  1668. * for now we set to 0 */
  1669. priv->rxon_timing.atim_window = 0;
  1670. }
  1671. interval_tm_unit =
  1672. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1673. result = do_div(tsf, interval_tm_unit);
  1674. priv->rxon_timing.beacon_init_val =
  1675. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1676. IWL_DEBUG_ASSOC
  1677. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1678. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1679. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1680. le16_to_cpu(priv->rxon_timing.atim_window));
  1681. }
  1682. static int iwl3945_scan_initiate(struct iwl_priv *priv)
  1683. {
  1684. if (!iwl3945_is_ready_rf(priv)) {
  1685. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1686. return -EIO;
  1687. }
  1688. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1689. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1690. return -EAGAIN;
  1691. }
  1692. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1693. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1694. "Queuing.\n");
  1695. return -EAGAIN;
  1696. }
  1697. IWL_DEBUG_INFO("Starting scan...\n");
  1698. if (priv->cfg->sku & IWL_SKU_G)
  1699. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1700. if (priv->cfg->sku & IWL_SKU_A)
  1701. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1702. set_bit(STATUS_SCANNING, &priv->status);
  1703. priv->scan_start = jiffies;
  1704. priv->scan_pass_start = priv->scan_start;
  1705. queue_work(priv->workqueue, &priv->request_scan);
  1706. return 0;
  1707. }
  1708. static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  1709. {
  1710. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  1711. if (hw_decrypt)
  1712. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1713. else
  1714. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1715. return 0;
  1716. }
  1717. static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
  1718. enum ieee80211_band band)
  1719. {
  1720. if (band == IEEE80211_BAND_5GHZ) {
  1721. priv->staging39_rxon.flags &=
  1722. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1723. | RXON_FLG_CCK_MSK);
  1724. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1725. } else {
  1726. /* Copied from iwl3945_bg_post_associate() */
  1727. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1728. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1729. else
  1730. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1731. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1732. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1733. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1734. priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1735. priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1736. }
  1737. }
  1738. /*
  1739. * initialize rxon structure with default values from eeprom
  1740. */
  1741. static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
  1742. int mode)
  1743. {
  1744. const struct iwl_channel_info *ch_info;
  1745. memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
  1746. switch (mode) {
  1747. case NL80211_IFTYPE_AP:
  1748. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
  1749. break;
  1750. case NL80211_IFTYPE_STATION:
  1751. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1752. priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1753. break;
  1754. case NL80211_IFTYPE_ADHOC:
  1755. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1756. priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1757. priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1758. RXON_FILTER_ACCEPT_GRP_MSK;
  1759. break;
  1760. case NL80211_IFTYPE_MONITOR:
  1761. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1762. priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1763. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1764. break;
  1765. default:
  1766. IWL_ERROR("Unsupported interface type %d\n", mode);
  1767. break;
  1768. }
  1769. #if 0
  1770. /* TODO: Figure out when short_preamble would be set and cache from
  1771. * that */
  1772. if (!hw_to_local(priv->hw)->short_preamble)
  1773. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1774. else
  1775. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1776. #endif
  1777. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1778. le16_to_cpu(priv->active39_rxon.channel));
  1779. if (!ch_info)
  1780. ch_info = &priv->channel_info[0];
  1781. /*
  1782. * in some case A channels are all non IBSS
  1783. * in this case force B/G channel
  1784. */
  1785. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1786. ch_info = &priv->channel_info[0];
  1787. priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
  1788. if (is_channel_a_band(ch_info))
  1789. priv->band = IEEE80211_BAND_5GHZ;
  1790. else
  1791. priv->band = IEEE80211_BAND_2GHZ;
  1792. iwl3945_set_flags_for_phymode(priv, priv->band);
  1793. priv->staging39_rxon.ofdm_basic_rates =
  1794. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1795. priv->staging39_rxon.cck_basic_rates =
  1796. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1797. }
  1798. static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
  1799. {
  1800. if (mode == NL80211_IFTYPE_ADHOC) {
  1801. const struct iwl_channel_info *ch_info;
  1802. ch_info = iwl3945_get_channel_info(priv,
  1803. priv->band,
  1804. le16_to_cpu(priv->staging39_rxon.channel));
  1805. if (!ch_info || !is_channel_ibss(ch_info)) {
  1806. IWL_ERROR("channel %d not IBSS channel\n",
  1807. le16_to_cpu(priv->staging39_rxon.channel));
  1808. return -EINVAL;
  1809. }
  1810. }
  1811. iwl3945_connection_init_rx_config(priv, mode);
  1812. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1813. iwl3945_clear_stations_table(priv);
  1814. /* don't commit rxon if rf-kill is on*/
  1815. if (!iwl3945_is_ready_rf(priv))
  1816. return -EAGAIN;
  1817. cancel_delayed_work(&priv->scan_check);
  1818. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1819. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1820. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1821. return -EAGAIN;
  1822. }
  1823. iwl3945_commit_rxon(priv);
  1824. return 0;
  1825. }
  1826. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  1827. struct ieee80211_tx_info *info,
  1828. struct iwl3945_cmd *cmd,
  1829. struct sk_buff *skb_frag,
  1830. int last_frag)
  1831. {
  1832. struct iwl3945_hw_key *keyinfo =
  1833. &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
  1834. switch (keyinfo->alg) {
  1835. case ALG_CCMP:
  1836. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1837. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1838. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1839. break;
  1840. case ALG_TKIP:
  1841. #if 0
  1842. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1843. if (last_frag)
  1844. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1845. 8);
  1846. else
  1847. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1848. #endif
  1849. break;
  1850. case ALG_WEP:
  1851. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1852. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1853. if (keyinfo->keylen == 13)
  1854. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1855. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1856. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1857. "with key %d\n", info->control.hw_key->hw_key_idx);
  1858. break;
  1859. default:
  1860. IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
  1861. break;
  1862. }
  1863. }
  1864. /*
  1865. * handle build REPLY_TX command notification.
  1866. */
  1867. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  1868. struct iwl3945_cmd *cmd,
  1869. struct ieee80211_tx_info *info,
  1870. struct ieee80211_hdr *hdr,
  1871. int is_unicast, u8 std_id)
  1872. {
  1873. __le16 fc = hdr->frame_control;
  1874. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1875. u8 rc_flags = info->control.rates[0].flags;
  1876. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1877. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1878. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1879. if (ieee80211_is_mgmt(fc))
  1880. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1881. if (ieee80211_is_probe_resp(fc) &&
  1882. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1883. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1884. } else {
  1885. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1886. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1887. }
  1888. cmd->cmd.tx.sta_id = std_id;
  1889. if (ieee80211_has_morefrags(fc))
  1890. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1891. if (ieee80211_is_data_qos(fc)) {
  1892. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1893. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  1894. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1895. } else {
  1896. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1897. }
  1898. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1899. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1900. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1901. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1902. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1903. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1904. }
  1905. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1906. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1907. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1908. if (ieee80211_is_mgmt(fc)) {
  1909. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1910. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  1911. else
  1912. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  1913. } else {
  1914. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  1915. #ifdef CONFIG_IWL3945_LEDS
  1916. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1917. #endif
  1918. }
  1919. cmd->cmd.tx.driver_txop = 0;
  1920. cmd->cmd.tx.tx_flags = tx_flags;
  1921. cmd->cmd.tx.next_frame_len = 0;
  1922. }
  1923. /**
  1924. * iwl3945_get_sta_id - Find station's index within station table
  1925. */
  1926. static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
  1927. {
  1928. int sta_id;
  1929. u16 fc = le16_to_cpu(hdr->frame_control);
  1930. /* If this frame is broadcast or management, use broadcast station id */
  1931. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1932. is_multicast_ether_addr(hdr->addr1))
  1933. return priv->hw_params.bcast_sta_id;
  1934. switch (priv->iw_mode) {
  1935. /* If we are a client station in a BSS network, use the special
  1936. * AP station entry (that's the only station we communicate with) */
  1937. case NL80211_IFTYPE_STATION:
  1938. return IWL_AP_ID;
  1939. /* If we are an AP, then find the station, or use BCAST */
  1940. case NL80211_IFTYPE_AP:
  1941. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1942. if (sta_id != IWL_INVALID_STATION)
  1943. return sta_id;
  1944. return priv->hw_params.bcast_sta_id;
  1945. /* If this frame is going out to an IBSS network, find the station,
  1946. * or create a new station table entry */
  1947. case NL80211_IFTYPE_ADHOC: {
  1948. /* Create new station table entry */
  1949. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1950. if (sta_id != IWL_INVALID_STATION)
  1951. return sta_id;
  1952. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1953. if (sta_id != IWL_INVALID_STATION)
  1954. return sta_id;
  1955. IWL_DEBUG_DROP("Station %pM not in station map. "
  1956. "Defaulting to broadcast...\n",
  1957. hdr->addr1);
  1958. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1959. return priv->hw_params.bcast_sta_id;
  1960. }
  1961. /* If we are in monitor mode, use BCAST. This is required for
  1962. * packet injection. */
  1963. case NL80211_IFTYPE_MONITOR:
  1964. return priv->hw_params.bcast_sta_id;
  1965. default:
  1966. IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
  1967. return priv->hw_params.bcast_sta_id;
  1968. }
  1969. }
  1970. /*
  1971. * start REPLY_TX command process
  1972. */
  1973. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  1974. {
  1975. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1976. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1977. struct iwl3945_tfd_frame *tfd;
  1978. u32 *control_flags;
  1979. int txq_id = skb_get_queue_mapping(skb);
  1980. struct iwl3945_tx_queue *txq = NULL;
  1981. struct iwl_queue *q = NULL;
  1982. dma_addr_t phys_addr;
  1983. dma_addr_t txcmd_phys;
  1984. struct iwl3945_cmd *out_cmd = NULL;
  1985. u16 len, idx, len_org, hdr_len;
  1986. u8 id;
  1987. u8 unicast;
  1988. u8 sta_id;
  1989. u8 tid = 0;
  1990. u16 seq_number = 0;
  1991. __le16 fc;
  1992. u8 wait_write_ptr = 0;
  1993. u8 *qc = NULL;
  1994. unsigned long flags;
  1995. int rc;
  1996. spin_lock_irqsave(&priv->lock, flags);
  1997. if (iwl3945_is_rfkill(priv)) {
  1998. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  1999. goto drop_unlock;
  2000. }
  2001. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2002. IWL_ERROR("ERROR: No TX rate available.\n");
  2003. goto drop_unlock;
  2004. }
  2005. unicast = !is_multicast_ether_addr(hdr->addr1);
  2006. id = 0;
  2007. fc = hdr->frame_control;
  2008. #ifdef CONFIG_IWL3945_DEBUG
  2009. if (ieee80211_is_auth(fc))
  2010. IWL_DEBUG_TX("Sending AUTH frame\n");
  2011. else if (ieee80211_is_assoc_req(fc))
  2012. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2013. else if (ieee80211_is_reassoc_req(fc))
  2014. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2015. #endif
  2016. /* drop all data frame if we are not associated */
  2017. if (ieee80211_is_data(fc) &&
  2018. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  2019. (!iwl3945_is_associated(priv) ||
  2020. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  2021. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2022. goto drop_unlock;
  2023. }
  2024. spin_unlock_irqrestore(&priv->lock, flags);
  2025. hdr_len = ieee80211_hdrlen(fc);
  2026. /* Find (or create) index into station table for destination station */
  2027. sta_id = iwl3945_get_sta_id(priv, hdr);
  2028. if (sta_id == IWL_INVALID_STATION) {
  2029. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  2030. hdr->addr1);
  2031. goto drop;
  2032. }
  2033. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2034. if (ieee80211_is_data_qos(fc)) {
  2035. qc = ieee80211_get_qos_ctl(hdr);
  2036. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  2037. seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
  2038. IEEE80211_SCTL_SEQ;
  2039. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2040. (hdr->seq_ctrl &
  2041. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2042. seq_number += 0x10;
  2043. }
  2044. /* Descriptor for chosen Tx queue */
  2045. txq = &priv->txq39[txq_id];
  2046. q = &txq->q;
  2047. spin_lock_irqsave(&priv->lock, flags);
  2048. /* Set up first empty TFD within this queue's circular TFD buffer */
  2049. tfd = &txq->bd[q->write_ptr];
  2050. memset(tfd, 0, sizeof(*tfd));
  2051. control_flags = (u32 *) tfd;
  2052. idx = get_cmd_index(q, q->write_ptr, 0);
  2053. /* Set up driver data for this TFD */
  2054. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2055. txq->txb[q->write_ptr].skb[0] = skb;
  2056. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2057. out_cmd = &txq->cmd[idx];
  2058. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2059. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2060. /*
  2061. * Set up the Tx-command (not MAC!) header.
  2062. * Store the chosen Tx queue and TFD index within the sequence field;
  2063. * after Tx, uCode's Tx response will return this value so driver can
  2064. * locate the frame within the tx queue and do post-tx processing.
  2065. */
  2066. out_cmd->hdr.cmd = REPLY_TX;
  2067. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2068. INDEX_TO_SEQ(q->write_ptr)));
  2069. /* Copy MAC header from skb into command buffer */
  2070. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2071. /*
  2072. * Use the first empty entry in this queue's command buffer array
  2073. * to contain the Tx command and MAC header concatenated together
  2074. * (payload data will be in another buffer).
  2075. * Size of this varies, due to varying MAC header length.
  2076. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2077. * of the MAC header (device reads on dword boundaries).
  2078. * We'll tell device about this padding later.
  2079. */
  2080. len = sizeof(struct iwl3945_tx_cmd) +
  2081. sizeof(struct iwl_cmd_header) + hdr_len;
  2082. len_org = len;
  2083. len = (len + 3) & ~3;
  2084. if (len_org != len)
  2085. len_org = 1;
  2086. else
  2087. len_org = 0;
  2088. /* Physical address of this Tx command's header (not MAC header!),
  2089. * within command buffer array. */
  2090. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2091. offsetof(struct iwl3945_cmd, hdr);
  2092. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2093. * first entry */
  2094. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2095. if (info->control.hw_key)
  2096. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2097. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2098. * if any (802.11 null frames have no payload). */
  2099. len = skb->len - hdr_len;
  2100. if (len) {
  2101. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2102. len, PCI_DMA_TODEVICE);
  2103. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2104. }
  2105. if (!len)
  2106. /* If there is no payload, then we use only one Tx buffer */
  2107. *control_flags = TFD_CTL_COUNT_SET(1);
  2108. else
  2109. /* Else use 2 buffers.
  2110. * Tell 3945 about any padding after MAC header */
  2111. *control_flags = TFD_CTL_COUNT_SET(2) |
  2112. TFD_CTL_PAD_SET(U32_PAD(len));
  2113. /* Total # bytes to be transmitted */
  2114. len = (u16)skb->len;
  2115. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2116. /* TODO need this for burst mode later on */
  2117. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2118. /* set is_hcca to 0; it probably will never be implemented */
  2119. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2120. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2121. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2122. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2123. txq->need_update = 1;
  2124. if (qc)
  2125. priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
  2126. } else {
  2127. wait_write_ptr = 1;
  2128. txq->need_update = 0;
  2129. }
  2130. iwl_print_hex_dump(priv, IWL_DL_TX, out_cmd->cmd.payload,
  2131. sizeof(out_cmd->cmd.tx));
  2132. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2133. ieee80211_hdrlen(fc));
  2134. /* Tell device the write index *just past* this latest filled TFD */
  2135. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2136. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2137. spin_unlock_irqrestore(&priv->lock, flags);
  2138. if (rc)
  2139. return rc;
  2140. if ((iwl_queue_space(q) < q->high_mark)
  2141. && priv->mac80211_registered) {
  2142. if (wait_write_ptr) {
  2143. spin_lock_irqsave(&priv->lock, flags);
  2144. txq->need_update = 1;
  2145. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2146. spin_unlock_irqrestore(&priv->lock, flags);
  2147. }
  2148. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2149. }
  2150. return 0;
  2151. drop_unlock:
  2152. spin_unlock_irqrestore(&priv->lock, flags);
  2153. drop:
  2154. return -1;
  2155. }
  2156. static void iwl3945_set_rate(struct iwl_priv *priv)
  2157. {
  2158. const struct ieee80211_supported_band *sband = NULL;
  2159. struct ieee80211_rate *rate;
  2160. int i;
  2161. sband = iwl3945_get_band(priv, priv->band);
  2162. if (!sband) {
  2163. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2164. return;
  2165. }
  2166. priv->active_rate = 0;
  2167. priv->active_rate_basic = 0;
  2168. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2169. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2170. for (i = 0; i < sband->n_bitrates; i++) {
  2171. rate = &sband->bitrates[i];
  2172. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2173. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2174. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2175. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2176. priv->active_rate |= (1 << rate->hw_value);
  2177. }
  2178. }
  2179. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2180. priv->active_rate, priv->active_rate_basic);
  2181. /*
  2182. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2183. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2184. * OFDM
  2185. */
  2186. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2187. priv->staging39_rxon.cck_basic_rates =
  2188. ((priv->active_rate_basic &
  2189. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2190. else
  2191. priv->staging39_rxon.cck_basic_rates =
  2192. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2193. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2194. priv->staging39_rxon.ofdm_basic_rates =
  2195. ((priv->active_rate_basic &
  2196. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2197. IWL_FIRST_OFDM_RATE) & 0xFF;
  2198. else
  2199. priv->staging39_rxon.ofdm_basic_rates =
  2200. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2201. }
  2202. static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
  2203. {
  2204. unsigned long flags;
  2205. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2206. return;
  2207. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2208. disable_radio ? "OFF" : "ON");
  2209. if (disable_radio) {
  2210. iwl3945_scan_cancel(priv);
  2211. /* FIXME: This is a workaround for AP */
  2212. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2213. spin_lock_irqsave(&priv->lock, flags);
  2214. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2215. CSR_UCODE_SW_BIT_RFKILL);
  2216. spin_unlock_irqrestore(&priv->lock, flags);
  2217. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2218. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2219. }
  2220. return;
  2221. }
  2222. spin_lock_irqsave(&priv->lock, flags);
  2223. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2224. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2225. spin_unlock_irqrestore(&priv->lock, flags);
  2226. /* wake up ucode */
  2227. msleep(10);
  2228. spin_lock_irqsave(&priv->lock, flags);
  2229. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2230. if (!iwl_grab_nic_access(priv))
  2231. iwl_release_nic_access(priv);
  2232. spin_unlock_irqrestore(&priv->lock, flags);
  2233. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2234. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2235. "disabled by HW switch\n");
  2236. return;
  2237. }
  2238. if (priv->is_open)
  2239. queue_work(priv->workqueue, &priv->restart);
  2240. return;
  2241. }
  2242. void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
  2243. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2244. {
  2245. u16 fc =
  2246. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2247. if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2248. return;
  2249. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2250. return;
  2251. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2252. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2253. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2254. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2255. RX_RES_STATUS_BAD_ICV_MIC)
  2256. stats->flag |= RX_FLAG_MMIC_ERROR;
  2257. case RX_RES_STATUS_SEC_TYPE_WEP:
  2258. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2259. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2260. RX_RES_STATUS_DECRYPT_OK) {
  2261. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2262. stats->flag |= RX_FLAG_DECRYPTED;
  2263. }
  2264. break;
  2265. default:
  2266. break;
  2267. }
  2268. }
  2269. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2270. #include "iwl-spectrum.h"
  2271. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2272. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2273. #define TIME_UNIT 1024
  2274. /*
  2275. * extended beacon time format
  2276. * time in usec will be changed into a 32-bit value in 8:24 format
  2277. * the high 1 byte is the beacon counts
  2278. * the lower 3 bytes is the time in usec within one beacon interval
  2279. */
  2280. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2281. {
  2282. u32 quot;
  2283. u32 rem;
  2284. u32 interval = beacon_interval * 1024;
  2285. if (!interval || !usec)
  2286. return 0;
  2287. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2288. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2289. return (quot << 24) + rem;
  2290. }
  2291. /* base is usually what we get from ucode with each received frame,
  2292. * the same as HW timer counter counting down
  2293. */
  2294. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2295. {
  2296. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2297. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2298. u32 interval = beacon_interval * TIME_UNIT;
  2299. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2300. (addon & BEACON_TIME_MASK_HIGH);
  2301. if (base_low > addon_low)
  2302. res += base_low - addon_low;
  2303. else if (base_low < addon_low) {
  2304. res += interval + base_low - addon_low;
  2305. res += (1 << 24);
  2306. } else
  2307. res += (1 << 24);
  2308. return cpu_to_le32(res);
  2309. }
  2310. static int iwl3945_get_measurement(struct iwl_priv *priv,
  2311. struct ieee80211_measurement_params *params,
  2312. u8 type)
  2313. {
  2314. struct iwl_spectrum_cmd spectrum;
  2315. struct iwl_rx_packet *res;
  2316. struct iwl3945_host_cmd cmd = {
  2317. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2318. .data = (void *)&spectrum,
  2319. .meta.flags = CMD_WANT_SKB,
  2320. };
  2321. u32 add_time = le64_to_cpu(params->start_time);
  2322. int rc;
  2323. int spectrum_resp_status;
  2324. int duration = le16_to_cpu(params->duration);
  2325. if (iwl3945_is_associated(priv))
  2326. add_time =
  2327. iwl3945_usecs_to_beacons(
  2328. le64_to_cpu(params->start_time) - priv->last_tsf,
  2329. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2330. memset(&spectrum, 0, sizeof(spectrum));
  2331. spectrum.channel_count = cpu_to_le16(1);
  2332. spectrum.flags =
  2333. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2334. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2335. cmd.len = sizeof(spectrum);
  2336. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2337. if (iwl3945_is_associated(priv))
  2338. spectrum.start_time =
  2339. iwl3945_add_beacon_time(priv->last_beacon_time,
  2340. add_time,
  2341. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2342. else
  2343. spectrum.start_time = 0;
  2344. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2345. spectrum.channels[0].channel = params->channel;
  2346. spectrum.channels[0].type = type;
  2347. if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2348. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2349. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2350. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2351. if (rc)
  2352. return rc;
  2353. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2354. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2355. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2356. rc = -EIO;
  2357. }
  2358. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2359. switch (spectrum_resp_status) {
  2360. case 0: /* Command will be handled */
  2361. if (res->u.spectrum.id != 0xff) {
  2362. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2363. res->u.spectrum.id);
  2364. priv->measurement_status &= ~MEASUREMENT_READY;
  2365. }
  2366. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2367. rc = 0;
  2368. break;
  2369. case 1: /* Command will not be handled */
  2370. rc = -EAGAIN;
  2371. break;
  2372. }
  2373. dev_kfree_skb_any(cmd.meta.u.skb);
  2374. return rc;
  2375. }
  2376. #endif
  2377. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  2378. struct iwl_rx_mem_buffer *rxb)
  2379. {
  2380. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2381. struct iwl_alive_resp *palive;
  2382. struct delayed_work *pwork;
  2383. palive = &pkt->u.alive_frame;
  2384. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2385. "0x%01X 0x%01X\n",
  2386. palive->is_valid, palive->ver_type,
  2387. palive->ver_subtype);
  2388. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2389. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2390. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2391. sizeof(struct iwl_alive_resp));
  2392. pwork = &priv->init_alive_start;
  2393. } else {
  2394. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2395. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2396. sizeof(struct iwl_alive_resp));
  2397. pwork = &priv->alive_start;
  2398. iwl3945_disable_events(priv);
  2399. }
  2400. /* We delay the ALIVE response by 5ms to
  2401. * give the HW RF Kill time to activate... */
  2402. if (palive->is_valid == UCODE_VALID_OK)
  2403. queue_delayed_work(priv->workqueue, pwork,
  2404. msecs_to_jiffies(5));
  2405. else
  2406. IWL_WARNING("uCode did not respond OK.\n");
  2407. }
  2408. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  2409. struct iwl_rx_mem_buffer *rxb)
  2410. {
  2411. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2412. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2413. return;
  2414. }
  2415. static void iwl3945_rx_reply_error(struct iwl_priv *priv,
  2416. struct iwl_rx_mem_buffer *rxb)
  2417. {
  2418. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2419. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2420. "seq 0x%04X ser 0x%08X\n",
  2421. le32_to_cpu(pkt->u.err_resp.error_type),
  2422. get_cmd_string(pkt->u.err_resp.cmd_id),
  2423. pkt->u.err_resp.cmd_id,
  2424. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2425. le32_to_cpu(pkt->u.err_resp.error_info));
  2426. }
  2427. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2428. static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2429. {
  2430. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2431. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
  2432. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2433. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2434. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2435. rxon->channel = csa->channel;
  2436. priv->staging39_rxon.channel = csa->channel;
  2437. }
  2438. static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
  2439. struct iwl_rx_mem_buffer *rxb)
  2440. {
  2441. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2442. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2443. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2444. if (!report->state) {
  2445. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2446. "Spectrum Measure Notification: Start\n");
  2447. return;
  2448. }
  2449. memcpy(&priv->measure_report, report, sizeof(*report));
  2450. priv->measurement_status |= MEASUREMENT_READY;
  2451. #endif
  2452. }
  2453. static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
  2454. struct iwl_rx_mem_buffer *rxb)
  2455. {
  2456. #ifdef CONFIG_IWL3945_DEBUG
  2457. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2458. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2459. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2460. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2461. #endif
  2462. }
  2463. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  2464. struct iwl_rx_mem_buffer *rxb)
  2465. {
  2466. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2467. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2468. "notification for %s:\n",
  2469. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2470. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2471. le32_to_cpu(pkt->len));
  2472. }
  2473. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2474. {
  2475. struct iwl_priv *priv =
  2476. container_of(work, struct iwl_priv, beacon_update);
  2477. struct sk_buff *beacon;
  2478. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2479. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2480. if (!beacon) {
  2481. IWL_ERROR("update beacon failed\n");
  2482. return;
  2483. }
  2484. mutex_lock(&priv->mutex);
  2485. /* new beacon skb is allocated every time; dispose previous.*/
  2486. if (priv->ibss_beacon)
  2487. dev_kfree_skb(priv->ibss_beacon);
  2488. priv->ibss_beacon = beacon;
  2489. mutex_unlock(&priv->mutex);
  2490. iwl3945_send_beacon_cmd(priv);
  2491. }
  2492. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  2493. struct iwl_rx_mem_buffer *rxb)
  2494. {
  2495. #ifdef CONFIG_IWL3945_DEBUG
  2496. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2497. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2498. u8 rate = beacon->beacon_notify_hdr.rate;
  2499. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2500. "tsf %d %d rate %d\n",
  2501. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2502. beacon->beacon_notify_hdr.failure_frame,
  2503. le32_to_cpu(beacon->ibss_mgr_status),
  2504. le32_to_cpu(beacon->high_tsf),
  2505. le32_to_cpu(beacon->low_tsf), rate);
  2506. #endif
  2507. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2508. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2509. queue_work(priv->workqueue, &priv->beacon_update);
  2510. }
  2511. /* Service response to REPLY_SCAN_CMD (0x80) */
  2512. static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
  2513. struct iwl_rx_mem_buffer *rxb)
  2514. {
  2515. #ifdef CONFIG_IWL3945_DEBUG
  2516. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2517. struct iwl_scanreq_notification *notif =
  2518. (struct iwl_scanreq_notification *)pkt->u.raw;
  2519. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2520. #endif
  2521. }
  2522. /* Service SCAN_START_NOTIFICATION (0x82) */
  2523. static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
  2524. struct iwl_rx_mem_buffer *rxb)
  2525. {
  2526. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2527. struct iwl_scanstart_notification *notif =
  2528. (struct iwl_scanstart_notification *)pkt->u.raw;
  2529. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2530. IWL_DEBUG_SCAN("Scan start: "
  2531. "%d [802.11%s] "
  2532. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2533. notif->channel,
  2534. notif->band ? "bg" : "a",
  2535. notif->tsf_high,
  2536. notif->tsf_low, notif->status, notif->beacon_timer);
  2537. }
  2538. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2539. static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
  2540. struct iwl_rx_mem_buffer *rxb)
  2541. {
  2542. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2543. struct iwl_scanresults_notification *notif =
  2544. (struct iwl_scanresults_notification *)pkt->u.raw;
  2545. IWL_DEBUG_SCAN("Scan ch.res: "
  2546. "%d [802.11%s] "
  2547. "(TSF: 0x%08X:%08X) - %d "
  2548. "elapsed=%lu usec (%dms since last)\n",
  2549. notif->channel,
  2550. notif->band ? "bg" : "a",
  2551. le32_to_cpu(notif->tsf_high),
  2552. le32_to_cpu(notif->tsf_low),
  2553. le32_to_cpu(notif->statistics[0]),
  2554. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2555. jiffies_to_msecs(elapsed_jiffies
  2556. (priv->last_scan_jiffies, jiffies)));
  2557. priv->last_scan_jiffies = jiffies;
  2558. priv->next_scan_jiffies = 0;
  2559. }
  2560. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2561. static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
  2562. struct iwl_rx_mem_buffer *rxb)
  2563. {
  2564. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2565. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2566. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2567. scan_notif->scanned_channels,
  2568. scan_notif->tsf_low,
  2569. scan_notif->tsf_high, scan_notif->status);
  2570. /* The HW is no longer scanning */
  2571. clear_bit(STATUS_SCAN_HW, &priv->status);
  2572. /* The scan completion notification came in, so kill that timer... */
  2573. cancel_delayed_work(&priv->scan_check);
  2574. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2575. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2576. "2.4" : "5.2",
  2577. jiffies_to_msecs(elapsed_jiffies
  2578. (priv->scan_pass_start, jiffies)));
  2579. /* Remove this scanned band from the list of pending
  2580. * bands to scan, band G precedes A in order of scanning
  2581. * as seen in iwl3945_bg_request_scan */
  2582. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2583. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2584. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2585. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2586. /* If a request to abort was given, or the scan did not succeed
  2587. * then we reset the scan state machine and terminate,
  2588. * re-queuing another scan if one has been requested */
  2589. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2590. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2591. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2592. } else {
  2593. /* If there are more bands on this scan pass reschedule */
  2594. if (priv->scan_bands > 0)
  2595. goto reschedule;
  2596. }
  2597. priv->last_scan_jiffies = jiffies;
  2598. priv->next_scan_jiffies = 0;
  2599. IWL_DEBUG_INFO("Setting scan to off\n");
  2600. clear_bit(STATUS_SCANNING, &priv->status);
  2601. IWL_DEBUG_INFO("Scan took %dms\n",
  2602. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2603. queue_work(priv->workqueue, &priv->scan_completed);
  2604. return;
  2605. reschedule:
  2606. priv->scan_pass_start = jiffies;
  2607. queue_work(priv->workqueue, &priv->request_scan);
  2608. }
  2609. /* Handle notification from uCode that card's power state is changing
  2610. * due to software, hardware, or critical temperature RFKILL */
  2611. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  2612. struct iwl_rx_mem_buffer *rxb)
  2613. {
  2614. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2615. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2616. unsigned long status = priv->status;
  2617. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2618. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2619. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2620. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2621. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2622. if (flags & HW_CARD_DISABLED)
  2623. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2624. else
  2625. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2626. if (flags & SW_CARD_DISABLED)
  2627. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2628. else
  2629. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2630. iwl3945_scan_cancel(priv);
  2631. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2632. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2633. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2634. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2635. queue_work(priv->workqueue, &priv->rf_kill);
  2636. else
  2637. wake_up_interruptible(&priv->wait_command_queue);
  2638. }
  2639. /**
  2640. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2641. *
  2642. * Setup the RX handlers for each of the reply types sent from the uCode
  2643. * to the host.
  2644. *
  2645. * This function chains into the hardware specific files for them to setup
  2646. * any hardware specific handlers as well.
  2647. */
  2648. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  2649. {
  2650. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2651. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2652. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2653. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2654. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2655. iwl3945_rx_spectrum_measure_notif;
  2656. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2657. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2658. iwl3945_rx_pm_debug_statistics_notif;
  2659. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2660. /*
  2661. * The same handler is used for both the REPLY to a discrete
  2662. * statistics request from the host as well as for the periodic
  2663. * statistics notifications (after received beacons) from the uCode.
  2664. */
  2665. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2666. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2667. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2668. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2669. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2670. iwl3945_rx_scan_results_notif;
  2671. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2672. iwl3945_rx_scan_complete_notif;
  2673. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2674. /* Set up hardware specific Rx handlers */
  2675. iwl3945_hw_rx_handler_setup(priv);
  2676. }
  2677. /**
  2678. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2679. * When FW advances 'R' index, all entries between old and new 'R' index
  2680. * need to be reclaimed.
  2681. */
  2682. static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
  2683. int txq_id, int index)
  2684. {
  2685. struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
  2686. struct iwl_queue *q = &txq->q;
  2687. int nfreed = 0;
  2688. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2689. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2690. "is out of range [0-%d] %d %d.\n", txq_id,
  2691. index, q->n_bd, q->write_ptr, q->read_ptr);
  2692. return;
  2693. }
  2694. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2695. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2696. if (nfreed > 1) {
  2697. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2698. q->write_ptr, q->read_ptr);
  2699. queue_work(priv->workqueue, &priv->restart);
  2700. break;
  2701. }
  2702. nfreed++;
  2703. }
  2704. }
  2705. /**
  2706. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2707. * @rxb: Rx buffer to reclaim
  2708. *
  2709. * If an Rx buffer has an async callback associated with it the callback
  2710. * will be executed. The attached skb (if present) will only be freed
  2711. * if the callback returns 1
  2712. */
  2713. static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
  2714. struct iwl_rx_mem_buffer *rxb)
  2715. {
  2716. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2717. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2718. int txq_id = SEQ_TO_QUEUE(sequence);
  2719. int index = SEQ_TO_INDEX(sequence);
  2720. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2721. int cmd_index;
  2722. struct iwl3945_cmd *cmd;
  2723. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2724. cmd_index = get_cmd_index(&priv->txq39[IWL_CMD_QUEUE_NUM].q, index, huge);
  2725. cmd = &priv->txq39[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2726. /* Input error checking is done when commands are added to queue. */
  2727. if (cmd->meta.flags & CMD_WANT_SKB) {
  2728. cmd->meta.source->u.skb = rxb->skb;
  2729. rxb->skb = NULL;
  2730. } else if (cmd->meta.u.callback &&
  2731. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2732. rxb->skb = NULL;
  2733. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2734. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2735. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2736. wake_up_interruptible(&priv->wait_command_queue);
  2737. }
  2738. }
  2739. /************************** RX-FUNCTIONS ****************************/
  2740. /*
  2741. * Rx theory of operation
  2742. *
  2743. * The host allocates 32 DMA target addresses and passes the host address
  2744. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2745. * 0 to 31
  2746. *
  2747. * Rx Queue Indexes
  2748. * The host/firmware share two index registers for managing the Rx buffers.
  2749. *
  2750. * The READ index maps to the first position that the firmware may be writing
  2751. * to -- the driver can read up to (but not including) this position and get
  2752. * good data.
  2753. * The READ index is managed by the firmware once the card is enabled.
  2754. *
  2755. * The WRITE index maps to the last position the driver has read from -- the
  2756. * position preceding WRITE is the last slot the firmware can place a packet.
  2757. *
  2758. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2759. * WRITE = READ.
  2760. *
  2761. * During initialization, the host sets up the READ queue position to the first
  2762. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2763. *
  2764. * When the firmware places a packet in a buffer, it will advance the READ index
  2765. * and fire the RX interrupt. The driver can then query the READ index and
  2766. * process as many packets as possible, moving the WRITE index forward as it
  2767. * resets the Rx queue buffers with new memory.
  2768. *
  2769. * The management in the driver is as follows:
  2770. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2771. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2772. * to replenish the iwl->rxq->rx_free.
  2773. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2774. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2775. * 'processed' and 'read' driver indexes as well)
  2776. * + A received packet is processed and handed to the kernel network stack,
  2777. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2778. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2779. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2780. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2781. * were enough free buffers and RX_STALLED is set it is cleared.
  2782. *
  2783. *
  2784. * Driver sequence:
  2785. *
  2786. * iwl3945_rx_queue_alloc() Allocates rx_free
  2787. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2788. * iwl3945_rx_queue_restock
  2789. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2790. * queue, updates firmware pointers, and updates
  2791. * the WRITE index. If insufficient rx_free buffers
  2792. * are available, schedules iwl3945_rx_replenish
  2793. *
  2794. * -- enable interrupts --
  2795. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  2796. * READ INDEX, detaching the SKB from the pool.
  2797. * Moves the packet buffer from queue to rx_used.
  2798. * Calls iwl3945_rx_queue_restock to refill any empty
  2799. * slots.
  2800. * ...
  2801. *
  2802. */
  2803. /**
  2804. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2805. */
  2806. static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q)
  2807. {
  2808. int s = q->read - q->write;
  2809. if (s <= 0)
  2810. s += RX_QUEUE_SIZE;
  2811. /* keep some buffer to not confuse full and empty queue */
  2812. s -= 2;
  2813. if (s < 0)
  2814. s = 0;
  2815. return s;
  2816. }
  2817. /**
  2818. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2819. */
  2820. int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  2821. {
  2822. u32 reg = 0;
  2823. int rc = 0;
  2824. unsigned long flags;
  2825. spin_lock_irqsave(&q->lock, flags);
  2826. if (q->need_update == 0)
  2827. goto exit_unlock;
  2828. /* If power-saving is in use, make sure device is awake */
  2829. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2830. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2831. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2832. iwl_set_bit(priv, CSR_GP_CNTRL,
  2833. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2834. goto exit_unlock;
  2835. }
  2836. rc = iwl_grab_nic_access(priv);
  2837. if (rc)
  2838. goto exit_unlock;
  2839. /* Device expects a multiple of 8 */
  2840. iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
  2841. q->write & ~0x7);
  2842. iwl_release_nic_access(priv);
  2843. /* Else device is assumed to be awake */
  2844. } else
  2845. /* Device expects a multiple of 8 */
  2846. iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2847. q->need_update = 0;
  2848. exit_unlock:
  2849. spin_unlock_irqrestore(&q->lock, flags);
  2850. return rc;
  2851. }
  2852. /**
  2853. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2854. */
  2855. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  2856. dma_addr_t dma_addr)
  2857. {
  2858. return cpu_to_le32((u32)dma_addr);
  2859. }
  2860. /**
  2861. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2862. *
  2863. * If there are slots in the RX queue that need to be restocked,
  2864. * and we have free pre-allocated buffers, fill the ranks as much
  2865. * as we can, pulling from rx_free.
  2866. *
  2867. * This moves the 'write' index forward to catch up with 'processed', and
  2868. * also updates the memory address in the firmware to reference the new
  2869. * target buffer.
  2870. */
  2871. static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
  2872. {
  2873. struct iwl_rx_queue *rxq = &priv->rxq;
  2874. struct list_head *element;
  2875. struct iwl_rx_mem_buffer *rxb;
  2876. unsigned long flags;
  2877. int write, rc;
  2878. spin_lock_irqsave(&rxq->lock, flags);
  2879. write = rxq->write & ~0x7;
  2880. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2881. /* Get next free Rx buffer, remove from free list */
  2882. element = rxq->rx_free.next;
  2883. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2884. list_del(element);
  2885. /* Point to Rx buffer via next RBD in circular buffer */
  2886. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
  2887. rxq->queue[rxq->write] = rxb;
  2888. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2889. rxq->free_count--;
  2890. }
  2891. spin_unlock_irqrestore(&rxq->lock, flags);
  2892. /* If the pre-allocated buffer pool is dropping low, schedule to
  2893. * refill it */
  2894. if (rxq->free_count <= RX_LOW_WATERMARK)
  2895. queue_work(priv->workqueue, &priv->rx_replenish);
  2896. /* If we've added more space for the firmware to place data, tell it.
  2897. * Increment device's write pointer in multiples of 8. */
  2898. if ((write != (rxq->write & ~0x7))
  2899. || (abs(rxq->write - rxq->read) > 7)) {
  2900. spin_lock_irqsave(&rxq->lock, flags);
  2901. rxq->need_update = 1;
  2902. spin_unlock_irqrestore(&rxq->lock, flags);
  2903. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2904. if (rc)
  2905. return rc;
  2906. }
  2907. return 0;
  2908. }
  2909. /**
  2910. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2911. *
  2912. * When moving to rx_free an SKB is allocated for the slot.
  2913. *
  2914. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2915. * This is called as a scheduled work item (except for during initialization)
  2916. */
  2917. static void iwl3945_rx_allocate(struct iwl_priv *priv)
  2918. {
  2919. struct iwl_rx_queue *rxq = &priv->rxq;
  2920. struct list_head *element;
  2921. struct iwl_rx_mem_buffer *rxb;
  2922. unsigned long flags;
  2923. spin_lock_irqsave(&rxq->lock, flags);
  2924. while (!list_empty(&rxq->rx_used)) {
  2925. element = rxq->rx_used.next;
  2926. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2927. /* Alloc a new receive buffer */
  2928. rxb->skb =
  2929. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  2930. if (!rxb->skb) {
  2931. if (net_ratelimit())
  2932. IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
  2933. /* We don't reschedule replenish work here -- we will
  2934. * call the restock method and if it still needs
  2935. * more buffers it will schedule replenish */
  2936. break;
  2937. }
  2938. /* If radiotap head is required, reserve some headroom here.
  2939. * The physical head count is a variable rx_stats->phy_count.
  2940. * We reserve 4 bytes here. Plus these extra bytes, the
  2941. * headroom of the physical head should be enough for the
  2942. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2943. */
  2944. skb_reserve(rxb->skb, 4);
  2945. priv->alloc_rxb_skb++;
  2946. list_del(element);
  2947. /* Get physical address of RB/SKB */
  2948. rxb->real_dma_addr =
  2949. pci_map_single(priv->pci_dev, rxb->skb->data,
  2950. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2951. list_add_tail(&rxb->list, &rxq->rx_free);
  2952. rxq->free_count++;
  2953. }
  2954. spin_unlock_irqrestore(&rxq->lock, flags);
  2955. }
  2956. /*
  2957. * this should be called while priv->lock is locked
  2958. */
  2959. static void __iwl3945_rx_replenish(void *data)
  2960. {
  2961. struct iwl_priv *priv = data;
  2962. iwl3945_rx_allocate(priv);
  2963. iwl3945_rx_queue_restock(priv);
  2964. }
  2965. void iwl3945_rx_replenish(void *data)
  2966. {
  2967. struct iwl_priv *priv = data;
  2968. unsigned long flags;
  2969. iwl3945_rx_allocate(priv);
  2970. spin_lock_irqsave(&priv->lock, flags);
  2971. iwl3945_rx_queue_restock(priv);
  2972. spin_unlock_irqrestore(&priv->lock, flags);
  2973. }
  2974. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  2975. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  2976. * This free routine walks the list of POOL entries and if SKB is set to
  2977. * non NULL it is unmapped and freed
  2978. */
  2979. static void iwl3945_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  2980. {
  2981. int i;
  2982. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  2983. if (rxq->pool[i].skb != NULL) {
  2984. pci_unmap_single(priv->pci_dev,
  2985. rxq->pool[i].real_dma_addr,
  2986. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2987. dev_kfree_skb(rxq->pool[i].skb);
  2988. }
  2989. }
  2990. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2991. rxq->dma_addr);
  2992. rxq->bd = NULL;
  2993. }
  2994. int iwl3945_rx_queue_alloc(struct iwl_priv *priv)
  2995. {
  2996. struct iwl_rx_queue *rxq = &priv->rxq;
  2997. struct pci_dev *dev = priv->pci_dev;
  2998. int i;
  2999. spin_lock_init(&rxq->lock);
  3000. INIT_LIST_HEAD(&rxq->rx_free);
  3001. INIT_LIST_HEAD(&rxq->rx_used);
  3002. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3003. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3004. if (!rxq->bd)
  3005. return -ENOMEM;
  3006. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3007. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3008. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3009. /* Set us so that we have processed and used all buffers, but have
  3010. * not restocked the Rx queue with fresh buffers */
  3011. rxq->read = rxq->write = 0;
  3012. rxq->free_count = 0;
  3013. rxq->need_update = 0;
  3014. return 0;
  3015. }
  3016. void iwl3945_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  3017. {
  3018. unsigned long flags;
  3019. int i;
  3020. spin_lock_irqsave(&rxq->lock, flags);
  3021. INIT_LIST_HEAD(&rxq->rx_free);
  3022. INIT_LIST_HEAD(&rxq->rx_used);
  3023. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3024. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3025. /* In the reset function, these buffers may have been allocated
  3026. * to an SKB, so we need to unmap and free potential storage */
  3027. if (rxq->pool[i].skb != NULL) {
  3028. pci_unmap_single(priv->pci_dev,
  3029. rxq->pool[i].real_dma_addr,
  3030. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3031. priv->alloc_rxb_skb--;
  3032. dev_kfree_skb(rxq->pool[i].skb);
  3033. rxq->pool[i].skb = NULL;
  3034. }
  3035. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3036. }
  3037. /* Set us so that we have processed and used all buffers, but have
  3038. * not restocked the Rx queue with fresh buffers */
  3039. rxq->read = rxq->write = 0;
  3040. rxq->free_count = 0;
  3041. spin_unlock_irqrestore(&rxq->lock, flags);
  3042. }
  3043. /* Convert linear signal-to-noise ratio into dB */
  3044. static u8 ratio2dB[100] = {
  3045. /* 0 1 2 3 4 5 6 7 8 9 */
  3046. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3047. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3048. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3049. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3050. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3051. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3052. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3053. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3054. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3055. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3056. };
  3057. /* Calculates a relative dB value from a ratio of linear
  3058. * (i.e. not dB) signal levels.
  3059. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3060. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3061. {
  3062. /* 1000:1 or higher just report as 60 dB */
  3063. if (sig_ratio >= 1000)
  3064. return 60;
  3065. /* 100:1 or higher, divide by 10 and use table,
  3066. * add 20 dB to make up for divide by 10 */
  3067. if (sig_ratio >= 100)
  3068. return 20 + (int)ratio2dB[sig_ratio/10];
  3069. /* We shouldn't see this */
  3070. if (sig_ratio < 1)
  3071. return 0;
  3072. /* Use table for ratios 1:1 - 99:1 */
  3073. return (int)ratio2dB[sig_ratio];
  3074. }
  3075. #define PERFECT_RSSI (-20) /* dBm */
  3076. #define WORST_RSSI (-95) /* dBm */
  3077. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3078. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3079. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3080. * about formulas used below. */
  3081. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3082. {
  3083. int sig_qual;
  3084. int degradation = PERFECT_RSSI - rssi_dbm;
  3085. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3086. * as indicator; formula is (signal dbm - noise dbm).
  3087. * SNR at or above 40 is a great signal (100%).
  3088. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3089. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3090. if (noise_dbm) {
  3091. if (rssi_dbm - noise_dbm >= 40)
  3092. return 100;
  3093. else if (rssi_dbm < noise_dbm)
  3094. return 0;
  3095. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3096. /* Else use just the signal level.
  3097. * This formula is a least squares fit of data points collected and
  3098. * compared with a reference system that had a percentage (%) display
  3099. * for signal quality. */
  3100. } else
  3101. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3102. (15 * RSSI_RANGE + 62 * degradation)) /
  3103. (RSSI_RANGE * RSSI_RANGE);
  3104. if (sig_qual > 100)
  3105. sig_qual = 100;
  3106. else if (sig_qual < 1)
  3107. sig_qual = 0;
  3108. return sig_qual;
  3109. }
  3110. /**
  3111. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3112. *
  3113. * Uses the priv->rx_handlers callback function array to invoke
  3114. * the appropriate handlers, including command responses,
  3115. * frame-received notifications, and other notifications.
  3116. */
  3117. static void iwl3945_rx_handle(struct iwl_priv *priv)
  3118. {
  3119. struct iwl_rx_mem_buffer *rxb;
  3120. struct iwl_rx_packet *pkt;
  3121. struct iwl_rx_queue *rxq = &priv->rxq;
  3122. u32 r, i;
  3123. int reclaim;
  3124. unsigned long flags;
  3125. u8 fill_rx = 0;
  3126. u32 count = 8;
  3127. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3128. * buffer that the driver may process (last buffer filled by ucode). */
  3129. r = iwl3945_hw_get_rx_read(priv);
  3130. i = rxq->read;
  3131. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3132. fill_rx = 1;
  3133. /* Rx interrupt, but nothing sent from uCode */
  3134. if (i == r)
  3135. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3136. while (i != r) {
  3137. rxb = rxq->queue[i];
  3138. /* If an RXB doesn't have a Rx queue slot associated with it,
  3139. * then a bug has been introduced in the queue refilling
  3140. * routines -- catch it here */
  3141. BUG_ON(rxb == NULL);
  3142. rxq->queue[i] = NULL;
  3143. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
  3144. IWL_RX_BUF_SIZE,
  3145. PCI_DMA_FROMDEVICE);
  3146. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  3147. /* Reclaim a command buffer only if this packet is a response
  3148. * to a (driver-originated) command.
  3149. * If the packet (e.g. Rx frame) originated from uCode,
  3150. * there is no command buffer to reclaim.
  3151. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3152. * but apparently a few don't get set; catch them here. */
  3153. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3154. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3155. (pkt->hdr.cmd != REPLY_TX);
  3156. /* Based on type of command response or notification,
  3157. * handle those that need handling via function in
  3158. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3159. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3160. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3161. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3162. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3163. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3164. } else {
  3165. /* No handling needed */
  3166. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  3167. "r %d i %d No handler needed for %s, 0x%02x\n",
  3168. r, i, get_cmd_string(pkt->hdr.cmd),
  3169. pkt->hdr.cmd);
  3170. }
  3171. if (reclaim) {
  3172. /* Invoke any callbacks, transfer the skb to caller, and
  3173. * fire off the (possibly) blocking iwl3945_send_cmd()
  3174. * as we reclaim the driver command queue */
  3175. if (rxb && rxb->skb)
  3176. iwl3945_tx_cmd_complete(priv, rxb);
  3177. else
  3178. IWL_WARNING("Claim null rxb?\n");
  3179. }
  3180. /* For now we just don't re-use anything. We can tweak this
  3181. * later to try and re-use notification packets and SKBs that
  3182. * fail to Rx correctly */
  3183. if (rxb->skb != NULL) {
  3184. priv->alloc_rxb_skb--;
  3185. dev_kfree_skb_any(rxb->skb);
  3186. rxb->skb = NULL;
  3187. }
  3188. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  3189. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3190. spin_lock_irqsave(&rxq->lock, flags);
  3191. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3192. spin_unlock_irqrestore(&rxq->lock, flags);
  3193. i = (i + 1) & RX_QUEUE_MASK;
  3194. /* If there are a lot of unused frames,
  3195. * restock the Rx queue so ucode won't assert. */
  3196. if (fill_rx) {
  3197. count++;
  3198. if (count >= 8) {
  3199. priv->rxq.read = i;
  3200. __iwl3945_rx_replenish(priv);
  3201. count = 0;
  3202. }
  3203. }
  3204. }
  3205. /* Backtrack one entry */
  3206. priv->rxq.read = i;
  3207. iwl3945_rx_queue_restock(priv);
  3208. }
  3209. /**
  3210. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3211. */
  3212. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  3213. struct iwl3945_tx_queue *txq)
  3214. {
  3215. u32 reg = 0;
  3216. int rc = 0;
  3217. int txq_id = txq->q.id;
  3218. if (txq->need_update == 0)
  3219. return rc;
  3220. /* if we're trying to save power */
  3221. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3222. /* wake up nic if it's powered down ...
  3223. * uCode will wake up, and interrupt us again, so next
  3224. * time we'll skip this part. */
  3225. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  3226. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3227. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3228. iwl_set_bit(priv, CSR_GP_CNTRL,
  3229. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3230. return rc;
  3231. }
  3232. /* restore this queue's parameters in nic hardware. */
  3233. rc = iwl_grab_nic_access(priv);
  3234. if (rc)
  3235. return rc;
  3236. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  3237. txq->q.write_ptr | (txq_id << 8));
  3238. iwl_release_nic_access(priv);
  3239. /* else not in power-save mode, uCode will never sleep when we're
  3240. * trying to tx (during RFKILL, we're not trying to tx). */
  3241. } else
  3242. iwl_write32(priv, HBUS_TARG_WRPTR,
  3243. txq->q.write_ptr | (txq_id << 8));
  3244. txq->need_update = 0;
  3245. return rc;
  3246. }
  3247. #ifdef CONFIG_IWL3945_DEBUG
  3248. static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
  3249. struct iwl3945_rxon_cmd *rxon)
  3250. {
  3251. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3252. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3253. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3254. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3255. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3256. le32_to_cpu(rxon->filter_flags));
  3257. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3258. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3259. rxon->ofdm_basic_rates);
  3260. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3261. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3262. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3263. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3264. }
  3265. #endif
  3266. static void iwl3945_enable_interrupts(struct iwl_priv *priv)
  3267. {
  3268. IWL_DEBUG_ISR("Enabling interrupts\n");
  3269. set_bit(STATUS_INT_ENABLED, &priv->status);
  3270. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3271. }
  3272. /* call this function to flush any scheduled tasklet */
  3273. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  3274. {
  3275. /* wait to make sure we flush pending tasklet*/
  3276. synchronize_irq(priv->pci_dev->irq);
  3277. tasklet_kill(&priv->irq_tasklet);
  3278. }
  3279. static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
  3280. {
  3281. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3282. /* disable interrupts from uCode/NIC to host */
  3283. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3284. /* acknowledge/clear/reset any interrupts still pending
  3285. * from uCode or flow handler (Rx/Tx DMA) */
  3286. iwl_write32(priv, CSR_INT, 0xffffffff);
  3287. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3288. IWL_DEBUG_ISR("Disabled interrupts\n");
  3289. }
  3290. static const char *desc_lookup(int i)
  3291. {
  3292. switch (i) {
  3293. case 1:
  3294. return "FAIL";
  3295. case 2:
  3296. return "BAD_PARAM";
  3297. case 3:
  3298. return "BAD_CHECKSUM";
  3299. case 4:
  3300. return "NMI_INTERRUPT";
  3301. case 5:
  3302. return "SYSASSERT";
  3303. case 6:
  3304. return "FATAL_ERROR";
  3305. }
  3306. return "UNKNOWN";
  3307. }
  3308. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3309. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3310. static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  3311. {
  3312. u32 i;
  3313. u32 desc, time, count, base, data1;
  3314. u32 blink1, blink2, ilink1, ilink2;
  3315. int rc;
  3316. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3317. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3318. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3319. return;
  3320. }
  3321. rc = iwl_grab_nic_access(priv);
  3322. if (rc) {
  3323. IWL_WARNING("Can not read from adapter at this time.\n");
  3324. return;
  3325. }
  3326. count = iwl_read_targ_mem(priv, base);
  3327. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3328. IWL_ERROR("Start IWL Error Log Dump:\n");
  3329. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3330. }
  3331. IWL_ERROR("Desc Time asrtPC blink2 "
  3332. "ilink1 nmiPC Line\n");
  3333. for (i = ERROR_START_OFFSET;
  3334. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3335. i += ERROR_ELEM_SIZE) {
  3336. desc = iwl_read_targ_mem(priv, base + i);
  3337. time =
  3338. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3339. blink1 =
  3340. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3341. blink2 =
  3342. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3343. ilink1 =
  3344. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3345. ilink2 =
  3346. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3347. data1 =
  3348. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3349. IWL_ERROR
  3350. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3351. desc_lookup(desc), desc, time, blink1, blink2,
  3352. ilink1, ilink2, data1);
  3353. }
  3354. iwl_release_nic_access(priv);
  3355. }
  3356. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3357. /**
  3358. * iwl3945_print_event_log - Dump error event log to syslog
  3359. *
  3360. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  3361. */
  3362. static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  3363. u32 num_events, u32 mode)
  3364. {
  3365. u32 i;
  3366. u32 base; /* SRAM byte address of event log header */
  3367. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3368. u32 ptr; /* SRAM byte address of log data */
  3369. u32 ev, time, data; /* event log data */
  3370. if (num_events == 0)
  3371. return;
  3372. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3373. if (mode == 0)
  3374. event_size = 2 * sizeof(u32);
  3375. else
  3376. event_size = 3 * sizeof(u32);
  3377. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3378. /* "time" is actually "data" for mode 0 (no timestamp).
  3379. * place event id # at far right for easier visual parsing. */
  3380. for (i = 0; i < num_events; i++) {
  3381. ev = iwl_read_targ_mem(priv, ptr);
  3382. ptr += sizeof(u32);
  3383. time = iwl_read_targ_mem(priv, ptr);
  3384. ptr += sizeof(u32);
  3385. if (mode == 0)
  3386. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3387. else {
  3388. data = iwl_read_targ_mem(priv, ptr);
  3389. ptr += sizeof(u32);
  3390. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3391. }
  3392. }
  3393. }
  3394. static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
  3395. {
  3396. int rc;
  3397. u32 base; /* SRAM byte address of event log header */
  3398. u32 capacity; /* event log capacity in # entries */
  3399. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3400. u32 num_wraps; /* # times uCode wrapped to top of log */
  3401. u32 next_entry; /* index of next entry to be written by uCode */
  3402. u32 size; /* # entries that we'll print */
  3403. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3404. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3405. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3406. return;
  3407. }
  3408. rc = iwl_grab_nic_access(priv);
  3409. if (rc) {
  3410. IWL_WARNING("Can not read from adapter at this time.\n");
  3411. return;
  3412. }
  3413. /* event log header */
  3414. capacity = iwl_read_targ_mem(priv, base);
  3415. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3416. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3417. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3418. size = num_wraps ? capacity : next_entry;
  3419. /* bail out if nothing in log */
  3420. if (size == 0) {
  3421. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3422. iwl_release_nic_access(priv);
  3423. return;
  3424. }
  3425. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3426. size, num_wraps);
  3427. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3428. * i.e the next one that uCode would fill. */
  3429. if (num_wraps)
  3430. iwl3945_print_event_log(priv, next_entry,
  3431. capacity - next_entry, mode);
  3432. /* (then/else) start at top of log */
  3433. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3434. iwl_release_nic_access(priv);
  3435. }
  3436. /**
  3437. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3438. */
  3439. static void iwl3945_irq_handle_error(struct iwl_priv *priv)
  3440. {
  3441. /* Set the FW error flag -- cleared on iwl3945_down */
  3442. set_bit(STATUS_FW_ERROR, &priv->status);
  3443. /* Cancel currently queued command. */
  3444. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3445. #ifdef CONFIG_IWL3945_DEBUG
  3446. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3447. iwl3945_dump_nic_error_log(priv);
  3448. iwl3945_dump_nic_event_log(priv);
  3449. iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
  3450. }
  3451. #endif
  3452. wake_up_interruptible(&priv->wait_command_queue);
  3453. /* Keep the restart process from trying to send host
  3454. * commands by clearing the INIT status bit */
  3455. clear_bit(STATUS_READY, &priv->status);
  3456. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3457. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3458. "Restarting adapter due to uCode error.\n");
  3459. if (iwl3945_is_associated(priv)) {
  3460. memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
  3461. sizeof(priv->recovery39_rxon));
  3462. priv->error_recovering = 1;
  3463. }
  3464. queue_work(priv->workqueue, &priv->restart);
  3465. }
  3466. }
  3467. static void iwl3945_error_recovery(struct iwl_priv *priv)
  3468. {
  3469. unsigned long flags;
  3470. memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
  3471. sizeof(priv->staging39_rxon));
  3472. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3473. iwl3945_commit_rxon(priv);
  3474. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3475. spin_lock_irqsave(&priv->lock, flags);
  3476. priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
  3477. priv->error_recovering = 0;
  3478. spin_unlock_irqrestore(&priv->lock, flags);
  3479. }
  3480. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  3481. {
  3482. u32 inta, handled = 0;
  3483. u32 inta_fh;
  3484. unsigned long flags;
  3485. #ifdef CONFIG_IWL3945_DEBUG
  3486. u32 inta_mask;
  3487. #endif
  3488. spin_lock_irqsave(&priv->lock, flags);
  3489. /* Ack/clear/reset pending uCode interrupts.
  3490. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3491. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3492. inta = iwl_read32(priv, CSR_INT);
  3493. iwl_write32(priv, CSR_INT, inta);
  3494. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3495. * Any new interrupts that happen after this, either while we're
  3496. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3497. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3498. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3499. #ifdef CONFIG_IWL3945_DEBUG
  3500. if (priv->debug_level & IWL_DL_ISR) {
  3501. /* just for debug */
  3502. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3503. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3504. inta, inta_mask, inta_fh);
  3505. }
  3506. #endif
  3507. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3508. * atomic, make sure that inta covers all the interrupts that
  3509. * we've discovered, even if FH interrupt came in just after
  3510. * reading CSR_INT. */
  3511. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3512. inta |= CSR_INT_BIT_FH_RX;
  3513. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3514. inta |= CSR_INT_BIT_FH_TX;
  3515. /* Now service all interrupt bits discovered above. */
  3516. if (inta & CSR_INT_BIT_HW_ERR) {
  3517. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3518. /* Tell the device to stop sending interrupts */
  3519. iwl3945_disable_interrupts(priv);
  3520. iwl3945_irq_handle_error(priv);
  3521. handled |= CSR_INT_BIT_HW_ERR;
  3522. spin_unlock_irqrestore(&priv->lock, flags);
  3523. return;
  3524. }
  3525. #ifdef CONFIG_IWL3945_DEBUG
  3526. if (priv->debug_level & (IWL_DL_ISR)) {
  3527. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3528. if (inta & CSR_INT_BIT_SCD)
  3529. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3530. "the frame/frames.\n");
  3531. /* Alive notification via Rx interrupt will do the real work */
  3532. if (inta & CSR_INT_BIT_ALIVE)
  3533. IWL_DEBUG_ISR("Alive interrupt\n");
  3534. }
  3535. #endif
  3536. /* Safely ignore these bits for debug checks below */
  3537. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3538. /* Error detected by uCode */
  3539. if (inta & CSR_INT_BIT_SW_ERR) {
  3540. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3541. inta);
  3542. iwl3945_irq_handle_error(priv);
  3543. handled |= CSR_INT_BIT_SW_ERR;
  3544. }
  3545. /* uCode wakes up after power-down sleep */
  3546. if (inta & CSR_INT_BIT_WAKEUP) {
  3547. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3548. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3549. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[0]);
  3550. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[1]);
  3551. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[2]);
  3552. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[3]);
  3553. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[4]);
  3554. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq39[5]);
  3555. handled |= CSR_INT_BIT_WAKEUP;
  3556. }
  3557. /* All uCode command responses, including Tx command responses,
  3558. * Rx "responses" (frame-received notification), and other
  3559. * notifications from uCode come through here*/
  3560. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3561. iwl3945_rx_handle(priv);
  3562. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3563. }
  3564. if (inta & CSR_INT_BIT_FH_TX) {
  3565. IWL_DEBUG_ISR("Tx interrupt\n");
  3566. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3567. if (!iwl_grab_nic_access(priv)) {
  3568. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  3569. (FH39_SRVC_CHNL), 0x0);
  3570. iwl_release_nic_access(priv);
  3571. }
  3572. handled |= CSR_INT_BIT_FH_TX;
  3573. }
  3574. if (inta & ~handled)
  3575. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3576. if (inta & ~CSR_INI_SET_MASK) {
  3577. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3578. inta & ~CSR_INI_SET_MASK);
  3579. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3580. }
  3581. /* Re-enable all interrupts */
  3582. /* only Re-enable if disabled by irq */
  3583. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3584. iwl3945_enable_interrupts(priv);
  3585. #ifdef CONFIG_IWL3945_DEBUG
  3586. if (priv->debug_level & (IWL_DL_ISR)) {
  3587. inta = iwl_read32(priv, CSR_INT);
  3588. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3589. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3590. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3591. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3592. }
  3593. #endif
  3594. spin_unlock_irqrestore(&priv->lock, flags);
  3595. }
  3596. static irqreturn_t iwl3945_isr(int irq, void *data)
  3597. {
  3598. struct iwl_priv *priv = data;
  3599. u32 inta, inta_mask;
  3600. u32 inta_fh;
  3601. if (!priv)
  3602. return IRQ_NONE;
  3603. spin_lock(&priv->lock);
  3604. /* Disable (but don't clear!) interrupts here to avoid
  3605. * back-to-back ISRs and sporadic interrupts from our NIC.
  3606. * If we have something to service, the tasklet will re-enable ints.
  3607. * If we *don't* have something, we'll re-enable before leaving here. */
  3608. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  3609. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3610. /* Discover which interrupts are active/pending */
  3611. inta = iwl_read32(priv, CSR_INT);
  3612. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3613. /* Ignore interrupt if there's nothing in NIC to service.
  3614. * This may be due to IRQ shared with another device,
  3615. * or due to sporadic interrupts thrown from our NIC. */
  3616. if (!inta && !inta_fh) {
  3617. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3618. goto none;
  3619. }
  3620. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3621. /* Hardware disappeared */
  3622. IWL_WARNING("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3623. goto unplugged;
  3624. }
  3625. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3626. inta, inta_mask, inta_fh);
  3627. inta &= ~CSR_INT_BIT_SCD;
  3628. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3629. if (likely(inta || inta_fh))
  3630. tasklet_schedule(&priv->irq_tasklet);
  3631. unplugged:
  3632. spin_unlock(&priv->lock);
  3633. return IRQ_HANDLED;
  3634. none:
  3635. /* re-enable interrupts here since we don't have anything to service. */
  3636. /* only Re-enable if disabled by irq */
  3637. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3638. iwl3945_enable_interrupts(priv);
  3639. spin_unlock(&priv->lock);
  3640. return IRQ_NONE;
  3641. }
  3642. /************************** EEPROM BANDS ****************************
  3643. *
  3644. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3645. * EEPROM contents to the specific channel number supported for each
  3646. * band.
  3647. *
  3648. * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
  3649. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3650. * The specific geography and calibration information for that channel
  3651. * is contained in the eeprom map itself.
  3652. *
  3653. * During init, we copy the eeprom information and channel map
  3654. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3655. *
  3656. * channel_map_24/52 provides the index in the channel_info array for a
  3657. * given channel. We have to have two separate maps as there is channel
  3658. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3659. * band_2
  3660. *
  3661. * A value of 0xff stored in the channel_map indicates that the channel
  3662. * is not supported by the hardware at all.
  3663. *
  3664. * A value of 0xfe in the channel_map indicates that the channel is not
  3665. * valid for Tx with the current hardware. This means that
  3666. * while the system can tune and receive on a given channel, it may not
  3667. * be able to associate or transmit any frames on that
  3668. * channel. There is no corresponding channel information for that
  3669. * entry.
  3670. *
  3671. *********************************************************************/
  3672. /* 2.4 GHz */
  3673. static const u8 iwl3945_eeprom_band_1[14] = {
  3674. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3675. };
  3676. /* 5.2 GHz bands */
  3677. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3678. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3679. };
  3680. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3681. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3682. };
  3683. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3684. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3685. };
  3686. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3687. 145, 149, 153, 157, 161, 165
  3688. };
  3689. static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
  3690. int *eeprom_ch_count,
  3691. const struct iwl_eeprom_channel
  3692. **eeprom_ch_info,
  3693. const u8 **eeprom_ch_index)
  3694. {
  3695. switch (band) {
  3696. case 1: /* 2.4GHz band */
  3697. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3698. *eeprom_ch_info = priv->eeprom39.band_1_channels;
  3699. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3700. break;
  3701. case 2: /* 4.9GHz band */
  3702. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3703. *eeprom_ch_info = priv->eeprom39.band_2_channels;
  3704. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3705. break;
  3706. case 3: /* 5.2GHz band */
  3707. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3708. *eeprom_ch_info = priv->eeprom39.band_3_channels;
  3709. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3710. break;
  3711. case 4: /* 5.5GHz band */
  3712. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3713. *eeprom_ch_info = priv->eeprom39.band_4_channels;
  3714. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3715. break;
  3716. case 5: /* 5.7GHz band */
  3717. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3718. *eeprom_ch_info = priv->eeprom39.band_5_channels;
  3719. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3720. break;
  3721. default:
  3722. BUG();
  3723. return;
  3724. }
  3725. }
  3726. /**
  3727. * iwl3945_get_channel_info - Find driver's private channel info
  3728. *
  3729. * Based on band and channel number.
  3730. */
  3731. const struct iwl_channel_info *
  3732. iwl3945_get_channel_info(const struct iwl_priv *priv,
  3733. enum ieee80211_band band, u16 channel)
  3734. {
  3735. int i;
  3736. switch (band) {
  3737. case IEEE80211_BAND_5GHZ:
  3738. for (i = 14; i < priv->channel_count; i++) {
  3739. if (priv->channel_info[i].channel == channel)
  3740. return &priv->channel_info[i];
  3741. }
  3742. break;
  3743. case IEEE80211_BAND_2GHZ:
  3744. if (channel >= 1 && channel <= 14)
  3745. return &priv->channel_info[channel - 1];
  3746. break;
  3747. case IEEE80211_NUM_BANDS:
  3748. WARN_ON(1);
  3749. }
  3750. return NULL;
  3751. }
  3752. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3753. ? # x " " : "")
  3754. /**
  3755. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3756. */
  3757. static int iwl3945_init_channel_map(struct iwl_priv *priv)
  3758. {
  3759. int eeprom_ch_count = 0;
  3760. const u8 *eeprom_ch_index = NULL;
  3761. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3762. int band, ch;
  3763. struct iwl_channel_info *ch_info;
  3764. if (priv->channel_count) {
  3765. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3766. return 0;
  3767. }
  3768. if (priv->eeprom39.version < 0x2f) {
  3769. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  3770. priv->eeprom39.version);
  3771. return -EINVAL;
  3772. }
  3773. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3774. priv->channel_count =
  3775. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3776. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3777. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3778. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3779. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3780. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3781. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3782. priv->channel_count, GFP_KERNEL);
  3783. if (!priv->channel_info) {
  3784. IWL_ERROR("Could not allocate channel_info\n");
  3785. priv->channel_count = 0;
  3786. return -ENOMEM;
  3787. }
  3788. ch_info = priv->channel_info;
  3789. /* Loop through the 5 EEPROM bands adding them in order to the
  3790. * channel map we maintain (that contains additional information than
  3791. * what just in the EEPROM) */
  3792. for (band = 1; band <= 5; band++) {
  3793. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3794. &eeprom_ch_info, &eeprom_ch_index);
  3795. /* Loop through each band adding each of the channels */
  3796. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3797. ch_info->channel = eeprom_ch_index[ch];
  3798. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3799. IEEE80211_BAND_5GHZ;
  3800. /* permanently store EEPROM's channel regulatory flags
  3801. * and max power in channel info database. */
  3802. ch_info->eeprom = eeprom_ch_info[ch];
  3803. /* Copy the run-time flags so they are there even on
  3804. * invalid channels */
  3805. ch_info->flags = eeprom_ch_info[ch].flags;
  3806. if (!(is_channel_valid(ch_info))) {
  3807. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3808. "No traffic\n",
  3809. ch_info->channel,
  3810. ch_info->flags,
  3811. is_channel_a_band(ch_info) ?
  3812. "5.2" : "2.4");
  3813. ch_info++;
  3814. continue;
  3815. }
  3816. /* Initialize regulatory-based run-time data */
  3817. ch_info->max_power_avg = ch_info->curr_txpow =
  3818. eeprom_ch_info[ch].max_power_avg;
  3819. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3820. ch_info->min_power = 0;
  3821. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3822. " %ddBm): Ad-Hoc %ssupported\n",
  3823. ch_info->channel,
  3824. is_channel_a_band(ch_info) ?
  3825. "5.2" : "2.4",
  3826. CHECK_AND_PRINT(VALID),
  3827. CHECK_AND_PRINT(IBSS),
  3828. CHECK_AND_PRINT(ACTIVE),
  3829. CHECK_AND_PRINT(RADAR),
  3830. CHECK_AND_PRINT(WIDE),
  3831. CHECK_AND_PRINT(DFS),
  3832. eeprom_ch_info[ch].flags,
  3833. eeprom_ch_info[ch].max_power_avg,
  3834. ((eeprom_ch_info[ch].
  3835. flags & EEPROM_CHANNEL_IBSS)
  3836. && !(eeprom_ch_info[ch].
  3837. flags & EEPROM_CHANNEL_RADAR))
  3838. ? "" : "not ");
  3839. /* Set the user_txpower_limit to the highest power
  3840. * supported by any channel */
  3841. if (eeprom_ch_info[ch].max_power_avg >
  3842. priv->user_txpower_limit)
  3843. priv->user_txpower_limit =
  3844. eeprom_ch_info[ch].max_power_avg;
  3845. ch_info++;
  3846. }
  3847. }
  3848. /* Set up txpower settings in driver for all channels */
  3849. if (iwl3945_txpower_set_from_eeprom(priv))
  3850. return -EIO;
  3851. return 0;
  3852. }
  3853. /*
  3854. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3855. */
  3856. static void iwl3945_free_channel_map(struct iwl_priv *priv)
  3857. {
  3858. kfree(priv->channel_info);
  3859. priv->channel_count = 0;
  3860. }
  3861. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3862. * sending probe req. This should be set long enough to hear probe responses
  3863. * from more than one AP. */
  3864. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3865. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3866. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3867. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3868. /* For faster active scanning, scan will move to the next channel if fewer than
  3869. * PLCP_QUIET_THRESH packets are heard on this channel within
  3870. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3871. * time if it's a quiet channel (nothing responded to our probe, and there's
  3872. * no other traffic).
  3873. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3874. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3875. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3876. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3877. * Must be set longer than active dwell time.
  3878. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3879. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3880. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3881. #define IWL_PASSIVE_DWELL_BASE (100)
  3882. #define IWL_CHANNEL_TUNE_TIME 5
  3883. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3884. static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
  3885. enum ieee80211_band band,
  3886. u8 n_probes)
  3887. {
  3888. if (band == IEEE80211_BAND_5GHZ)
  3889. return IWL_ACTIVE_DWELL_TIME_52 +
  3890. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3891. else
  3892. return IWL_ACTIVE_DWELL_TIME_24 +
  3893. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3894. }
  3895. static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
  3896. enum ieee80211_band band)
  3897. {
  3898. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3899. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3900. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3901. if (iwl3945_is_associated(priv)) {
  3902. /* If we're associated, we clamp the maximum passive
  3903. * dwell time to be 98% of the beacon interval (minus
  3904. * 2 * channel tune time) */
  3905. passive = priv->beacon_int;
  3906. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3907. passive = IWL_PASSIVE_DWELL_BASE;
  3908. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3909. }
  3910. return passive;
  3911. }
  3912. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  3913. enum ieee80211_band band,
  3914. u8 is_active, u8 n_probes,
  3915. struct iwl3945_scan_channel *scan_ch)
  3916. {
  3917. const struct ieee80211_channel *channels = NULL;
  3918. const struct ieee80211_supported_band *sband;
  3919. const struct iwl_channel_info *ch_info;
  3920. u16 passive_dwell = 0;
  3921. u16 active_dwell = 0;
  3922. int added, i;
  3923. sband = iwl3945_get_band(priv, band);
  3924. if (!sband)
  3925. return 0;
  3926. channels = sband->channels;
  3927. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3928. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3929. if (passive_dwell <= active_dwell)
  3930. passive_dwell = active_dwell + 1;
  3931. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3932. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3933. continue;
  3934. scan_ch->channel = channels[i].hw_value;
  3935. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3936. if (!is_channel_valid(ch_info)) {
  3937. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3938. scan_ch->channel);
  3939. continue;
  3940. }
  3941. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3942. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3943. /* If passive , set up for auto-switch
  3944. * and use long active_dwell time.
  3945. */
  3946. if (!is_active || is_channel_passive(ch_info) ||
  3947. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3948. scan_ch->type = 0; /* passive */
  3949. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3950. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3951. } else {
  3952. scan_ch->type = 1; /* active */
  3953. }
  3954. /* Set direct probe bits. These may be used both for active
  3955. * scan channels (probes gets sent right away),
  3956. * or for passive channels (probes get se sent only after
  3957. * hearing clear Rx packet).*/
  3958. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3959. if (n_probes)
  3960. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3961. } else {
  3962. /* uCode v1 does not allow setting direct probe bits on
  3963. * passive channel. */
  3964. if ((scan_ch->type & 1) && n_probes)
  3965. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3966. }
  3967. /* Set txpower levels to defaults */
  3968. scan_ch->tpc.dsp_atten = 110;
  3969. /* scan_pwr_info->tpc.dsp_atten; */
  3970. /*scan_pwr_info->tpc.tx_gain; */
  3971. if (band == IEEE80211_BAND_5GHZ)
  3972. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3973. else {
  3974. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3975. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3976. * power level:
  3977. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3978. */
  3979. }
  3980. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3981. scan_ch->channel,
  3982. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3983. (scan_ch->type & 1) ?
  3984. active_dwell : passive_dwell);
  3985. scan_ch++;
  3986. added++;
  3987. }
  3988. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3989. return added;
  3990. }
  3991. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  3992. struct ieee80211_rate *rates)
  3993. {
  3994. int i;
  3995. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3996. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3997. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3998. rates[i].hw_value_short = i;
  3999. rates[i].flags = 0;
  4000. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4001. /*
  4002. * If CCK != 1M then set short preamble rate flag.
  4003. */
  4004. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4005. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4006. }
  4007. }
  4008. }
  4009. /**
  4010. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4011. */
  4012. static int iwl3945_init_geos(struct iwl_priv *priv)
  4013. {
  4014. struct iwl_channel_info *ch;
  4015. struct ieee80211_supported_band *sband;
  4016. struct ieee80211_channel *channels;
  4017. struct ieee80211_channel *geo_ch;
  4018. struct ieee80211_rate *rates;
  4019. int i = 0;
  4020. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4021. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4022. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4023. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4024. return 0;
  4025. }
  4026. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4027. priv->channel_count, GFP_KERNEL);
  4028. if (!channels)
  4029. return -ENOMEM;
  4030. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4031. GFP_KERNEL);
  4032. if (!rates) {
  4033. kfree(channels);
  4034. return -ENOMEM;
  4035. }
  4036. /* 5.2GHz channels start after the 2.4GHz channels */
  4037. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4038. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4039. /* just OFDM */
  4040. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4041. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4042. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4043. sband->channels = channels;
  4044. /* OFDM & CCK */
  4045. sband->bitrates = rates;
  4046. sband->n_bitrates = IWL_RATE_COUNT;
  4047. priv->ieee_channels = channels;
  4048. priv->ieee_rates = rates;
  4049. iwl3945_init_hw_rates(priv, rates);
  4050. for (i = 0; i < priv->channel_count; i++) {
  4051. ch = &priv->channel_info[i];
  4052. /* FIXME: might be removed if scan is OK*/
  4053. if (!is_channel_valid(ch))
  4054. continue;
  4055. if (is_channel_a_band(ch))
  4056. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4057. else
  4058. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4059. geo_ch = &sband->channels[sband->n_channels++];
  4060. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4061. geo_ch->max_power = ch->max_power_avg;
  4062. geo_ch->max_antenna_gain = 0xff;
  4063. geo_ch->hw_value = ch->channel;
  4064. if (is_channel_valid(ch)) {
  4065. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4066. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4067. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4068. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4069. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4070. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4071. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4072. priv->max_channel_txpower_limit =
  4073. ch->max_power_avg;
  4074. } else {
  4075. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4076. }
  4077. /* Save flags for reg domain usage */
  4078. geo_ch->orig_flags = geo_ch->flags;
  4079. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4080. ch->channel, geo_ch->center_freq,
  4081. is_channel_a_band(ch) ? "5.2" : "2.4",
  4082. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4083. "restricted" : "valid",
  4084. geo_ch->flags);
  4085. }
  4086. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4087. priv->cfg->sku & IWL_SKU_A) {
  4088. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  4089. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4090. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4091. priv->cfg->sku &= ~IWL_SKU_A;
  4092. }
  4093. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4094. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4095. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4096. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4097. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4098. &priv->bands[IEEE80211_BAND_2GHZ];
  4099. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4100. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4101. &priv->bands[IEEE80211_BAND_5GHZ];
  4102. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4103. return 0;
  4104. }
  4105. /*
  4106. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4107. */
  4108. static void iwl3945_free_geos(struct iwl_priv *priv)
  4109. {
  4110. kfree(priv->ieee_channels);
  4111. kfree(priv->ieee_rates);
  4112. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4113. }
  4114. /******************************************************************************
  4115. *
  4116. * uCode download functions
  4117. *
  4118. ******************************************************************************/
  4119. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  4120. {
  4121. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4122. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4123. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4124. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4125. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4126. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4127. }
  4128. /**
  4129. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4130. * looking at all data.
  4131. */
  4132. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  4133. {
  4134. u32 val;
  4135. u32 save_len = len;
  4136. int rc = 0;
  4137. u32 errcnt;
  4138. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4139. rc = iwl_grab_nic_access(priv);
  4140. if (rc)
  4141. return rc;
  4142. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4143. IWL39_RTC_INST_LOWER_BOUND);
  4144. errcnt = 0;
  4145. for (; len > 0; len -= sizeof(u32), image++) {
  4146. /* read data comes through single port, auto-incr addr */
  4147. /* NOTE: Use the debugless read so we don't flood kernel log
  4148. * if IWL_DL_IO is set */
  4149. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4150. if (val != le32_to_cpu(*image)) {
  4151. IWL_ERROR("uCode INST section is invalid at "
  4152. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4153. save_len - len, val, le32_to_cpu(*image));
  4154. rc = -EIO;
  4155. errcnt++;
  4156. if (errcnt >= 20)
  4157. break;
  4158. }
  4159. }
  4160. iwl_release_nic_access(priv);
  4161. if (!errcnt)
  4162. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4163. return rc;
  4164. }
  4165. /**
  4166. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4167. * using sample data 100 bytes apart. If these sample points are good,
  4168. * it's a pretty good bet that everything between them is good, too.
  4169. */
  4170. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  4171. {
  4172. u32 val;
  4173. int rc = 0;
  4174. u32 errcnt = 0;
  4175. u32 i;
  4176. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4177. rc = iwl_grab_nic_access(priv);
  4178. if (rc)
  4179. return rc;
  4180. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4181. /* read data comes through single port, auto-incr addr */
  4182. /* NOTE: Use the debugless read so we don't flood kernel log
  4183. * if IWL_DL_IO is set */
  4184. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4185. i + IWL39_RTC_INST_LOWER_BOUND);
  4186. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4187. if (val != le32_to_cpu(*image)) {
  4188. #if 0 /* Enable this if you want to see details */
  4189. IWL_ERROR("uCode INST section is invalid at "
  4190. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4191. i, val, *image);
  4192. #endif
  4193. rc = -EIO;
  4194. errcnt++;
  4195. if (errcnt >= 3)
  4196. break;
  4197. }
  4198. }
  4199. iwl_release_nic_access(priv);
  4200. return rc;
  4201. }
  4202. /**
  4203. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4204. * and verify its contents
  4205. */
  4206. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  4207. {
  4208. __le32 *image;
  4209. u32 len;
  4210. int rc = 0;
  4211. /* Try bootstrap */
  4212. image = (__le32 *)priv->ucode_boot.v_addr;
  4213. len = priv->ucode_boot.len;
  4214. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4215. if (rc == 0) {
  4216. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4217. return 0;
  4218. }
  4219. /* Try initialize */
  4220. image = (__le32 *)priv->ucode_init.v_addr;
  4221. len = priv->ucode_init.len;
  4222. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4223. if (rc == 0) {
  4224. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4225. return 0;
  4226. }
  4227. /* Try runtime/protocol */
  4228. image = (__le32 *)priv->ucode_code.v_addr;
  4229. len = priv->ucode_code.len;
  4230. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4231. if (rc == 0) {
  4232. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4233. return 0;
  4234. }
  4235. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4236. /* Since nothing seems to match, show first several data entries in
  4237. * instruction SRAM, so maybe visual inspection will give a clue.
  4238. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4239. image = (__le32 *)priv->ucode_boot.v_addr;
  4240. len = priv->ucode_boot.len;
  4241. rc = iwl3945_verify_inst_full(priv, image, len);
  4242. return rc;
  4243. }
  4244. /* check contents of special bootstrap uCode SRAM */
  4245. static int iwl3945_verify_bsm(struct iwl_priv *priv)
  4246. {
  4247. __le32 *image = priv->ucode_boot.v_addr;
  4248. u32 len = priv->ucode_boot.len;
  4249. u32 reg;
  4250. u32 val;
  4251. IWL_DEBUG_INFO("Begin verify bsm\n");
  4252. /* verify BSM SRAM contents */
  4253. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4254. for (reg = BSM_SRAM_LOWER_BOUND;
  4255. reg < BSM_SRAM_LOWER_BOUND + len;
  4256. reg += sizeof(u32), image++) {
  4257. val = iwl_read_prph(priv, reg);
  4258. if (val != le32_to_cpu(*image)) {
  4259. IWL_ERROR("BSM uCode verification failed at "
  4260. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4261. BSM_SRAM_LOWER_BOUND,
  4262. reg - BSM_SRAM_LOWER_BOUND, len,
  4263. val, le32_to_cpu(*image));
  4264. return -EIO;
  4265. }
  4266. }
  4267. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4268. return 0;
  4269. }
  4270. /**
  4271. * iwl3945_load_bsm - Load bootstrap instructions
  4272. *
  4273. * BSM operation:
  4274. *
  4275. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4276. * in special SRAM that does not power down during RFKILL. When powering back
  4277. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4278. * the bootstrap program into the on-board processor, and starts it.
  4279. *
  4280. * The bootstrap program loads (via DMA) instructions and data for a new
  4281. * program from host DRAM locations indicated by the host driver in the
  4282. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4283. * automatically.
  4284. *
  4285. * When initializing the NIC, the host driver points the BSM to the
  4286. * "initialize" uCode image. This uCode sets up some internal data, then
  4287. * notifies host via "initialize alive" that it is complete.
  4288. *
  4289. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4290. * normal runtime uCode instructions and a backup uCode data cache buffer
  4291. * (filled initially with starting data values for the on-board processor),
  4292. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4293. * which begins normal operation.
  4294. *
  4295. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4296. * the backup data cache in DRAM before SRAM is powered down.
  4297. *
  4298. * When powering back up, the BSM loads the bootstrap program. This reloads
  4299. * the runtime uCode instructions and the backup data cache into SRAM,
  4300. * and re-launches the runtime uCode from where it left off.
  4301. */
  4302. static int iwl3945_load_bsm(struct iwl_priv *priv)
  4303. {
  4304. __le32 *image = priv->ucode_boot.v_addr;
  4305. u32 len = priv->ucode_boot.len;
  4306. dma_addr_t pinst;
  4307. dma_addr_t pdata;
  4308. u32 inst_len;
  4309. u32 data_len;
  4310. int rc;
  4311. int i;
  4312. u32 done;
  4313. u32 reg_offset;
  4314. IWL_DEBUG_INFO("Begin load bsm\n");
  4315. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4316. if (len > IWL39_MAX_BSM_SIZE)
  4317. return -EINVAL;
  4318. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4319. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4320. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4321. * after the "initialize" uCode has run, to point to
  4322. * runtime/protocol instructions and backup data cache. */
  4323. pinst = priv->ucode_init.p_addr;
  4324. pdata = priv->ucode_init_data.p_addr;
  4325. inst_len = priv->ucode_init.len;
  4326. data_len = priv->ucode_init_data.len;
  4327. rc = iwl_grab_nic_access(priv);
  4328. if (rc)
  4329. return rc;
  4330. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4331. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4332. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4333. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4334. /* Fill BSM memory with bootstrap instructions */
  4335. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4336. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4337. reg_offset += sizeof(u32), image++)
  4338. _iwl_write_prph(priv, reg_offset,
  4339. le32_to_cpu(*image));
  4340. rc = iwl3945_verify_bsm(priv);
  4341. if (rc) {
  4342. iwl_release_nic_access(priv);
  4343. return rc;
  4344. }
  4345. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4346. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4347. iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
  4348. IWL39_RTC_INST_LOWER_BOUND);
  4349. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4350. /* Load bootstrap code into instruction SRAM now,
  4351. * to prepare to load "initialize" uCode */
  4352. iwl_write_prph(priv, BSM_WR_CTRL_REG,
  4353. BSM_WR_CTRL_REG_BIT_START);
  4354. /* Wait for load of bootstrap uCode to finish */
  4355. for (i = 0; i < 100; i++) {
  4356. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  4357. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4358. break;
  4359. udelay(10);
  4360. }
  4361. if (i < 100)
  4362. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4363. else {
  4364. IWL_ERROR("BSM write did not complete!\n");
  4365. return -EIO;
  4366. }
  4367. /* Enable future boot loads whenever power management unit triggers it
  4368. * (e.g. when powering back up after power-save shutdown) */
  4369. iwl_write_prph(priv, BSM_WR_CTRL_REG,
  4370. BSM_WR_CTRL_REG_BIT_START_EN);
  4371. iwl_release_nic_access(priv);
  4372. return 0;
  4373. }
  4374. static void iwl3945_nic_start(struct iwl_priv *priv)
  4375. {
  4376. /* Remove all resets to allow NIC to operate */
  4377. iwl_write32(priv, CSR_RESET, 0);
  4378. }
  4379. /**
  4380. * iwl3945_read_ucode - Read uCode images from disk file.
  4381. *
  4382. * Copy into buffers for card to fetch via bus-mastering
  4383. */
  4384. static int iwl3945_read_ucode(struct iwl_priv *priv)
  4385. {
  4386. struct iwl_ucode *ucode;
  4387. int ret = -EINVAL, index;
  4388. const struct firmware *ucode_raw;
  4389. /* firmware file name contains uCode/driver compatibility version */
  4390. const char *name_pre = priv->cfg->fw_name_pre;
  4391. const unsigned int api_max = priv->cfg->ucode_api_max;
  4392. const unsigned int api_min = priv->cfg->ucode_api_min;
  4393. char buf[25];
  4394. u8 *src;
  4395. size_t len;
  4396. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4397. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4398. * request_firmware() is synchronous, file is in memory on return. */
  4399. for (index = api_max; index >= api_min; index--) {
  4400. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4401. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4402. if (ret < 0) {
  4403. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4404. buf, ret);
  4405. if (ret == -ENOENT)
  4406. continue;
  4407. else
  4408. goto error;
  4409. } else {
  4410. if (index < api_max)
  4411. IWL_ERROR("Loaded firmware %s, which is deprecated. Please use API v%u instead.\n",
  4412. buf, api_max);
  4413. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4414. buf, ucode_raw->size);
  4415. break;
  4416. }
  4417. }
  4418. if (ret < 0)
  4419. goto error;
  4420. /* Make sure that we got at least our header! */
  4421. if (ucode_raw->size < sizeof(*ucode)) {
  4422. IWL_ERROR("File size way too small!\n");
  4423. ret = -EINVAL;
  4424. goto err_release;
  4425. }
  4426. /* Data from ucode file: header followed by uCode images */
  4427. ucode = (void *)ucode_raw->data;
  4428. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4429. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4430. inst_size = le32_to_cpu(ucode->inst_size);
  4431. data_size = le32_to_cpu(ucode->data_size);
  4432. init_size = le32_to_cpu(ucode->init_size);
  4433. init_data_size = le32_to_cpu(ucode->init_data_size);
  4434. boot_size = le32_to_cpu(ucode->boot_size);
  4435. /* api_ver should match the api version forming part of the
  4436. * firmware filename ... but we don't check for that and only rely
  4437. * on the API version read from firware header from here on forward */
  4438. if (api_ver < api_min || api_ver > api_max) {
  4439. IWL_ERROR("Driver unable to support your firmware API. "
  4440. "Driver supports v%u, firmware is v%u.\n",
  4441. api_max, api_ver);
  4442. priv->ucode_ver = 0;
  4443. ret = -EINVAL;
  4444. goto err_release;
  4445. }
  4446. if (api_ver != api_max)
  4447. IWL_ERROR("Firmware has old API version. Expected %u, "
  4448. "got %u. New firmware can be obtained "
  4449. "from http://www.intellinuxwireless.org.\n",
  4450. api_max, api_ver);
  4451. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  4452. IWL_UCODE_MAJOR(priv->ucode_ver),
  4453. IWL_UCODE_MINOR(priv->ucode_ver),
  4454. IWL_UCODE_API(priv->ucode_ver),
  4455. IWL_UCODE_SERIAL(priv->ucode_ver));
  4456. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4457. priv->ucode_ver);
  4458. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4459. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4460. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4461. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4462. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4463. /* Verify size of file vs. image size info in file's header */
  4464. if (ucode_raw->size < sizeof(*ucode) +
  4465. inst_size + data_size + init_size +
  4466. init_data_size + boot_size) {
  4467. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4468. (int)ucode_raw->size);
  4469. ret = -EINVAL;
  4470. goto err_release;
  4471. }
  4472. /* Verify that uCode images will fit in card's SRAM */
  4473. if (inst_size > IWL39_MAX_INST_SIZE) {
  4474. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4475. inst_size);
  4476. ret = -EINVAL;
  4477. goto err_release;
  4478. }
  4479. if (data_size > IWL39_MAX_DATA_SIZE) {
  4480. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4481. data_size);
  4482. ret = -EINVAL;
  4483. goto err_release;
  4484. }
  4485. if (init_size > IWL39_MAX_INST_SIZE) {
  4486. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4487. init_size);
  4488. ret = -EINVAL;
  4489. goto err_release;
  4490. }
  4491. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  4492. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4493. init_data_size);
  4494. ret = -EINVAL;
  4495. goto err_release;
  4496. }
  4497. if (boot_size > IWL39_MAX_BSM_SIZE) {
  4498. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4499. boot_size);
  4500. ret = -EINVAL;
  4501. goto err_release;
  4502. }
  4503. /* Allocate ucode buffers for card's bus-master loading ... */
  4504. /* Runtime instructions and 2 copies of data:
  4505. * 1) unmodified from disk
  4506. * 2) backup cache for save/restore during power-downs */
  4507. priv->ucode_code.len = inst_size;
  4508. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4509. priv->ucode_data.len = data_size;
  4510. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4511. priv->ucode_data_backup.len = data_size;
  4512. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4513. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4514. !priv->ucode_data_backup.v_addr)
  4515. goto err_pci_alloc;
  4516. /* Initialization instructions and data */
  4517. if (init_size && init_data_size) {
  4518. priv->ucode_init.len = init_size;
  4519. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4520. priv->ucode_init_data.len = init_data_size;
  4521. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4522. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4523. goto err_pci_alloc;
  4524. }
  4525. /* Bootstrap (instructions only, no data) */
  4526. if (boot_size) {
  4527. priv->ucode_boot.len = boot_size;
  4528. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4529. if (!priv->ucode_boot.v_addr)
  4530. goto err_pci_alloc;
  4531. }
  4532. /* Copy images into buffers for card's bus-master reads ... */
  4533. /* Runtime instructions (first block of data in file) */
  4534. src = &ucode->data[0];
  4535. len = priv->ucode_code.len;
  4536. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4537. memcpy(priv->ucode_code.v_addr, src, len);
  4538. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4539. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4540. /* Runtime data (2nd block)
  4541. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4542. src = &ucode->data[inst_size];
  4543. len = priv->ucode_data.len;
  4544. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4545. memcpy(priv->ucode_data.v_addr, src, len);
  4546. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4547. /* Initialization instructions (3rd block) */
  4548. if (init_size) {
  4549. src = &ucode->data[inst_size + data_size];
  4550. len = priv->ucode_init.len;
  4551. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4552. len);
  4553. memcpy(priv->ucode_init.v_addr, src, len);
  4554. }
  4555. /* Initialization data (4th block) */
  4556. if (init_data_size) {
  4557. src = &ucode->data[inst_size + data_size + init_size];
  4558. len = priv->ucode_init_data.len;
  4559. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4560. (int)len);
  4561. memcpy(priv->ucode_init_data.v_addr, src, len);
  4562. }
  4563. /* Bootstrap instructions (5th block) */
  4564. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4565. len = priv->ucode_boot.len;
  4566. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4567. (int)len);
  4568. memcpy(priv->ucode_boot.v_addr, src, len);
  4569. /* We have our copies now, allow OS release its copies */
  4570. release_firmware(ucode_raw);
  4571. return 0;
  4572. err_pci_alloc:
  4573. IWL_ERROR("failed to allocate pci memory\n");
  4574. ret = -ENOMEM;
  4575. iwl3945_dealloc_ucode_pci(priv);
  4576. err_release:
  4577. release_firmware(ucode_raw);
  4578. error:
  4579. return ret;
  4580. }
  4581. /**
  4582. * iwl3945_set_ucode_ptrs - Set uCode address location
  4583. *
  4584. * Tell initialization uCode where to find runtime uCode.
  4585. *
  4586. * BSM registers initially contain pointers to initialization uCode.
  4587. * We need to replace them to load runtime uCode inst and data,
  4588. * and to save runtime data when powering down.
  4589. */
  4590. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  4591. {
  4592. dma_addr_t pinst;
  4593. dma_addr_t pdata;
  4594. int rc = 0;
  4595. unsigned long flags;
  4596. /* bits 31:0 for 3945 */
  4597. pinst = priv->ucode_code.p_addr;
  4598. pdata = priv->ucode_data_backup.p_addr;
  4599. spin_lock_irqsave(&priv->lock, flags);
  4600. rc = iwl_grab_nic_access(priv);
  4601. if (rc) {
  4602. spin_unlock_irqrestore(&priv->lock, flags);
  4603. return rc;
  4604. }
  4605. /* Tell bootstrap uCode where to find image to load */
  4606. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4607. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4608. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4609. priv->ucode_data.len);
  4610. /* Inst byte count must be last to set up, bit 31 signals uCode
  4611. * that all new ptr/size info is in place */
  4612. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4613. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4614. iwl_release_nic_access(priv);
  4615. spin_unlock_irqrestore(&priv->lock, flags);
  4616. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4617. return rc;
  4618. }
  4619. /**
  4620. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4621. *
  4622. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4623. *
  4624. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4625. */
  4626. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  4627. {
  4628. /* Check alive response for "valid" sign from uCode */
  4629. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4630. /* We had an error bringing up the hardware, so take it
  4631. * all the way back down so we can try again */
  4632. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4633. goto restart;
  4634. }
  4635. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4636. * This is a paranoid check, because we would not have gotten the
  4637. * "initialize" alive if code weren't properly loaded. */
  4638. if (iwl3945_verify_ucode(priv)) {
  4639. /* Runtime instruction load was bad;
  4640. * take it all the way back down so we can try again */
  4641. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4642. goto restart;
  4643. }
  4644. /* Send pointers to protocol/runtime uCode image ... init code will
  4645. * load and launch runtime uCode, which will send us another "Alive"
  4646. * notification. */
  4647. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4648. if (iwl3945_set_ucode_ptrs(priv)) {
  4649. /* Runtime instruction load won't happen;
  4650. * take it all the way back down so we can try again */
  4651. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4652. goto restart;
  4653. }
  4654. return;
  4655. restart:
  4656. queue_work(priv->workqueue, &priv->restart);
  4657. }
  4658. /* temporary */
  4659. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4660. struct sk_buff *skb);
  4661. /**
  4662. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4663. * from protocol/runtime uCode (initialization uCode's
  4664. * Alive gets handled by iwl3945_init_alive_start()).
  4665. */
  4666. static void iwl3945_alive_start(struct iwl_priv *priv)
  4667. {
  4668. int rc = 0;
  4669. int thermal_spin = 0;
  4670. u32 rfkill;
  4671. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4672. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4673. /* We had an error bringing up the hardware, so take it
  4674. * all the way back down so we can try again */
  4675. IWL_DEBUG_INFO("Alive failed.\n");
  4676. goto restart;
  4677. }
  4678. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4679. * This is a paranoid check, because we would not have gotten the
  4680. * "runtime" alive if code weren't properly loaded. */
  4681. if (iwl3945_verify_ucode(priv)) {
  4682. /* Runtime instruction load was bad;
  4683. * take it all the way back down so we can try again */
  4684. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4685. goto restart;
  4686. }
  4687. iwl3945_clear_stations_table(priv);
  4688. rc = iwl_grab_nic_access(priv);
  4689. if (rc) {
  4690. IWL_WARNING("Can not read RFKILL status from adapter\n");
  4691. return;
  4692. }
  4693. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  4694. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4695. iwl_release_nic_access(priv);
  4696. if (rfkill & 0x1) {
  4697. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4698. /* if RFKILL is not on, then wait for thermal
  4699. * sensor in adapter to kick in */
  4700. while (iwl3945_hw_get_temperature(priv) == 0) {
  4701. thermal_spin++;
  4702. udelay(10);
  4703. }
  4704. if (thermal_spin)
  4705. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4706. thermal_spin * 10);
  4707. } else
  4708. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4709. /* After the ALIVE response, we can send commands to 3945 uCode */
  4710. set_bit(STATUS_ALIVE, &priv->status);
  4711. /* Clear out the uCode error bit if it is set */
  4712. clear_bit(STATUS_FW_ERROR, &priv->status);
  4713. if (iwl3945_is_rfkill(priv))
  4714. return;
  4715. ieee80211_wake_queues(priv->hw);
  4716. priv->active_rate = priv->rates_mask;
  4717. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4718. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4719. if (iwl3945_is_associated(priv)) {
  4720. struct iwl3945_rxon_cmd *active_rxon =
  4721. (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
  4722. memcpy(&priv->staging39_rxon, &priv->active39_rxon,
  4723. sizeof(priv->staging39_rxon));
  4724. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4725. } else {
  4726. /* Initialize our rx_config data */
  4727. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4728. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4729. }
  4730. /* Configure Bluetooth device coexistence support */
  4731. iwl3945_send_bt_config(priv);
  4732. /* Configure the adapter for unassociated operation */
  4733. iwl3945_commit_rxon(priv);
  4734. iwl3945_reg_txpower_periodic(priv);
  4735. iwl3945_led_register(priv);
  4736. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4737. set_bit(STATUS_READY, &priv->status);
  4738. wake_up_interruptible(&priv->wait_command_queue);
  4739. if (priv->error_recovering)
  4740. iwl3945_error_recovery(priv);
  4741. /* reassociate for ADHOC mode */
  4742. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4743. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4744. priv->vif);
  4745. if (beacon)
  4746. iwl3945_mac_beacon_update(priv->hw, beacon);
  4747. }
  4748. return;
  4749. restart:
  4750. queue_work(priv->workqueue, &priv->restart);
  4751. }
  4752. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  4753. static void __iwl3945_down(struct iwl_priv *priv)
  4754. {
  4755. unsigned long flags;
  4756. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4757. struct ieee80211_conf *conf = NULL;
  4758. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4759. conf = ieee80211_get_hw_conf(priv->hw);
  4760. if (!exit_pending)
  4761. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4762. iwl3945_led_unregister(priv);
  4763. iwl3945_clear_stations_table(priv);
  4764. /* Unblock any waiting calls */
  4765. wake_up_interruptible_all(&priv->wait_command_queue);
  4766. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4767. * exiting the module */
  4768. if (!exit_pending)
  4769. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4770. /* stop and reset the on-board processor */
  4771. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4772. /* tell the device to stop sending interrupts */
  4773. spin_lock_irqsave(&priv->lock, flags);
  4774. iwl3945_disable_interrupts(priv);
  4775. spin_unlock_irqrestore(&priv->lock, flags);
  4776. iwl_synchronize_irq(priv);
  4777. if (priv->mac80211_registered)
  4778. ieee80211_stop_queues(priv->hw);
  4779. /* If we have not previously called iwl3945_init() then
  4780. * clear all bits but the RF Kill and SUSPEND bits and return */
  4781. if (!iwl3945_is_init(priv)) {
  4782. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4783. STATUS_RF_KILL_HW |
  4784. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4785. STATUS_RF_KILL_SW |
  4786. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4787. STATUS_GEO_CONFIGURED |
  4788. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4789. STATUS_IN_SUSPEND |
  4790. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4791. STATUS_EXIT_PENDING;
  4792. goto exit;
  4793. }
  4794. /* ...otherwise clear out all the status bits but the RF Kill and
  4795. * SUSPEND bits and continue taking the NIC down. */
  4796. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4797. STATUS_RF_KILL_HW |
  4798. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4799. STATUS_RF_KILL_SW |
  4800. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4801. STATUS_GEO_CONFIGURED |
  4802. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4803. STATUS_IN_SUSPEND |
  4804. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4805. STATUS_FW_ERROR |
  4806. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4807. STATUS_EXIT_PENDING;
  4808. spin_lock_irqsave(&priv->lock, flags);
  4809. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4810. spin_unlock_irqrestore(&priv->lock, flags);
  4811. iwl3945_hw_txq_ctx_stop(priv);
  4812. iwl3945_hw_rxq_stop(priv);
  4813. spin_lock_irqsave(&priv->lock, flags);
  4814. if (!iwl_grab_nic_access(priv)) {
  4815. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  4816. APMG_CLK_VAL_DMA_CLK_RQT);
  4817. iwl_release_nic_access(priv);
  4818. }
  4819. spin_unlock_irqrestore(&priv->lock, flags);
  4820. udelay(5);
  4821. iwl3945_hw_nic_stop_master(priv);
  4822. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4823. iwl3945_hw_nic_reset(priv);
  4824. exit:
  4825. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4826. if (priv->ibss_beacon)
  4827. dev_kfree_skb(priv->ibss_beacon);
  4828. priv->ibss_beacon = NULL;
  4829. /* clear out any free frames */
  4830. iwl3945_clear_free_frames(priv);
  4831. }
  4832. static void iwl3945_down(struct iwl_priv *priv)
  4833. {
  4834. mutex_lock(&priv->mutex);
  4835. __iwl3945_down(priv);
  4836. mutex_unlock(&priv->mutex);
  4837. iwl3945_cancel_deferred_work(priv);
  4838. }
  4839. #define MAX_HW_RESTARTS 5
  4840. static int __iwl3945_up(struct iwl_priv *priv)
  4841. {
  4842. int rc, i;
  4843. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4844. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  4845. return -EIO;
  4846. }
  4847. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4848. IWL_WARNING("Radio disabled by SW RF kill (module "
  4849. "parameter)\n");
  4850. return -ENODEV;
  4851. }
  4852. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4853. IWL_ERROR("ucode not available for device bring up\n");
  4854. return -EIO;
  4855. }
  4856. /* If platform's RF_KILL switch is NOT set to KILL */
  4857. if (iwl_read32(priv, CSR_GP_CNTRL) &
  4858. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4859. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4860. else {
  4861. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4862. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4863. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  4864. return -ENODEV;
  4865. }
  4866. }
  4867. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4868. rc = iwl3945_hw_nic_init(priv);
  4869. if (rc) {
  4870. IWL_ERROR("Unable to int nic\n");
  4871. return rc;
  4872. }
  4873. /* make sure rfkill handshake bits are cleared */
  4874. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4875. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4876. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4877. /* clear (again), then enable host interrupts */
  4878. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4879. iwl3945_enable_interrupts(priv);
  4880. /* really make sure rfkill handshake bits are cleared */
  4881. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4882. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4883. /* Copy original ucode data image from disk into backup cache.
  4884. * This will be used to initialize the on-board processor's
  4885. * data SRAM for a clean start when the runtime program first loads. */
  4886. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4887. priv->ucode_data.len);
  4888. /* We return success when we resume from suspend and rf_kill is on. */
  4889. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4890. return 0;
  4891. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4892. iwl3945_clear_stations_table(priv);
  4893. /* load bootstrap state machine,
  4894. * load bootstrap program into processor's memory,
  4895. * prepare to load the "initialize" uCode */
  4896. rc = iwl3945_load_bsm(priv);
  4897. if (rc) {
  4898. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  4899. continue;
  4900. }
  4901. /* start card; "initialize" will load runtime ucode */
  4902. iwl3945_nic_start(priv);
  4903. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4904. return 0;
  4905. }
  4906. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4907. __iwl3945_down(priv);
  4908. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4909. /* tried to restart and config the device for as long as our
  4910. * patience could withstand */
  4911. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  4912. return -EIO;
  4913. }
  4914. /*****************************************************************************
  4915. *
  4916. * Workqueue callbacks
  4917. *
  4918. *****************************************************************************/
  4919. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4920. {
  4921. struct iwl_priv *priv =
  4922. container_of(data, struct iwl_priv, init_alive_start.work);
  4923. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4924. return;
  4925. mutex_lock(&priv->mutex);
  4926. iwl3945_init_alive_start(priv);
  4927. mutex_unlock(&priv->mutex);
  4928. }
  4929. static void iwl3945_bg_alive_start(struct work_struct *data)
  4930. {
  4931. struct iwl_priv *priv =
  4932. container_of(data, struct iwl_priv, alive_start.work);
  4933. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4934. return;
  4935. mutex_lock(&priv->mutex);
  4936. iwl3945_alive_start(priv);
  4937. mutex_unlock(&priv->mutex);
  4938. }
  4939. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4940. {
  4941. struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
  4942. wake_up_interruptible(&priv->wait_command_queue);
  4943. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4944. return;
  4945. mutex_lock(&priv->mutex);
  4946. if (!iwl3945_is_rfkill(priv)) {
  4947. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4948. "HW and/or SW RF Kill no longer active, restarting "
  4949. "device\n");
  4950. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4951. queue_work(priv->workqueue, &priv->restart);
  4952. } else {
  4953. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4954. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4955. "disabled by SW switch\n");
  4956. else
  4957. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  4958. "Kill switch must be turned off for "
  4959. "wireless networking to work.\n");
  4960. }
  4961. mutex_unlock(&priv->mutex);
  4962. iwl3945_rfkill_set_hw_state(priv);
  4963. }
  4964. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4965. static void iwl3945_bg_scan_check(struct work_struct *data)
  4966. {
  4967. struct iwl_priv *priv =
  4968. container_of(data, struct iwl_priv, scan_check.work);
  4969. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4970. return;
  4971. mutex_lock(&priv->mutex);
  4972. if (test_bit(STATUS_SCANNING, &priv->status) ||
  4973. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4974. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  4975. "Scan completion watchdog resetting adapter (%dms)\n",
  4976. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  4977. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4978. iwl3945_send_scan_abort(priv);
  4979. }
  4980. mutex_unlock(&priv->mutex);
  4981. }
  4982. static void iwl3945_bg_request_scan(struct work_struct *data)
  4983. {
  4984. struct iwl_priv *priv =
  4985. container_of(data, struct iwl_priv, request_scan);
  4986. struct iwl3945_host_cmd cmd = {
  4987. .id = REPLY_SCAN_CMD,
  4988. .len = sizeof(struct iwl3945_scan_cmd),
  4989. .meta.flags = CMD_SIZE_HUGE,
  4990. };
  4991. int rc = 0;
  4992. struct iwl3945_scan_cmd *scan;
  4993. struct ieee80211_conf *conf = NULL;
  4994. u8 n_probes = 2;
  4995. enum ieee80211_band band;
  4996. DECLARE_SSID_BUF(ssid);
  4997. conf = ieee80211_get_hw_conf(priv->hw);
  4998. mutex_lock(&priv->mutex);
  4999. if (!iwl3945_is_ready(priv)) {
  5000. IWL_WARNING("request scan called when driver not ready.\n");
  5001. goto done;
  5002. }
  5003. /* Make sure the scan wasn't canceled before this queued work
  5004. * was given the chance to run... */
  5005. if (!test_bit(STATUS_SCANNING, &priv->status))
  5006. goto done;
  5007. /* This should never be called or scheduled if there is currently
  5008. * a scan active in the hardware. */
  5009. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5010. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5011. "Ignoring second request.\n");
  5012. rc = -EIO;
  5013. goto done;
  5014. }
  5015. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5016. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5017. goto done;
  5018. }
  5019. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5020. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5021. goto done;
  5022. }
  5023. if (iwl3945_is_rfkill(priv)) {
  5024. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5025. goto done;
  5026. }
  5027. if (!test_bit(STATUS_READY, &priv->status)) {
  5028. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5029. goto done;
  5030. }
  5031. if (!priv->scan_bands) {
  5032. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5033. goto done;
  5034. }
  5035. if (!priv->scan39) {
  5036. priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5037. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5038. if (!priv->scan39) {
  5039. rc = -ENOMEM;
  5040. goto done;
  5041. }
  5042. }
  5043. scan = priv->scan39;
  5044. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5045. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5046. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5047. if (iwl3945_is_associated(priv)) {
  5048. u16 interval = 0;
  5049. u32 extra;
  5050. u32 suspend_time = 100;
  5051. u32 scan_suspend_time = 100;
  5052. unsigned long flags;
  5053. IWL_DEBUG_INFO("Scanning while associated...\n");
  5054. spin_lock_irqsave(&priv->lock, flags);
  5055. interval = priv->beacon_int;
  5056. spin_unlock_irqrestore(&priv->lock, flags);
  5057. scan->suspend_time = 0;
  5058. scan->max_out_time = cpu_to_le32(200 * 1024);
  5059. if (!interval)
  5060. interval = suspend_time;
  5061. /*
  5062. * suspend time format:
  5063. * 0-19: beacon interval in usec (time before exec.)
  5064. * 20-23: 0
  5065. * 24-31: number of beacons (suspend between channels)
  5066. */
  5067. extra = (suspend_time / interval) << 24;
  5068. scan_suspend_time = 0xFF0FFFFF &
  5069. (extra | ((suspend_time % interval) * 1024));
  5070. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5071. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5072. scan_suspend_time, interval);
  5073. }
  5074. /* We should add the ability for user to lock to PASSIVE ONLY */
  5075. if (priv->one_direct_scan) {
  5076. IWL_DEBUG_SCAN
  5077. ("Kicking off one direct scan for '%s'\n",
  5078. print_ssid(ssid, priv->direct_ssid,
  5079. priv->direct_ssid_len));
  5080. scan->direct_scan[0].id = WLAN_EID_SSID;
  5081. scan->direct_scan[0].len = priv->direct_ssid_len;
  5082. memcpy(scan->direct_scan[0].ssid,
  5083. priv->direct_ssid, priv->direct_ssid_len);
  5084. n_probes++;
  5085. } else
  5086. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5087. /* We don't build a direct scan probe request; the uCode will do
  5088. * that based on the direct_mask added to each channel entry */
  5089. scan->tx_cmd.len = cpu_to_le16(
  5090. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5091. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  5092. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5093. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  5094. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5095. /* flags + rate selection */
  5096. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5097. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5098. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5099. scan->good_CRC_th = 0;
  5100. band = IEEE80211_BAND_2GHZ;
  5101. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5102. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5103. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5104. band = IEEE80211_BAND_5GHZ;
  5105. } else {
  5106. IWL_WARNING("Invalid scan band count\n");
  5107. goto done;
  5108. }
  5109. /* select Rx antennas */
  5110. scan->flags |= iwl3945_get_antenna_flags(priv);
  5111. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  5112. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5113. scan->channel_count =
  5114. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  5115. n_probes,
  5116. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5117. if (scan->channel_count == 0) {
  5118. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  5119. goto done;
  5120. }
  5121. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5122. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5123. cmd.data = scan;
  5124. scan->len = cpu_to_le16(cmd.len);
  5125. set_bit(STATUS_SCAN_HW, &priv->status);
  5126. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5127. if (rc)
  5128. goto done;
  5129. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5130. IWL_SCAN_CHECK_WATCHDOG);
  5131. mutex_unlock(&priv->mutex);
  5132. return;
  5133. done:
  5134. /* can not perform scan make sure we clear scanning
  5135. * bits from status so next scan request can be performed.
  5136. * if we dont clear scanning status bit here all next scan
  5137. * will fail
  5138. */
  5139. clear_bit(STATUS_SCAN_HW, &priv->status);
  5140. clear_bit(STATUS_SCANNING, &priv->status);
  5141. /* inform mac80211 scan aborted */
  5142. queue_work(priv->workqueue, &priv->scan_completed);
  5143. mutex_unlock(&priv->mutex);
  5144. }
  5145. static void iwl3945_bg_up(struct work_struct *data)
  5146. {
  5147. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  5148. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5149. return;
  5150. mutex_lock(&priv->mutex);
  5151. __iwl3945_up(priv);
  5152. mutex_unlock(&priv->mutex);
  5153. iwl3945_rfkill_set_hw_state(priv);
  5154. }
  5155. static void iwl3945_bg_restart(struct work_struct *data)
  5156. {
  5157. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  5158. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5159. return;
  5160. iwl3945_down(priv);
  5161. queue_work(priv->workqueue, &priv->up);
  5162. }
  5163. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5164. {
  5165. struct iwl_priv *priv =
  5166. container_of(data, struct iwl_priv, rx_replenish);
  5167. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5168. return;
  5169. mutex_lock(&priv->mutex);
  5170. iwl3945_rx_replenish(priv);
  5171. mutex_unlock(&priv->mutex);
  5172. }
  5173. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5174. static void iwl3945_post_associate(struct iwl_priv *priv)
  5175. {
  5176. int rc = 0;
  5177. struct ieee80211_conf *conf = NULL;
  5178. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5179. IWL_ERROR("%s Should not be called in AP mode\n", __func__);
  5180. return;
  5181. }
  5182. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  5183. priv->assoc_id, priv->active39_rxon.bssid_addr);
  5184. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5185. return;
  5186. if (!priv->vif || !priv->is_open)
  5187. return;
  5188. iwl3945_scan_cancel_timeout(priv, 200);
  5189. conf = ieee80211_get_hw_conf(priv->hw);
  5190. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5191. iwl3945_commit_rxon(priv);
  5192. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5193. iwl3945_setup_rxon_timing(priv);
  5194. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5195. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5196. if (rc)
  5197. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5198. "Attempting to continue.\n");
  5199. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5200. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5201. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5202. priv->assoc_id, priv->beacon_int);
  5203. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5204. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5205. else
  5206. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5207. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5208. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5209. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5210. else
  5211. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5212. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5213. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5214. }
  5215. iwl3945_commit_rxon(priv);
  5216. switch (priv->iw_mode) {
  5217. case NL80211_IFTYPE_STATION:
  5218. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5219. break;
  5220. case NL80211_IFTYPE_ADHOC:
  5221. priv->assoc_id = 1;
  5222. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5223. iwl3945_sync_sta(priv, IWL_STA_ID,
  5224. (priv->band == IEEE80211_BAND_5GHZ) ?
  5225. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5226. CMD_ASYNC);
  5227. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5228. iwl3945_send_beacon_cmd(priv);
  5229. break;
  5230. default:
  5231. IWL_ERROR("%s Should not be called in %d mode\n",
  5232. __func__, priv->iw_mode);
  5233. break;
  5234. }
  5235. iwl3945_activate_qos(priv, 0);
  5236. /* we have just associated, don't start scan too early */
  5237. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5238. }
  5239. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5240. {
  5241. struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
  5242. if (!iwl3945_is_ready(priv))
  5243. return;
  5244. mutex_lock(&priv->mutex);
  5245. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5246. iwl3945_send_scan_abort(priv);
  5247. mutex_unlock(&priv->mutex);
  5248. }
  5249. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  5250. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5251. {
  5252. struct iwl_priv *priv =
  5253. container_of(work, struct iwl_priv, scan_completed);
  5254. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5255. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5256. return;
  5257. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5258. iwl3945_mac_config(priv->hw, 0);
  5259. ieee80211_scan_completed(priv->hw);
  5260. /* Since setting the TXPOWER may have been deferred while
  5261. * performing the scan, fire one off */
  5262. mutex_lock(&priv->mutex);
  5263. iwl3945_hw_reg_send_txpower(priv);
  5264. mutex_unlock(&priv->mutex);
  5265. }
  5266. /*****************************************************************************
  5267. *
  5268. * mac80211 entry point functions
  5269. *
  5270. *****************************************************************************/
  5271. #define UCODE_READY_TIMEOUT (2 * HZ)
  5272. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5273. {
  5274. struct iwl_priv *priv = hw->priv;
  5275. int ret;
  5276. IWL_DEBUG_MAC80211("enter\n");
  5277. if (pci_enable_device(priv->pci_dev)) {
  5278. IWL_ERROR("Fail to pci_enable_device\n");
  5279. return -ENODEV;
  5280. }
  5281. pci_restore_state(priv->pci_dev);
  5282. pci_enable_msi(priv->pci_dev);
  5283. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5284. DRV_NAME, priv);
  5285. if (ret) {
  5286. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5287. goto out_disable_msi;
  5288. }
  5289. /* we should be verifying the device is ready to be opened */
  5290. mutex_lock(&priv->mutex);
  5291. memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5292. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5293. * ucode filename and max sizes are card-specific. */
  5294. if (!priv->ucode_code.len) {
  5295. ret = iwl3945_read_ucode(priv);
  5296. if (ret) {
  5297. IWL_ERROR("Could not read microcode: %d\n", ret);
  5298. mutex_unlock(&priv->mutex);
  5299. goto out_release_irq;
  5300. }
  5301. }
  5302. ret = __iwl3945_up(priv);
  5303. mutex_unlock(&priv->mutex);
  5304. iwl3945_rfkill_set_hw_state(priv);
  5305. if (ret)
  5306. goto out_release_irq;
  5307. IWL_DEBUG_INFO("Start UP work.\n");
  5308. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5309. return 0;
  5310. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5311. * mac80211 will not be run successfully. */
  5312. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5313. test_bit(STATUS_READY, &priv->status),
  5314. UCODE_READY_TIMEOUT);
  5315. if (!ret) {
  5316. if (!test_bit(STATUS_READY, &priv->status)) {
  5317. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5318. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5319. ret = -ETIMEDOUT;
  5320. goto out_release_irq;
  5321. }
  5322. }
  5323. priv->is_open = 1;
  5324. IWL_DEBUG_MAC80211("leave\n");
  5325. return 0;
  5326. out_release_irq:
  5327. free_irq(priv->pci_dev->irq, priv);
  5328. out_disable_msi:
  5329. pci_disable_msi(priv->pci_dev);
  5330. pci_disable_device(priv->pci_dev);
  5331. priv->is_open = 0;
  5332. IWL_DEBUG_MAC80211("leave - failed\n");
  5333. return ret;
  5334. }
  5335. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5336. {
  5337. struct iwl_priv *priv = hw->priv;
  5338. IWL_DEBUG_MAC80211("enter\n");
  5339. if (!priv->is_open) {
  5340. IWL_DEBUG_MAC80211("leave - skip\n");
  5341. return;
  5342. }
  5343. priv->is_open = 0;
  5344. if (iwl3945_is_ready_rf(priv)) {
  5345. /* stop mac, cancel any scan request and clear
  5346. * RXON_FILTER_ASSOC_MSK BIT
  5347. */
  5348. mutex_lock(&priv->mutex);
  5349. iwl3945_scan_cancel_timeout(priv, 100);
  5350. mutex_unlock(&priv->mutex);
  5351. }
  5352. iwl3945_down(priv);
  5353. flush_workqueue(priv->workqueue);
  5354. free_irq(priv->pci_dev->irq, priv);
  5355. pci_disable_msi(priv->pci_dev);
  5356. pci_save_state(priv->pci_dev);
  5357. pci_disable_device(priv->pci_dev);
  5358. IWL_DEBUG_MAC80211("leave\n");
  5359. }
  5360. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5361. {
  5362. struct iwl_priv *priv = hw->priv;
  5363. IWL_DEBUG_MAC80211("enter\n");
  5364. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5365. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5366. if (iwl3945_tx_skb(priv, skb))
  5367. dev_kfree_skb_any(skb);
  5368. IWL_DEBUG_MAC80211("leave\n");
  5369. return NETDEV_TX_OK;
  5370. }
  5371. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5372. struct ieee80211_if_init_conf *conf)
  5373. {
  5374. struct iwl_priv *priv = hw->priv;
  5375. unsigned long flags;
  5376. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5377. if (priv->vif) {
  5378. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5379. return -EOPNOTSUPP;
  5380. }
  5381. spin_lock_irqsave(&priv->lock, flags);
  5382. priv->vif = conf->vif;
  5383. priv->iw_mode = conf->type;
  5384. spin_unlock_irqrestore(&priv->lock, flags);
  5385. mutex_lock(&priv->mutex);
  5386. if (conf->mac_addr) {
  5387. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5388. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5389. }
  5390. if (iwl3945_is_ready(priv))
  5391. iwl3945_set_mode(priv, conf->type);
  5392. mutex_unlock(&priv->mutex);
  5393. IWL_DEBUG_MAC80211("leave\n");
  5394. return 0;
  5395. }
  5396. /**
  5397. * iwl3945_mac_config - mac80211 config callback
  5398. *
  5399. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5400. * be set inappropriately and the driver currently sets the hardware up to
  5401. * use it whenever needed.
  5402. */
  5403. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5404. {
  5405. struct iwl_priv *priv = hw->priv;
  5406. const struct iwl_channel_info *ch_info;
  5407. struct ieee80211_conf *conf = &hw->conf;
  5408. unsigned long flags;
  5409. int ret = 0;
  5410. mutex_lock(&priv->mutex);
  5411. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5412. if (!iwl3945_is_ready(priv)) {
  5413. IWL_DEBUG_MAC80211("leave - not ready\n");
  5414. ret = -EIO;
  5415. goto out;
  5416. }
  5417. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5418. test_bit(STATUS_SCANNING, &priv->status))) {
  5419. IWL_DEBUG_MAC80211("leave - scanning\n");
  5420. set_bit(STATUS_CONF_PENDING, &priv->status);
  5421. mutex_unlock(&priv->mutex);
  5422. return 0;
  5423. }
  5424. spin_lock_irqsave(&priv->lock, flags);
  5425. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5426. conf->channel->hw_value);
  5427. if (!is_channel_valid(ch_info)) {
  5428. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5429. conf->channel->hw_value, conf->channel->band);
  5430. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5431. spin_unlock_irqrestore(&priv->lock, flags);
  5432. ret = -EINVAL;
  5433. goto out;
  5434. }
  5435. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5436. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5437. /* The list of supported rates and rate mask can be different
  5438. * for each phymode; since the phymode may have changed, reset
  5439. * the rate mask to what mac80211 lists */
  5440. iwl3945_set_rate(priv);
  5441. spin_unlock_irqrestore(&priv->lock, flags);
  5442. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5443. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5444. iwl3945_hw_channel_switch(priv, conf->channel);
  5445. goto out;
  5446. }
  5447. #endif
  5448. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5449. if (!conf->radio_enabled) {
  5450. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5451. goto out;
  5452. }
  5453. if (iwl3945_is_rfkill(priv)) {
  5454. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5455. ret = -EIO;
  5456. goto out;
  5457. }
  5458. iwl3945_set_rate(priv);
  5459. if (memcmp(&priv->active39_rxon,
  5460. &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
  5461. iwl3945_commit_rxon(priv);
  5462. else
  5463. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5464. IWL_DEBUG_MAC80211("leave\n");
  5465. out:
  5466. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5467. mutex_unlock(&priv->mutex);
  5468. return ret;
  5469. }
  5470. static void iwl3945_config_ap(struct iwl_priv *priv)
  5471. {
  5472. int rc = 0;
  5473. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5474. return;
  5475. /* The following should be done only at AP bring up */
  5476. if (!(iwl3945_is_associated(priv))) {
  5477. /* RXON - unassoc (to set timing command) */
  5478. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5479. iwl3945_commit_rxon(priv);
  5480. /* RXON Timing */
  5481. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5482. iwl3945_setup_rxon_timing(priv);
  5483. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5484. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5485. if (rc)
  5486. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5487. "Attempting to continue.\n");
  5488. /* FIXME: what should be the assoc_id for AP? */
  5489. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5490. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5491. priv->staging39_rxon.flags |=
  5492. RXON_FLG_SHORT_PREAMBLE_MSK;
  5493. else
  5494. priv->staging39_rxon.flags &=
  5495. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5496. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5497. if (priv->assoc_capability &
  5498. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5499. priv->staging39_rxon.flags |=
  5500. RXON_FLG_SHORT_SLOT_MSK;
  5501. else
  5502. priv->staging39_rxon.flags &=
  5503. ~RXON_FLG_SHORT_SLOT_MSK;
  5504. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5505. priv->staging39_rxon.flags &=
  5506. ~RXON_FLG_SHORT_SLOT_MSK;
  5507. }
  5508. /* restore RXON assoc */
  5509. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5510. iwl3945_commit_rxon(priv);
  5511. iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
  5512. }
  5513. iwl3945_send_beacon_cmd(priv);
  5514. /* FIXME - we need to add code here to detect a totally new
  5515. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5516. * clear sta table, add BCAST sta... */
  5517. }
  5518. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5519. struct ieee80211_vif *vif,
  5520. struct ieee80211_if_conf *conf)
  5521. {
  5522. struct iwl_priv *priv = hw->priv;
  5523. int rc;
  5524. if (conf == NULL)
  5525. return -EIO;
  5526. if (priv->vif != vif) {
  5527. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5528. return 0;
  5529. }
  5530. /* handle this temporarily here */
  5531. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5532. conf->changed & IEEE80211_IFCC_BEACON) {
  5533. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5534. if (!beacon)
  5535. return -ENOMEM;
  5536. mutex_lock(&priv->mutex);
  5537. rc = iwl3945_mac_beacon_update(hw, beacon);
  5538. mutex_unlock(&priv->mutex);
  5539. if (rc)
  5540. return rc;
  5541. }
  5542. if (!iwl3945_is_alive(priv))
  5543. return -EAGAIN;
  5544. mutex_lock(&priv->mutex);
  5545. if (conf->bssid)
  5546. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5547. /*
  5548. * very dubious code was here; the probe filtering flag is never set:
  5549. *
  5550. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5551. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5552. */
  5553. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5554. if (!conf->bssid) {
  5555. conf->bssid = priv->mac_addr;
  5556. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5557. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5558. conf->bssid);
  5559. }
  5560. if (priv->ibss_beacon)
  5561. dev_kfree_skb(priv->ibss_beacon);
  5562. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5563. }
  5564. if (iwl3945_is_rfkill(priv))
  5565. goto done;
  5566. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5567. !is_multicast_ether_addr(conf->bssid)) {
  5568. /* If there is currently a HW scan going on in the background
  5569. * then we need to cancel it else the RXON below will fail. */
  5570. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5571. IWL_WARNING("Aborted scan still in progress "
  5572. "after 100ms\n");
  5573. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5574. mutex_unlock(&priv->mutex);
  5575. return -EAGAIN;
  5576. }
  5577. memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5578. /* TODO: Audit driver for usage of these members and see
  5579. * if mac80211 deprecates them (priv->bssid looks like it
  5580. * shouldn't be there, but I haven't scanned the IBSS code
  5581. * to verify) - jpk */
  5582. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5583. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5584. iwl3945_config_ap(priv);
  5585. else {
  5586. rc = iwl3945_commit_rxon(priv);
  5587. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5588. iwl3945_add_station(priv,
  5589. priv->active39_rxon.bssid_addr, 1, 0);
  5590. }
  5591. } else {
  5592. iwl3945_scan_cancel_timeout(priv, 100);
  5593. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5594. iwl3945_commit_rxon(priv);
  5595. }
  5596. done:
  5597. IWL_DEBUG_MAC80211("leave\n");
  5598. mutex_unlock(&priv->mutex);
  5599. return 0;
  5600. }
  5601. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5602. unsigned int changed_flags,
  5603. unsigned int *total_flags,
  5604. int mc_count, struct dev_addr_list *mc_list)
  5605. {
  5606. struct iwl_priv *priv = hw->priv;
  5607. __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
  5608. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5609. changed_flags, *total_flags);
  5610. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5611. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5612. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5613. else
  5614. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5615. }
  5616. if (changed_flags & FIF_ALLMULTI) {
  5617. if (*total_flags & FIF_ALLMULTI)
  5618. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5619. else
  5620. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5621. }
  5622. if (changed_flags & FIF_CONTROL) {
  5623. if (*total_flags & FIF_CONTROL)
  5624. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5625. else
  5626. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5627. }
  5628. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5629. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5630. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5631. else
  5632. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5633. }
  5634. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5635. * since mac80211 will call ieee80211_hw_config immediately.
  5636. * (mc_list is not supported at this time). Otherwise, we need to
  5637. * queue a background iwl_commit_rxon work.
  5638. */
  5639. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5640. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5641. }
  5642. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5643. struct ieee80211_if_init_conf *conf)
  5644. {
  5645. struct iwl_priv *priv = hw->priv;
  5646. IWL_DEBUG_MAC80211("enter\n");
  5647. mutex_lock(&priv->mutex);
  5648. if (iwl3945_is_ready_rf(priv)) {
  5649. iwl3945_scan_cancel_timeout(priv, 100);
  5650. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5651. iwl3945_commit_rxon(priv);
  5652. }
  5653. if (priv->vif == conf->vif) {
  5654. priv->vif = NULL;
  5655. memset(priv->bssid, 0, ETH_ALEN);
  5656. }
  5657. mutex_unlock(&priv->mutex);
  5658. IWL_DEBUG_MAC80211("leave\n");
  5659. }
  5660. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5661. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5662. struct ieee80211_vif *vif,
  5663. struct ieee80211_bss_conf *bss_conf,
  5664. u32 changes)
  5665. {
  5666. struct iwl_priv *priv = hw->priv;
  5667. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5668. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5669. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5670. bss_conf->use_short_preamble);
  5671. if (bss_conf->use_short_preamble)
  5672. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5673. else
  5674. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5675. }
  5676. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5677. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5678. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5679. priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5680. else
  5681. priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5682. }
  5683. if (changes & BSS_CHANGED_ASSOC) {
  5684. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5685. /* This should never happen as this function should
  5686. * never be called from interrupt context. */
  5687. if (WARN_ON_ONCE(in_interrupt()))
  5688. return;
  5689. if (bss_conf->assoc) {
  5690. priv->assoc_id = bss_conf->aid;
  5691. priv->beacon_int = bss_conf->beacon_int;
  5692. priv->timestamp = bss_conf->timestamp;
  5693. priv->assoc_capability = bss_conf->assoc_capability;
  5694. priv->next_scan_jiffies = jiffies +
  5695. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5696. mutex_lock(&priv->mutex);
  5697. iwl3945_post_associate(priv);
  5698. mutex_unlock(&priv->mutex);
  5699. } else {
  5700. priv->assoc_id = 0;
  5701. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5702. }
  5703. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5704. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5705. iwl3945_send_rxon_assoc(priv);
  5706. }
  5707. }
  5708. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5709. {
  5710. int rc = 0;
  5711. unsigned long flags;
  5712. struct iwl_priv *priv = hw->priv;
  5713. DECLARE_SSID_BUF(ssid_buf);
  5714. IWL_DEBUG_MAC80211("enter\n");
  5715. mutex_lock(&priv->mutex);
  5716. spin_lock_irqsave(&priv->lock, flags);
  5717. if (!iwl3945_is_ready_rf(priv)) {
  5718. rc = -EIO;
  5719. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5720. goto out_unlock;
  5721. }
  5722. /* we don't schedule scan within next_scan_jiffies period */
  5723. if (priv->next_scan_jiffies &&
  5724. time_after(priv->next_scan_jiffies, jiffies)) {
  5725. rc = -EAGAIN;
  5726. goto out_unlock;
  5727. }
  5728. /* if we just finished scan ask for delay for a broadcast scan */
  5729. if ((len == 0) && priv->last_scan_jiffies &&
  5730. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5731. jiffies)) {
  5732. rc = -EAGAIN;
  5733. goto out_unlock;
  5734. }
  5735. if (len) {
  5736. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5737. print_ssid(ssid_buf, ssid, len), (int)len);
  5738. priv->one_direct_scan = 1;
  5739. priv->direct_ssid_len = (u8)
  5740. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5741. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5742. } else
  5743. priv->one_direct_scan = 0;
  5744. rc = iwl3945_scan_initiate(priv);
  5745. IWL_DEBUG_MAC80211("leave\n");
  5746. out_unlock:
  5747. spin_unlock_irqrestore(&priv->lock, flags);
  5748. mutex_unlock(&priv->mutex);
  5749. return rc;
  5750. }
  5751. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5752. const u8 *local_addr, const u8 *addr,
  5753. struct ieee80211_key_conf *key)
  5754. {
  5755. struct iwl_priv *priv = hw->priv;
  5756. int rc = 0;
  5757. u8 sta_id;
  5758. IWL_DEBUG_MAC80211("enter\n");
  5759. if (!iwl3945_param_hwcrypto) {
  5760. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5761. return -EOPNOTSUPP;
  5762. }
  5763. if (is_zero_ether_addr(addr))
  5764. /* only support pairwise keys */
  5765. return -EOPNOTSUPP;
  5766. sta_id = iwl3945_hw_find_station(priv, addr);
  5767. if (sta_id == IWL_INVALID_STATION) {
  5768. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5769. addr);
  5770. return -EINVAL;
  5771. }
  5772. mutex_lock(&priv->mutex);
  5773. iwl3945_scan_cancel_timeout(priv, 100);
  5774. switch (cmd) {
  5775. case SET_KEY:
  5776. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5777. if (!rc) {
  5778. iwl3945_set_rxon_hwcrypto(priv, 1);
  5779. iwl3945_commit_rxon(priv);
  5780. key->hw_key_idx = sta_id;
  5781. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5782. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5783. }
  5784. break;
  5785. case DISABLE_KEY:
  5786. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5787. if (!rc) {
  5788. iwl3945_set_rxon_hwcrypto(priv, 0);
  5789. iwl3945_commit_rxon(priv);
  5790. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5791. }
  5792. break;
  5793. default:
  5794. rc = -EINVAL;
  5795. }
  5796. IWL_DEBUG_MAC80211("leave\n");
  5797. mutex_unlock(&priv->mutex);
  5798. return rc;
  5799. }
  5800. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5801. const struct ieee80211_tx_queue_params *params)
  5802. {
  5803. struct iwl_priv *priv = hw->priv;
  5804. unsigned long flags;
  5805. int q;
  5806. IWL_DEBUG_MAC80211("enter\n");
  5807. if (!iwl3945_is_ready_rf(priv)) {
  5808. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5809. return -EIO;
  5810. }
  5811. if (queue >= AC_NUM) {
  5812. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5813. return 0;
  5814. }
  5815. q = AC_NUM - 1 - queue;
  5816. spin_lock_irqsave(&priv->lock, flags);
  5817. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5818. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5819. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5820. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5821. cpu_to_le16((params->txop * 32));
  5822. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5823. priv->qos_data.qos_active = 1;
  5824. spin_unlock_irqrestore(&priv->lock, flags);
  5825. mutex_lock(&priv->mutex);
  5826. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5827. iwl3945_activate_qos(priv, 1);
  5828. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5829. iwl3945_activate_qos(priv, 0);
  5830. mutex_unlock(&priv->mutex);
  5831. IWL_DEBUG_MAC80211("leave\n");
  5832. return 0;
  5833. }
  5834. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5835. struct ieee80211_tx_queue_stats *stats)
  5836. {
  5837. struct iwl_priv *priv = hw->priv;
  5838. int i, avail;
  5839. struct iwl3945_tx_queue *txq;
  5840. struct iwl_queue *q;
  5841. unsigned long flags;
  5842. IWL_DEBUG_MAC80211("enter\n");
  5843. if (!iwl3945_is_ready_rf(priv)) {
  5844. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5845. return -EIO;
  5846. }
  5847. spin_lock_irqsave(&priv->lock, flags);
  5848. for (i = 0; i < AC_NUM; i++) {
  5849. txq = &priv->txq39[i];
  5850. q = &txq->q;
  5851. avail = iwl_queue_space(q);
  5852. stats[i].len = q->n_window - avail;
  5853. stats[i].limit = q->n_window - q->high_mark;
  5854. stats[i].count = q->n_window;
  5855. }
  5856. spin_unlock_irqrestore(&priv->lock, flags);
  5857. IWL_DEBUG_MAC80211("leave\n");
  5858. return 0;
  5859. }
  5860. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5861. {
  5862. struct iwl_priv *priv = hw->priv;
  5863. unsigned long flags;
  5864. mutex_lock(&priv->mutex);
  5865. IWL_DEBUG_MAC80211("enter\n");
  5866. iwl3945_reset_qos(priv);
  5867. spin_lock_irqsave(&priv->lock, flags);
  5868. priv->assoc_id = 0;
  5869. priv->assoc_capability = 0;
  5870. priv->call_post_assoc_from_beacon = 0;
  5871. /* new association get rid of ibss beacon skb */
  5872. if (priv->ibss_beacon)
  5873. dev_kfree_skb(priv->ibss_beacon);
  5874. priv->ibss_beacon = NULL;
  5875. priv->beacon_int = priv->hw->conf.beacon_int;
  5876. priv->timestamp = 0;
  5877. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5878. priv->beacon_int = 0;
  5879. spin_unlock_irqrestore(&priv->lock, flags);
  5880. if (!iwl3945_is_ready_rf(priv)) {
  5881. IWL_DEBUG_MAC80211("leave - not ready\n");
  5882. mutex_unlock(&priv->mutex);
  5883. return;
  5884. }
  5885. /* we are restarting association process
  5886. * clear RXON_FILTER_ASSOC_MSK bit
  5887. */
  5888. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5889. iwl3945_scan_cancel_timeout(priv, 100);
  5890. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5891. iwl3945_commit_rxon(priv);
  5892. }
  5893. /* Per mac80211.h: This is only used in IBSS mode... */
  5894. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5895. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5896. mutex_unlock(&priv->mutex);
  5897. return;
  5898. }
  5899. iwl3945_set_rate(priv);
  5900. mutex_unlock(&priv->mutex);
  5901. IWL_DEBUG_MAC80211("leave\n");
  5902. }
  5903. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5904. {
  5905. struct iwl_priv *priv = hw->priv;
  5906. unsigned long flags;
  5907. IWL_DEBUG_MAC80211("enter\n");
  5908. if (!iwl3945_is_ready_rf(priv)) {
  5909. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5910. return -EIO;
  5911. }
  5912. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5913. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5914. return -EIO;
  5915. }
  5916. spin_lock_irqsave(&priv->lock, flags);
  5917. if (priv->ibss_beacon)
  5918. dev_kfree_skb(priv->ibss_beacon);
  5919. priv->ibss_beacon = skb;
  5920. priv->assoc_id = 0;
  5921. IWL_DEBUG_MAC80211("leave\n");
  5922. spin_unlock_irqrestore(&priv->lock, flags);
  5923. iwl3945_reset_qos(priv);
  5924. iwl3945_post_associate(priv);
  5925. return 0;
  5926. }
  5927. /*****************************************************************************
  5928. *
  5929. * sysfs attributes
  5930. *
  5931. *****************************************************************************/
  5932. #ifdef CONFIG_IWL3945_DEBUG
  5933. /*
  5934. * The following adds a new attribute to the sysfs representation
  5935. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5936. * used for controlling the debug level.
  5937. *
  5938. * See the level definitions in iwl for details.
  5939. */
  5940. static ssize_t show_debug_level(struct device *d,
  5941. struct device_attribute *attr, char *buf)
  5942. {
  5943. struct iwl_priv *priv = d->driver_data;
  5944. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5945. }
  5946. static ssize_t store_debug_level(struct device *d,
  5947. struct device_attribute *attr,
  5948. const char *buf, size_t count)
  5949. {
  5950. struct iwl_priv *priv = d->driver_data;
  5951. unsigned long val;
  5952. int ret;
  5953. ret = strict_strtoul(buf, 0, &val);
  5954. if (ret)
  5955. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  5956. else
  5957. priv->debug_level = val;
  5958. return strnlen(buf, count);
  5959. }
  5960. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5961. show_debug_level, store_debug_level);
  5962. #endif /* CONFIG_IWL3945_DEBUG */
  5963. static ssize_t show_temperature(struct device *d,
  5964. struct device_attribute *attr, char *buf)
  5965. {
  5966. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5967. if (!iwl3945_is_alive(priv))
  5968. return -EAGAIN;
  5969. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5970. }
  5971. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5972. static ssize_t show_tx_power(struct device *d,
  5973. struct device_attribute *attr, char *buf)
  5974. {
  5975. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5976. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  5977. }
  5978. static ssize_t store_tx_power(struct device *d,
  5979. struct device_attribute *attr,
  5980. const char *buf, size_t count)
  5981. {
  5982. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5983. char *p = (char *)buf;
  5984. u32 val;
  5985. val = simple_strtoul(p, &p, 10);
  5986. if (p == buf)
  5987. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  5988. else
  5989. iwl3945_hw_reg_set_txpower(priv, val);
  5990. return count;
  5991. }
  5992. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5993. static ssize_t show_flags(struct device *d,
  5994. struct device_attribute *attr, char *buf)
  5995. {
  5996. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5997. return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
  5998. }
  5999. static ssize_t store_flags(struct device *d,
  6000. struct device_attribute *attr,
  6001. const char *buf, size_t count)
  6002. {
  6003. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  6004. u32 flags = simple_strtoul(buf, NULL, 0);
  6005. mutex_lock(&priv->mutex);
  6006. if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
  6007. /* Cancel any currently running scans... */
  6008. if (iwl3945_scan_cancel_timeout(priv, 100))
  6009. IWL_WARNING("Could not cancel scan.\n");
  6010. else {
  6011. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6012. flags);
  6013. priv->staging39_rxon.flags = cpu_to_le32(flags);
  6014. iwl3945_commit_rxon(priv);
  6015. }
  6016. }
  6017. mutex_unlock(&priv->mutex);
  6018. return count;
  6019. }
  6020. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6021. static ssize_t show_filter_flags(struct device *d,
  6022. struct device_attribute *attr, char *buf)
  6023. {
  6024. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  6025. return sprintf(buf, "0x%04X\n",
  6026. le32_to_cpu(priv->active39_rxon.filter_flags));
  6027. }
  6028. static ssize_t store_filter_flags(struct device *d,
  6029. struct device_attribute *attr,
  6030. const char *buf, size_t count)
  6031. {
  6032. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  6033. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6034. mutex_lock(&priv->mutex);
  6035. if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
  6036. /* Cancel any currently running scans... */
  6037. if (iwl3945_scan_cancel_timeout(priv, 100))
  6038. IWL_WARNING("Could not cancel scan.\n");
  6039. else {
  6040. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6041. "0x%04X\n", filter_flags);
  6042. priv->staging39_rxon.filter_flags =
  6043. cpu_to_le32(filter_flags);
  6044. iwl3945_commit_rxon(priv);
  6045. }
  6046. }
  6047. mutex_unlock(&priv->mutex);
  6048. return count;
  6049. }
  6050. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6051. store_filter_flags);
  6052. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6053. static ssize_t show_measurement(struct device *d,
  6054. struct device_attribute *attr, char *buf)
  6055. {
  6056. struct iwl_priv *priv = dev_get_drvdata(d);
  6057. struct iwl_spectrum_notification measure_report;
  6058. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6059. u8 *data = (u8 *)&measure_report;
  6060. unsigned long flags;
  6061. spin_lock_irqsave(&priv->lock, flags);
  6062. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6063. spin_unlock_irqrestore(&priv->lock, flags);
  6064. return 0;
  6065. }
  6066. memcpy(&measure_report, &priv->measure_report, size);
  6067. priv->measurement_status = 0;
  6068. spin_unlock_irqrestore(&priv->lock, flags);
  6069. while (size && (PAGE_SIZE - len)) {
  6070. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6071. PAGE_SIZE - len, 1);
  6072. len = strlen(buf);
  6073. if (PAGE_SIZE - len)
  6074. buf[len++] = '\n';
  6075. ofs += 16;
  6076. size -= min(size, 16U);
  6077. }
  6078. return len;
  6079. }
  6080. static ssize_t store_measurement(struct device *d,
  6081. struct device_attribute *attr,
  6082. const char *buf, size_t count)
  6083. {
  6084. struct iwl_priv *priv = dev_get_drvdata(d);
  6085. struct ieee80211_measurement_params params = {
  6086. .channel = le16_to_cpu(priv->active39_rxon.channel),
  6087. .start_time = cpu_to_le64(priv->last_tsf),
  6088. .duration = cpu_to_le16(1),
  6089. };
  6090. u8 type = IWL_MEASURE_BASIC;
  6091. u8 buffer[32];
  6092. u8 channel;
  6093. if (count) {
  6094. char *p = buffer;
  6095. strncpy(buffer, buf, min(sizeof(buffer), count));
  6096. channel = simple_strtoul(p, NULL, 0);
  6097. if (channel)
  6098. params.channel = channel;
  6099. p = buffer;
  6100. while (*p && *p != ' ')
  6101. p++;
  6102. if (*p)
  6103. type = simple_strtoul(p + 1, NULL, 0);
  6104. }
  6105. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6106. "channel %d (for '%s')\n", type, params.channel, buf);
  6107. iwl3945_get_measurement(priv, &params, type);
  6108. return count;
  6109. }
  6110. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6111. show_measurement, store_measurement);
  6112. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6113. static ssize_t store_retry_rate(struct device *d,
  6114. struct device_attribute *attr,
  6115. const char *buf, size_t count)
  6116. {
  6117. struct iwl_priv *priv = dev_get_drvdata(d);
  6118. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6119. if (priv->retry_rate <= 0)
  6120. priv->retry_rate = 1;
  6121. return count;
  6122. }
  6123. static ssize_t show_retry_rate(struct device *d,
  6124. struct device_attribute *attr, char *buf)
  6125. {
  6126. struct iwl_priv *priv = dev_get_drvdata(d);
  6127. return sprintf(buf, "%d", priv->retry_rate);
  6128. }
  6129. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6130. store_retry_rate);
  6131. static ssize_t store_power_level(struct device *d,
  6132. struct device_attribute *attr,
  6133. const char *buf, size_t count)
  6134. {
  6135. struct iwl_priv *priv = dev_get_drvdata(d);
  6136. int rc;
  6137. int mode;
  6138. mode = simple_strtoul(buf, NULL, 0);
  6139. mutex_lock(&priv->mutex);
  6140. if (!iwl3945_is_ready(priv)) {
  6141. rc = -EAGAIN;
  6142. goto out;
  6143. }
  6144. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  6145. (mode == IWL39_POWER_AC))
  6146. mode = IWL39_POWER_AC;
  6147. else
  6148. mode |= IWL_POWER_ENABLED;
  6149. if (mode != priv->power_mode) {
  6150. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6151. if (rc) {
  6152. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6153. goto out;
  6154. }
  6155. priv->power_mode = mode;
  6156. }
  6157. rc = count;
  6158. out:
  6159. mutex_unlock(&priv->mutex);
  6160. return rc;
  6161. }
  6162. #define MAX_WX_STRING 80
  6163. /* Values are in microsecond */
  6164. static const s32 timeout_duration[] = {
  6165. 350000,
  6166. 250000,
  6167. 75000,
  6168. 37000,
  6169. 25000,
  6170. };
  6171. static const s32 period_duration[] = {
  6172. 400000,
  6173. 700000,
  6174. 1000000,
  6175. 1000000,
  6176. 1000000
  6177. };
  6178. static ssize_t show_power_level(struct device *d,
  6179. struct device_attribute *attr, char *buf)
  6180. {
  6181. struct iwl_priv *priv = dev_get_drvdata(d);
  6182. int level = IWL_POWER_LEVEL(priv->power_mode);
  6183. char *p = buf;
  6184. p += sprintf(p, "%d ", level);
  6185. switch (level) {
  6186. case IWL_POWER_MODE_CAM:
  6187. case IWL39_POWER_AC:
  6188. p += sprintf(p, "(AC)");
  6189. break;
  6190. case IWL39_POWER_BATTERY:
  6191. p += sprintf(p, "(BATTERY)");
  6192. break;
  6193. default:
  6194. p += sprintf(p,
  6195. "(Timeout %dms, Period %dms)",
  6196. timeout_duration[level - 1] / 1000,
  6197. period_duration[level - 1] / 1000);
  6198. }
  6199. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6200. p += sprintf(p, " OFF\n");
  6201. else
  6202. p += sprintf(p, " \n");
  6203. return p - buf + 1;
  6204. }
  6205. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6206. store_power_level);
  6207. static ssize_t show_channels(struct device *d,
  6208. struct device_attribute *attr, char *buf)
  6209. {
  6210. /* all this shit doesn't belong into sysfs anyway */
  6211. return 0;
  6212. }
  6213. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6214. static ssize_t show_statistics(struct device *d,
  6215. struct device_attribute *attr, char *buf)
  6216. {
  6217. struct iwl_priv *priv = dev_get_drvdata(d);
  6218. u32 size = sizeof(struct iwl3945_notif_statistics);
  6219. u32 len = 0, ofs = 0;
  6220. u8 *data = (u8 *)&priv->statistics_39;
  6221. int rc = 0;
  6222. if (!iwl3945_is_alive(priv))
  6223. return -EAGAIN;
  6224. mutex_lock(&priv->mutex);
  6225. rc = iwl3945_send_statistics_request(priv);
  6226. mutex_unlock(&priv->mutex);
  6227. if (rc) {
  6228. len = sprintf(buf,
  6229. "Error sending statistics request: 0x%08X\n", rc);
  6230. return len;
  6231. }
  6232. while (size && (PAGE_SIZE - len)) {
  6233. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6234. PAGE_SIZE - len, 1);
  6235. len = strlen(buf);
  6236. if (PAGE_SIZE - len)
  6237. buf[len++] = '\n';
  6238. ofs += 16;
  6239. size -= min(size, 16U);
  6240. }
  6241. return len;
  6242. }
  6243. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6244. static ssize_t show_antenna(struct device *d,
  6245. struct device_attribute *attr, char *buf)
  6246. {
  6247. struct iwl_priv *priv = dev_get_drvdata(d);
  6248. if (!iwl3945_is_alive(priv))
  6249. return -EAGAIN;
  6250. return sprintf(buf, "%d\n", priv->antenna);
  6251. }
  6252. static ssize_t store_antenna(struct device *d,
  6253. struct device_attribute *attr,
  6254. const char *buf, size_t count)
  6255. {
  6256. int ant;
  6257. struct iwl_priv *priv = dev_get_drvdata(d);
  6258. if (count == 0)
  6259. return 0;
  6260. if (sscanf(buf, "%1i", &ant) != 1) {
  6261. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6262. return count;
  6263. }
  6264. if ((ant >= 0) && (ant <= 2)) {
  6265. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6266. priv->antenna = (enum iwl3945_antenna)ant;
  6267. } else
  6268. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6269. return count;
  6270. }
  6271. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6272. static ssize_t show_status(struct device *d,
  6273. struct device_attribute *attr, char *buf)
  6274. {
  6275. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  6276. if (!iwl3945_is_alive(priv))
  6277. return -EAGAIN;
  6278. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6279. }
  6280. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6281. static ssize_t dump_error_log(struct device *d,
  6282. struct device_attribute *attr,
  6283. const char *buf, size_t count)
  6284. {
  6285. char *p = (char *)buf;
  6286. if (p[0] == '1')
  6287. iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
  6288. return strnlen(buf, count);
  6289. }
  6290. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6291. static ssize_t dump_event_log(struct device *d,
  6292. struct device_attribute *attr,
  6293. const char *buf, size_t count)
  6294. {
  6295. char *p = (char *)buf;
  6296. if (p[0] == '1')
  6297. iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
  6298. return strnlen(buf, count);
  6299. }
  6300. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6301. /*****************************************************************************
  6302. *
  6303. * driver setup and tear down
  6304. *
  6305. *****************************************************************************/
  6306. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  6307. {
  6308. priv->workqueue = create_workqueue(DRV_NAME);
  6309. init_waitqueue_head(&priv->wait_command_queue);
  6310. INIT_WORK(&priv->up, iwl3945_bg_up);
  6311. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6312. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6313. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6314. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6315. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6316. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6317. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6318. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6319. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6320. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6321. iwl3945_hw_setup_deferred_work(priv);
  6322. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6323. iwl3945_irq_tasklet, (unsigned long)priv);
  6324. }
  6325. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  6326. {
  6327. iwl3945_hw_cancel_deferred_work(priv);
  6328. cancel_delayed_work_sync(&priv->init_alive_start);
  6329. cancel_delayed_work(&priv->scan_check);
  6330. cancel_delayed_work(&priv->alive_start);
  6331. cancel_work_sync(&priv->beacon_update);
  6332. }
  6333. static struct attribute *iwl3945_sysfs_entries[] = {
  6334. &dev_attr_antenna.attr,
  6335. &dev_attr_channels.attr,
  6336. &dev_attr_dump_errors.attr,
  6337. &dev_attr_dump_events.attr,
  6338. &dev_attr_flags.attr,
  6339. &dev_attr_filter_flags.attr,
  6340. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6341. &dev_attr_measurement.attr,
  6342. #endif
  6343. &dev_attr_power_level.attr,
  6344. &dev_attr_retry_rate.attr,
  6345. &dev_attr_statistics.attr,
  6346. &dev_attr_status.attr,
  6347. &dev_attr_temperature.attr,
  6348. &dev_attr_tx_power.attr,
  6349. #ifdef CONFIG_IWL3945_DEBUG
  6350. &dev_attr_debug_level.attr,
  6351. #endif
  6352. NULL
  6353. };
  6354. static struct attribute_group iwl3945_attribute_group = {
  6355. .name = NULL, /* put in device directory */
  6356. .attrs = iwl3945_sysfs_entries,
  6357. };
  6358. static struct ieee80211_ops iwl3945_hw_ops = {
  6359. .tx = iwl3945_mac_tx,
  6360. .start = iwl3945_mac_start,
  6361. .stop = iwl3945_mac_stop,
  6362. .add_interface = iwl3945_mac_add_interface,
  6363. .remove_interface = iwl3945_mac_remove_interface,
  6364. .config = iwl3945_mac_config,
  6365. .config_interface = iwl3945_mac_config_interface,
  6366. .configure_filter = iwl3945_configure_filter,
  6367. .set_key = iwl3945_mac_set_key,
  6368. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6369. .conf_tx = iwl3945_mac_conf_tx,
  6370. .reset_tsf = iwl3945_mac_reset_tsf,
  6371. .bss_info_changed = iwl3945_bss_info_changed,
  6372. .hw_scan = iwl3945_mac_hw_scan
  6373. };
  6374. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6375. {
  6376. int err = 0;
  6377. struct iwl_priv *priv;
  6378. struct ieee80211_hw *hw;
  6379. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  6380. unsigned long flags;
  6381. /***********************
  6382. * 1. Allocating HW data
  6383. * ********************/
  6384. /* mac80211 allocates memory for this device instance, including
  6385. * space for this driver's private structure */
  6386. hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwl3945_hw_ops);
  6387. if (hw == NULL) {
  6388. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6389. err = -ENOMEM;
  6390. goto out;
  6391. }
  6392. SET_IEEE80211_DEV(hw, &pdev->dev);
  6393. priv = hw->priv;
  6394. priv->hw = hw;
  6395. priv->pci_dev = pdev;
  6396. priv->cfg = cfg;
  6397. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6398. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6399. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6400. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6401. err = -EINVAL;
  6402. goto out;
  6403. }
  6404. /* Disabling hardware scan means that mac80211 will perform scans
  6405. * "the hard way", rather than using device's scan. */
  6406. if (iwl3945_param_disable_hw_scan) {
  6407. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6408. iwl3945_hw_ops.hw_scan = NULL;
  6409. }
  6410. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6411. hw->rate_control_algorithm = "iwl-3945-rs";
  6412. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6413. /* Select antenna (may be helpful if only one antenna is connected) */
  6414. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6415. #ifdef CONFIG_IWL3945_DEBUG
  6416. priv->debug_level = iwl3945_param_debug;
  6417. atomic_set(&priv->restrict_refcnt, 0);
  6418. #endif
  6419. /* Tell mac80211 our characteristics */
  6420. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6421. IEEE80211_HW_NOISE_DBM;
  6422. hw->wiphy->interface_modes =
  6423. BIT(NL80211_IFTYPE_STATION) |
  6424. BIT(NL80211_IFTYPE_ADHOC);
  6425. hw->wiphy->fw_handles_regulatory = true;
  6426. /* 4 EDCA QOS priorities */
  6427. hw->queues = 4;
  6428. /***************************
  6429. * 2. Initializing PCI bus
  6430. * *************************/
  6431. if (pci_enable_device(pdev)) {
  6432. err = -ENODEV;
  6433. goto out_ieee80211_free_hw;
  6434. }
  6435. pci_set_master(pdev);
  6436. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6437. if (!err)
  6438. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6439. if (err) {
  6440. IWL_WARN(priv, "No suitable DMA available.\n");
  6441. goto out_pci_disable_device;
  6442. }
  6443. pci_set_drvdata(pdev, priv);
  6444. err = pci_request_regions(pdev, DRV_NAME);
  6445. if (err)
  6446. goto out_pci_disable_device;
  6447. /***********************
  6448. * 3. Read REV Register
  6449. * ********************/
  6450. priv->hw_base = pci_iomap(pdev, 0, 0);
  6451. if (!priv->hw_base) {
  6452. err = -ENODEV;
  6453. goto out_pci_release_regions;
  6454. }
  6455. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6456. (unsigned long long) pci_resource_len(pdev, 0));
  6457. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6458. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6459. * PCI Tx retries from interfering with C3 CPU state */
  6460. pci_write_config_byte(pdev, 0x41, 0x00);
  6461. /* nic init */
  6462. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6463. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6464. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6465. err = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
  6466. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6467. if (err < 0) {
  6468. IWL_DEBUG_INFO("Failed to init the card\n");
  6469. goto out_remove_sysfs;
  6470. }
  6471. /***********************
  6472. * 4. Read EEPROM
  6473. * ********************/
  6474. /* Read the EEPROM */
  6475. err = iwl3945_eeprom_init(priv);
  6476. if (err) {
  6477. IWL_ERROR("Unable to init EEPROM\n");
  6478. goto out_remove_sysfs;
  6479. }
  6480. /* MAC Address location in EEPROM same for 3945/4965 */
  6481. get_eeprom_mac(priv, priv->mac_addr);
  6482. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6483. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6484. /***********************
  6485. * 5. Setup HW Constants
  6486. * ********************/
  6487. /* Device-specific setup */
  6488. if (iwl3945_hw_set_hw_params(priv)) {
  6489. IWL_ERROR("failed to set hw settings\n");
  6490. goto out_iounmap;
  6491. }
  6492. /***********************
  6493. * 6. Setup priv
  6494. * ********************/
  6495. priv->retry_rate = 1;
  6496. priv->ibss_beacon = NULL;
  6497. spin_lock_init(&priv->lock);
  6498. spin_lock_init(&priv->power_data_39.lock);
  6499. spin_lock_init(&priv->sta_lock);
  6500. spin_lock_init(&priv->hcmd_lock);
  6501. INIT_LIST_HEAD(&priv->free_frames);
  6502. mutex_init(&priv->mutex);
  6503. /* Clear the driver's (not device's) station table */
  6504. iwl3945_clear_stations_table(priv);
  6505. priv->data_retry_limit = -1;
  6506. priv->ieee_channels = NULL;
  6507. priv->ieee_rates = NULL;
  6508. priv->band = IEEE80211_BAND_2GHZ;
  6509. priv->iw_mode = NL80211_IFTYPE_STATION;
  6510. iwl3945_reset_qos(priv);
  6511. priv->qos_data.qos_active = 0;
  6512. priv->qos_data.qos_cap.val = 0;
  6513. priv->rates_mask = IWL_RATES_MASK;
  6514. /* If power management is turned on, default to AC mode */
  6515. priv->power_mode = IWL39_POWER_AC;
  6516. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6517. err = iwl3945_init_channel_map(priv);
  6518. if (err) {
  6519. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6520. goto out_release_irq;
  6521. }
  6522. err = iwl3945_init_geos(priv);
  6523. if (err) {
  6524. IWL_ERROR("initializing geos failed: %d\n", err);
  6525. goto out_free_channel_map;
  6526. }
  6527. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  6528. priv->cfg->name);
  6529. /***********************************
  6530. * 7. Initialize Module Parameters
  6531. * **********************************/
  6532. /* Initialize module parameter values here */
  6533. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6534. if (iwl3945_param_disable) {
  6535. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6536. IWL_DEBUG_INFO("Radio disabled.\n");
  6537. }
  6538. /***********************
  6539. * 8. Setup Services
  6540. * ********************/
  6541. spin_lock_irqsave(&priv->lock, flags);
  6542. iwl3945_disable_interrupts(priv);
  6543. spin_unlock_irqrestore(&priv->lock, flags);
  6544. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6545. if (err) {
  6546. IWL_ERROR("failed to create sysfs device attributes\n");
  6547. goto out_free_geos;
  6548. }
  6549. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6550. iwl3945_setup_deferred_work(priv);
  6551. iwl3945_setup_rx_handlers(priv);
  6552. /***********************
  6553. * 9. Conclude
  6554. * ********************/
  6555. pci_save_state(pdev);
  6556. pci_disable_device(pdev);
  6557. /*********************************
  6558. * 10. Setup and Register mac80211
  6559. * *******************************/
  6560. err = ieee80211_register_hw(priv->hw);
  6561. if (err) {
  6562. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6563. goto out_remove_sysfs;
  6564. }
  6565. priv->hw->conf.beacon_int = 100;
  6566. priv->mac80211_registered = 1;
  6567. err = iwl3945_rfkill_init(priv);
  6568. if (err)
  6569. IWL_ERROR("Unable to initialize RFKILL system. "
  6570. "Ignoring error: %d\n", err);
  6571. return 0;
  6572. out_remove_sysfs:
  6573. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6574. out_free_geos:
  6575. iwl3945_free_geos(priv);
  6576. out_free_channel_map:
  6577. iwl3945_free_channel_map(priv);
  6578. out_release_irq:
  6579. destroy_workqueue(priv->workqueue);
  6580. priv->workqueue = NULL;
  6581. iwl3945_unset_hw_params(priv);
  6582. out_iounmap:
  6583. pci_iounmap(pdev, priv->hw_base);
  6584. out_pci_release_regions:
  6585. pci_release_regions(pdev);
  6586. out_pci_disable_device:
  6587. pci_disable_device(pdev);
  6588. pci_set_drvdata(pdev, NULL);
  6589. out_ieee80211_free_hw:
  6590. ieee80211_free_hw(priv->hw);
  6591. out:
  6592. return err;
  6593. }
  6594. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6595. {
  6596. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6597. unsigned long flags;
  6598. if (!priv)
  6599. return;
  6600. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6601. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6602. iwl3945_down(priv);
  6603. /* make sure we flush any pending irq or
  6604. * tasklet for the driver
  6605. */
  6606. spin_lock_irqsave(&priv->lock, flags);
  6607. iwl3945_disable_interrupts(priv);
  6608. spin_unlock_irqrestore(&priv->lock, flags);
  6609. iwl_synchronize_irq(priv);
  6610. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6611. iwl3945_rfkill_unregister(priv);
  6612. iwl3945_dealloc_ucode_pci(priv);
  6613. if (priv->rxq.bd)
  6614. iwl3945_rx_queue_free(priv, &priv->rxq);
  6615. iwl3945_hw_txq_ctx_free(priv);
  6616. iwl3945_unset_hw_params(priv);
  6617. iwl3945_clear_stations_table(priv);
  6618. if (priv->mac80211_registered)
  6619. ieee80211_unregister_hw(priv->hw);
  6620. /*netif_stop_queue(dev); */
  6621. flush_workqueue(priv->workqueue);
  6622. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6623. * priv->workqueue... so we can't take down the workqueue
  6624. * until now... */
  6625. destroy_workqueue(priv->workqueue);
  6626. priv->workqueue = NULL;
  6627. pci_iounmap(pdev, priv->hw_base);
  6628. pci_release_regions(pdev);
  6629. pci_disable_device(pdev);
  6630. pci_set_drvdata(pdev, NULL);
  6631. iwl3945_free_channel_map(priv);
  6632. iwl3945_free_geos(priv);
  6633. kfree(priv->scan39);
  6634. if (priv->ibss_beacon)
  6635. dev_kfree_skb(priv->ibss_beacon);
  6636. ieee80211_free_hw(priv->hw);
  6637. }
  6638. #ifdef CONFIG_PM
  6639. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6640. {
  6641. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6642. if (priv->is_open) {
  6643. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6644. iwl3945_mac_stop(priv->hw);
  6645. priv->is_open = 1;
  6646. }
  6647. pci_set_power_state(pdev, PCI_D3hot);
  6648. return 0;
  6649. }
  6650. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6651. {
  6652. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6653. pci_set_power_state(pdev, PCI_D0);
  6654. if (priv->is_open)
  6655. iwl3945_mac_start(priv->hw);
  6656. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6657. return 0;
  6658. }
  6659. #endif /* CONFIG_PM */
  6660. /*************** RFKILL FUNCTIONS **********/
  6661. #ifdef CONFIG_IWL3945_RFKILL
  6662. /* software rf-kill from user */
  6663. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6664. {
  6665. struct iwl_priv *priv = data;
  6666. int err = 0;
  6667. if (!priv->rfkill)
  6668. return 0;
  6669. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6670. return 0;
  6671. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6672. mutex_lock(&priv->mutex);
  6673. switch (state) {
  6674. case RFKILL_STATE_UNBLOCKED:
  6675. if (iwl3945_is_rfkill_hw(priv)) {
  6676. err = -EBUSY;
  6677. goto out_unlock;
  6678. }
  6679. iwl3945_radio_kill_sw(priv, 0);
  6680. break;
  6681. case RFKILL_STATE_SOFT_BLOCKED:
  6682. iwl3945_radio_kill_sw(priv, 1);
  6683. break;
  6684. default:
  6685. IWL_WARNING("we received unexpected RFKILL state %d\n", state);
  6686. break;
  6687. }
  6688. out_unlock:
  6689. mutex_unlock(&priv->mutex);
  6690. return err;
  6691. }
  6692. int iwl3945_rfkill_init(struct iwl_priv *priv)
  6693. {
  6694. struct device *device = wiphy_dev(priv->hw->wiphy);
  6695. int ret = 0;
  6696. BUG_ON(device == NULL);
  6697. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6698. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6699. if (!priv->rfkill) {
  6700. IWL_ERROR("Unable to allocate rfkill device.\n");
  6701. ret = -ENOMEM;
  6702. goto error;
  6703. }
  6704. priv->rfkill->name = priv->cfg->name;
  6705. priv->rfkill->data = priv;
  6706. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6707. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6708. priv->rfkill->user_claim_unsupported = 1;
  6709. priv->rfkill->dev.class->suspend = NULL;
  6710. priv->rfkill->dev.class->resume = NULL;
  6711. ret = rfkill_register(priv->rfkill);
  6712. if (ret) {
  6713. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6714. goto freed_rfkill;
  6715. }
  6716. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6717. return ret;
  6718. freed_rfkill:
  6719. if (priv->rfkill != NULL)
  6720. rfkill_free(priv->rfkill);
  6721. priv->rfkill = NULL;
  6722. error:
  6723. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6724. return ret;
  6725. }
  6726. void iwl3945_rfkill_unregister(struct iwl_priv *priv)
  6727. {
  6728. if (priv->rfkill)
  6729. rfkill_unregister(priv->rfkill);
  6730. priv->rfkill = NULL;
  6731. }
  6732. /* set rf-kill to the right state. */
  6733. void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
  6734. {
  6735. if (!priv->rfkill)
  6736. return;
  6737. if (iwl3945_is_rfkill_hw(priv)) {
  6738. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6739. return;
  6740. }
  6741. if (!iwl3945_is_rfkill_sw(priv))
  6742. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6743. else
  6744. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6745. }
  6746. #endif
  6747. /*****************************************************************************
  6748. *
  6749. * driver and module entry point
  6750. *
  6751. *****************************************************************************/
  6752. static struct pci_driver iwl3945_driver = {
  6753. .name = DRV_NAME,
  6754. .id_table = iwl3945_hw_card_ids,
  6755. .probe = iwl3945_pci_probe,
  6756. .remove = __devexit_p(iwl3945_pci_remove),
  6757. #ifdef CONFIG_PM
  6758. .suspend = iwl3945_pci_suspend,
  6759. .resume = iwl3945_pci_resume,
  6760. #endif
  6761. };
  6762. static int __init iwl3945_init(void)
  6763. {
  6764. int ret;
  6765. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6766. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6767. ret = iwl3945_rate_control_register();
  6768. if (ret) {
  6769. printk(KERN_ERR DRV_NAME
  6770. "Unable to register rate control algorithm: %d\n", ret);
  6771. return ret;
  6772. }
  6773. ret = pci_register_driver(&iwl3945_driver);
  6774. if (ret) {
  6775. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6776. goto error_register;
  6777. }
  6778. return ret;
  6779. error_register:
  6780. iwl3945_rate_control_unregister();
  6781. return ret;
  6782. }
  6783. static void __exit iwl3945_exit(void)
  6784. {
  6785. pci_unregister_driver(&iwl3945_driver);
  6786. iwl3945_rate_control_unregister();
  6787. }
  6788. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6789. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6790. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6791. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6792. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6793. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6794. MODULE_PARM_DESC(hwcrypto,
  6795. "using hardware crypto engine (default 0 [software])\n");
  6796. module_param_named(debug, iwl3945_param_debug, uint, 0444);
  6797. MODULE_PARM_DESC(debug, "debug output mask");
  6798. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6799. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6800. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6801. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6802. module_exit(iwl3945_exit);
  6803. module_init(iwl3945_init);