omap_hwmod_44xx_data.c 38 KB

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  1. /*
  2. * Hardware modules present on the OMAP44xx chips
  3. *
  4. * Copyright (C) 2009-2010 Texas Instruments, Inc.
  5. * Copyright (C) 2009-2010 Nokia Corporation
  6. *
  7. * Paul Walmsley
  8. * Benoit Cousson
  9. *
  10. * This file is automatically generated from the OMAP hardware databases.
  11. * We respectfully ask that any modifications to this file be coordinated
  12. * with the public linux-omap@vger.kernel.org mailing list and the
  13. * authors above to ensure that the autogeneration scripts are kept
  14. * up-to-date with the file contents.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License version 2 as
  18. * published by the Free Software Foundation.
  19. */
  20. #include <linux/io.h>
  21. #include <plat/omap_hwmod.h>
  22. #include <plat/cpu.h>
  23. #include <plat/gpio.h>
  24. #include "omap_hwmod_common_data.h"
  25. #include "cm.h"
  26. #include "prm-regbits-44xx.h"
  27. /* Base offset for all OMAP4 interrupts external to MPUSS */
  28. #define OMAP44XX_IRQ_GIC_START 32
  29. /* Base offset for all OMAP4 dma requests */
  30. #define OMAP44XX_DMA_REQ_START 1
  31. /* Backward references (IPs with Bus Master capability) */
  32. static struct omap_hwmod omap44xx_dmm_hwmod;
  33. static struct omap_hwmod omap44xx_emif_fw_hwmod;
  34. static struct omap_hwmod omap44xx_l3_instr_hwmod;
  35. static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  36. static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  37. static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  38. static struct omap_hwmod omap44xx_l4_abe_hwmod;
  39. static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  40. static struct omap_hwmod omap44xx_l4_per_hwmod;
  41. static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  42. static struct omap_hwmod omap44xx_mpu_hwmod;
  43. static struct omap_hwmod omap44xx_mpu_private_hwmod;
  44. /*
  45. * Interconnects omap_hwmod structures
  46. * hwmods that compose the global OMAP interconnect
  47. */
  48. /*
  49. * 'dmm' class
  50. * instance(s): dmm
  51. */
  52. static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  53. .name = "dmm",
  54. };
  55. /* dmm interface data */
  56. /* l3_main_1 -> dmm */
  57. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  58. .master = &omap44xx_l3_main_1_hwmod,
  59. .slave = &omap44xx_dmm_hwmod,
  60. .clk = "l3_div_ck",
  61. .user = OCP_USER_MPU | OCP_USER_SDMA,
  62. };
  63. /* mpu -> dmm */
  64. static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  65. .master = &omap44xx_mpu_hwmod,
  66. .slave = &omap44xx_dmm_hwmod,
  67. .clk = "l3_div_ck",
  68. .user = OCP_USER_MPU | OCP_USER_SDMA,
  69. };
  70. /* dmm slave ports */
  71. static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
  72. &omap44xx_l3_main_1__dmm,
  73. &omap44xx_mpu__dmm,
  74. };
  75. static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  76. { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  77. };
  78. static struct omap_hwmod omap44xx_dmm_hwmod = {
  79. .name = "dmm",
  80. .class = &omap44xx_dmm_hwmod_class,
  81. .slaves = omap44xx_dmm_slaves,
  82. .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
  83. .mpu_irqs = omap44xx_dmm_irqs,
  84. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
  85. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  86. };
  87. /*
  88. * 'emif_fw' class
  89. * instance(s): emif_fw
  90. */
  91. static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
  92. .name = "emif_fw",
  93. };
  94. /* emif_fw interface data */
  95. /* dmm -> emif_fw */
  96. static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
  97. .master = &omap44xx_dmm_hwmod,
  98. .slave = &omap44xx_emif_fw_hwmod,
  99. .clk = "l3_div_ck",
  100. .user = OCP_USER_MPU | OCP_USER_SDMA,
  101. };
  102. /* l4_cfg -> emif_fw */
  103. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
  104. .master = &omap44xx_l4_cfg_hwmod,
  105. .slave = &omap44xx_emif_fw_hwmod,
  106. .clk = "l4_div_ck",
  107. .user = OCP_USER_MPU | OCP_USER_SDMA,
  108. };
  109. /* emif_fw slave ports */
  110. static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
  111. &omap44xx_dmm__emif_fw,
  112. &omap44xx_l4_cfg__emif_fw,
  113. };
  114. static struct omap_hwmod omap44xx_emif_fw_hwmod = {
  115. .name = "emif_fw",
  116. .class = &omap44xx_emif_fw_hwmod_class,
  117. .slaves = omap44xx_emif_fw_slaves,
  118. .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
  119. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  120. };
  121. /*
  122. * 'l3' class
  123. * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  124. */
  125. static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  126. .name = "l3",
  127. };
  128. /* l3_instr interface data */
  129. /* l3_main_3 -> l3_instr */
  130. static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
  131. .master = &omap44xx_l3_main_3_hwmod,
  132. .slave = &omap44xx_l3_instr_hwmod,
  133. .clk = "l3_div_ck",
  134. .user = OCP_USER_MPU | OCP_USER_SDMA,
  135. };
  136. /* l3_instr slave ports */
  137. static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
  138. &omap44xx_l3_main_3__l3_instr,
  139. };
  140. static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  141. .name = "l3_instr",
  142. .class = &omap44xx_l3_hwmod_class,
  143. .slaves = omap44xx_l3_instr_slaves,
  144. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
  145. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  146. };
  147. /* l3_main_2 -> l3_main_1 */
  148. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
  149. .master = &omap44xx_l3_main_2_hwmod,
  150. .slave = &omap44xx_l3_main_1_hwmod,
  151. .clk = "l3_div_ck",
  152. .user = OCP_USER_MPU | OCP_USER_SDMA,
  153. };
  154. /* l4_cfg -> l3_main_1 */
  155. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
  156. .master = &omap44xx_l4_cfg_hwmod,
  157. .slave = &omap44xx_l3_main_1_hwmod,
  158. .clk = "l4_div_ck",
  159. .user = OCP_USER_MPU | OCP_USER_SDMA,
  160. };
  161. /* mpu -> l3_main_1 */
  162. static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
  163. .master = &omap44xx_mpu_hwmod,
  164. .slave = &omap44xx_l3_main_1_hwmod,
  165. .clk = "l3_div_ck",
  166. .user = OCP_USER_MPU | OCP_USER_SDMA,
  167. };
  168. /* l3_main_1 slave ports */
  169. static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
  170. &omap44xx_l3_main_2__l3_main_1,
  171. &omap44xx_l4_cfg__l3_main_1,
  172. &omap44xx_mpu__l3_main_1,
  173. };
  174. static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  175. .name = "l3_main_1",
  176. .class = &omap44xx_l3_hwmod_class,
  177. .slaves = omap44xx_l3_main_1_slaves,
  178. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
  179. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  180. };
  181. /* l3_main_2 interface data */
  182. /* l3_main_1 -> l3_main_2 */
  183. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
  184. .master = &omap44xx_l3_main_1_hwmod,
  185. .slave = &omap44xx_l3_main_2_hwmod,
  186. .clk = "l3_div_ck",
  187. .user = OCP_USER_MPU | OCP_USER_SDMA,
  188. };
  189. /* l4_cfg -> l3_main_2 */
  190. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
  191. .master = &omap44xx_l4_cfg_hwmod,
  192. .slave = &omap44xx_l3_main_2_hwmod,
  193. .clk = "l4_div_ck",
  194. .user = OCP_USER_MPU | OCP_USER_SDMA,
  195. };
  196. /* l3_main_2 slave ports */
  197. static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
  198. &omap44xx_l3_main_1__l3_main_2,
  199. &omap44xx_l4_cfg__l3_main_2,
  200. };
  201. static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  202. .name = "l3_main_2",
  203. .class = &omap44xx_l3_hwmod_class,
  204. .slaves = omap44xx_l3_main_2_slaves,
  205. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
  206. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  207. };
  208. /* l3_main_3 interface data */
  209. /* l3_main_1 -> l3_main_3 */
  210. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
  211. .master = &omap44xx_l3_main_1_hwmod,
  212. .slave = &omap44xx_l3_main_3_hwmod,
  213. .clk = "l3_div_ck",
  214. .user = OCP_USER_MPU | OCP_USER_SDMA,
  215. };
  216. /* l3_main_2 -> l3_main_3 */
  217. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
  218. .master = &omap44xx_l3_main_2_hwmod,
  219. .slave = &omap44xx_l3_main_3_hwmod,
  220. .clk = "l3_div_ck",
  221. .user = OCP_USER_MPU | OCP_USER_SDMA,
  222. };
  223. /* l4_cfg -> l3_main_3 */
  224. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
  225. .master = &omap44xx_l4_cfg_hwmod,
  226. .slave = &omap44xx_l3_main_3_hwmod,
  227. .clk = "l4_div_ck",
  228. .user = OCP_USER_MPU | OCP_USER_SDMA,
  229. };
  230. /* l3_main_3 slave ports */
  231. static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
  232. &omap44xx_l3_main_1__l3_main_3,
  233. &omap44xx_l3_main_2__l3_main_3,
  234. &omap44xx_l4_cfg__l3_main_3,
  235. };
  236. static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
  237. .name = "l3_main_3",
  238. .class = &omap44xx_l3_hwmod_class,
  239. .slaves = omap44xx_l3_main_3_slaves,
  240. .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
  241. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  242. };
  243. /*
  244. * 'l4' class
  245. * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
  246. */
  247. static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
  248. .name = "l4",
  249. };
  250. /* l4_abe interface data */
  251. /* l3_main_1 -> l4_abe */
  252. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
  253. .master = &omap44xx_l3_main_1_hwmod,
  254. .slave = &omap44xx_l4_abe_hwmod,
  255. .clk = "l3_div_ck",
  256. .user = OCP_USER_MPU | OCP_USER_SDMA,
  257. };
  258. /* mpu -> l4_abe */
  259. static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
  260. .master = &omap44xx_mpu_hwmod,
  261. .slave = &omap44xx_l4_abe_hwmod,
  262. .clk = "ocp_abe_iclk",
  263. .user = OCP_USER_MPU | OCP_USER_SDMA,
  264. };
  265. /* l4_abe slave ports */
  266. static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
  267. &omap44xx_l3_main_1__l4_abe,
  268. &omap44xx_mpu__l4_abe,
  269. };
  270. static struct omap_hwmod omap44xx_l4_abe_hwmod = {
  271. .name = "l4_abe",
  272. .class = &omap44xx_l4_hwmod_class,
  273. .slaves = omap44xx_l4_abe_slaves,
  274. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
  275. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  276. };
  277. /* l4_cfg interface data */
  278. /* l3_main_1 -> l4_cfg */
  279. static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
  280. .master = &omap44xx_l3_main_1_hwmod,
  281. .slave = &omap44xx_l4_cfg_hwmod,
  282. .clk = "l3_div_ck",
  283. .user = OCP_USER_MPU | OCP_USER_SDMA,
  284. };
  285. /* l4_cfg slave ports */
  286. static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
  287. &omap44xx_l3_main_1__l4_cfg,
  288. };
  289. static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
  290. .name = "l4_cfg",
  291. .class = &omap44xx_l4_hwmod_class,
  292. .slaves = omap44xx_l4_cfg_slaves,
  293. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
  294. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  295. };
  296. /* l4_per interface data */
  297. /* l3_main_2 -> l4_per */
  298. static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
  299. .master = &omap44xx_l3_main_2_hwmod,
  300. .slave = &omap44xx_l4_per_hwmod,
  301. .clk = "l3_div_ck",
  302. .user = OCP_USER_MPU | OCP_USER_SDMA,
  303. };
  304. /* l4_per slave ports */
  305. static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
  306. &omap44xx_l3_main_2__l4_per,
  307. };
  308. static struct omap_hwmod omap44xx_l4_per_hwmod = {
  309. .name = "l4_per",
  310. .class = &omap44xx_l4_hwmod_class,
  311. .slaves = omap44xx_l4_per_slaves,
  312. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
  313. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  314. };
  315. /* l4_wkup interface data */
  316. /* l4_cfg -> l4_wkup */
  317. static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
  318. .master = &omap44xx_l4_cfg_hwmod,
  319. .slave = &omap44xx_l4_wkup_hwmod,
  320. .clk = "l4_div_ck",
  321. .user = OCP_USER_MPU | OCP_USER_SDMA,
  322. };
  323. /* l4_wkup slave ports */
  324. static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
  325. &omap44xx_l4_cfg__l4_wkup,
  326. };
  327. static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
  328. .name = "l4_wkup",
  329. .class = &omap44xx_l4_hwmod_class,
  330. .slaves = omap44xx_l4_wkup_slaves,
  331. .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
  332. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  333. };
  334. /*
  335. * 'i2c' class
  336. * multimaster high-speed i2c controller
  337. */
  338. static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
  339. .sysc_offs = 0x0010,
  340. .syss_offs = 0x0090,
  341. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  342. SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
  343. SYSC_HAS_AUTOIDLE),
  344. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  345. .sysc_fields = &omap_hwmod_sysc_type1,
  346. };
  347. static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
  348. .name = "i2c",
  349. .sysc = &omap44xx_i2c_sysc,
  350. };
  351. /* i2c1 */
  352. static struct omap_hwmod omap44xx_i2c1_hwmod;
  353. static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
  354. { .irq = 56 + OMAP44XX_IRQ_GIC_START },
  355. };
  356. static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
  357. { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
  358. { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
  359. };
  360. static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
  361. {
  362. .pa_start = 0x48070000,
  363. .pa_end = 0x480700ff,
  364. .flags = ADDR_TYPE_RT
  365. },
  366. };
  367. /* l4_per -> i2c1 */
  368. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
  369. .master = &omap44xx_l4_per_hwmod,
  370. .slave = &omap44xx_i2c1_hwmod,
  371. .clk = "l4_div_ck",
  372. .addr = omap44xx_i2c1_addrs,
  373. .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
  374. .user = OCP_USER_MPU | OCP_USER_SDMA,
  375. };
  376. /* i2c1 slave ports */
  377. static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
  378. &omap44xx_l4_per__i2c1,
  379. };
  380. static struct omap_hwmod omap44xx_i2c1_hwmod = {
  381. .name = "i2c1",
  382. .class = &omap44xx_i2c_hwmod_class,
  383. .flags = HWMOD_INIT_NO_RESET,
  384. .mpu_irqs = omap44xx_i2c1_irqs,
  385. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
  386. .sdma_reqs = omap44xx_i2c1_sdma_reqs,
  387. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
  388. .main_clk = "i2c1_fck",
  389. .prcm = {
  390. .omap4 = {
  391. .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
  392. },
  393. },
  394. .slaves = omap44xx_i2c1_slaves,
  395. .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
  396. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  397. };
  398. /* i2c2 */
  399. static struct omap_hwmod omap44xx_i2c2_hwmod;
  400. static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
  401. { .irq = 57 + OMAP44XX_IRQ_GIC_START },
  402. };
  403. static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
  404. { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
  405. { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
  406. };
  407. static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
  408. {
  409. .pa_start = 0x48072000,
  410. .pa_end = 0x480720ff,
  411. .flags = ADDR_TYPE_RT
  412. },
  413. };
  414. /* l4_per -> i2c2 */
  415. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
  416. .master = &omap44xx_l4_per_hwmod,
  417. .slave = &omap44xx_i2c2_hwmod,
  418. .clk = "l4_div_ck",
  419. .addr = omap44xx_i2c2_addrs,
  420. .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
  421. .user = OCP_USER_MPU | OCP_USER_SDMA,
  422. };
  423. /* i2c2 slave ports */
  424. static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
  425. &omap44xx_l4_per__i2c2,
  426. };
  427. static struct omap_hwmod omap44xx_i2c2_hwmod = {
  428. .name = "i2c2",
  429. .class = &omap44xx_i2c_hwmod_class,
  430. .flags = HWMOD_INIT_NO_RESET,
  431. .mpu_irqs = omap44xx_i2c2_irqs,
  432. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
  433. .sdma_reqs = omap44xx_i2c2_sdma_reqs,
  434. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
  435. .main_clk = "i2c2_fck",
  436. .prcm = {
  437. .omap4 = {
  438. .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
  439. },
  440. },
  441. .slaves = omap44xx_i2c2_slaves,
  442. .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
  443. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  444. };
  445. /* i2c3 */
  446. static struct omap_hwmod omap44xx_i2c3_hwmod;
  447. static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
  448. { .irq = 61 + OMAP44XX_IRQ_GIC_START },
  449. };
  450. static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
  451. { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
  452. { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
  453. };
  454. static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
  455. {
  456. .pa_start = 0x48060000,
  457. .pa_end = 0x480600ff,
  458. .flags = ADDR_TYPE_RT
  459. },
  460. };
  461. /* l4_per -> i2c3 */
  462. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
  463. .master = &omap44xx_l4_per_hwmod,
  464. .slave = &omap44xx_i2c3_hwmod,
  465. .clk = "l4_div_ck",
  466. .addr = omap44xx_i2c3_addrs,
  467. .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
  468. .user = OCP_USER_MPU | OCP_USER_SDMA,
  469. };
  470. /* i2c3 slave ports */
  471. static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
  472. &omap44xx_l4_per__i2c3,
  473. };
  474. static struct omap_hwmod omap44xx_i2c3_hwmod = {
  475. .name = "i2c3",
  476. .class = &omap44xx_i2c_hwmod_class,
  477. .flags = HWMOD_INIT_NO_RESET,
  478. .mpu_irqs = omap44xx_i2c3_irqs,
  479. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
  480. .sdma_reqs = omap44xx_i2c3_sdma_reqs,
  481. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
  482. .main_clk = "i2c3_fck",
  483. .prcm = {
  484. .omap4 = {
  485. .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
  486. },
  487. },
  488. .slaves = omap44xx_i2c3_slaves,
  489. .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
  490. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  491. };
  492. /* i2c4 */
  493. static struct omap_hwmod omap44xx_i2c4_hwmod;
  494. static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
  495. { .irq = 62 + OMAP44XX_IRQ_GIC_START },
  496. };
  497. static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
  498. { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
  499. { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
  500. };
  501. static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
  502. {
  503. .pa_start = 0x48350000,
  504. .pa_end = 0x483500ff,
  505. .flags = ADDR_TYPE_RT
  506. },
  507. };
  508. /* l4_per -> i2c4 */
  509. static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
  510. .master = &omap44xx_l4_per_hwmod,
  511. .slave = &omap44xx_i2c4_hwmod,
  512. .clk = "l4_div_ck",
  513. .addr = omap44xx_i2c4_addrs,
  514. .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
  515. .user = OCP_USER_MPU | OCP_USER_SDMA,
  516. };
  517. /* i2c4 slave ports */
  518. static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
  519. &omap44xx_l4_per__i2c4,
  520. };
  521. static struct omap_hwmod omap44xx_i2c4_hwmod = {
  522. .name = "i2c4",
  523. .class = &omap44xx_i2c_hwmod_class,
  524. .flags = HWMOD_INIT_NO_RESET,
  525. .mpu_irqs = omap44xx_i2c4_irqs,
  526. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
  527. .sdma_reqs = omap44xx_i2c4_sdma_reqs,
  528. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
  529. .main_clk = "i2c4_fck",
  530. .prcm = {
  531. .omap4 = {
  532. .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
  533. },
  534. },
  535. .slaves = omap44xx_i2c4_slaves,
  536. .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
  537. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  538. };
  539. /*
  540. * 'mpu_bus' class
  541. * instance(s): mpu_private
  542. */
  543. static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
  544. .name = "mpu_bus",
  545. };
  546. /* mpu_private interface data */
  547. /* mpu -> mpu_private */
  548. static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
  549. .master = &omap44xx_mpu_hwmod,
  550. .slave = &omap44xx_mpu_private_hwmod,
  551. .clk = "l3_div_ck",
  552. .user = OCP_USER_MPU | OCP_USER_SDMA,
  553. };
  554. /* mpu_private slave ports */
  555. static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
  556. &omap44xx_mpu__mpu_private,
  557. };
  558. static struct omap_hwmod omap44xx_mpu_private_hwmod = {
  559. .name = "mpu_private",
  560. .class = &omap44xx_mpu_bus_hwmod_class,
  561. .slaves = omap44xx_mpu_private_slaves,
  562. .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
  563. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  564. };
  565. /*
  566. * 'mpu' class
  567. * mpu sub-system
  568. */
  569. static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
  570. .name = "mpu",
  571. };
  572. /* mpu */
  573. static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
  574. { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
  575. { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
  576. { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
  577. };
  578. /* mpu master ports */
  579. static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
  580. &omap44xx_mpu__l3_main_1,
  581. &omap44xx_mpu__l4_abe,
  582. &omap44xx_mpu__dmm,
  583. };
  584. static struct omap_hwmod omap44xx_mpu_hwmod = {
  585. .name = "mpu",
  586. .class = &omap44xx_mpu_hwmod_class,
  587. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  588. .mpu_irqs = omap44xx_mpu_irqs,
  589. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
  590. .main_clk = "dpll_mpu_m2_ck",
  591. .prcm = {
  592. .omap4 = {
  593. .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
  594. },
  595. },
  596. .masters = omap44xx_mpu_masters,
  597. .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
  598. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  599. };
  600. /*
  601. * 'wd_timer' class
  602. * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  603. * overflow condition
  604. */
  605. static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
  606. .rev_offs = 0x0000,
  607. .sysc_offs = 0x0010,
  608. .syss_offs = 0x0014,
  609. .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
  610. SYSC_HAS_SOFTRESET),
  611. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  612. .sysc_fields = &omap_hwmod_sysc_type1,
  613. };
  614. /*
  615. * 'uart' class
  616. * universal asynchronous receiver/transmitter (uart)
  617. */
  618. static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
  619. .rev_offs = 0x0050,
  620. .sysc_offs = 0x0054,
  621. .syss_offs = 0x0058,
  622. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  623. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  624. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  625. .sysc_fields = &omap_hwmod_sysc_type1,
  626. };
  627. static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
  628. .name = "wd_timer",
  629. .sysc = &omap44xx_wd_timer_sysc,
  630. };
  631. /* wd_timer2 */
  632. static struct omap_hwmod omap44xx_wd_timer2_hwmod;
  633. static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
  634. { .irq = 80 + OMAP44XX_IRQ_GIC_START },
  635. };
  636. static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
  637. {
  638. .pa_start = 0x4a314000,
  639. .pa_end = 0x4a31407f,
  640. .flags = ADDR_TYPE_RT
  641. },
  642. };
  643. static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
  644. .name = "uart",
  645. .sysc = &omap44xx_uart_sysc,
  646. };
  647. /* uart1 */
  648. static struct omap_hwmod omap44xx_uart1_hwmod;
  649. static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
  650. { .irq = 72 + OMAP44XX_IRQ_GIC_START },
  651. };
  652. static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
  653. { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
  654. { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
  655. };
  656. static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
  657. {
  658. .pa_start = 0x4806a000,
  659. .pa_end = 0x4806a0ff,
  660. .flags = ADDR_TYPE_RT
  661. },
  662. };
  663. /* l4_per -> uart1 */
  664. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
  665. .master = &omap44xx_l4_per_hwmod,
  666. .slave = &omap44xx_uart1_hwmod,
  667. .clk = "l4_div_ck",
  668. .addr = omap44xx_uart1_addrs,
  669. .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
  670. .user = OCP_USER_MPU | OCP_USER_SDMA,
  671. };
  672. /* uart1 slave ports */
  673. static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
  674. &omap44xx_l4_per__uart1,
  675. };
  676. static struct omap_hwmod omap44xx_uart1_hwmod = {
  677. .name = "uart1",
  678. .class = &omap44xx_uart_hwmod_class,
  679. .mpu_irqs = omap44xx_uart1_irqs,
  680. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
  681. .sdma_reqs = omap44xx_uart1_sdma_reqs,
  682. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
  683. .main_clk = "uart1_fck",
  684. .prcm = {
  685. .omap4 = {
  686. .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
  687. },
  688. },
  689. .slaves = omap44xx_uart1_slaves,
  690. .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
  691. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  692. };
  693. /* uart2 */
  694. static struct omap_hwmod omap44xx_uart2_hwmod;
  695. static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
  696. { .irq = 73 + OMAP44XX_IRQ_GIC_START },
  697. };
  698. static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
  699. { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
  700. { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
  701. };
  702. static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
  703. {
  704. .pa_start = 0x4806c000,
  705. .pa_end = 0x4806c0ff,
  706. .flags = ADDR_TYPE_RT
  707. },
  708. };
  709. /* l4_wkup -> wd_timer2 */
  710. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
  711. .master = &omap44xx_l4_wkup_hwmod,
  712. .slave = &omap44xx_wd_timer2_hwmod,
  713. .clk = "l4_wkup_clk_mux_ck",
  714. .addr = omap44xx_wd_timer2_addrs,
  715. .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
  716. .user = OCP_USER_MPU | OCP_USER_SDMA,
  717. };
  718. /* wd_timer2 slave ports */
  719. static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
  720. &omap44xx_l4_wkup__wd_timer2,
  721. };
  722. static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
  723. .name = "wd_timer2",
  724. .class = &omap44xx_wd_timer_hwmod_class,
  725. .mpu_irqs = omap44xx_wd_timer2_irqs,
  726. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
  727. .main_clk = "wd_timer2_fck",
  728. .prcm = {
  729. .omap4 = {
  730. .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
  731. },
  732. },
  733. .slaves = omap44xx_wd_timer2_slaves,
  734. .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
  735. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  736. };
  737. /* wd_timer3 */
  738. static struct omap_hwmod omap44xx_wd_timer3_hwmod;
  739. static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
  740. { .irq = 36 + OMAP44XX_IRQ_GIC_START },
  741. };
  742. static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
  743. {
  744. .pa_start = 0x40130000,
  745. .pa_end = 0x4013007f,
  746. .flags = ADDR_TYPE_RT
  747. },
  748. };
  749. /* l4_per -> uart2 */
  750. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
  751. .master = &omap44xx_l4_per_hwmod,
  752. .slave = &omap44xx_uart2_hwmod,
  753. .clk = "l4_div_ck",
  754. .addr = omap44xx_uart2_addrs,
  755. .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
  756. .user = OCP_USER_MPU | OCP_USER_SDMA,
  757. };
  758. /* uart2 slave ports */
  759. static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
  760. &omap44xx_l4_per__uart2,
  761. };
  762. static struct omap_hwmod omap44xx_uart2_hwmod = {
  763. .name = "uart2",
  764. .class = &omap44xx_uart_hwmod_class,
  765. .mpu_irqs = omap44xx_uart2_irqs,
  766. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
  767. .sdma_reqs = omap44xx_uart2_sdma_reqs,
  768. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
  769. .main_clk = "uart2_fck",
  770. .prcm = {
  771. .omap4 = {
  772. .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
  773. },
  774. },
  775. .slaves = omap44xx_uart2_slaves,
  776. .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
  777. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  778. };
  779. /* uart3 */
  780. static struct omap_hwmod omap44xx_uart3_hwmod;
  781. static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
  782. { .irq = 74 + OMAP44XX_IRQ_GIC_START },
  783. };
  784. static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
  785. { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
  786. { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
  787. };
  788. static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
  789. {
  790. .pa_start = 0x48020000,
  791. .pa_end = 0x480200ff,
  792. .flags = ADDR_TYPE_RT
  793. },
  794. };
  795. /* l4_abe -> wd_timer3 */
  796. static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
  797. .master = &omap44xx_l4_abe_hwmod,
  798. .slave = &omap44xx_wd_timer3_hwmod,
  799. .clk = "ocp_abe_iclk",
  800. .addr = omap44xx_wd_timer3_addrs,
  801. .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
  802. .user = OCP_USER_MPU,
  803. };
  804. /* l4_abe -> wd_timer3 (dma) */
  805. static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
  806. {
  807. .pa_start = 0x49030000,
  808. .pa_end = 0x4903007f,
  809. .flags = ADDR_TYPE_RT
  810. },
  811. };
  812. /* l4_per -> uart3 */
  813. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
  814. .master = &omap44xx_l4_per_hwmod,
  815. .slave = &omap44xx_uart3_hwmod,
  816. .clk = "l4_div_ck",
  817. .addr = omap44xx_uart3_addrs,
  818. .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
  819. .user = OCP_USER_MPU | OCP_USER_SDMA,
  820. };
  821. /* uart3 slave ports */
  822. static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
  823. &omap44xx_l4_per__uart3,
  824. };
  825. static struct omap_hwmod omap44xx_uart3_hwmod = {
  826. .name = "uart3",
  827. .class = &omap44xx_uart_hwmod_class,
  828. .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
  829. .mpu_irqs = omap44xx_uart3_irqs,
  830. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
  831. .sdma_reqs = omap44xx_uart3_sdma_reqs,
  832. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
  833. .main_clk = "uart3_fck",
  834. .prcm = {
  835. .omap4 = {
  836. .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
  837. },
  838. },
  839. .slaves = omap44xx_uart3_slaves,
  840. .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
  841. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  842. };
  843. /* uart4 */
  844. static struct omap_hwmod omap44xx_uart4_hwmod;
  845. static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
  846. { .irq = 70 + OMAP44XX_IRQ_GIC_START },
  847. };
  848. static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
  849. { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
  850. { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
  851. };
  852. static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
  853. {
  854. .pa_start = 0x4806e000,
  855. .pa_end = 0x4806e0ff,
  856. .flags = ADDR_TYPE_RT
  857. },
  858. };
  859. static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
  860. .master = &omap44xx_l4_abe_hwmod,
  861. .slave = &omap44xx_wd_timer3_hwmod,
  862. .clk = "ocp_abe_iclk",
  863. .addr = omap44xx_wd_timer3_dma_addrs,
  864. .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
  865. .user = OCP_USER_SDMA,
  866. };
  867. /* wd_timer3 slave ports */
  868. static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
  869. &omap44xx_l4_abe__wd_timer3,
  870. &omap44xx_l4_abe__wd_timer3_dma,
  871. };
  872. static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
  873. .name = "wd_timer3",
  874. .class = &omap44xx_wd_timer_hwmod_class,
  875. .mpu_irqs = omap44xx_wd_timer3_irqs,
  876. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
  877. .main_clk = "wd_timer3_fck",
  878. .prcm = {
  879. .omap4 = {
  880. .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
  881. },
  882. },
  883. .slaves = omap44xx_wd_timer3_slaves,
  884. .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
  885. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  886. };
  887. /* l4_per -> uart4 */
  888. static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
  889. .master = &omap44xx_l4_per_hwmod,
  890. .slave = &omap44xx_uart4_hwmod,
  891. .clk = "l4_div_ck",
  892. .addr = omap44xx_uart4_addrs,
  893. .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
  894. .user = OCP_USER_MPU | OCP_USER_SDMA,
  895. };
  896. /* uart4 slave ports */
  897. static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
  898. &omap44xx_l4_per__uart4,
  899. };
  900. static struct omap_hwmod omap44xx_uart4_hwmod = {
  901. .name = "uart4",
  902. .class = &omap44xx_uart_hwmod_class,
  903. .mpu_irqs = omap44xx_uart4_irqs,
  904. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
  905. .sdma_reqs = omap44xx_uart4_sdma_reqs,
  906. .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
  907. .main_clk = "uart4_fck",
  908. .prcm = {
  909. .omap4 = {
  910. .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
  911. },
  912. },
  913. .slaves = omap44xx_uart4_slaves,
  914. .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
  915. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  916. };
  917. /*
  918. * 'gpio' class
  919. * general purpose io module
  920. */
  921. static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
  922. .rev_offs = 0x0000,
  923. .sysc_offs = 0x0010,
  924. .syss_offs = 0x0114,
  925. .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  926. SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  927. .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  928. .sysc_fields = &omap_hwmod_sysc_type1,
  929. };
  930. static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
  931. .name = "gpio",
  932. .sysc = &omap44xx_gpio_sysc,
  933. .rev = 2,
  934. };
  935. /* gpio dev_attr */
  936. static struct omap_gpio_dev_attr gpio_dev_attr = {
  937. .bank_width = 32,
  938. .dbck_flag = true,
  939. };
  940. /* gpio1 */
  941. static struct omap_hwmod omap44xx_gpio1_hwmod;
  942. static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
  943. { .irq = 29 + OMAP44XX_IRQ_GIC_START },
  944. };
  945. static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
  946. {
  947. .pa_start = 0x4a310000,
  948. .pa_end = 0x4a3101ff,
  949. .flags = ADDR_TYPE_RT
  950. },
  951. };
  952. /* l4_wkup -> gpio1 */
  953. static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
  954. .master = &omap44xx_l4_wkup_hwmod,
  955. .slave = &omap44xx_gpio1_hwmod,
  956. .addr = omap44xx_gpio1_addrs,
  957. .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
  958. .user = OCP_USER_MPU | OCP_USER_SDMA,
  959. };
  960. /* gpio1 slave ports */
  961. static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
  962. &omap44xx_l4_wkup__gpio1,
  963. };
  964. static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
  965. { .role = "dbclk", .clk = "sys_32k_ck" },
  966. };
  967. static struct omap_hwmod omap44xx_gpio1_hwmod = {
  968. .name = "gpio1",
  969. .class = &omap44xx_gpio_hwmod_class,
  970. .mpu_irqs = omap44xx_gpio1_irqs,
  971. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
  972. .main_clk = "gpio1_ick",
  973. .prcm = {
  974. .omap4 = {
  975. .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
  976. },
  977. },
  978. .opt_clks = gpio1_opt_clks,
  979. .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
  980. .dev_attr = &gpio_dev_attr,
  981. .slaves = omap44xx_gpio1_slaves,
  982. .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
  983. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  984. };
  985. /* gpio2 */
  986. static struct omap_hwmod omap44xx_gpio2_hwmod;
  987. static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
  988. { .irq = 30 + OMAP44XX_IRQ_GIC_START },
  989. };
  990. static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
  991. {
  992. .pa_start = 0x48055000,
  993. .pa_end = 0x480551ff,
  994. .flags = ADDR_TYPE_RT
  995. },
  996. };
  997. /* l4_per -> gpio2 */
  998. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
  999. .master = &omap44xx_l4_per_hwmod,
  1000. .slave = &omap44xx_gpio2_hwmod,
  1001. .addr = omap44xx_gpio2_addrs,
  1002. .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
  1003. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1004. };
  1005. /* gpio2 slave ports */
  1006. static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
  1007. &omap44xx_l4_per__gpio2,
  1008. };
  1009. static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
  1010. { .role = "dbclk", .clk = "sys_32k_ck" },
  1011. };
  1012. static struct omap_hwmod omap44xx_gpio2_hwmod = {
  1013. .name = "gpio2",
  1014. .class = &omap44xx_gpio_hwmod_class,
  1015. .mpu_irqs = omap44xx_gpio2_irqs,
  1016. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
  1017. .main_clk = "gpio2_ick",
  1018. .prcm = {
  1019. .omap4 = {
  1020. .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
  1021. },
  1022. },
  1023. .opt_clks = gpio2_opt_clks,
  1024. .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
  1025. .dev_attr = &gpio_dev_attr,
  1026. .slaves = omap44xx_gpio2_slaves,
  1027. .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
  1028. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1029. };
  1030. /* gpio3 */
  1031. static struct omap_hwmod omap44xx_gpio3_hwmod;
  1032. static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
  1033. { .irq = 31 + OMAP44XX_IRQ_GIC_START },
  1034. };
  1035. static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
  1036. {
  1037. .pa_start = 0x48057000,
  1038. .pa_end = 0x480571ff,
  1039. .flags = ADDR_TYPE_RT
  1040. },
  1041. };
  1042. /* l4_per -> gpio3 */
  1043. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
  1044. .master = &omap44xx_l4_per_hwmod,
  1045. .slave = &omap44xx_gpio3_hwmod,
  1046. .addr = omap44xx_gpio3_addrs,
  1047. .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
  1048. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1049. };
  1050. /* gpio3 slave ports */
  1051. static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
  1052. &omap44xx_l4_per__gpio3,
  1053. };
  1054. static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
  1055. { .role = "dbclk", .clk = "sys_32k_ck" },
  1056. };
  1057. static struct omap_hwmod omap44xx_gpio3_hwmod = {
  1058. .name = "gpio3",
  1059. .class = &omap44xx_gpio_hwmod_class,
  1060. .mpu_irqs = omap44xx_gpio3_irqs,
  1061. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
  1062. .main_clk = "gpio3_ick",
  1063. .prcm = {
  1064. .omap4 = {
  1065. .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
  1066. },
  1067. },
  1068. .opt_clks = gpio3_opt_clks,
  1069. .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
  1070. .dev_attr = &gpio_dev_attr,
  1071. .slaves = omap44xx_gpio3_slaves,
  1072. .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
  1073. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1074. };
  1075. /* gpio4 */
  1076. static struct omap_hwmod omap44xx_gpio4_hwmod;
  1077. static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
  1078. { .irq = 32 + OMAP44XX_IRQ_GIC_START },
  1079. };
  1080. static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
  1081. {
  1082. .pa_start = 0x48059000,
  1083. .pa_end = 0x480591ff,
  1084. .flags = ADDR_TYPE_RT
  1085. },
  1086. };
  1087. /* l4_per -> gpio4 */
  1088. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
  1089. .master = &omap44xx_l4_per_hwmod,
  1090. .slave = &omap44xx_gpio4_hwmod,
  1091. .addr = omap44xx_gpio4_addrs,
  1092. .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
  1093. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1094. };
  1095. /* gpio4 slave ports */
  1096. static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
  1097. &omap44xx_l4_per__gpio4,
  1098. };
  1099. static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
  1100. { .role = "dbclk", .clk = "sys_32k_ck" },
  1101. };
  1102. static struct omap_hwmod omap44xx_gpio4_hwmod = {
  1103. .name = "gpio4",
  1104. .class = &omap44xx_gpio_hwmod_class,
  1105. .mpu_irqs = omap44xx_gpio4_irqs,
  1106. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
  1107. .main_clk = "gpio4_ick",
  1108. .prcm = {
  1109. .omap4 = {
  1110. .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
  1111. },
  1112. },
  1113. .opt_clks = gpio4_opt_clks,
  1114. .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
  1115. .dev_attr = &gpio_dev_attr,
  1116. .slaves = omap44xx_gpio4_slaves,
  1117. .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
  1118. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1119. };
  1120. /* gpio5 */
  1121. static struct omap_hwmod omap44xx_gpio5_hwmod;
  1122. static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
  1123. { .irq = 33 + OMAP44XX_IRQ_GIC_START },
  1124. };
  1125. static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
  1126. {
  1127. .pa_start = 0x4805b000,
  1128. .pa_end = 0x4805b1ff,
  1129. .flags = ADDR_TYPE_RT
  1130. },
  1131. };
  1132. /* l4_per -> gpio5 */
  1133. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
  1134. .master = &omap44xx_l4_per_hwmod,
  1135. .slave = &omap44xx_gpio5_hwmod,
  1136. .addr = omap44xx_gpio5_addrs,
  1137. .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
  1138. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1139. };
  1140. /* gpio5 slave ports */
  1141. static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
  1142. &omap44xx_l4_per__gpio5,
  1143. };
  1144. static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
  1145. { .role = "dbclk", .clk = "sys_32k_ck" },
  1146. };
  1147. static struct omap_hwmod omap44xx_gpio5_hwmod = {
  1148. .name = "gpio5",
  1149. .class = &omap44xx_gpio_hwmod_class,
  1150. .mpu_irqs = omap44xx_gpio5_irqs,
  1151. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
  1152. .main_clk = "gpio5_ick",
  1153. .prcm = {
  1154. .omap4 = {
  1155. .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
  1156. },
  1157. },
  1158. .opt_clks = gpio5_opt_clks,
  1159. .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
  1160. .dev_attr = &gpio_dev_attr,
  1161. .slaves = omap44xx_gpio5_slaves,
  1162. .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
  1163. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1164. };
  1165. /* gpio6 */
  1166. static struct omap_hwmod omap44xx_gpio6_hwmod;
  1167. static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
  1168. { .irq = 34 + OMAP44XX_IRQ_GIC_START },
  1169. };
  1170. static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
  1171. {
  1172. .pa_start = 0x4805d000,
  1173. .pa_end = 0x4805d1ff,
  1174. .flags = ADDR_TYPE_RT
  1175. },
  1176. };
  1177. /* l4_per -> gpio6 */
  1178. static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
  1179. .master = &omap44xx_l4_per_hwmod,
  1180. .slave = &omap44xx_gpio6_hwmod,
  1181. .addr = omap44xx_gpio6_addrs,
  1182. .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
  1183. .user = OCP_USER_MPU | OCP_USER_SDMA,
  1184. };
  1185. /* gpio6 slave ports */
  1186. static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
  1187. &omap44xx_l4_per__gpio6,
  1188. };
  1189. static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
  1190. { .role = "dbclk", .clk = "sys_32k_ck" },
  1191. };
  1192. static struct omap_hwmod omap44xx_gpio6_hwmod = {
  1193. .name = "gpio6",
  1194. .class = &omap44xx_gpio_hwmod_class,
  1195. .mpu_irqs = omap44xx_gpio6_irqs,
  1196. .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
  1197. .main_clk = "gpio6_ick",
  1198. .prcm = {
  1199. .omap4 = {
  1200. .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
  1201. },
  1202. },
  1203. .opt_clks = gpio6_opt_clks,
  1204. .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
  1205. .dev_attr = &gpio_dev_attr,
  1206. .slaves = omap44xx_gpio6_slaves,
  1207. .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
  1208. .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  1209. };
  1210. static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
  1211. /* dmm class */
  1212. &omap44xx_dmm_hwmod,
  1213. /* emif_fw class */
  1214. &omap44xx_emif_fw_hwmod,
  1215. /* l3 class */
  1216. &omap44xx_l3_instr_hwmod,
  1217. &omap44xx_l3_main_1_hwmod,
  1218. &omap44xx_l3_main_2_hwmod,
  1219. &omap44xx_l3_main_3_hwmod,
  1220. /* l4 class */
  1221. &omap44xx_l4_abe_hwmod,
  1222. &omap44xx_l4_cfg_hwmod,
  1223. &omap44xx_l4_per_hwmod,
  1224. &omap44xx_l4_wkup_hwmod,
  1225. /* i2c class */
  1226. &omap44xx_i2c1_hwmod,
  1227. &omap44xx_i2c2_hwmod,
  1228. &omap44xx_i2c3_hwmod,
  1229. &omap44xx_i2c4_hwmod,
  1230. /* mpu_bus class */
  1231. &omap44xx_mpu_private_hwmod,
  1232. /* gpio class */
  1233. &omap44xx_gpio1_hwmod,
  1234. &omap44xx_gpio2_hwmod,
  1235. &omap44xx_gpio3_hwmod,
  1236. &omap44xx_gpio4_hwmod,
  1237. &omap44xx_gpio5_hwmod,
  1238. &omap44xx_gpio6_hwmod,
  1239. /* mpu class */
  1240. &omap44xx_mpu_hwmod,
  1241. /* wd_timer class */
  1242. &omap44xx_wd_timer2_hwmod,
  1243. &omap44xx_wd_timer3_hwmod,
  1244. /* uart class */
  1245. &omap44xx_uart1_hwmod,
  1246. &omap44xx_uart2_hwmod,
  1247. &omap44xx_uart3_hwmod,
  1248. &omap44xx_uart4_hwmod,
  1249. NULL,
  1250. };
  1251. int __init omap44xx_hwmod_init(void)
  1252. {
  1253. return omap_hwmod_init(omap44xx_hwmods);
  1254. }