oxygen_pcm.c 20 KB

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  1. /*
  2. * C-Media CMI8788 driver - PCM code
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. *
  7. * This driver is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License, version 2.
  9. *
  10. * This driver is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this driver; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/pci.h>
  20. #include <sound/control.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include "oxygen.h"
  25. static const struct snd_pcm_hardware oxygen_stereo_hardware = {
  26. .info = SNDRV_PCM_INFO_MMAP |
  27. SNDRV_PCM_INFO_MMAP_VALID |
  28. SNDRV_PCM_INFO_INTERLEAVED |
  29. SNDRV_PCM_INFO_PAUSE |
  30. SNDRV_PCM_INFO_SYNC_START,
  31. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  32. SNDRV_PCM_FMTBIT_S32_LE,
  33. .rates = SNDRV_PCM_RATE_32000 |
  34. SNDRV_PCM_RATE_44100 |
  35. SNDRV_PCM_RATE_48000 |
  36. SNDRV_PCM_RATE_64000 |
  37. SNDRV_PCM_RATE_88200 |
  38. SNDRV_PCM_RATE_96000 |
  39. SNDRV_PCM_RATE_176400 |
  40. SNDRV_PCM_RATE_192000,
  41. .rate_min = 32000,
  42. .rate_max = 192000,
  43. .channels_min = 2,
  44. .channels_max = 2,
  45. .buffer_bytes_max = 256 * 1024,
  46. .period_bytes_min = 128,
  47. .period_bytes_max = 128 * 1024,
  48. .periods_min = 2,
  49. .periods_max = 2048,
  50. };
  51. static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
  52. .info = SNDRV_PCM_INFO_MMAP |
  53. SNDRV_PCM_INFO_MMAP_VALID |
  54. SNDRV_PCM_INFO_INTERLEAVED |
  55. SNDRV_PCM_INFO_PAUSE |
  56. SNDRV_PCM_INFO_SYNC_START,
  57. .formats = SNDRV_PCM_FMTBIT_S16_LE |
  58. SNDRV_PCM_FMTBIT_S32_LE,
  59. .rates = SNDRV_PCM_RATE_32000 |
  60. SNDRV_PCM_RATE_44100 |
  61. SNDRV_PCM_RATE_48000 |
  62. SNDRV_PCM_RATE_64000 |
  63. SNDRV_PCM_RATE_88200 |
  64. SNDRV_PCM_RATE_96000 |
  65. SNDRV_PCM_RATE_176400 |
  66. SNDRV_PCM_RATE_192000,
  67. .rate_min = 32000,
  68. .rate_max = 192000,
  69. .channels_min = 2,
  70. .channels_max = 8,
  71. .buffer_bytes_max = 2048 * 1024,
  72. .period_bytes_min = 128,
  73. .period_bytes_max = 256 * 1024,
  74. .periods_min = 2,
  75. .periods_max = 16384,
  76. };
  77. static const struct snd_pcm_hardware oxygen_ac97_hardware = {
  78. .info = SNDRV_PCM_INFO_MMAP |
  79. SNDRV_PCM_INFO_MMAP_VALID |
  80. SNDRV_PCM_INFO_INTERLEAVED |
  81. SNDRV_PCM_INFO_PAUSE |
  82. SNDRV_PCM_INFO_SYNC_START,
  83. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  84. .rates = SNDRV_PCM_RATE_48000,
  85. .rate_min = 48000,
  86. .rate_max = 48000,
  87. .channels_min = 2,
  88. .channels_max = 2,
  89. .buffer_bytes_max = 256 * 1024,
  90. .period_bytes_min = 128,
  91. .period_bytes_max = 128 * 1024,
  92. .periods_min = 2,
  93. .periods_max = 2048,
  94. };
  95. static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
  96. [PCM_A] = &oxygen_stereo_hardware,
  97. [PCM_B] = &oxygen_stereo_hardware,
  98. [PCM_C] = &oxygen_stereo_hardware,
  99. [PCM_SPDIF] = &oxygen_stereo_hardware,
  100. [PCM_MULTICH] = &oxygen_multichannel_hardware,
  101. [PCM_AC97] = &oxygen_ac97_hardware,
  102. };
  103. static inline unsigned int
  104. oxygen_substream_channel(struct snd_pcm_substream *substream)
  105. {
  106. return (unsigned int)(uintptr_t)substream->runtime->private_data;
  107. }
  108. static int oxygen_open(struct snd_pcm_substream *substream,
  109. unsigned int channel)
  110. {
  111. struct oxygen *chip = snd_pcm_substream_chip(substream);
  112. struct snd_pcm_runtime *runtime = substream->runtime;
  113. int err;
  114. runtime->private_data = (void *)(uintptr_t)channel;
  115. runtime->hw = *oxygen_hardware[channel];
  116. switch (channel) {
  117. case PCM_C:
  118. runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
  119. SNDRV_PCM_RATE_64000);
  120. runtime->hw.rate_min = 44100;
  121. break;
  122. case PCM_MULTICH:
  123. runtime->hw.channels_max = chip->model->dac_channels;
  124. break;
  125. }
  126. if (chip->model->pcm_hardware_filter)
  127. chip->model->pcm_hardware_filter(channel, &runtime->hw);
  128. err = snd_pcm_hw_constraint_step(runtime, 0,
  129. SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
  130. if (err < 0)
  131. return err;
  132. err = snd_pcm_hw_constraint_step(runtime, 0,
  133. SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
  134. if (err < 0)
  135. return err;
  136. if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
  137. err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  138. if (err < 0)
  139. return err;
  140. }
  141. if (runtime->hw.channels_max > 2) {
  142. err = snd_pcm_hw_constraint_step(runtime, 0,
  143. SNDRV_PCM_HW_PARAM_CHANNELS,
  144. 2);
  145. if (err < 0)
  146. return err;
  147. }
  148. snd_pcm_set_sync(substream);
  149. chip->streams[channel] = substream;
  150. mutex_lock(&chip->mutex);
  151. chip->pcm_active |= 1 << channel;
  152. if (channel == PCM_SPDIF) {
  153. chip->spdif_pcm_bits = chip->spdif_bits;
  154. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
  155. ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  156. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  157. SNDRV_CTL_EVENT_MASK_INFO,
  158. &chip->controls[CONTROL_SPDIF_PCM]->id);
  159. }
  160. mutex_unlock(&chip->mutex);
  161. return 0;
  162. }
  163. static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
  164. {
  165. return oxygen_open(substream, PCM_A);
  166. }
  167. static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
  168. {
  169. return oxygen_open(substream, PCM_B);
  170. }
  171. static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
  172. {
  173. return oxygen_open(substream, PCM_C);
  174. }
  175. static int oxygen_spdif_open(struct snd_pcm_substream *substream)
  176. {
  177. return oxygen_open(substream, PCM_SPDIF);
  178. }
  179. static int oxygen_multich_open(struct snd_pcm_substream *substream)
  180. {
  181. return oxygen_open(substream, PCM_MULTICH);
  182. }
  183. static int oxygen_ac97_open(struct snd_pcm_substream *substream)
  184. {
  185. return oxygen_open(substream, PCM_AC97);
  186. }
  187. static int oxygen_close(struct snd_pcm_substream *substream)
  188. {
  189. struct oxygen *chip = snd_pcm_substream_chip(substream);
  190. unsigned int channel = oxygen_substream_channel(substream);
  191. mutex_lock(&chip->mutex);
  192. chip->pcm_active &= ~(1 << channel);
  193. if (channel == PCM_SPDIF) {
  194. chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
  195. SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  196. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  197. SNDRV_CTL_EVENT_MASK_INFO,
  198. &chip->controls[CONTROL_SPDIF_PCM]->id);
  199. }
  200. if (channel == PCM_SPDIF || channel == PCM_MULTICH)
  201. oxygen_update_spdif_source(chip);
  202. mutex_unlock(&chip->mutex);
  203. chip->streams[channel] = NULL;
  204. return 0;
  205. }
  206. static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
  207. {
  208. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  209. return OXYGEN_FORMAT_24;
  210. else
  211. return OXYGEN_FORMAT_16;
  212. }
  213. static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
  214. {
  215. switch (params_rate(hw_params)) {
  216. case 32000:
  217. return OXYGEN_RATE_32000;
  218. case 44100:
  219. return OXYGEN_RATE_44100;
  220. default: /* 48000 */
  221. return OXYGEN_RATE_48000;
  222. case 64000:
  223. return OXYGEN_RATE_64000;
  224. case 88200:
  225. return OXYGEN_RATE_88200;
  226. case 96000:
  227. return OXYGEN_RATE_96000;
  228. case 176400:
  229. return OXYGEN_RATE_176400;
  230. case 192000:
  231. return OXYGEN_RATE_192000;
  232. }
  233. }
  234. static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
  235. {
  236. return params_rate(hw_params) <= 96000
  237. ? OXYGEN_I2S_MCLK_256 : OXYGEN_I2S_MCLK_128;
  238. }
  239. static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
  240. {
  241. if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
  242. return OXYGEN_I2S_BITS_24;
  243. else
  244. return OXYGEN_I2S_BITS_16;
  245. }
  246. static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
  247. {
  248. switch (params_channels(hw_params)) {
  249. default: /* 2 */
  250. return OXYGEN_PLAY_CHANNELS_2;
  251. case 4:
  252. return OXYGEN_PLAY_CHANNELS_4;
  253. case 6:
  254. return OXYGEN_PLAY_CHANNELS_6;
  255. case 8:
  256. return OXYGEN_PLAY_CHANNELS_8;
  257. }
  258. }
  259. static const unsigned int channel_base_registers[PCM_COUNT] = {
  260. [PCM_A] = OXYGEN_DMA_A_ADDRESS,
  261. [PCM_B] = OXYGEN_DMA_B_ADDRESS,
  262. [PCM_C] = OXYGEN_DMA_C_ADDRESS,
  263. [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
  264. [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
  265. [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
  266. };
  267. static int oxygen_hw_params(struct snd_pcm_substream *substream,
  268. struct snd_pcm_hw_params *hw_params)
  269. {
  270. struct oxygen *chip = snd_pcm_substream_chip(substream);
  271. unsigned int channel = oxygen_substream_channel(substream);
  272. int err;
  273. err = snd_pcm_lib_malloc_pages(substream,
  274. params_buffer_bytes(hw_params));
  275. if (err < 0)
  276. return err;
  277. oxygen_write32(chip, channel_base_registers[channel],
  278. (u32)substream->runtime->dma_addr);
  279. if (channel == PCM_MULTICH) {
  280. oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
  281. params_buffer_bytes(hw_params) / 4 - 1);
  282. oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
  283. params_period_bytes(hw_params) / 4 - 1);
  284. } else {
  285. oxygen_write16(chip, channel_base_registers[channel] + 4,
  286. params_buffer_bytes(hw_params) / 4 - 1);
  287. oxygen_write16(chip, channel_base_registers[channel] + 6,
  288. params_period_bytes(hw_params) / 4 - 1);
  289. }
  290. return 0;
  291. }
  292. static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
  293. struct snd_pcm_hw_params *hw_params)
  294. {
  295. struct oxygen *chip = snd_pcm_substream_chip(substream);
  296. int err;
  297. err = oxygen_hw_params(substream, hw_params);
  298. if (err < 0)
  299. return err;
  300. spin_lock_irq(&chip->reg_lock);
  301. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  302. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
  303. OXYGEN_REC_FORMAT_A_MASK);
  304. oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
  305. oxygen_rate(hw_params) |
  306. oxygen_i2s_mclk(hw_params) |
  307. chip->model->adc_i2s_format |
  308. oxygen_i2s_bits(hw_params),
  309. OXYGEN_I2S_RATE_MASK |
  310. OXYGEN_I2S_FORMAT_MASK |
  311. OXYGEN_I2S_MCLK_MASK |
  312. OXYGEN_I2S_BITS_MASK);
  313. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  314. OXYGEN_REC_A_ROUTE_I2S_ADC_1,
  315. OXYGEN_REC_A_ROUTE_MASK);
  316. spin_unlock_irq(&chip->reg_lock);
  317. mutex_lock(&chip->mutex);
  318. chip->model->set_adc_params(chip, hw_params);
  319. mutex_unlock(&chip->mutex);
  320. return 0;
  321. }
  322. static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
  323. struct snd_pcm_hw_params *hw_params)
  324. {
  325. struct oxygen *chip = snd_pcm_substream_chip(substream);
  326. int err;
  327. err = oxygen_hw_params(substream, hw_params);
  328. if (err < 0)
  329. return err;
  330. spin_lock_irq(&chip->reg_lock);
  331. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  332. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
  333. OXYGEN_REC_FORMAT_B_MASK);
  334. oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
  335. oxygen_rate(hw_params) |
  336. oxygen_i2s_mclk(hw_params) |
  337. chip->model->adc_i2s_format |
  338. oxygen_i2s_bits(hw_params),
  339. OXYGEN_I2S_RATE_MASK |
  340. OXYGEN_I2S_FORMAT_MASK |
  341. OXYGEN_I2S_MCLK_MASK |
  342. OXYGEN_I2S_BITS_MASK);
  343. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  344. OXYGEN_REC_B_ROUTE_I2S_ADC_2,
  345. OXYGEN_REC_B_ROUTE_MASK);
  346. spin_unlock_irq(&chip->reg_lock);
  347. mutex_lock(&chip->mutex);
  348. chip->model->set_adc_params(chip, hw_params);
  349. mutex_unlock(&chip->mutex);
  350. return 0;
  351. }
  352. static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
  353. struct snd_pcm_hw_params *hw_params)
  354. {
  355. struct oxygen *chip = snd_pcm_substream_chip(substream);
  356. int err;
  357. err = oxygen_hw_params(substream, hw_params);
  358. if (err < 0)
  359. return err;
  360. spin_lock_irq(&chip->reg_lock);
  361. oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
  362. oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
  363. OXYGEN_REC_FORMAT_C_MASK);
  364. oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
  365. OXYGEN_REC_C_ROUTE_SPDIF,
  366. OXYGEN_REC_C_ROUTE_MASK);
  367. spin_unlock_irq(&chip->reg_lock);
  368. return 0;
  369. }
  370. static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
  371. struct snd_pcm_hw_params *hw_params)
  372. {
  373. struct oxygen *chip = snd_pcm_substream_chip(substream);
  374. int err;
  375. err = oxygen_hw_params(substream, hw_params);
  376. if (err < 0)
  377. return err;
  378. spin_lock_irq(&chip->reg_lock);
  379. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  380. OXYGEN_SPDIF_OUT_ENABLE);
  381. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  382. oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
  383. OXYGEN_SPDIF_FORMAT_MASK);
  384. oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
  385. oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
  386. OXYGEN_SPDIF_OUT_RATE_MASK);
  387. oxygen_update_spdif_source(chip);
  388. spin_unlock_irq(&chip->reg_lock);
  389. return 0;
  390. }
  391. static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
  392. struct snd_pcm_hw_params *hw_params)
  393. {
  394. struct oxygen *chip = snd_pcm_substream_chip(substream);
  395. int err;
  396. err = oxygen_hw_params(substream, hw_params);
  397. if (err < 0)
  398. return err;
  399. spin_lock_irq(&chip->reg_lock);
  400. oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
  401. oxygen_play_channels(hw_params),
  402. OXYGEN_PLAY_CHANNELS_MASK);
  403. oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
  404. oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
  405. OXYGEN_MULTICH_FORMAT_MASK);
  406. oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
  407. oxygen_rate(hw_params) |
  408. chip->model->dac_i2s_format |
  409. oxygen_i2s_bits(hw_params),
  410. OXYGEN_I2S_RATE_MASK |
  411. OXYGEN_I2S_FORMAT_MASK |
  412. OXYGEN_I2S_BITS_MASK);
  413. oxygen_write16_masked(chip, OXYGEN_PLAY_ROUTING,
  414. OXYGEN_PLAY_MULTICH_I2S_DAC,
  415. OXYGEN_PLAY_MUTE01 | OXYGEN_PLAY_MUTE23 |
  416. OXYGEN_PLAY_MUTE45 | OXYGEN_PLAY_MUTE67 |
  417. OXYGEN_PLAY_MULTICH_MASK);
  418. oxygen_update_dac_routing(chip);
  419. oxygen_update_spdif_source(chip);
  420. spin_unlock_irq(&chip->reg_lock);
  421. mutex_lock(&chip->mutex);
  422. chip->model->set_dac_params(chip, hw_params);
  423. mutex_unlock(&chip->mutex);
  424. return 0;
  425. }
  426. static int oxygen_hw_free(struct snd_pcm_substream *substream)
  427. {
  428. struct oxygen *chip = snd_pcm_substream_chip(substream);
  429. unsigned int channel = oxygen_substream_channel(substream);
  430. spin_lock_irq(&chip->reg_lock);
  431. chip->interrupt_mask &= ~(1 << channel);
  432. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  433. spin_unlock_irq(&chip->reg_lock);
  434. return snd_pcm_lib_free_pages(substream);
  435. }
  436. static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
  437. {
  438. struct oxygen *chip = snd_pcm_substream_chip(substream);
  439. spin_lock_irq(&chip->reg_lock);
  440. oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
  441. OXYGEN_SPDIF_OUT_ENABLE);
  442. spin_unlock_irq(&chip->reg_lock);
  443. return oxygen_hw_free(substream);
  444. }
  445. static int oxygen_prepare(struct snd_pcm_substream *substream)
  446. {
  447. struct oxygen *chip = snd_pcm_substream_chip(substream);
  448. unsigned int channel = oxygen_substream_channel(substream);
  449. unsigned int channel_mask = 1 << channel;
  450. spin_lock_irq(&chip->reg_lock);
  451. oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  452. oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
  453. chip->interrupt_mask |= channel_mask;
  454. oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
  455. spin_unlock_irq(&chip->reg_lock);
  456. return 0;
  457. }
  458. static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
  459. {
  460. struct oxygen *chip = snd_pcm_substream_chip(substream);
  461. struct snd_pcm_substream *s;
  462. unsigned int mask = 0;
  463. int pausing;
  464. switch (cmd) {
  465. case SNDRV_PCM_TRIGGER_STOP:
  466. case SNDRV_PCM_TRIGGER_START:
  467. pausing = 0;
  468. break;
  469. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  470. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  471. pausing = 1;
  472. break;
  473. default:
  474. return -EINVAL;
  475. }
  476. snd_pcm_group_for_each_entry(s, substream) {
  477. if (snd_pcm_substream_chip(s) == chip) {
  478. mask |= 1 << oxygen_substream_channel(s);
  479. snd_pcm_trigger_done(s, substream);
  480. }
  481. }
  482. spin_lock(&chip->reg_lock);
  483. if (!pausing) {
  484. if (cmd == SNDRV_PCM_TRIGGER_START)
  485. chip->pcm_running |= mask;
  486. else
  487. chip->pcm_running &= ~mask;
  488. oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
  489. } else {
  490. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  491. oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  492. else
  493. oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
  494. }
  495. spin_unlock(&chip->reg_lock);
  496. return 0;
  497. }
  498. static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
  499. {
  500. struct oxygen *chip = snd_pcm_substream_chip(substream);
  501. struct snd_pcm_runtime *runtime = substream->runtime;
  502. unsigned int channel = oxygen_substream_channel(substream);
  503. u32 curr_addr;
  504. /* no spinlock, this read should be atomic */
  505. curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
  506. return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
  507. }
  508. static struct snd_pcm_ops oxygen_rec_a_ops = {
  509. .open = oxygen_rec_a_open,
  510. .close = oxygen_close,
  511. .ioctl = snd_pcm_lib_ioctl,
  512. .hw_params = oxygen_rec_a_hw_params,
  513. .hw_free = oxygen_hw_free,
  514. .prepare = oxygen_prepare,
  515. .trigger = oxygen_trigger,
  516. .pointer = oxygen_pointer,
  517. };
  518. static struct snd_pcm_ops oxygen_rec_b_ops = {
  519. .open = oxygen_rec_b_open,
  520. .close = oxygen_close,
  521. .ioctl = snd_pcm_lib_ioctl,
  522. .hw_params = oxygen_rec_b_hw_params,
  523. .hw_free = oxygen_hw_free,
  524. .prepare = oxygen_prepare,
  525. .trigger = oxygen_trigger,
  526. .pointer = oxygen_pointer,
  527. };
  528. static struct snd_pcm_ops oxygen_rec_c_ops = {
  529. .open = oxygen_rec_c_open,
  530. .close = oxygen_close,
  531. .ioctl = snd_pcm_lib_ioctl,
  532. .hw_params = oxygen_rec_c_hw_params,
  533. .hw_free = oxygen_hw_free,
  534. .prepare = oxygen_prepare,
  535. .trigger = oxygen_trigger,
  536. .pointer = oxygen_pointer,
  537. };
  538. static struct snd_pcm_ops oxygen_spdif_ops = {
  539. .open = oxygen_spdif_open,
  540. .close = oxygen_close,
  541. .ioctl = snd_pcm_lib_ioctl,
  542. .hw_params = oxygen_spdif_hw_params,
  543. .hw_free = oxygen_spdif_hw_free,
  544. .prepare = oxygen_prepare,
  545. .trigger = oxygen_trigger,
  546. .pointer = oxygen_pointer,
  547. };
  548. static struct snd_pcm_ops oxygen_multich_ops = {
  549. .open = oxygen_multich_open,
  550. .close = oxygen_close,
  551. .ioctl = snd_pcm_lib_ioctl,
  552. .hw_params = oxygen_multich_hw_params,
  553. .hw_free = oxygen_hw_free,
  554. .prepare = oxygen_prepare,
  555. .trigger = oxygen_trigger,
  556. .pointer = oxygen_pointer,
  557. };
  558. static struct snd_pcm_ops oxygen_ac97_ops = {
  559. .open = oxygen_ac97_open,
  560. .close = oxygen_close,
  561. .ioctl = snd_pcm_lib_ioctl,
  562. .hw_params = oxygen_hw_params,
  563. .hw_free = oxygen_hw_free,
  564. .prepare = oxygen_prepare,
  565. .trigger = oxygen_trigger,
  566. .pointer = oxygen_pointer,
  567. };
  568. static void oxygen_pcm_free(struct snd_pcm *pcm)
  569. {
  570. snd_pcm_lib_preallocate_free_for_all(pcm);
  571. }
  572. int __devinit oxygen_pcm_init(struct oxygen *chip)
  573. {
  574. struct snd_pcm *pcm;
  575. int outs, ins;
  576. int err;
  577. outs = 1; /* OXYGEN_CHANNEL_MULTICH is always used */
  578. ins = !!(chip->model->used_channels & (OXYGEN_CHANNEL_A |
  579. OXYGEN_CHANNEL_B));
  580. err = snd_pcm_new(chip->card, "Analog", 0, outs, ins, &pcm);
  581. if (err < 0)
  582. return err;
  583. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &oxygen_multich_ops);
  584. if (chip->model->used_channels & OXYGEN_CHANNEL_A)
  585. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  586. &oxygen_rec_a_ops);
  587. else if (chip->model->used_channels & OXYGEN_CHANNEL_B)
  588. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  589. &oxygen_rec_b_ops);
  590. pcm->private_data = chip;
  591. pcm->private_free = oxygen_pcm_free;
  592. strcpy(pcm->name, "Analog");
  593. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
  594. SNDRV_DMA_TYPE_DEV,
  595. snd_dma_pci_data(chip->pci),
  596. 512 * 1024, 2048 * 1024);
  597. if (ins)
  598. snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
  599. SNDRV_DMA_TYPE_DEV,
  600. snd_dma_pci_data(chip->pci),
  601. 128 * 1024, 256 * 1024);
  602. outs = !!(chip->model->used_channels & OXYGEN_CHANNEL_SPDIF);
  603. ins = !!(chip->model->used_channels & OXYGEN_CHANNEL_C);
  604. if (outs | ins) {
  605. err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
  606. if (err < 0)
  607. return err;
  608. if (outs)
  609. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  610. &oxygen_spdif_ops);
  611. if (ins)
  612. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  613. &oxygen_rec_c_ops);
  614. pcm->private_data = chip;
  615. pcm->private_free = oxygen_pcm_free;
  616. strcpy(pcm->name, "Digital");
  617. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  618. snd_dma_pci_data(chip->pci),
  619. 128 * 1024, 256 * 1024);
  620. }
  621. outs = chip->has_ac97_1 &&
  622. (chip->model->used_channels & OXYGEN_CHANNEL_AC97);
  623. ins = (chip->model->used_channels & (OXYGEN_CHANNEL_A |
  624. OXYGEN_CHANNEL_B))
  625. == (OXYGEN_CHANNEL_A | OXYGEN_CHANNEL_B);
  626. if (outs | ins) {
  627. err = snd_pcm_new(chip->card, ins ? "Analog2" : "AC97",
  628. 2, outs, ins, &pcm);
  629. if (err < 0)
  630. return err;
  631. if (outs)
  632. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  633. &oxygen_ac97_ops);
  634. if (ins)
  635. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  636. &oxygen_rec_b_ops);
  637. pcm->private_data = chip;
  638. pcm->private_free = oxygen_pcm_free;
  639. strcpy(pcm->name, ins ? "Analog 2" : "Front Panel");
  640. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  641. snd_dma_pci_data(chip->pci),
  642. 128 * 1024, 256 * 1024);
  643. }
  644. return 0;
  645. }