be_main.c 127 KB

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  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <scsi/libiscsi.h>
  31. #include <scsi/scsi_transport_iscsi.h>
  32. #include <scsi/scsi_transport.h>
  33. #include <scsi/scsi_cmnd.h>
  34. #include <scsi/scsi_device.h>
  35. #include <scsi/scsi_host.h>
  36. #include <scsi/scsi.h>
  37. #include "be_main.h"
  38. #include "be_iscsi.h"
  39. #include "be_mgmt.h"
  40. static unsigned int be_iopoll_budget = 10;
  41. static unsigned int be_max_phys_size = 64;
  42. static unsigned int enable_msix = 1;
  43. static unsigned int gcrashmode = 0;
  44. static unsigned int num_hba = 0;
  45. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  46. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  47. MODULE_VERSION(BUILD_STR);
  48. MODULE_AUTHOR("Emulex Corporation");
  49. MODULE_LICENSE("GPL");
  50. module_param(be_iopoll_budget, int, 0);
  51. module_param(enable_msix, int, 0);
  52. module_param(be_max_phys_size, uint, S_IRUGO);
  53. MODULE_PARM_DESC(be_max_phys_size, "Maximum Size (In Kilobytes) of physically"
  54. "contiguous memory that can be allocated."
  55. "Range is 16 - 128");
  56. static int beiscsi_slave_configure(struct scsi_device *sdev)
  57. {
  58. blk_queue_max_segment_size(sdev->request_queue, 65536);
  59. return 0;
  60. }
  61. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  62. {
  63. struct iscsi_cls_session *cls_session;
  64. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  65. struct beiscsi_io_task *aborted_io_task;
  66. struct iscsi_conn *conn;
  67. struct beiscsi_conn *beiscsi_conn;
  68. struct beiscsi_hba *phba;
  69. struct iscsi_session *session;
  70. struct invalidate_command_table *inv_tbl;
  71. struct be_dma_mem nonemb_cmd;
  72. unsigned int cid, tag, num_invalidate;
  73. cls_session = starget_to_session(scsi_target(sc->device));
  74. session = cls_session->dd_data;
  75. spin_lock_bh(&session->lock);
  76. if (!aborted_task || !aborted_task->sc) {
  77. /* we raced */
  78. spin_unlock_bh(&session->lock);
  79. return SUCCESS;
  80. }
  81. aborted_io_task = aborted_task->dd_data;
  82. if (!aborted_io_task->scsi_cmnd) {
  83. /* raced or invalid command */
  84. spin_unlock_bh(&session->lock);
  85. return SUCCESS;
  86. }
  87. spin_unlock_bh(&session->lock);
  88. conn = aborted_task->conn;
  89. beiscsi_conn = conn->dd_data;
  90. phba = beiscsi_conn->phba;
  91. /* invalidate iocb */
  92. cid = beiscsi_conn->beiscsi_conn_cid;
  93. inv_tbl = phba->inv_tbl;
  94. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  95. inv_tbl->cid = cid;
  96. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  97. num_invalidate = 1;
  98. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  99. sizeof(struct invalidate_commands_params_in),
  100. &nonemb_cmd.dma);
  101. if (nonemb_cmd.va == NULL) {
  102. SE_DEBUG(DBG_LVL_1,
  103. "Failed to allocate memory for"
  104. "mgmt_invalidate_icds\n");
  105. return FAILED;
  106. }
  107. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  108. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  109. cid, &nonemb_cmd);
  110. if (!tag) {
  111. shost_printk(KERN_WARNING, phba->shost,
  112. "mgmt_invalidate_icds could not be"
  113. " submitted\n");
  114. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  115. nonemb_cmd.va, nonemb_cmd.dma);
  116. return FAILED;
  117. } else {
  118. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  119. phba->ctrl.mcc_numtag[tag]);
  120. free_mcc_tag(&phba->ctrl, tag);
  121. }
  122. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  123. nonemb_cmd.va, nonemb_cmd.dma);
  124. return iscsi_eh_abort(sc);
  125. }
  126. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  127. {
  128. struct iscsi_task *abrt_task;
  129. struct beiscsi_io_task *abrt_io_task;
  130. struct iscsi_conn *conn;
  131. struct beiscsi_conn *beiscsi_conn;
  132. struct beiscsi_hba *phba;
  133. struct iscsi_session *session;
  134. struct iscsi_cls_session *cls_session;
  135. struct invalidate_command_table *inv_tbl;
  136. struct be_dma_mem nonemb_cmd;
  137. unsigned int cid, tag, i, num_invalidate;
  138. /* invalidate iocbs */
  139. cls_session = starget_to_session(scsi_target(sc->device));
  140. session = cls_session->dd_data;
  141. spin_lock_bh(&session->lock);
  142. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  143. spin_unlock_bh(&session->lock);
  144. return FAILED;
  145. }
  146. conn = session->leadconn;
  147. beiscsi_conn = conn->dd_data;
  148. phba = beiscsi_conn->phba;
  149. cid = beiscsi_conn->beiscsi_conn_cid;
  150. inv_tbl = phba->inv_tbl;
  151. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  152. num_invalidate = 0;
  153. for (i = 0; i < conn->session->cmds_max; i++) {
  154. abrt_task = conn->session->cmds[i];
  155. abrt_io_task = abrt_task->dd_data;
  156. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  157. continue;
  158. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  159. continue;
  160. inv_tbl->cid = cid;
  161. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  162. num_invalidate++;
  163. inv_tbl++;
  164. }
  165. spin_unlock_bh(&session->lock);
  166. inv_tbl = phba->inv_tbl;
  167. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  168. sizeof(struct invalidate_commands_params_in),
  169. &nonemb_cmd.dma);
  170. if (nonemb_cmd.va == NULL) {
  171. SE_DEBUG(DBG_LVL_1,
  172. "Failed to allocate memory for"
  173. "mgmt_invalidate_icds\n");
  174. return FAILED;
  175. }
  176. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  177. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  178. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  179. cid, &nonemb_cmd);
  180. if (!tag) {
  181. shost_printk(KERN_WARNING, phba->shost,
  182. "mgmt_invalidate_icds could not be"
  183. " submitted\n");
  184. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  185. nonemb_cmd.va, nonemb_cmd.dma);
  186. return FAILED;
  187. } else {
  188. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  189. phba->ctrl.mcc_numtag[tag]);
  190. free_mcc_tag(&phba->ctrl, tag);
  191. }
  192. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  193. nonemb_cmd.va, nonemb_cmd.dma);
  194. return iscsi_eh_device_reset(sc);
  195. }
  196. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  197. {
  198. struct beiscsi_hba *phba = data;
  199. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  200. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  201. char *str = buf;
  202. int rc;
  203. switch (type) {
  204. case ISCSI_BOOT_TGT_NAME:
  205. rc = sprintf(buf, "%.*s\n",
  206. (int)strlen(boot_sess->target_name),
  207. (char *)&boot_sess->target_name);
  208. break;
  209. case ISCSI_BOOT_TGT_IP_ADDR:
  210. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  211. rc = sprintf(buf, "%pI4\n",
  212. (char *)&boot_conn->dest_ipaddr.ip_address);
  213. else
  214. rc = sprintf(str, "%pI6\n",
  215. (char *)&boot_conn->dest_ipaddr.ip_address);
  216. break;
  217. case ISCSI_BOOT_TGT_PORT:
  218. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  219. break;
  220. case ISCSI_BOOT_TGT_CHAP_NAME:
  221. rc = sprintf(str, "%.*s\n",
  222. boot_conn->negotiated_login_options.auth_data.chap.
  223. target_chap_name_length,
  224. (char *)&boot_conn->negotiated_login_options.
  225. auth_data.chap.target_chap_name);
  226. break;
  227. case ISCSI_BOOT_TGT_CHAP_SECRET:
  228. rc = sprintf(str, "%.*s\n",
  229. boot_conn->negotiated_login_options.auth_data.chap.
  230. target_secret_length,
  231. (char *)&boot_conn->negotiated_login_options.
  232. auth_data.chap.target_secret);
  233. break;
  234. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  235. rc = sprintf(str, "%.*s\n",
  236. boot_conn->negotiated_login_options.auth_data.chap.
  237. intr_chap_name_length,
  238. (char *)&boot_conn->negotiated_login_options.
  239. auth_data.chap.intr_chap_name);
  240. break;
  241. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  242. rc = sprintf(str, "%.*s\n",
  243. boot_conn->negotiated_login_options.auth_data.chap.
  244. intr_secret_length,
  245. (char *)&boot_conn->negotiated_login_options.
  246. auth_data.chap.intr_secret);
  247. break;
  248. case ISCSI_BOOT_TGT_FLAGS:
  249. rc = sprintf(str, "2\n");
  250. break;
  251. case ISCSI_BOOT_TGT_NIC_ASSOC:
  252. rc = sprintf(str, "0\n");
  253. break;
  254. default:
  255. rc = -ENOSYS;
  256. break;
  257. }
  258. return rc;
  259. }
  260. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  261. {
  262. struct beiscsi_hba *phba = data;
  263. char *str = buf;
  264. int rc;
  265. switch (type) {
  266. case ISCSI_BOOT_INI_INITIATOR_NAME:
  267. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  268. break;
  269. default:
  270. rc = -ENOSYS;
  271. break;
  272. }
  273. return rc;
  274. }
  275. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  276. {
  277. struct beiscsi_hba *phba = data;
  278. char *str = buf;
  279. int rc;
  280. switch (type) {
  281. case ISCSI_BOOT_ETH_FLAGS:
  282. rc = sprintf(str, "2\n");
  283. break;
  284. case ISCSI_BOOT_ETH_INDEX:
  285. rc = sprintf(str, "0\n");
  286. break;
  287. case ISCSI_BOOT_ETH_MAC:
  288. rc = beiscsi_get_macaddr(buf, phba);
  289. if (rc < 0) {
  290. SE_DEBUG(DBG_LVL_1, "beiscsi_get_macaddr Failed\n");
  291. return rc;
  292. }
  293. break;
  294. default:
  295. rc = -ENOSYS;
  296. break;
  297. }
  298. return rc;
  299. }
  300. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  301. {
  302. umode_t rc;
  303. switch (type) {
  304. case ISCSI_BOOT_TGT_NAME:
  305. case ISCSI_BOOT_TGT_IP_ADDR:
  306. case ISCSI_BOOT_TGT_PORT:
  307. case ISCSI_BOOT_TGT_CHAP_NAME:
  308. case ISCSI_BOOT_TGT_CHAP_SECRET:
  309. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  310. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  311. case ISCSI_BOOT_TGT_NIC_ASSOC:
  312. case ISCSI_BOOT_TGT_FLAGS:
  313. rc = S_IRUGO;
  314. break;
  315. default:
  316. rc = 0;
  317. break;
  318. }
  319. return rc;
  320. }
  321. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  322. {
  323. umode_t rc;
  324. switch (type) {
  325. case ISCSI_BOOT_INI_INITIATOR_NAME:
  326. rc = S_IRUGO;
  327. break;
  328. default:
  329. rc = 0;
  330. break;
  331. }
  332. return rc;
  333. }
  334. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  335. {
  336. umode_t rc;
  337. switch (type) {
  338. case ISCSI_BOOT_ETH_FLAGS:
  339. case ISCSI_BOOT_ETH_MAC:
  340. case ISCSI_BOOT_ETH_INDEX:
  341. rc = S_IRUGO;
  342. break;
  343. default:
  344. rc = 0;
  345. break;
  346. }
  347. return rc;
  348. }
  349. /*------------------- PCI Driver operations and data ----------------- */
  350. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  351. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  352. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  353. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  354. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  355. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  356. { 0 }
  357. };
  358. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  359. static struct scsi_host_template beiscsi_sht = {
  360. .module = THIS_MODULE,
  361. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  362. .proc_name = DRV_NAME,
  363. .queuecommand = iscsi_queuecommand,
  364. .change_queue_depth = iscsi_change_queue_depth,
  365. .slave_configure = beiscsi_slave_configure,
  366. .target_alloc = iscsi_target_alloc,
  367. .eh_abort_handler = beiscsi_eh_abort,
  368. .eh_device_reset_handler = beiscsi_eh_device_reset,
  369. .eh_target_reset_handler = iscsi_eh_session_reset,
  370. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  371. .can_queue = BE2_IO_DEPTH,
  372. .this_id = -1,
  373. .max_sectors = BEISCSI_MAX_SECTORS,
  374. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  375. .use_clustering = ENABLE_CLUSTERING,
  376. };
  377. static struct scsi_transport_template *beiscsi_scsi_transport;
  378. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  379. {
  380. struct beiscsi_hba *phba;
  381. struct Scsi_Host *shost;
  382. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  383. if (!shost) {
  384. dev_err(&pcidev->dev, "beiscsi_hba_alloc -"
  385. "iscsi_host_alloc failed\n");
  386. return NULL;
  387. }
  388. shost->dma_boundary = pcidev->dma_mask;
  389. shost->max_id = BE2_MAX_SESSIONS;
  390. shost->max_channel = 0;
  391. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  392. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  393. shost->transportt = beiscsi_scsi_transport;
  394. phba = iscsi_host_priv(shost);
  395. memset(phba, 0, sizeof(*phba));
  396. phba->shost = shost;
  397. phba->pcidev = pci_dev_get(pcidev);
  398. pci_set_drvdata(pcidev, phba);
  399. if (iscsi_host_add(shost, &phba->pcidev->dev))
  400. goto free_devices;
  401. return phba;
  402. free_devices:
  403. pci_dev_put(phba->pcidev);
  404. iscsi_host_free(phba->shost);
  405. return NULL;
  406. }
  407. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  408. {
  409. if (phba->csr_va) {
  410. iounmap(phba->csr_va);
  411. phba->csr_va = NULL;
  412. }
  413. if (phba->db_va) {
  414. iounmap(phba->db_va);
  415. phba->db_va = NULL;
  416. }
  417. if (phba->pci_va) {
  418. iounmap(phba->pci_va);
  419. phba->pci_va = NULL;
  420. }
  421. }
  422. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  423. struct pci_dev *pcidev)
  424. {
  425. u8 __iomem *addr;
  426. int pcicfg_reg;
  427. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  428. pci_resource_len(pcidev, 2));
  429. if (addr == NULL)
  430. return -ENOMEM;
  431. phba->ctrl.csr = addr;
  432. phba->csr_va = addr;
  433. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  434. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  435. if (addr == NULL)
  436. goto pci_map_err;
  437. phba->ctrl.db = addr;
  438. phba->db_va = addr;
  439. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  440. if (phba->generation == BE_GEN2)
  441. pcicfg_reg = 1;
  442. else
  443. pcicfg_reg = 0;
  444. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  445. pci_resource_len(pcidev, pcicfg_reg));
  446. if (addr == NULL)
  447. goto pci_map_err;
  448. phba->ctrl.pcicfg = addr;
  449. phba->pci_va = addr;
  450. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  451. return 0;
  452. pci_map_err:
  453. beiscsi_unmap_pci_function(phba);
  454. return -ENOMEM;
  455. }
  456. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  457. {
  458. int ret;
  459. ret = pci_enable_device(pcidev);
  460. if (ret) {
  461. dev_err(&pcidev->dev, "beiscsi_enable_pci - enable device "
  462. "failed. Returning -ENODEV\n");
  463. return ret;
  464. }
  465. pci_set_master(pcidev);
  466. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  467. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  468. if (ret) {
  469. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  470. pci_disable_device(pcidev);
  471. return ret;
  472. }
  473. }
  474. return 0;
  475. }
  476. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  477. {
  478. struct be_ctrl_info *ctrl = &phba->ctrl;
  479. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  480. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  481. int status = 0;
  482. ctrl->pdev = pdev;
  483. status = beiscsi_map_pci_bars(phba, pdev);
  484. if (status)
  485. return status;
  486. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  487. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  488. mbox_mem_alloc->size,
  489. &mbox_mem_alloc->dma);
  490. if (!mbox_mem_alloc->va) {
  491. beiscsi_unmap_pci_function(phba);
  492. return -ENOMEM;
  493. }
  494. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  495. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  496. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  497. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  498. spin_lock_init(&ctrl->mbox_lock);
  499. spin_lock_init(&phba->ctrl.mcc_lock);
  500. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  501. return status;
  502. }
  503. static void beiscsi_get_params(struct beiscsi_hba *phba)
  504. {
  505. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  506. - (phba->fw_config.iscsi_cid_count
  507. + BE2_TMFS
  508. + BE2_NOPOUT_REQ));
  509. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  510. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  511. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  512. phba->params.num_sge_per_io = BE2_SGE;
  513. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  514. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  515. phba->params.eq_timer = 64;
  516. phba->params.num_eq_entries =
  517. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  518. + BE2_TMFS) / 512) + 1) * 512;
  519. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  520. ? 1024 : phba->params.num_eq_entries;
  521. SE_DEBUG(DBG_LVL_8, "phba->params.num_eq_entries=%d\n",
  522. phba->params.num_eq_entries);
  523. phba->params.num_cq_entries =
  524. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  525. + BE2_TMFS) / 512) + 1) * 512;
  526. phba->params.wrbs_per_cxn = 256;
  527. }
  528. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  529. unsigned int id, unsigned int clr_interrupt,
  530. unsigned int num_processed,
  531. unsigned char rearm, unsigned char event)
  532. {
  533. u32 val = 0;
  534. val |= id & DB_EQ_RING_ID_MASK;
  535. if (rearm)
  536. val |= 1 << DB_EQ_REARM_SHIFT;
  537. if (clr_interrupt)
  538. val |= 1 << DB_EQ_CLR_SHIFT;
  539. if (event)
  540. val |= 1 << DB_EQ_EVNT_SHIFT;
  541. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  542. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  543. }
  544. /**
  545. * be_isr_mcc - The isr routine of the driver.
  546. * @irq: Not used
  547. * @dev_id: Pointer to host adapter structure
  548. */
  549. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  550. {
  551. struct beiscsi_hba *phba;
  552. struct be_eq_entry *eqe = NULL;
  553. struct be_queue_info *eq;
  554. struct be_queue_info *mcc;
  555. unsigned int num_eq_processed;
  556. struct be_eq_obj *pbe_eq;
  557. unsigned long flags;
  558. pbe_eq = dev_id;
  559. eq = &pbe_eq->q;
  560. phba = pbe_eq->phba;
  561. mcc = &phba->ctrl.mcc_obj.cq;
  562. eqe = queue_tail_node(eq);
  563. if (!eqe)
  564. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  565. num_eq_processed = 0;
  566. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  567. & EQE_VALID_MASK) {
  568. if (((eqe->dw[offsetof(struct amap_eq_entry,
  569. resource_id) / 32] &
  570. EQE_RESID_MASK) >> 16) == mcc->id) {
  571. spin_lock_irqsave(&phba->isr_lock, flags);
  572. phba->todo_mcc_cq = 1;
  573. spin_unlock_irqrestore(&phba->isr_lock, flags);
  574. }
  575. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  576. queue_tail_inc(eq);
  577. eqe = queue_tail_node(eq);
  578. num_eq_processed++;
  579. }
  580. if (phba->todo_mcc_cq)
  581. queue_work(phba->wq, &phba->work_cqs);
  582. if (num_eq_processed)
  583. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  584. return IRQ_HANDLED;
  585. }
  586. /**
  587. * be_isr_msix - The isr routine of the driver.
  588. * @irq: Not used
  589. * @dev_id: Pointer to host adapter structure
  590. */
  591. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  592. {
  593. struct beiscsi_hba *phba;
  594. struct be_eq_entry *eqe = NULL;
  595. struct be_queue_info *eq;
  596. struct be_queue_info *cq;
  597. unsigned int num_eq_processed;
  598. struct be_eq_obj *pbe_eq;
  599. unsigned long flags;
  600. pbe_eq = dev_id;
  601. eq = &pbe_eq->q;
  602. cq = pbe_eq->cq;
  603. eqe = queue_tail_node(eq);
  604. if (!eqe)
  605. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  606. phba = pbe_eq->phba;
  607. num_eq_processed = 0;
  608. if (blk_iopoll_enabled) {
  609. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  610. & EQE_VALID_MASK) {
  611. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  612. blk_iopoll_sched(&pbe_eq->iopoll);
  613. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  614. queue_tail_inc(eq);
  615. eqe = queue_tail_node(eq);
  616. num_eq_processed++;
  617. }
  618. if (num_eq_processed)
  619. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  620. return IRQ_HANDLED;
  621. } else {
  622. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  623. & EQE_VALID_MASK) {
  624. spin_lock_irqsave(&phba->isr_lock, flags);
  625. phba->todo_cq = 1;
  626. spin_unlock_irqrestore(&phba->isr_lock, flags);
  627. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  628. queue_tail_inc(eq);
  629. eqe = queue_tail_node(eq);
  630. num_eq_processed++;
  631. }
  632. if (phba->todo_cq)
  633. queue_work(phba->wq, &phba->work_cqs);
  634. if (num_eq_processed)
  635. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  636. return IRQ_HANDLED;
  637. }
  638. }
  639. /**
  640. * be_isr - The isr routine of the driver.
  641. * @irq: Not used
  642. * @dev_id: Pointer to host adapter structure
  643. */
  644. static irqreturn_t be_isr(int irq, void *dev_id)
  645. {
  646. struct beiscsi_hba *phba;
  647. struct hwi_controller *phwi_ctrlr;
  648. struct hwi_context_memory *phwi_context;
  649. struct be_eq_entry *eqe = NULL;
  650. struct be_queue_info *eq;
  651. struct be_queue_info *cq;
  652. struct be_queue_info *mcc;
  653. unsigned long flags, index;
  654. unsigned int num_mcceq_processed, num_ioeq_processed;
  655. struct be_ctrl_info *ctrl;
  656. struct be_eq_obj *pbe_eq;
  657. int isr;
  658. phba = dev_id;
  659. ctrl = &phba->ctrl;
  660. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  661. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  662. if (!isr)
  663. return IRQ_NONE;
  664. phwi_ctrlr = phba->phwi_ctrlr;
  665. phwi_context = phwi_ctrlr->phwi_ctxt;
  666. pbe_eq = &phwi_context->be_eq[0];
  667. eq = &phwi_context->be_eq[0].q;
  668. mcc = &phba->ctrl.mcc_obj.cq;
  669. index = 0;
  670. eqe = queue_tail_node(eq);
  671. if (!eqe)
  672. SE_DEBUG(DBG_LVL_1, "eqe is NULL\n");
  673. num_ioeq_processed = 0;
  674. num_mcceq_processed = 0;
  675. if (blk_iopoll_enabled) {
  676. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  677. & EQE_VALID_MASK) {
  678. if (((eqe->dw[offsetof(struct amap_eq_entry,
  679. resource_id) / 32] &
  680. EQE_RESID_MASK) >> 16) == mcc->id) {
  681. spin_lock_irqsave(&phba->isr_lock, flags);
  682. phba->todo_mcc_cq = 1;
  683. spin_unlock_irqrestore(&phba->isr_lock, flags);
  684. num_mcceq_processed++;
  685. } else {
  686. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  687. blk_iopoll_sched(&pbe_eq->iopoll);
  688. num_ioeq_processed++;
  689. }
  690. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  691. queue_tail_inc(eq);
  692. eqe = queue_tail_node(eq);
  693. }
  694. if (num_ioeq_processed || num_mcceq_processed) {
  695. if (phba->todo_mcc_cq)
  696. queue_work(phba->wq, &phba->work_cqs);
  697. if ((num_mcceq_processed) && (!num_ioeq_processed))
  698. hwi_ring_eq_db(phba, eq->id, 0,
  699. (num_ioeq_processed +
  700. num_mcceq_processed) , 1, 1);
  701. else
  702. hwi_ring_eq_db(phba, eq->id, 0,
  703. (num_ioeq_processed +
  704. num_mcceq_processed), 0, 1);
  705. return IRQ_HANDLED;
  706. } else
  707. return IRQ_NONE;
  708. } else {
  709. cq = &phwi_context->be_cq[0];
  710. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  711. & EQE_VALID_MASK) {
  712. if (((eqe->dw[offsetof(struct amap_eq_entry,
  713. resource_id) / 32] &
  714. EQE_RESID_MASK) >> 16) != cq->id) {
  715. spin_lock_irqsave(&phba->isr_lock, flags);
  716. phba->todo_mcc_cq = 1;
  717. spin_unlock_irqrestore(&phba->isr_lock, flags);
  718. } else {
  719. spin_lock_irqsave(&phba->isr_lock, flags);
  720. phba->todo_cq = 1;
  721. spin_unlock_irqrestore(&phba->isr_lock, flags);
  722. }
  723. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  724. queue_tail_inc(eq);
  725. eqe = queue_tail_node(eq);
  726. num_ioeq_processed++;
  727. }
  728. if (phba->todo_cq || phba->todo_mcc_cq)
  729. queue_work(phba->wq, &phba->work_cqs);
  730. if (num_ioeq_processed) {
  731. hwi_ring_eq_db(phba, eq->id, 0,
  732. num_ioeq_processed, 1, 1);
  733. return IRQ_HANDLED;
  734. } else
  735. return IRQ_NONE;
  736. }
  737. }
  738. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  739. {
  740. struct pci_dev *pcidev = phba->pcidev;
  741. struct hwi_controller *phwi_ctrlr;
  742. struct hwi_context_memory *phwi_context;
  743. int ret, msix_vec, i, j;
  744. phwi_ctrlr = phba->phwi_ctrlr;
  745. phwi_context = phwi_ctrlr->phwi_ctxt;
  746. if (phba->msix_enabled) {
  747. for (i = 0; i < phba->num_cpus; i++) {
  748. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  749. GFP_KERNEL);
  750. if (!phba->msi_name[i]) {
  751. ret = -ENOMEM;
  752. goto free_msix_irqs;
  753. }
  754. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  755. phba->shost->host_no, i);
  756. msix_vec = phba->msix_entries[i].vector;
  757. ret = request_irq(msix_vec, be_isr_msix, 0,
  758. phba->msi_name[i],
  759. &phwi_context->be_eq[i]);
  760. if (ret) {
  761. shost_printk(KERN_ERR, phba->shost,
  762. "beiscsi_init_irqs-Failed to"
  763. "register msix for i = %d\n", i);
  764. kfree(phba->msi_name[i]);
  765. goto free_msix_irqs;
  766. }
  767. }
  768. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  769. if (!phba->msi_name[i]) {
  770. ret = -ENOMEM;
  771. goto free_msix_irqs;
  772. }
  773. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  774. phba->shost->host_no);
  775. msix_vec = phba->msix_entries[i].vector;
  776. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  777. &phwi_context->be_eq[i]);
  778. if (ret) {
  779. shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
  780. "Failed to register beiscsi_msix_mcc\n");
  781. kfree(phba->msi_name[i]);
  782. goto free_msix_irqs;
  783. }
  784. } else {
  785. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  786. "beiscsi", phba);
  787. if (ret) {
  788. shost_printk(KERN_ERR, phba->shost, "beiscsi_init_irqs-"
  789. "Failed to register irq\\n");
  790. return ret;
  791. }
  792. }
  793. return 0;
  794. free_msix_irqs:
  795. for (j = i - 1; j >= 0; j--) {
  796. kfree(phba->msi_name[j]);
  797. msix_vec = phba->msix_entries[j].vector;
  798. free_irq(msix_vec, &phwi_context->be_eq[j]);
  799. }
  800. return ret;
  801. }
  802. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  803. unsigned int id, unsigned int num_processed,
  804. unsigned char rearm, unsigned char event)
  805. {
  806. u32 val = 0;
  807. val |= id & DB_CQ_RING_ID_MASK;
  808. if (rearm)
  809. val |= 1 << DB_CQ_REARM_SHIFT;
  810. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  811. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  812. }
  813. static unsigned int
  814. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  815. struct beiscsi_hba *phba,
  816. unsigned short cid,
  817. struct pdu_base *ppdu,
  818. unsigned long pdu_len,
  819. void *pbuffer, unsigned long buf_len)
  820. {
  821. struct iscsi_conn *conn = beiscsi_conn->conn;
  822. struct iscsi_session *session = conn->session;
  823. struct iscsi_task *task;
  824. struct beiscsi_io_task *io_task;
  825. struct iscsi_hdr *login_hdr;
  826. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  827. PDUBASE_OPCODE_MASK) {
  828. case ISCSI_OP_NOOP_IN:
  829. pbuffer = NULL;
  830. buf_len = 0;
  831. break;
  832. case ISCSI_OP_ASYNC_EVENT:
  833. break;
  834. case ISCSI_OP_REJECT:
  835. WARN_ON(!pbuffer);
  836. WARN_ON(!(buf_len == 48));
  837. SE_DEBUG(DBG_LVL_1, "In ISCSI_OP_REJECT\n");
  838. break;
  839. case ISCSI_OP_LOGIN_RSP:
  840. case ISCSI_OP_TEXT_RSP:
  841. task = conn->login_task;
  842. io_task = task->dd_data;
  843. login_hdr = (struct iscsi_hdr *)ppdu;
  844. login_hdr->itt = io_task->libiscsi_itt;
  845. break;
  846. default:
  847. shost_printk(KERN_WARNING, phba->shost,
  848. "Unrecognized opcode 0x%x in async msg\n",
  849. (ppdu->
  850. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  851. & PDUBASE_OPCODE_MASK));
  852. return 1;
  853. }
  854. spin_lock_bh(&session->lock);
  855. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  856. spin_unlock_bh(&session->lock);
  857. return 0;
  858. }
  859. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  860. {
  861. struct sgl_handle *psgl_handle;
  862. if (phba->io_sgl_hndl_avbl) {
  863. SE_DEBUG(DBG_LVL_8,
  864. "In alloc_io_sgl_handle,io_sgl_alloc_index=%d\n",
  865. phba->io_sgl_alloc_index);
  866. psgl_handle = phba->io_sgl_hndl_base[phba->
  867. io_sgl_alloc_index];
  868. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  869. phba->io_sgl_hndl_avbl--;
  870. if (phba->io_sgl_alloc_index == (phba->params.
  871. ios_per_ctrl - 1))
  872. phba->io_sgl_alloc_index = 0;
  873. else
  874. phba->io_sgl_alloc_index++;
  875. } else
  876. psgl_handle = NULL;
  877. return psgl_handle;
  878. }
  879. static void
  880. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  881. {
  882. SE_DEBUG(DBG_LVL_8, "In free_,io_sgl_free_index=%d\n",
  883. phba->io_sgl_free_index);
  884. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  885. /*
  886. * this can happen if clean_task is called on a task that
  887. * failed in xmit_task or alloc_pdu.
  888. */
  889. SE_DEBUG(DBG_LVL_8,
  890. "Double Free in IO SGL io_sgl_free_index=%d,"
  891. "value there=%p\n", phba->io_sgl_free_index,
  892. phba->io_sgl_hndl_base[phba->io_sgl_free_index]);
  893. return;
  894. }
  895. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  896. phba->io_sgl_hndl_avbl++;
  897. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  898. phba->io_sgl_free_index = 0;
  899. else
  900. phba->io_sgl_free_index++;
  901. }
  902. /**
  903. * alloc_wrb_handle - To allocate a wrb handle
  904. * @phba: The hba pointer
  905. * @cid: The cid to use for allocation
  906. *
  907. * This happens under session_lock until submission to chip
  908. */
  909. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  910. {
  911. struct hwi_wrb_context *pwrb_context;
  912. struct hwi_controller *phwi_ctrlr;
  913. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  914. phwi_ctrlr = phba->phwi_ctrlr;
  915. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  916. if (pwrb_context->wrb_handles_available >= 2) {
  917. pwrb_handle = pwrb_context->pwrb_handle_base[
  918. pwrb_context->alloc_index];
  919. pwrb_context->wrb_handles_available--;
  920. if (pwrb_context->alloc_index ==
  921. (phba->params.wrbs_per_cxn - 1))
  922. pwrb_context->alloc_index = 0;
  923. else
  924. pwrb_context->alloc_index++;
  925. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  926. pwrb_context->alloc_index];
  927. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  928. } else
  929. pwrb_handle = NULL;
  930. return pwrb_handle;
  931. }
  932. /**
  933. * free_wrb_handle - To free the wrb handle back to pool
  934. * @phba: The hba pointer
  935. * @pwrb_context: The context to free from
  936. * @pwrb_handle: The wrb_handle to free
  937. *
  938. * This happens under session_lock until submission to chip
  939. */
  940. static void
  941. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  942. struct wrb_handle *pwrb_handle)
  943. {
  944. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  945. pwrb_context->wrb_handles_available++;
  946. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  947. pwrb_context->free_index = 0;
  948. else
  949. pwrb_context->free_index++;
  950. SE_DEBUG(DBG_LVL_8,
  951. "FREE WRB: pwrb_handle=%p free_index=0x%x"
  952. "wrb_handles_available=%d\n",
  953. pwrb_handle, pwrb_context->free_index,
  954. pwrb_context->wrb_handles_available);
  955. }
  956. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  957. {
  958. struct sgl_handle *psgl_handle;
  959. if (phba->eh_sgl_hndl_avbl) {
  960. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  961. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  962. SE_DEBUG(DBG_LVL_8, "mgmt_sgl_alloc_index=%d=0x%x\n",
  963. phba->eh_sgl_alloc_index, phba->eh_sgl_alloc_index);
  964. phba->eh_sgl_hndl_avbl--;
  965. if (phba->eh_sgl_alloc_index ==
  966. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  967. 1))
  968. phba->eh_sgl_alloc_index = 0;
  969. else
  970. phba->eh_sgl_alloc_index++;
  971. } else
  972. psgl_handle = NULL;
  973. return psgl_handle;
  974. }
  975. void
  976. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  977. {
  978. SE_DEBUG(DBG_LVL_8, "In free_mgmt_sgl_handle,eh_sgl_free_index=%d\n",
  979. phba->eh_sgl_free_index);
  980. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  981. /*
  982. * this can happen if clean_task is called on a task that
  983. * failed in xmit_task or alloc_pdu.
  984. */
  985. SE_DEBUG(DBG_LVL_8,
  986. "Double Free in eh SGL ,eh_sgl_free_index=%d\n",
  987. phba->eh_sgl_free_index);
  988. return;
  989. }
  990. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  991. phba->eh_sgl_hndl_avbl++;
  992. if (phba->eh_sgl_free_index ==
  993. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  994. phba->eh_sgl_free_index = 0;
  995. else
  996. phba->eh_sgl_free_index++;
  997. }
  998. static void
  999. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1000. struct iscsi_task *task, struct sol_cqe *psol)
  1001. {
  1002. struct beiscsi_io_task *io_task = task->dd_data;
  1003. struct be_status_bhs *sts_bhs =
  1004. (struct be_status_bhs *)io_task->cmd_bhs;
  1005. struct iscsi_conn *conn = beiscsi_conn->conn;
  1006. unsigned char *sense;
  1007. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1008. u8 rsp, status, flags;
  1009. exp_cmdsn = (psol->
  1010. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1011. & SOL_EXP_CMD_SN_MASK);
  1012. max_cmdsn = ((psol->
  1013. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1014. & SOL_EXP_CMD_SN_MASK) +
  1015. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1016. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1017. rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
  1018. & SOL_RESP_MASK) >> 16);
  1019. status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
  1020. & SOL_STS_MASK) >> 8);
  1021. flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1022. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1023. if (!task->sc) {
  1024. if (io_task->scsi_cmnd)
  1025. scsi_dma_unmap(io_task->scsi_cmnd);
  1026. return;
  1027. }
  1028. task->sc->result = (DID_OK << 16) | status;
  1029. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1030. task->sc->result = DID_ERROR << 16;
  1031. goto unmap;
  1032. }
  1033. /* bidi not initially supported */
  1034. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1035. resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
  1036. 32] & SOL_RES_CNT_MASK);
  1037. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1038. task->sc->result = DID_ERROR << 16;
  1039. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1040. scsi_set_resid(task->sc, resid);
  1041. if (!status && (scsi_bufflen(task->sc) - resid <
  1042. task->sc->underflow))
  1043. task->sc->result = DID_ERROR << 16;
  1044. }
  1045. }
  1046. if (status == SAM_STAT_CHECK_CONDITION) {
  1047. u16 sense_len;
  1048. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1049. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1050. sense_len = be16_to_cpu(*slen);
  1051. memcpy(task->sc->sense_buffer, sense,
  1052. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1053. }
  1054. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
  1055. if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1056. & SOL_RES_CNT_MASK)
  1057. conn->rxdata_octets += (psol->
  1058. dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1059. & SOL_RES_CNT_MASK);
  1060. }
  1061. unmap:
  1062. scsi_dma_unmap(io_task->scsi_cmnd);
  1063. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1064. }
  1065. static void
  1066. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1067. struct iscsi_task *task, struct sol_cqe *psol)
  1068. {
  1069. struct iscsi_logout_rsp *hdr;
  1070. struct beiscsi_io_task *io_task = task->dd_data;
  1071. struct iscsi_conn *conn = beiscsi_conn->conn;
  1072. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1073. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1074. hdr->t2wait = 5;
  1075. hdr->t2retain = 0;
  1076. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1077. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1078. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1079. 32] & SOL_RESP_MASK);
  1080. hdr->exp_cmdsn = cpu_to_be32(psol->
  1081. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1082. & SOL_EXP_CMD_SN_MASK);
  1083. hdr->max_cmdsn = be32_to_cpu((psol->
  1084. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1085. & SOL_EXP_CMD_SN_MASK) +
  1086. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1087. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1088. hdr->dlength[0] = 0;
  1089. hdr->dlength[1] = 0;
  1090. hdr->dlength[2] = 0;
  1091. hdr->hlength = 0;
  1092. hdr->itt = io_task->libiscsi_itt;
  1093. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1094. }
  1095. static void
  1096. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1097. struct iscsi_task *task, struct sol_cqe *psol)
  1098. {
  1099. struct iscsi_tm_rsp *hdr;
  1100. struct iscsi_conn *conn = beiscsi_conn->conn;
  1101. struct beiscsi_io_task *io_task = task->dd_data;
  1102. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1103. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1104. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1105. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1106. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1107. 32] & SOL_RESP_MASK);
  1108. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1109. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1110. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1111. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1112. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1113. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1114. hdr->itt = io_task->libiscsi_itt;
  1115. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1116. }
  1117. static void
  1118. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1119. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1120. {
  1121. struct hwi_wrb_context *pwrb_context;
  1122. struct wrb_handle *pwrb_handle = NULL;
  1123. struct hwi_controller *phwi_ctrlr;
  1124. struct iscsi_task *task;
  1125. struct beiscsi_io_task *io_task;
  1126. struct iscsi_conn *conn = beiscsi_conn->conn;
  1127. struct iscsi_session *session = conn->session;
  1128. phwi_ctrlr = phba->phwi_ctrlr;
  1129. pwrb_context = &phwi_ctrlr->wrb_context[((psol->
  1130. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1131. SOL_CID_MASK) >> 6) -
  1132. phba->fw_config.iscsi_cid_start];
  1133. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1134. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1135. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1136. task = pwrb_handle->pio_handle;
  1137. io_task = task->dd_data;
  1138. spin_lock_bh(&phba->mgmt_sgl_lock);
  1139. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1140. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1141. spin_lock_bh(&session->lock);
  1142. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1143. spin_unlock_bh(&session->lock);
  1144. }
  1145. static void
  1146. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1147. struct iscsi_task *task, struct sol_cqe *psol)
  1148. {
  1149. struct iscsi_nopin *hdr;
  1150. struct iscsi_conn *conn = beiscsi_conn->conn;
  1151. struct beiscsi_io_task *io_task = task->dd_data;
  1152. hdr = (struct iscsi_nopin *)task->hdr;
  1153. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1154. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1155. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1156. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1157. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1158. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1159. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1160. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1161. hdr->opcode = ISCSI_OP_NOOP_IN;
  1162. hdr->itt = io_task->libiscsi_itt;
  1163. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1164. }
  1165. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1166. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1167. {
  1168. struct hwi_wrb_context *pwrb_context;
  1169. struct wrb_handle *pwrb_handle;
  1170. struct iscsi_wrb *pwrb = NULL;
  1171. struct hwi_controller *phwi_ctrlr;
  1172. struct iscsi_task *task;
  1173. unsigned int type;
  1174. struct iscsi_conn *conn = beiscsi_conn->conn;
  1175. struct iscsi_session *session = conn->session;
  1176. phwi_ctrlr = phba->phwi_ctrlr;
  1177. pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
  1178. (struct amap_sol_cqe, cid) / 32]
  1179. & SOL_CID_MASK) >> 6) -
  1180. phba->fw_config.iscsi_cid_start];
  1181. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1182. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1183. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1184. task = pwrb_handle->pio_handle;
  1185. pwrb = pwrb_handle->pwrb;
  1186. type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
  1187. WRB_TYPE_MASK) >> 28;
  1188. spin_lock_bh(&session->lock);
  1189. switch (type) {
  1190. case HWH_TYPE_IO:
  1191. case HWH_TYPE_IO_RD:
  1192. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1193. ISCSI_OP_NOOP_OUT)
  1194. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1195. else
  1196. be_complete_io(beiscsi_conn, task, psol);
  1197. break;
  1198. case HWH_TYPE_LOGOUT:
  1199. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1200. be_complete_logout(beiscsi_conn, task, psol);
  1201. else
  1202. be_complete_tmf(beiscsi_conn, task, psol);
  1203. break;
  1204. case HWH_TYPE_LOGIN:
  1205. SE_DEBUG(DBG_LVL_1,
  1206. "\t\t No HWH_TYPE_LOGIN Expected in hwi_complete_cmd"
  1207. "- Solicited path\n");
  1208. break;
  1209. case HWH_TYPE_NOP:
  1210. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1211. break;
  1212. default:
  1213. shost_printk(KERN_WARNING, phba->shost,
  1214. "In hwi_complete_cmd, unknown type = %d"
  1215. "wrb_index 0x%x CID 0x%x\n", type,
  1216. ((psol->dw[offsetof(struct amap_iscsi_wrb,
  1217. type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
  1218. ((psol->dw[offsetof(struct amap_sol_cqe,
  1219. cid) / 32] & SOL_CID_MASK) >> 6));
  1220. break;
  1221. }
  1222. spin_unlock_bh(&session->lock);
  1223. }
  1224. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1225. *pasync_ctx, unsigned int is_header,
  1226. unsigned int host_write_ptr)
  1227. {
  1228. if (is_header)
  1229. return &pasync_ctx->async_entry[host_write_ptr].
  1230. header_busy_list;
  1231. else
  1232. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1233. }
  1234. static struct async_pdu_handle *
  1235. hwi_get_async_handle(struct beiscsi_hba *phba,
  1236. struct beiscsi_conn *beiscsi_conn,
  1237. struct hwi_async_pdu_context *pasync_ctx,
  1238. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1239. {
  1240. struct be_bus_address phys_addr;
  1241. struct list_head *pbusy_list;
  1242. struct async_pdu_handle *pasync_handle = NULL;
  1243. unsigned char is_header = 0;
  1244. phys_addr.u.a32.address_lo =
  1245. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
  1246. ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1247. & PDUCQE_DPL_MASK) >> 16);
  1248. phys_addr.u.a32.address_hi =
  1249. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
  1250. phys_addr.u.a64.address =
  1251. *((unsigned long long *)(&phys_addr.u.a64.address));
  1252. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1253. & PDUCQE_CODE_MASK) {
  1254. case UNSOL_HDR_NOTIFY:
  1255. is_header = 1;
  1256. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
  1257. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1258. index) / 32] & PDUCQE_INDEX_MASK));
  1259. break;
  1260. case UNSOL_DATA_NOTIFY:
  1261. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
  1262. dw[offsetof(struct amap_i_t_dpdu_cqe,
  1263. index) / 32] & PDUCQE_INDEX_MASK));
  1264. break;
  1265. default:
  1266. pbusy_list = NULL;
  1267. shost_printk(KERN_WARNING, phba->shost,
  1268. "Unexpected code=%d\n",
  1269. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1270. code) / 32] & PDUCQE_CODE_MASK);
  1271. return NULL;
  1272. }
  1273. WARN_ON(list_empty(pbusy_list));
  1274. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1275. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1276. break;
  1277. }
  1278. WARN_ON(!pasync_handle);
  1279. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1280. phba->fw_config.iscsi_cid_start;
  1281. pasync_handle->is_header = is_header;
  1282. pasync_handle->buffer_len = ((pdpdu_cqe->
  1283. dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1284. & PDUCQE_DPL_MASK) >> 16);
  1285. *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1286. index) / 32] & PDUCQE_INDEX_MASK);
  1287. return pasync_handle;
  1288. }
  1289. static unsigned int
  1290. hwi_update_async_writables(struct hwi_async_pdu_context *pasync_ctx,
  1291. unsigned int is_header, unsigned int cq_index)
  1292. {
  1293. struct list_head *pbusy_list;
  1294. struct async_pdu_handle *pasync_handle;
  1295. unsigned int num_entries, writables = 0;
  1296. unsigned int *pep_read_ptr, *pwritables;
  1297. num_entries = pasync_ctx->num_entries;
  1298. if (is_header) {
  1299. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1300. pwritables = &pasync_ctx->async_header.writables;
  1301. } else {
  1302. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1303. pwritables = &pasync_ctx->async_data.writables;
  1304. }
  1305. while ((*pep_read_ptr) != cq_index) {
  1306. (*pep_read_ptr)++;
  1307. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1308. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1309. *pep_read_ptr);
  1310. if (writables == 0)
  1311. WARN_ON(list_empty(pbusy_list));
  1312. if (!list_empty(pbusy_list)) {
  1313. pasync_handle = list_entry(pbusy_list->next,
  1314. struct async_pdu_handle,
  1315. link);
  1316. WARN_ON(!pasync_handle);
  1317. pasync_handle->consumed = 1;
  1318. }
  1319. writables++;
  1320. }
  1321. if (!writables) {
  1322. SE_DEBUG(DBG_LVL_1,
  1323. "Duplicate notification received - index 0x%x!!\n",
  1324. cq_index);
  1325. WARN_ON(1);
  1326. }
  1327. *pwritables = *pwritables + writables;
  1328. return 0;
  1329. }
  1330. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1331. unsigned int cri)
  1332. {
  1333. struct hwi_controller *phwi_ctrlr;
  1334. struct hwi_async_pdu_context *pasync_ctx;
  1335. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1336. struct list_head *plist;
  1337. phwi_ctrlr = phba->phwi_ctrlr;
  1338. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1339. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1340. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1341. list_del(&pasync_handle->link);
  1342. if (pasync_handle->is_header) {
  1343. list_add_tail(&pasync_handle->link,
  1344. &pasync_ctx->async_header.free_list);
  1345. pasync_ctx->async_header.free_entries++;
  1346. } else {
  1347. list_add_tail(&pasync_handle->link,
  1348. &pasync_ctx->async_data.free_list);
  1349. pasync_ctx->async_data.free_entries++;
  1350. }
  1351. }
  1352. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1353. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1354. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1355. }
  1356. static struct phys_addr *
  1357. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1358. unsigned int is_header, unsigned int host_write_ptr)
  1359. {
  1360. struct phys_addr *pasync_sge = NULL;
  1361. if (is_header)
  1362. pasync_sge = pasync_ctx->async_header.ring_base;
  1363. else
  1364. pasync_sge = pasync_ctx->async_data.ring_base;
  1365. return pasync_sge + host_write_ptr;
  1366. }
  1367. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1368. unsigned int is_header)
  1369. {
  1370. struct hwi_controller *phwi_ctrlr;
  1371. struct hwi_async_pdu_context *pasync_ctx;
  1372. struct async_pdu_handle *pasync_handle;
  1373. struct list_head *pfree_link, *pbusy_list;
  1374. struct phys_addr *pasync_sge;
  1375. unsigned int ring_id, num_entries;
  1376. unsigned int host_write_num;
  1377. unsigned int writables;
  1378. unsigned int i = 0;
  1379. u32 doorbell = 0;
  1380. phwi_ctrlr = phba->phwi_ctrlr;
  1381. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1382. num_entries = pasync_ctx->num_entries;
  1383. if (is_header) {
  1384. writables = min(pasync_ctx->async_header.writables,
  1385. pasync_ctx->async_header.free_entries);
  1386. pfree_link = pasync_ctx->async_header.free_list.next;
  1387. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1388. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1389. } else {
  1390. writables = min(pasync_ctx->async_data.writables,
  1391. pasync_ctx->async_data.free_entries);
  1392. pfree_link = pasync_ctx->async_data.free_list.next;
  1393. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1394. ring_id = phwi_ctrlr->default_pdu_data.id;
  1395. }
  1396. writables = (writables / 8) * 8;
  1397. if (writables) {
  1398. for (i = 0; i < writables; i++) {
  1399. pbusy_list =
  1400. hwi_get_async_busy_list(pasync_ctx, is_header,
  1401. host_write_num);
  1402. pasync_handle =
  1403. list_entry(pfree_link, struct async_pdu_handle,
  1404. link);
  1405. WARN_ON(!pasync_handle);
  1406. pasync_handle->consumed = 0;
  1407. pfree_link = pfree_link->next;
  1408. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1409. is_header, host_write_num);
  1410. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1411. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1412. list_move(&pasync_handle->link, pbusy_list);
  1413. host_write_num++;
  1414. host_write_num = host_write_num % num_entries;
  1415. }
  1416. if (is_header) {
  1417. pasync_ctx->async_header.host_write_ptr =
  1418. host_write_num;
  1419. pasync_ctx->async_header.free_entries -= writables;
  1420. pasync_ctx->async_header.writables -= writables;
  1421. pasync_ctx->async_header.busy_entries += writables;
  1422. } else {
  1423. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1424. pasync_ctx->async_data.free_entries -= writables;
  1425. pasync_ctx->async_data.writables -= writables;
  1426. pasync_ctx->async_data.busy_entries += writables;
  1427. }
  1428. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1429. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1430. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1431. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1432. << DB_DEF_PDU_CQPROC_SHIFT;
  1433. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1434. }
  1435. }
  1436. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1437. struct beiscsi_conn *beiscsi_conn,
  1438. struct i_t_dpdu_cqe *pdpdu_cqe)
  1439. {
  1440. struct hwi_controller *phwi_ctrlr;
  1441. struct hwi_async_pdu_context *pasync_ctx;
  1442. struct async_pdu_handle *pasync_handle = NULL;
  1443. unsigned int cq_index = -1;
  1444. phwi_ctrlr = phba->phwi_ctrlr;
  1445. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1446. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1447. pdpdu_cqe, &cq_index);
  1448. BUG_ON(pasync_handle->is_header != 0);
  1449. if (pasync_handle->consumed == 0)
  1450. hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
  1451. cq_index);
  1452. hwi_free_async_msg(phba, pasync_handle->cri);
  1453. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1454. }
  1455. static unsigned int
  1456. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1457. struct beiscsi_hba *phba,
  1458. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1459. {
  1460. struct list_head *plist;
  1461. struct async_pdu_handle *pasync_handle;
  1462. void *phdr = NULL;
  1463. unsigned int hdr_len = 0, buf_len = 0;
  1464. unsigned int status, index = 0, offset = 0;
  1465. void *pfirst_buffer = NULL;
  1466. unsigned int num_buf = 0;
  1467. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1468. list_for_each_entry(pasync_handle, plist, link) {
  1469. if (index == 0) {
  1470. phdr = pasync_handle->pbuffer;
  1471. hdr_len = pasync_handle->buffer_len;
  1472. } else {
  1473. buf_len = pasync_handle->buffer_len;
  1474. if (!num_buf) {
  1475. pfirst_buffer = pasync_handle->pbuffer;
  1476. num_buf++;
  1477. }
  1478. memcpy(pfirst_buffer + offset,
  1479. pasync_handle->pbuffer, buf_len);
  1480. offset += buf_len;
  1481. }
  1482. index++;
  1483. }
  1484. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1485. (beiscsi_conn->beiscsi_conn_cid -
  1486. phba->fw_config.iscsi_cid_start),
  1487. phdr, hdr_len, pfirst_buffer,
  1488. offset);
  1489. if (status == 0)
  1490. hwi_free_async_msg(phba, cri);
  1491. return 0;
  1492. }
  1493. static unsigned int
  1494. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1495. struct beiscsi_hba *phba,
  1496. struct async_pdu_handle *pasync_handle)
  1497. {
  1498. struct hwi_async_pdu_context *pasync_ctx;
  1499. struct hwi_controller *phwi_ctrlr;
  1500. unsigned int bytes_needed = 0, status = 0;
  1501. unsigned short cri = pasync_handle->cri;
  1502. struct pdu_base *ppdu;
  1503. phwi_ctrlr = phba->phwi_ctrlr;
  1504. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1505. list_del(&pasync_handle->link);
  1506. if (pasync_handle->is_header) {
  1507. pasync_ctx->async_header.busy_entries--;
  1508. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1509. hwi_free_async_msg(phba, cri);
  1510. BUG();
  1511. }
  1512. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1513. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1514. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1515. (unsigned short)pasync_handle->buffer_len;
  1516. list_add_tail(&pasync_handle->link,
  1517. &pasync_ctx->async_entry[cri].wait_queue.list);
  1518. ppdu = pasync_handle->pbuffer;
  1519. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1520. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1521. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1522. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1523. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1524. if (status == 0) {
  1525. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1526. bytes_needed;
  1527. if (bytes_needed == 0)
  1528. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1529. pasync_ctx, cri);
  1530. }
  1531. } else {
  1532. pasync_ctx->async_data.busy_entries--;
  1533. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1534. list_add_tail(&pasync_handle->link,
  1535. &pasync_ctx->async_entry[cri].wait_queue.
  1536. list);
  1537. pasync_ctx->async_entry[cri].wait_queue.
  1538. bytes_received +=
  1539. (unsigned short)pasync_handle->buffer_len;
  1540. if (pasync_ctx->async_entry[cri].wait_queue.
  1541. bytes_received >=
  1542. pasync_ctx->async_entry[cri].wait_queue.
  1543. bytes_needed)
  1544. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1545. pasync_ctx, cri);
  1546. }
  1547. }
  1548. return status;
  1549. }
  1550. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1551. struct beiscsi_hba *phba,
  1552. struct i_t_dpdu_cqe *pdpdu_cqe)
  1553. {
  1554. struct hwi_controller *phwi_ctrlr;
  1555. struct hwi_async_pdu_context *pasync_ctx;
  1556. struct async_pdu_handle *pasync_handle = NULL;
  1557. unsigned int cq_index = -1;
  1558. phwi_ctrlr = phba->phwi_ctrlr;
  1559. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1560. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1561. pdpdu_cqe, &cq_index);
  1562. if (pasync_handle->consumed == 0)
  1563. hwi_update_async_writables(pasync_ctx, pasync_handle->is_header,
  1564. cq_index);
  1565. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1566. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1567. }
  1568. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1569. {
  1570. struct be_queue_info *mcc_cq;
  1571. struct be_mcc_compl *mcc_compl;
  1572. unsigned int num_processed = 0;
  1573. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1574. mcc_compl = queue_tail_node(mcc_cq);
  1575. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1576. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1577. if (num_processed >= 32) {
  1578. hwi_ring_cq_db(phba, mcc_cq->id,
  1579. num_processed, 0, 0);
  1580. num_processed = 0;
  1581. }
  1582. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1583. /* Interpret flags as an async trailer */
  1584. if (is_link_state_evt(mcc_compl->flags))
  1585. /* Interpret compl as a async link evt */
  1586. beiscsi_async_link_state_process(phba,
  1587. (struct be_async_event_link_state *) mcc_compl);
  1588. else
  1589. SE_DEBUG(DBG_LVL_1,
  1590. " Unsupported Async Event, flags"
  1591. " = 0x%08x\n", mcc_compl->flags);
  1592. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1593. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1594. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1595. }
  1596. mcc_compl->flags = 0;
  1597. queue_tail_inc(mcc_cq);
  1598. mcc_compl = queue_tail_node(mcc_cq);
  1599. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1600. num_processed++;
  1601. }
  1602. if (num_processed > 0)
  1603. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1604. }
  1605. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1606. {
  1607. struct be_queue_info *cq;
  1608. struct sol_cqe *sol;
  1609. struct dmsg_cqe *dmsg;
  1610. unsigned int num_processed = 0;
  1611. unsigned int tot_nump = 0;
  1612. struct beiscsi_conn *beiscsi_conn;
  1613. struct beiscsi_endpoint *beiscsi_ep;
  1614. struct iscsi_endpoint *ep;
  1615. struct beiscsi_hba *phba;
  1616. cq = pbe_eq->cq;
  1617. sol = queue_tail_node(cq);
  1618. phba = pbe_eq->phba;
  1619. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1620. CQE_VALID_MASK) {
  1621. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1622. ep = phba->ep_array[(u32) ((sol->
  1623. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1624. SOL_CID_MASK) >> 6) -
  1625. phba->fw_config.iscsi_cid_start];
  1626. beiscsi_ep = ep->dd_data;
  1627. beiscsi_conn = beiscsi_ep->conn;
  1628. if (num_processed >= 32) {
  1629. hwi_ring_cq_db(phba, cq->id,
  1630. num_processed, 0, 0);
  1631. tot_nump += num_processed;
  1632. num_processed = 0;
  1633. }
  1634. switch ((u32) sol->dw[offsetof(struct amap_sol_cqe, code) /
  1635. 32] & CQE_CODE_MASK) {
  1636. case SOL_CMD_COMPLETE:
  1637. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1638. break;
  1639. case DRIVERMSG_NOTIFY:
  1640. SE_DEBUG(DBG_LVL_8, "Received DRIVERMSG_NOTIFY\n");
  1641. dmsg = (struct dmsg_cqe *)sol;
  1642. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1643. break;
  1644. case UNSOL_HDR_NOTIFY:
  1645. SE_DEBUG(DBG_LVL_8, "Received UNSOL_HDR_ NOTIFY\n");
  1646. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1647. (struct i_t_dpdu_cqe *)sol);
  1648. break;
  1649. case UNSOL_DATA_NOTIFY:
  1650. SE_DEBUG(DBG_LVL_8, "Received UNSOL_DATA_NOTIFY\n");
  1651. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1652. (struct i_t_dpdu_cqe *)sol);
  1653. break;
  1654. case CXN_INVALIDATE_INDEX_NOTIFY:
  1655. case CMD_INVALIDATED_NOTIFY:
  1656. case CXN_INVALIDATE_NOTIFY:
  1657. SE_DEBUG(DBG_LVL_1,
  1658. "Ignoring CQ Error notification for cmd/cxn"
  1659. "invalidate\n");
  1660. break;
  1661. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1662. case CMD_KILLED_INVALID_STATSN_RCVD:
  1663. case CMD_KILLED_INVALID_R2T_RCVD:
  1664. case CMD_CXN_KILLED_LUN_INVALID:
  1665. case CMD_CXN_KILLED_ICD_INVALID:
  1666. case CMD_CXN_KILLED_ITT_INVALID:
  1667. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1668. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1669. SE_DEBUG(DBG_LVL_1,
  1670. "CQ Error notification for cmd.. "
  1671. "code %d cid 0x%x\n",
  1672. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1673. 32] & CQE_CODE_MASK,
  1674. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1675. 32] & SOL_CID_MASK));
  1676. break;
  1677. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1678. SE_DEBUG(DBG_LVL_1,
  1679. "Digest error on def pdu ring, dropping..\n");
  1680. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1681. (struct i_t_dpdu_cqe *) sol);
  1682. break;
  1683. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1684. case CXN_KILLED_BURST_LEN_MISMATCH:
  1685. case CXN_KILLED_AHS_RCVD:
  1686. case CXN_KILLED_HDR_DIGEST_ERR:
  1687. case CXN_KILLED_UNKNOWN_HDR:
  1688. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1689. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1690. case CXN_KILLED_TIMED_OUT:
  1691. case CXN_KILLED_FIN_RCVD:
  1692. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1693. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1694. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1695. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1696. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1697. SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset CID "
  1698. "0x%x...\n",
  1699. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1700. 32] & CQE_CODE_MASK,
  1701. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1702. 32] & CQE_CID_MASK));
  1703. iscsi_conn_failure(beiscsi_conn->conn,
  1704. ISCSI_ERR_CONN_FAILED);
  1705. break;
  1706. case CXN_KILLED_RST_SENT:
  1707. case CXN_KILLED_RST_RCVD:
  1708. SE_DEBUG(DBG_LVL_1, "CQ Error %d, reset"
  1709. "received/sent on CID 0x%x...\n",
  1710. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1711. 32] & CQE_CODE_MASK,
  1712. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1713. 32] & CQE_CID_MASK));
  1714. iscsi_conn_failure(beiscsi_conn->conn,
  1715. ISCSI_ERR_CONN_FAILED);
  1716. break;
  1717. default:
  1718. SE_DEBUG(DBG_LVL_1, "CQ Error Invalid code= %d "
  1719. "received on CID 0x%x...\n",
  1720. sol->dw[offsetof(struct amap_sol_cqe, code) /
  1721. 32] & CQE_CODE_MASK,
  1722. (sol->dw[offsetof(struct amap_sol_cqe, cid) /
  1723. 32] & CQE_CID_MASK));
  1724. break;
  1725. }
  1726. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1727. queue_tail_inc(cq);
  1728. sol = queue_tail_node(cq);
  1729. num_processed++;
  1730. }
  1731. if (num_processed > 0) {
  1732. tot_nump += num_processed;
  1733. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1734. }
  1735. return tot_nump;
  1736. }
  1737. void beiscsi_process_all_cqs(struct work_struct *work)
  1738. {
  1739. unsigned long flags;
  1740. struct hwi_controller *phwi_ctrlr;
  1741. struct hwi_context_memory *phwi_context;
  1742. struct be_eq_obj *pbe_eq;
  1743. struct beiscsi_hba *phba =
  1744. container_of(work, struct beiscsi_hba, work_cqs);
  1745. phwi_ctrlr = phba->phwi_ctrlr;
  1746. phwi_context = phwi_ctrlr->phwi_ctxt;
  1747. if (phba->msix_enabled)
  1748. pbe_eq = &phwi_context->be_eq[phba->num_cpus];
  1749. else
  1750. pbe_eq = &phwi_context->be_eq[0];
  1751. if (phba->todo_mcc_cq) {
  1752. spin_lock_irqsave(&phba->isr_lock, flags);
  1753. phba->todo_mcc_cq = 0;
  1754. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1755. beiscsi_process_mcc_isr(phba);
  1756. }
  1757. if (phba->todo_cq) {
  1758. spin_lock_irqsave(&phba->isr_lock, flags);
  1759. phba->todo_cq = 0;
  1760. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1761. beiscsi_process_cq(pbe_eq);
  1762. }
  1763. }
  1764. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1765. {
  1766. static unsigned int ret;
  1767. struct beiscsi_hba *phba;
  1768. struct be_eq_obj *pbe_eq;
  1769. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1770. ret = beiscsi_process_cq(pbe_eq);
  1771. if (ret < budget) {
  1772. phba = pbe_eq->phba;
  1773. blk_iopoll_complete(iop);
  1774. SE_DEBUG(DBG_LVL_8, "rearm pbe_eq->q.id =%d\n", pbe_eq->q.id);
  1775. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1776. }
  1777. return ret;
  1778. }
  1779. static void
  1780. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1781. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1782. {
  1783. struct iscsi_sge *psgl;
  1784. unsigned int sg_len, index;
  1785. unsigned int sge_len = 0;
  1786. unsigned long long addr;
  1787. struct scatterlist *l_sg;
  1788. unsigned int offset;
  1789. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1790. io_task->bhs_pa.u.a32.address_lo);
  1791. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1792. io_task->bhs_pa.u.a32.address_hi);
  1793. l_sg = sg;
  1794. for (index = 0; (index < num_sg) && (index < 2); index++,
  1795. sg = sg_next(sg)) {
  1796. if (index == 0) {
  1797. sg_len = sg_dma_len(sg);
  1798. addr = (u64) sg_dma_address(sg);
  1799. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1800. ((u32)(addr & 0xFFFFFFFF)));
  1801. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1802. ((u32)(addr >> 32)));
  1803. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1804. sg_len);
  1805. sge_len = sg_len;
  1806. } else {
  1807. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  1808. pwrb, sge_len);
  1809. sg_len = sg_dma_len(sg);
  1810. addr = (u64) sg_dma_address(sg);
  1811. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  1812. ((u32)(addr & 0xFFFFFFFF)));
  1813. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  1814. ((u32)(addr >> 32)));
  1815. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  1816. sg_len);
  1817. }
  1818. }
  1819. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1820. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  1821. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  1822. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1823. io_task->bhs_pa.u.a32.address_hi);
  1824. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1825. io_task->bhs_pa.u.a32.address_lo);
  1826. if (num_sg == 1) {
  1827. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1828. 1);
  1829. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1830. 0);
  1831. } else if (num_sg == 2) {
  1832. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1833. 0);
  1834. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1835. 1);
  1836. } else {
  1837. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1838. 0);
  1839. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1840. 0);
  1841. }
  1842. sg = l_sg;
  1843. psgl++;
  1844. psgl++;
  1845. offset = 0;
  1846. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  1847. sg_len = sg_dma_len(sg);
  1848. addr = (u64) sg_dma_address(sg);
  1849. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1850. (addr & 0xFFFFFFFF));
  1851. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1852. (addr >> 32));
  1853. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  1854. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  1855. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  1856. offset += sg_len;
  1857. }
  1858. psgl--;
  1859. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  1860. }
  1861. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  1862. {
  1863. struct iscsi_sge *psgl;
  1864. unsigned long long addr;
  1865. struct beiscsi_io_task *io_task = task->dd_data;
  1866. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  1867. struct beiscsi_hba *phba = beiscsi_conn->phba;
  1868. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  1869. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1870. io_task->bhs_pa.u.a32.address_lo);
  1871. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1872. io_task->bhs_pa.u.a32.address_hi);
  1873. if (task->data) {
  1874. if (task->data_count) {
  1875. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  1876. addr = (u64) pci_map_single(phba->pcidev,
  1877. task->data,
  1878. task->data_count, 1);
  1879. } else {
  1880. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  1881. addr = 0;
  1882. }
  1883. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1884. ((u32)(addr & 0xFFFFFFFF)));
  1885. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1886. ((u32)(addr >> 32)));
  1887. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1888. task->data_count);
  1889. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  1890. } else {
  1891. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  1892. addr = 0;
  1893. }
  1894. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1895. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  1896. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1897. io_task->bhs_pa.u.a32.address_hi);
  1898. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1899. io_task->bhs_pa.u.a32.address_lo);
  1900. if (task->data) {
  1901. psgl++;
  1902. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  1903. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  1904. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  1905. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  1906. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  1907. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  1908. psgl++;
  1909. if (task->data) {
  1910. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1911. ((u32)(addr & 0xFFFFFFFF)));
  1912. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1913. ((u32)(addr >> 32)));
  1914. }
  1915. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  1916. }
  1917. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  1918. }
  1919. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  1920. {
  1921. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  1922. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  1923. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  1924. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  1925. sizeof(struct sol_cqe));
  1926. num_async_pdu_buf_pages =
  1927. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1928. phba->params.defpdu_hdr_sz);
  1929. num_async_pdu_buf_sgl_pages =
  1930. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1931. sizeof(struct phys_addr));
  1932. num_async_pdu_data_pages =
  1933. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1934. phba->params.defpdu_data_sz);
  1935. num_async_pdu_data_sgl_pages =
  1936. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  1937. sizeof(struct phys_addr));
  1938. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  1939. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  1940. BE_ISCSI_PDU_HEADER_SIZE;
  1941. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  1942. sizeof(struct hwi_context_memory);
  1943. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  1944. * (phba->params.wrbs_per_cxn)
  1945. * phba->params.cxns_per_ctrl;
  1946. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  1947. (phba->params.wrbs_per_cxn);
  1948. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  1949. phba->params.cxns_per_ctrl);
  1950. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  1951. phba->params.icds_per_ctrl;
  1952. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  1953. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  1954. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  1955. num_async_pdu_buf_pages * PAGE_SIZE;
  1956. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  1957. num_async_pdu_data_pages * PAGE_SIZE;
  1958. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  1959. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  1960. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  1961. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  1962. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  1963. phba->params.asyncpdus_per_ctrl *
  1964. sizeof(struct async_pdu_handle);
  1965. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  1966. phba->params.asyncpdus_per_ctrl *
  1967. sizeof(struct async_pdu_handle);
  1968. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  1969. sizeof(struct hwi_async_pdu_context) +
  1970. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  1971. }
  1972. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  1973. {
  1974. struct be_mem_descriptor *mem_descr;
  1975. dma_addr_t bus_add;
  1976. struct mem_array *mem_arr, *mem_arr_orig;
  1977. unsigned int i, j, alloc_size, curr_alloc_size;
  1978. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  1979. if (!phba->phwi_ctrlr)
  1980. return -ENOMEM;
  1981. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  1982. GFP_KERNEL);
  1983. if (!phba->init_mem) {
  1984. kfree(phba->phwi_ctrlr);
  1985. return -ENOMEM;
  1986. }
  1987. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  1988. GFP_KERNEL);
  1989. if (!mem_arr_orig) {
  1990. kfree(phba->init_mem);
  1991. kfree(phba->phwi_ctrlr);
  1992. return -ENOMEM;
  1993. }
  1994. mem_descr = phba->init_mem;
  1995. for (i = 0; i < SE_MEM_MAX; i++) {
  1996. j = 0;
  1997. mem_arr = mem_arr_orig;
  1998. alloc_size = phba->mem_req[i];
  1999. memset(mem_arr, 0, sizeof(struct mem_array) *
  2000. BEISCSI_MAX_FRAGS_INIT);
  2001. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2002. do {
  2003. mem_arr->virtual_address = pci_alloc_consistent(
  2004. phba->pcidev,
  2005. curr_alloc_size,
  2006. &bus_add);
  2007. if (!mem_arr->virtual_address) {
  2008. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2009. goto free_mem;
  2010. if (curr_alloc_size -
  2011. rounddown_pow_of_two(curr_alloc_size))
  2012. curr_alloc_size = rounddown_pow_of_two
  2013. (curr_alloc_size);
  2014. else
  2015. curr_alloc_size = curr_alloc_size / 2;
  2016. } else {
  2017. mem_arr->bus_address.u.
  2018. a64.address = (__u64) bus_add;
  2019. mem_arr->size = curr_alloc_size;
  2020. alloc_size -= curr_alloc_size;
  2021. curr_alloc_size = min(be_max_phys_size *
  2022. 1024, alloc_size);
  2023. j++;
  2024. mem_arr++;
  2025. }
  2026. } while (alloc_size);
  2027. mem_descr->num_elements = j;
  2028. mem_descr->size_in_bytes = phba->mem_req[i];
  2029. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2030. GFP_KERNEL);
  2031. if (!mem_descr->mem_array)
  2032. goto free_mem;
  2033. memcpy(mem_descr->mem_array, mem_arr_orig,
  2034. sizeof(struct mem_array) * j);
  2035. mem_descr++;
  2036. }
  2037. kfree(mem_arr_orig);
  2038. return 0;
  2039. free_mem:
  2040. mem_descr->num_elements = j;
  2041. while ((i) || (j)) {
  2042. for (j = mem_descr->num_elements; j > 0; j--) {
  2043. pci_free_consistent(phba->pcidev,
  2044. mem_descr->mem_array[j - 1].size,
  2045. mem_descr->mem_array[j - 1].
  2046. virtual_address,
  2047. (unsigned long)mem_descr->
  2048. mem_array[j - 1].
  2049. bus_address.u.a64.address);
  2050. }
  2051. if (i) {
  2052. i--;
  2053. kfree(mem_descr->mem_array);
  2054. mem_descr--;
  2055. }
  2056. }
  2057. kfree(mem_arr_orig);
  2058. kfree(phba->init_mem);
  2059. kfree(phba->phwi_ctrlr);
  2060. return -ENOMEM;
  2061. }
  2062. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2063. {
  2064. beiscsi_find_mem_req(phba);
  2065. return beiscsi_alloc_mem(phba);
  2066. }
  2067. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2068. {
  2069. struct pdu_data_out *pdata_out;
  2070. struct pdu_nop_out *pnop_out;
  2071. struct be_mem_descriptor *mem_descr;
  2072. mem_descr = phba->init_mem;
  2073. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2074. pdata_out =
  2075. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2076. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2077. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2078. IIOC_SCSI_DATA);
  2079. pnop_out =
  2080. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2081. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2082. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2083. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2084. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2085. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2086. }
  2087. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2088. {
  2089. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2090. struct wrb_handle *pwrb_handle = NULL;
  2091. struct hwi_controller *phwi_ctrlr;
  2092. struct hwi_wrb_context *pwrb_context;
  2093. struct iscsi_wrb *pwrb = NULL;
  2094. unsigned int num_cxn_wrbh = 0;
  2095. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2096. mem_descr_wrbh = phba->init_mem;
  2097. mem_descr_wrbh += HWI_MEM_WRBH;
  2098. mem_descr_wrb = phba->init_mem;
  2099. mem_descr_wrb += HWI_MEM_WRB;
  2100. phwi_ctrlr = phba->phwi_ctrlr;
  2101. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2102. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2103. pwrb_context->pwrb_handle_base =
  2104. kzalloc(sizeof(struct wrb_handle *) *
  2105. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2106. if (!pwrb_context->pwrb_handle_base) {
  2107. shost_printk(KERN_ERR, phba->shost,
  2108. "Mem Alloc Failed. Failing to load\n");
  2109. goto init_wrb_hndl_failed;
  2110. }
  2111. pwrb_context->pwrb_handle_basestd =
  2112. kzalloc(sizeof(struct wrb_handle *) *
  2113. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2114. if (!pwrb_context->pwrb_handle_basestd) {
  2115. shost_printk(KERN_ERR, phba->shost,
  2116. "Mem Alloc Failed. Failing to load\n");
  2117. goto init_wrb_hndl_failed;
  2118. }
  2119. if (!num_cxn_wrbh) {
  2120. pwrb_handle =
  2121. mem_descr_wrbh->mem_array[idx].virtual_address;
  2122. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2123. ((sizeof(struct wrb_handle)) *
  2124. phba->params.wrbs_per_cxn));
  2125. idx++;
  2126. }
  2127. pwrb_context->alloc_index = 0;
  2128. pwrb_context->wrb_handles_available = 0;
  2129. pwrb_context->free_index = 0;
  2130. if (num_cxn_wrbh) {
  2131. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2132. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2133. pwrb_context->pwrb_handle_basestd[j] =
  2134. pwrb_handle;
  2135. pwrb_context->wrb_handles_available++;
  2136. pwrb_handle->wrb_index = j;
  2137. pwrb_handle++;
  2138. }
  2139. num_cxn_wrbh--;
  2140. }
  2141. }
  2142. idx = 0;
  2143. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2144. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2145. if (!num_cxn_wrb) {
  2146. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2147. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2148. ((sizeof(struct iscsi_wrb) *
  2149. phba->params.wrbs_per_cxn));
  2150. idx++;
  2151. }
  2152. if (num_cxn_wrb) {
  2153. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2154. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2155. pwrb_handle->pwrb = pwrb;
  2156. pwrb++;
  2157. }
  2158. num_cxn_wrb--;
  2159. }
  2160. }
  2161. return 0;
  2162. init_wrb_hndl_failed:
  2163. for (j = index; j > 0; j--) {
  2164. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2165. kfree(pwrb_context->pwrb_handle_base);
  2166. kfree(pwrb_context->pwrb_handle_basestd);
  2167. }
  2168. return -ENOMEM;
  2169. }
  2170. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2171. {
  2172. struct hwi_controller *phwi_ctrlr;
  2173. struct hba_parameters *p = &phba->params;
  2174. struct hwi_async_pdu_context *pasync_ctx;
  2175. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2176. unsigned int index, idx, num_per_mem, num_async_data;
  2177. struct be_mem_descriptor *mem_descr;
  2178. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2179. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2180. phwi_ctrlr = phba->phwi_ctrlr;
  2181. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2182. mem_descr->mem_array[0].virtual_address;
  2183. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2184. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2185. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2186. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2187. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2188. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2189. if (mem_descr->mem_array[0].virtual_address) {
  2190. SE_DEBUG(DBG_LVL_8,
  2191. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_BUF"
  2192. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2193. } else
  2194. shost_printk(KERN_WARNING, phba->shost,
  2195. "No Virtual address\n");
  2196. pasync_ctx->async_header.va_base =
  2197. mem_descr->mem_array[0].virtual_address;
  2198. pasync_ctx->async_header.pa_base.u.a64.address =
  2199. mem_descr->mem_array[0].bus_address.u.a64.address;
  2200. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2201. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2202. if (mem_descr->mem_array[0].virtual_address) {
  2203. SE_DEBUG(DBG_LVL_8,
  2204. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_RING"
  2205. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2206. } else
  2207. shost_printk(KERN_WARNING, phba->shost,
  2208. "No Virtual address\n");
  2209. pasync_ctx->async_header.ring_base =
  2210. mem_descr->mem_array[0].virtual_address;
  2211. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2212. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2213. if (mem_descr->mem_array[0].virtual_address) {
  2214. SE_DEBUG(DBG_LVL_8,
  2215. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_HEADER_HANDLE"
  2216. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2217. } else
  2218. shost_printk(KERN_WARNING, phba->shost,
  2219. "No Virtual address\n");
  2220. pasync_ctx->async_header.handle_base =
  2221. mem_descr->mem_array[0].virtual_address;
  2222. pasync_ctx->async_header.writables = 0;
  2223. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2224. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2225. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2226. if (mem_descr->mem_array[0].virtual_address) {
  2227. SE_DEBUG(DBG_LVL_8,
  2228. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_RING"
  2229. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2230. } else
  2231. shost_printk(KERN_WARNING, phba->shost,
  2232. "No Virtual address\n");
  2233. pasync_ctx->async_data.ring_base =
  2234. mem_descr->mem_array[0].virtual_address;
  2235. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2236. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2237. if (!mem_descr->mem_array[0].virtual_address)
  2238. shost_printk(KERN_WARNING, phba->shost,
  2239. "No Virtual address\n");
  2240. pasync_ctx->async_data.handle_base =
  2241. mem_descr->mem_array[0].virtual_address;
  2242. pasync_ctx->async_data.writables = 0;
  2243. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2244. pasync_header_h =
  2245. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2246. pasync_data_h =
  2247. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2248. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2249. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2250. if (mem_descr->mem_array[0].virtual_address) {
  2251. SE_DEBUG(DBG_LVL_8,
  2252. "hwi_init_async_pdu_ctx HWI_MEM_ASYNC_DATA_BUF"
  2253. "va=%p\n", mem_descr->mem_array[0].virtual_address);
  2254. } else
  2255. shost_printk(KERN_WARNING, phba->shost,
  2256. "No Virtual address\n");
  2257. idx = 0;
  2258. pasync_ctx->async_data.va_base =
  2259. mem_descr->mem_array[idx].virtual_address;
  2260. pasync_ctx->async_data.pa_base.u.a64.address =
  2261. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2262. num_async_data = ((mem_descr->mem_array[idx].size) /
  2263. phba->params.defpdu_data_sz);
  2264. num_per_mem = 0;
  2265. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2266. pasync_header_h->cri = -1;
  2267. pasync_header_h->index = (char)index;
  2268. INIT_LIST_HEAD(&pasync_header_h->link);
  2269. pasync_header_h->pbuffer =
  2270. (void *)((unsigned long)
  2271. (pasync_ctx->async_header.va_base) +
  2272. (p->defpdu_hdr_sz * index));
  2273. pasync_header_h->pa.u.a64.address =
  2274. pasync_ctx->async_header.pa_base.u.a64.address +
  2275. (p->defpdu_hdr_sz * index);
  2276. list_add_tail(&pasync_header_h->link,
  2277. &pasync_ctx->async_header.free_list);
  2278. pasync_header_h++;
  2279. pasync_ctx->async_header.free_entries++;
  2280. pasync_ctx->async_header.writables++;
  2281. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2282. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2283. header_busy_list);
  2284. pasync_data_h->cri = -1;
  2285. pasync_data_h->index = (char)index;
  2286. INIT_LIST_HEAD(&pasync_data_h->link);
  2287. if (!num_async_data) {
  2288. num_per_mem = 0;
  2289. idx++;
  2290. pasync_ctx->async_data.va_base =
  2291. mem_descr->mem_array[idx].virtual_address;
  2292. pasync_ctx->async_data.pa_base.u.a64.address =
  2293. mem_descr->mem_array[idx].
  2294. bus_address.u.a64.address;
  2295. num_async_data = ((mem_descr->mem_array[idx].size) /
  2296. phba->params.defpdu_data_sz);
  2297. }
  2298. pasync_data_h->pbuffer =
  2299. (void *)((unsigned long)
  2300. (pasync_ctx->async_data.va_base) +
  2301. (p->defpdu_data_sz * num_per_mem));
  2302. pasync_data_h->pa.u.a64.address =
  2303. pasync_ctx->async_data.pa_base.u.a64.address +
  2304. (p->defpdu_data_sz * num_per_mem);
  2305. num_per_mem++;
  2306. num_async_data--;
  2307. list_add_tail(&pasync_data_h->link,
  2308. &pasync_ctx->async_data.free_list);
  2309. pasync_data_h++;
  2310. pasync_ctx->async_data.free_entries++;
  2311. pasync_ctx->async_data.writables++;
  2312. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2313. }
  2314. pasync_ctx->async_header.host_write_ptr = 0;
  2315. pasync_ctx->async_header.ep_read_ptr = -1;
  2316. pasync_ctx->async_data.host_write_ptr = 0;
  2317. pasync_ctx->async_data.ep_read_ptr = -1;
  2318. }
  2319. static int
  2320. be_sgl_create_contiguous(void *virtual_address,
  2321. u64 physical_address, u32 length,
  2322. struct be_dma_mem *sgl)
  2323. {
  2324. WARN_ON(!virtual_address);
  2325. WARN_ON(!physical_address);
  2326. WARN_ON(!length > 0);
  2327. WARN_ON(!sgl);
  2328. sgl->va = virtual_address;
  2329. sgl->dma = (unsigned long)physical_address;
  2330. sgl->size = length;
  2331. return 0;
  2332. }
  2333. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2334. {
  2335. memset(sgl, 0, sizeof(*sgl));
  2336. }
  2337. static void
  2338. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2339. struct mem_array *pmem, struct be_dma_mem *sgl)
  2340. {
  2341. if (sgl->va)
  2342. be_sgl_destroy_contiguous(sgl);
  2343. be_sgl_create_contiguous(pmem->virtual_address,
  2344. pmem->bus_address.u.a64.address,
  2345. pmem->size, sgl);
  2346. }
  2347. static void
  2348. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2349. struct mem_array *pmem, struct be_dma_mem *sgl)
  2350. {
  2351. if (sgl->va)
  2352. be_sgl_destroy_contiguous(sgl);
  2353. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2354. pmem->bus_address.u.a64.address,
  2355. pmem->size, sgl);
  2356. }
  2357. static int be_fill_queue(struct be_queue_info *q,
  2358. u16 len, u16 entry_size, void *vaddress)
  2359. {
  2360. struct be_dma_mem *mem = &q->dma_mem;
  2361. memset(q, 0, sizeof(*q));
  2362. q->len = len;
  2363. q->entry_size = entry_size;
  2364. mem->size = len * entry_size;
  2365. mem->va = vaddress;
  2366. if (!mem->va)
  2367. return -ENOMEM;
  2368. memset(mem->va, 0, mem->size);
  2369. return 0;
  2370. }
  2371. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2372. struct hwi_context_memory *phwi_context)
  2373. {
  2374. unsigned int i, num_eq_pages;
  2375. int ret, eq_for_mcc;
  2376. struct be_queue_info *eq;
  2377. struct be_dma_mem *mem;
  2378. void *eq_vaddress;
  2379. dma_addr_t paddr;
  2380. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2381. sizeof(struct be_eq_entry));
  2382. if (phba->msix_enabled)
  2383. eq_for_mcc = 1;
  2384. else
  2385. eq_for_mcc = 0;
  2386. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2387. eq = &phwi_context->be_eq[i].q;
  2388. mem = &eq->dma_mem;
  2389. phwi_context->be_eq[i].phba = phba;
  2390. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2391. num_eq_pages * PAGE_SIZE,
  2392. &paddr);
  2393. if (!eq_vaddress)
  2394. goto create_eq_error;
  2395. mem->va = eq_vaddress;
  2396. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2397. sizeof(struct be_eq_entry), eq_vaddress);
  2398. if (ret) {
  2399. shost_printk(KERN_ERR, phba->shost,
  2400. "be_fill_queue Failed for EQ\n");
  2401. goto create_eq_error;
  2402. }
  2403. mem->dma = paddr;
  2404. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2405. phwi_context->cur_eqd);
  2406. if (ret) {
  2407. shost_printk(KERN_ERR, phba->shost,
  2408. "beiscsi_cmd_eq_create"
  2409. "Failedfor EQ\n");
  2410. goto create_eq_error;
  2411. }
  2412. SE_DEBUG(DBG_LVL_8, "eqid = %d\n", phwi_context->be_eq[i].q.id);
  2413. }
  2414. return 0;
  2415. create_eq_error:
  2416. for (i = 0; i < (phba->num_cpus + 1); i++) {
  2417. eq = &phwi_context->be_eq[i].q;
  2418. mem = &eq->dma_mem;
  2419. if (mem->va)
  2420. pci_free_consistent(phba->pcidev, num_eq_pages
  2421. * PAGE_SIZE,
  2422. mem->va, mem->dma);
  2423. }
  2424. return ret;
  2425. }
  2426. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2427. struct hwi_context_memory *phwi_context)
  2428. {
  2429. unsigned int i, num_cq_pages;
  2430. int ret;
  2431. struct be_queue_info *cq, *eq;
  2432. struct be_dma_mem *mem;
  2433. struct be_eq_obj *pbe_eq;
  2434. void *cq_vaddress;
  2435. dma_addr_t paddr;
  2436. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2437. sizeof(struct sol_cqe));
  2438. for (i = 0; i < phba->num_cpus; i++) {
  2439. cq = &phwi_context->be_cq[i];
  2440. eq = &phwi_context->be_eq[i].q;
  2441. pbe_eq = &phwi_context->be_eq[i];
  2442. pbe_eq->cq = cq;
  2443. pbe_eq->phba = phba;
  2444. mem = &cq->dma_mem;
  2445. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2446. num_cq_pages * PAGE_SIZE,
  2447. &paddr);
  2448. if (!cq_vaddress)
  2449. goto create_cq_error;
  2450. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2451. sizeof(struct sol_cqe), cq_vaddress);
  2452. if (ret) {
  2453. shost_printk(KERN_ERR, phba->shost,
  2454. "be_fill_queue Failed for ISCSI CQ\n");
  2455. goto create_cq_error;
  2456. }
  2457. mem->dma = paddr;
  2458. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2459. false, 0);
  2460. if (ret) {
  2461. shost_printk(KERN_ERR, phba->shost,
  2462. "beiscsi_cmd_eq_create"
  2463. "Failed for ISCSI CQ\n");
  2464. goto create_cq_error;
  2465. }
  2466. SE_DEBUG(DBG_LVL_8, "iscsi cq_id is %d for eq_id %d\n",
  2467. cq->id, eq->id);
  2468. SE_DEBUG(DBG_LVL_8, "ISCSI CQ CREATED\n");
  2469. }
  2470. return 0;
  2471. create_cq_error:
  2472. for (i = 0; i < phba->num_cpus; i++) {
  2473. cq = &phwi_context->be_cq[i];
  2474. mem = &cq->dma_mem;
  2475. if (mem->va)
  2476. pci_free_consistent(phba->pcidev, num_cq_pages
  2477. * PAGE_SIZE,
  2478. mem->va, mem->dma);
  2479. }
  2480. return ret;
  2481. }
  2482. static int
  2483. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2484. struct hwi_context_memory *phwi_context,
  2485. struct hwi_controller *phwi_ctrlr,
  2486. unsigned int def_pdu_ring_sz)
  2487. {
  2488. unsigned int idx;
  2489. int ret;
  2490. struct be_queue_info *dq, *cq;
  2491. struct be_dma_mem *mem;
  2492. struct be_mem_descriptor *mem_descr;
  2493. void *dq_vaddress;
  2494. idx = 0;
  2495. dq = &phwi_context->be_def_hdrq;
  2496. cq = &phwi_context->be_cq[0];
  2497. mem = &dq->dma_mem;
  2498. mem_descr = phba->init_mem;
  2499. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2500. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2501. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2502. sizeof(struct phys_addr),
  2503. sizeof(struct phys_addr), dq_vaddress);
  2504. if (ret) {
  2505. shost_printk(KERN_ERR, phba->shost,
  2506. "be_fill_queue Failed for DEF PDU HDR\n");
  2507. return ret;
  2508. }
  2509. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2510. bus_address.u.a64.address;
  2511. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2512. def_pdu_ring_sz,
  2513. phba->params.defpdu_hdr_sz);
  2514. if (ret) {
  2515. shost_printk(KERN_ERR, phba->shost,
  2516. "be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2517. return ret;
  2518. }
  2519. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2520. SE_DEBUG(DBG_LVL_8, "iscsi def pdu id is %d\n",
  2521. phwi_context->be_def_hdrq.id);
  2522. hwi_post_async_buffers(phba, 1);
  2523. return 0;
  2524. }
  2525. static int
  2526. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2527. struct hwi_context_memory *phwi_context,
  2528. struct hwi_controller *phwi_ctrlr,
  2529. unsigned int def_pdu_ring_sz)
  2530. {
  2531. unsigned int idx;
  2532. int ret;
  2533. struct be_queue_info *dataq, *cq;
  2534. struct be_dma_mem *mem;
  2535. struct be_mem_descriptor *mem_descr;
  2536. void *dq_vaddress;
  2537. idx = 0;
  2538. dataq = &phwi_context->be_def_dataq;
  2539. cq = &phwi_context->be_cq[0];
  2540. mem = &dataq->dma_mem;
  2541. mem_descr = phba->init_mem;
  2542. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2543. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2544. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2545. sizeof(struct phys_addr),
  2546. sizeof(struct phys_addr), dq_vaddress);
  2547. if (ret) {
  2548. shost_printk(KERN_ERR, phba->shost,
  2549. "be_fill_queue Failed for DEF PDU DATA\n");
  2550. return ret;
  2551. }
  2552. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2553. bus_address.u.a64.address;
  2554. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2555. def_pdu_ring_sz,
  2556. phba->params.defpdu_data_sz);
  2557. if (ret) {
  2558. shost_printk(KERN_ERR, phba->shost,
  2559. "be_cmd_create_default_pdu_queue Failed"
  2560. " for DEF PDU DATA\n");
  2561. return ret;
  2562. }
  2563. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2564. SE_DEBUG(DBG_LVL_8, "iscsi def data id is %d\n",
  2565. phwi_context->be_def_dataq.id);
  2566. hwi_post_async_buffers(phba, 0);
  2567. SE_DEBUG(DBG_LVL_8, "DEFAULT PDU DATA RING CREATED\n");
  2568. return 0;
  2569. }
  2570. static int
  2571. beiscsi_post_pages(struct beiscsi_hba *phba)
  2572. {
  2573. struct be_mem_descriptor *mem_descr;
  2574. struct mem_array *pm_arr;
  2575. unsigned int page_offset, i;
  2576. struct be_dma_mem sgl;
  2577. int status;
  2578. mem_descr = phba->init_mem;
  2579. mem_descr += HWI_MEM_SGE;
  2580. pm_arr = mem_descr->mem_array;
  2581. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2582. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2583. for (i = 0; i < mem_descr->num_elements; i++) {
  2584. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2585. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2586. page_offset,
  2587. (pm_arr->size / PAGE_SIZE));
  2588. page_offset += pm_arr->size / PAGE_SIZE;
  2589. if (status != 0) {
  2590. shost_printk(KERN_ERR, phba->shost,
  2591. "post sgl failed.\n");
  2592. return status;
  2593. }
  2594. pm_arr++;
  2595. }
  2596. SE_DEBUG(DBG_LVL_8, "POSTED PAGES\n");
  2597. return 0;
  2598. }
  2599. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2600. {
  2601. struct be_dma_mem *mem = &q->dma_mem;
  2602. if (mem->va) {
  2603. pci_free_consistent(phba->pcidev, mem->size,
  2604. mem->va, mem->dma);
  2605. mem->va = NULL;
  2606. }
  2607. }
  2608. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2609. u16 len, u16 entry_size)
  2610. {
  2611. struct be_dma_mem *mem = &q->dma_mem;
  2612. memset(q, 0, sizeof(*q));
  2613. q->len = len;
  2614. q->entry_size = entry_size;
  2615. mem->size = len * entry_size;
  2616. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2617. if (!mem->va)
  2618. return -ENOMEM;
  2619. memset(mem->va, 0, mem->size);
  2620. return 0;
  2621. }
  2622. static int
  2623. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2624. struct hwi_context_memory *phwi_context,
  2625. struct hwi_controller *phwi_ctrlr)
  2626. {
  2627. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2628. u64 pa_addr_lo;
  2629. unsigned int idx, num, i;
  2630. struct mem_array *pwrb_arr;
  2631. void *wrb_vaddr;
  2632. struct be_dma_mem sgl;
  2633. struct be_mem_descriptor *mem_descr;
  2634. int status;
  2635. idx = 0;
  2636. mem_descr = phba->init_mem;
  2637. mem_descr += HWI_MEM_WRB;
  2638. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2639. GFP_KERNEL);
  2640. if (!pwrb_arr) {
  2641. shost_printk(KERN_ERR, phba->shost,
  2642. "Memory alloc failed in create wrb ring.\n");
  2643. return -ENOMEM;
  2644. }
  2645. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2646. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2647. num_wrb_rings = mem_descr->mem_array[idx].size /
  2648. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2649. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2650. if (num_wrb_rings) {
  2651. pwrb_arr[num].virtual_address = wrb_vaddr;
  2652. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2653. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2654. sizeof(struct iscsi_wrb);
  2655. wrb_vaddr += pwrb_arr[num].size;
  2656. pa_addr_lo += pwrb_arr[num].size;
  2657. num_wrb_rings--;
  2658. } else {
  2659. idx++;
  2660. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2661. pa_addr_lo = mem_descr->mem_array[idx].\
  2662. bus_address.u.a64.address;
  2663. num_wrb_rings = mem_descr->mem_array[idx].size /
  2664. (phba->params.wrbs_per_cxn *
  2665. sizeof(struct iscsi_wrb));
  2666. pwrb_arr[num].virtual_address = wrb_vaddr;
  2667. pwrb_arr[num].bus_address.u.a64.address\
  2668. = pa_addr_lo;
  2669. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2670. sizeof(struct iscsi_wrb);
  2671. wrb_vaddr += pwrb_arr[num].size;
  2672. pa_addr_lo += pwrb_arr[num].size;
  2673. num_wrb_rings--;
  2674. }
  2675. }
  2676. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2677. wrb_mem_index = 0;
  2678. offset = 0;
  2679. size = 0;
  2680. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2681. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2682. &phwi_context->be_wrbq[i]);
  2683. if (status != 0) {
  2684. shost_printk(KERN_ERR, phba->shost,
  2685. "wrbq create failed.");
  2686. kfree(pwrb_arr);
  2687. return status;
  2688. }
  2689. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2690. id;
  2691. }
  2692. kfree(pwrb_arr);
  2693. return 0;
  2694. }
  2695. static void free_wrb_handles(struct beiscsi_hba *phba)
  2696. {
  2697. unsigned int index;
  2698. struct hwi_controller *phwi_ctrlr;
  2699. struct hwi_wrb_context *pwrb_context;
  2700. phwi_ctrlr = phba->phwi_ctrlr;
  2701. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2702. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2703. kfree(pwrb_context->pwrb_handle_base);
  2704. kfree(pwrb_context->pwrb_handle_basestd);
  2705. }
  2706. }
  2707. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  2708. {
  2709. struct be_queue_info *q;
  2710. struct be_ctrl_info *ctrl = &phba->ctrl;
  2711. q = &phba->ctrl.mcc_obj.q;
  2712. if (q->created)
  2713. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  2714. be_queue_free(phba, q);
  2715. q = &phba->ctrl.mcc_obj.cq;
  2716. if (q->created)
  2717. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2718. be_queue_free(phba, q);
  2719. }
  2720. static void hwi_cleanup(struct beiscsi_hba *phba)
  2721. {
  2722. struct be_queue_info *q;
  2723. struct be_ctrl_info *ctrl = &phba->ctrl;
  2724. struct hwi_controller *phwi_ctrlr;
  2725. struct hwi_context_memory *phwi_context;
  2726. int i, eq_num;
  2727. phwi_ctrlr = phba->phwi_ctrlr;
  2728. phwi_context = phwi_ctrlr->phwi_ctxt;
  2729. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2730. q = &phwi_context->be_wrbq[i];
  2731. if (q->created)
  2732. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  2733. }
  2734. free_wrb_handles(phba);
  2735. q = &phwi_context->be_def_hdrq;
  2736. if (q->created)
  2737. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2738. q = &phwi_context->be_def_dataq;
  2739. if (q->created)
  2740. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2741. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  2742. for (i = 0; i < (phba->num_cpus); i++) {
  2743. q = &phwi_context->be_cq[i];
  2744. if (q->created)
  2745. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2746. }
  2747. if (phba->msix_enabled)
  2748. eq_num = 1;
  2749. else
  2750. eq_num = 0;
  2751. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  2752. q = &phwi_context->be_eq[i].q;
  2753. if (q->created)
  2754. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  2755. }
  2756. be_mcc_queues_destroy(phba);
  2757. }
  2758. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  2759. struct hwi_context_memory *phwi_context)
  2760. {
  2761. struct be_queue_info *q, *cq;
  2762. struct be_ctrl_info *ctrl = &phba->ctrl;
  2763. /* Alloc MCC compl queue */
  2764. cq = &phba->ctrl.mcc_obj.cq;
  2765. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  2766. sizeof(struct be_mcc_compl)))
  2767. goto err;
  2768. /* Ask BE to create MCC compl queue; */
  2769. if (phba->msix_enabled) {
  2770. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  2771. [phba->num_cpus].q, false, true, 0))
  2772. goto mcc_cq_free;
  2773. } else {
  2774. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  2775. false, true, 0))
  2776. goto mcc_cq_free;
  2777. }
  2778. /* Alloc MCC queue */
  2779. q = &phba->ctrl.mcc_obj.q;
  2780. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  2781. goto mcc_cq_destroy;
  2782. /* Ask BE to create MCC queue */
  2783. if (beiscsi_cmd_mccq_create(phba, q, cq))
  2784. goto mcc_q_free;
  2785. return 0;
  2786. mcc_q_free:
  2787. be_queue_free(phba, q);
  2788. mcc_cq_destroy:
  2789. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  2790. mcc_cq_free:
  2791. be_queue_free(phba, cq);
  2792. err:
  2793. return -ENOMEM;
  2794. }
  2795. static int find_num_cpus(void)
  2796. {
  2797. int num_cpus = 0;
  2798. num_cpus = num_online_cpus();
  2799. if (num_cpus >= MAX_CPUS)
  2800. num_cpus = MAX_CPUS - 1;
  2801. SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", num_cpus);
  2802. return num_cpus;
  2803. }
  2804. static int hwi_init_port(struct beiscsi_hba *phba)
  2805. {
  2806. struct hwi_controller *phwi_ctrlr;
  2807. struct hwi_context_memory *phwi_context;
  2808. unsigned int def_pdu_ring_sz;
  2809. struct be_ctrl_info *ctrl = &phba->ctrl;
  2810. int status;
  2811. def_pdu_ring_sz =
  2812. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  2813. phwi_ctrlr = phba->phwi_ctrlr;
  2814. phwi_context = phwi_ctrlr->phwi_ctxt;
  2815. phwi_context->max_eqd = 0;
  2816. phwi_context->min_eqd = 0;
  2817. phwi_context->cur_eqd = 64;
  2818. be_cmd_fw_initialize(&phba->ctrl);
  2819. status = beiscsi_create_eqs(phba, phwi_context);
  2820. if (status != 0) {
  2821. shost_printk(KERN_ERR, phba->shost, "EQ not created\n");
  2822. goto error;
  2823. }
  2824. status = be_mcc_queues_create(phba, phwi_context);
  2825. if (status != 0)
  2826. goto error;
  2827. status = mgmt_check_supported_fw(ctrl, phba);
  2828. if (status != 0) {
  2829. shost_printk(KERN_ERR, phba->shost,
  2830. "Unsupported fw version\n");
  2831. goto error;
  2832. }
  2833. status = beiscsi_create_cqs(phba, phwi_context);
  2834. if (status != 0) {
  2835. shost_printk(KERN_ERR, phba->shost, "CQ not created\n");
  2836. goto error;
  2837. }
  2838. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  2839. def_pdu_ring_sz);
  2840. if (status != 0) {
  2841. shost_printk(KERN_ERR, phba->shost,
  2842. "Default Header not created\n");
  2843. goto error;
  2844. }
  2845. status = beiscsi_create_def_data(phba, phwi_context,
  2846. phwi_ctrlr, def_pdu_ring_sz);
  2847. if (status != 0) {
  2848. shost_printk(KERN_ERR, phba->shost,
  2849. "Default Data not created\n");
  2850. goto error;
  2851. }
  2852. status = beiscsi_post_pages(phba);
  2853. if (status != 0) {
  2854. shost_printk(KERN_ERR, phba->shost, "Post SGL Pages Failed\n");
  2855. goto error;
  2856. }
  2857. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  2858. if (status != 0) {
  2859. shost_printk(KERN_ERR, phba->shost,
  2860. "WRB Rings not created\n");
  2861. goto error;
  2862. }
  2863. SE_DEBUG(DBG_LVL_8, "hwi_init_port success\n");
  2864. return 0;
  2865. error:
  2866. shost_printk(KERN_ERR, phba->shost, "hwi_init_port failed");
  2867. hwi_cleanup(phba);
  2868. return status;
  2869. }
  2870. static int hwi_init_controller(struct beiscsi_hba *phba)
  2871. {
  2872. struct hwi_controller *phwi_ctrlr;
  2873. phwi_ctrlr = phba->phwi_ctrlr;
  2874. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  2875. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  2876. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  2877. SE_DEBUG(DBG_LVL_8, " phwi_ctrlr->phwi_ctxt=%p\n",
  2878. phwi_ctrlr->phwi_ctxt);
  2879. } else {
  2880. shost_printk(KERN_ERR, phba->shost,
  2881. "HWI_MEM_ADDN_CONTEXT is more than one element."
  2882. "Failing to load\n");
  2883. return -ENOMEM;
  2884. }
  2885. iscsi_init_global_templates(phba);
  2886. if (beiscsi_init_wrb_handle(phba))
  2887. return -ENOMEM;
  2888. hwi_init_async_pdu_ctx(phba);
  2889. if (hwi_init_port(phba) != 0) {
  2890. shost_printk(KERN_ERR, phba->shost,
  2891. "hwi_init_controller failed\n");
  2892. return -ENOMEM;
  2893. }
  2894. return 0;
  2895. }
  2896. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  2897. {
  2898. struct be_mem_descriptor *mem_descr;
  2899. int i, j;
  2900. mem_descr = phba->init_mem;
  2901. i = 0;
  2902. j = 0;
  2903. for (i = 0; i < SE_MEM_MAX; i++) {
  2904. for (j = mem_descr->num_elements; j > 0; j--) {
  2905. pci_free_consistent(phba->pcidev,
  2906. mem_descr->mem_array[j - 1].size,
  2907. mem_descr->mem_array[j - 1].virtual_address,
  2908. (unsigned long)mem_descr->mem_array[j - 1].
  2909. bus_address.u.a64.address);
  2910. }
  2911. kfree(mem_descr->mem_array);
  2912. mem_descr++;
  2913. }
  2914. kfree(phba->init_mem);
  2915. kfree(phba->phwi_ctrlr);
  2916. }
  2917. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  2918. {
  2919. int ret = -ENOMEM;
  2920. ret = beiscsi_get_memory(phba);
  2921. if (ret < 0) {
  2922. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe -"
  2923. "Failed in beiscsi_alloc_memory\n");
  2924. return ret;
  2925. }
  2926. ret = hwi_init_controller(phba);
  2927. if (ret)
  2928. goto free_init;
  2929. SE_DEBUG(DBG_LVL_8, "Return success from beiscsi_init_controller");
  2930. return 0;
  2931. free_init:
  2932. beiscsi_free_mem(phba);
  2933. return ret;
  2934. }
  2935. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  2936. {
  2937. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  2938. struct sgl_handle *psgl_handle;
  2939. struct iscsi_sge *pfrag;
  2940. unsigned int arr_index, i, idx;
  2941. phba->io_sgl_hndl_avbl = 0;
  2942. phba->eh_sgl_hndl_avbl = 0;
  2943. mem_descr_sglh = phba->init_mem;
  2944. mem_descr_sglh += HWI_MEM_SGLH;
  2945. if (1 == mem_descr_sglh->num_elements) {
  2946. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  2947. phba->params.ios_per_ctrl,
  2948. GFP_KERNEL);
  2949. if (!phba->io_sgl_hndl_base) {
  2950. shost_printk(KERN_ERR, phba->shost,
  2951. "Mem Alloc Failed. Failing to load\n");
  2952. return -ENOMEM;
  2953. }
  2954. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  2955. (phba->params.icds_per_ctrl -
  2956. phba->params.ios_per_ctrl),
  2957. GFP_KERNEL);
  2958. if (!phba->eh_sgl_hndl_base) {
  2959. kfree(phba->io_sgl_hndl_base);
  2960. shost_printk(KERN_ERR, phba->shost,
  2961. "Mem Alloc Failed. Failing to load\n");
  2962. return -ENOMEM;
  2963. }
  2964. } else {
  2965. shost_printk(KERN_ERR, phba->shost,
  2966. "HWI_MEM_SGLH is more than one element."
  2967. "Failing to load\n");
  2968. return -ENOMEM;
  2969. }
  2970. arr_index = 0;
  2971. idx = 0;
  2972. while (idx < mem_descr_sglh->num_elements) {
  2973. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  2974. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  2975. sizeof(struct sgl_handle)); i++) {
  2976. if (arr_index < phba->params.ios_per_ctrl) {
  2977. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  2978. phba->io_sgl_hndl_avbl++;
  2979. arr_index++;
  2980. } else {
  2981. phba->eh_sgl_hndl_base[arr_index -
  2982. phba->params.ios_per_ctrl] =
  2983. psgl_handle;
  2984. arr_index++;
  2985. phba->eh_sgl_hndl_avbl++;
  2986. }
  2987. psgl_handle++;
  2988. }
  2989. idx++;
  2990. }
  2991. SE_DEBUG(DBG_LVL_8,
  2992. "phba->io_sgl_hndl_avbl=%d"
  2993. "phba->eh_sgl_hndl_avbl=%d\n",
  2994. phba->io_sgl_hndl_avbl,
  2995. phba->eh_sgl_hndl_avbl);
  2996. mem_descr_sg = phba->init_mem;
  2997. mem_descr_sg += HWI_MEM_SGE;
  2998. SE_DEBUG(DBG_LVL_8, "\n mem_descr_sg->num_elements=%d\n",
  2999. mem_descr_sg->num_elements);
  3000. arr_index = 0;
  3001. idx = 0;
  3002. while (idx < mem_descr_sg->num_elements) {
  3003. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3004. for (i = 0;
  3005. i < (mem_descr_sg->mem_array[idx].size) /
  3006. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3007. i++) {
  3008. if (arr_index < phba->params.ios_per_ctrl)
  3009. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3010. else
  3011. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3012. phba->params.ios_per_ctrl];
  3013. psgl_handle->pfrag = pfrag;
  3014. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3015. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3016. pfrag += phba->params.num_sge_per_io;
  3017. psgl_handle->sgl_index =
  3018. phba->fw_config.iscsi_icd_start + arr_index++;
  3019. }
  3020. idx++;
  3021. }
  3022. phba->io_sgl_free_index = 0;
  3023. phba->io_sgl_alloc_index = 0;
  3024. phba->eh_sgl_free_index = 0;
  3025. phba->eh_sgl_alloc_index = 0;
  3026. return 0;
  3027. }
  3028. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3029. {
  3030. int i, new_cid;
  3031. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3032. GFP_KERNEL);
  3033. if (!phba->cid_array) {
  3034. shost_printk(KERN_ERR, phba->shost,
  3035. "Failed to allocate memory in "
  3036. "hba_setup_cid_tbls\n");
  3037. return -ENOMEM;
  3038. }
  3039. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3040. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3041. if (!phba->ep_array) {
  3042. shost_printk(KERN_ERR, phba->shost,
  3043. "Failed to allocate memory in "
  3044. "hba_setup_cid_tbls\n");
  3045. kfree(phba->cid_array);
  3046. return -ENOMEM;
  3047. }
  3048. new_cid = phba->fw_config.iscsi_cid_start;
  3049. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3050. phba->cid_array[i] = new_cid;
  3051. new_cid += 2;
  3052. }
  3053. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3054. return 0;
  3055. }
  3056. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3057. {
  3058. struct be_ctrl_info *ctrl = &phba->ctrl;
  3059. struct hwi_controller *phwi_ctrlr;
  3060. struct hwi_context_memory *phwi_context;
  3061. struct be_queue_info *eq;
  3062. u8 __iomem *addr;
  3063. u32 reg, i;
  3064. u32 enabled;
  3065. phwi_ctrlr = phba->phwi_ctrlr;
  3066. phwi_context = phwi_ctrlr->phwi_ctxt;
  3067. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3068. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3069. reg = ioread32(addr);
  3070. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3071. if (!enabled) {
  3072. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3073. SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr);
  3074. iowrite32(reg, addr);
  3075. }
  3076. if (!phba->msix_enabled) {
  3077. eq = &phwi_context->be_eq[0].q;
  3078. SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
  3079. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3080. } else {
  3081. for (i = 0; i <= phba->num_cpus; i++) {
  3082. eq = &phwi_context->be_eq[i].q;
  3083. SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
  3084. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3085. }
  3086. }
  3087. }
  3088. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3089. {
  3090. struct be_ctrl_info *ctrl = &phba->ctrl;
  3091. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3092. u32 reg = ioread32(addr);
  3093. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3094. if (enabled) {
  3095. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3096. iowrite32(reg, addr);
  3097. } else
  3098. shost_printk(KERN_WARNING, phba->shost,
  3099. "In hwi_disable_intr, Already Disabled\n");
  3100. }
  3101. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3102. {
  3103. struct be_cmd_resp_get_boot_target *boot_resp;
  3104. struct be_cmd_resp_get_session *session_resp;
  3105. struct be_mcc_wrb *wrb;
  3106. struct be_dma_mem nonemb_cmd;
  3107. unsigned int tag, wrb_num;
  3108. unsigned short status, extd_status;
  3109. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3110. int ret = -ENOMEM;
  3111. tag = beiscsi_get_boot_target(phba);
  3112. if (!tag) {
  3113. SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed\n");
  3114. return -EAGAIN;
  3115. } else
  3116. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3117. phba->ctrl.mcc_numtag[tag]);
  3118. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3119. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3120. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3121. if (status || extd_status) {
  3122. SE_DEBUG(DBG_LVL_1, "be_cmd_get_mac_addr Failed"
  3123. " status = %d extd_status = %d\n",
  3124. status, extd_status);
  3125. free_mcc_tag(&phba->ctrl, tag);
  3126. return -EBUSY;
  3127. }
  3128. wrb = queue_get_wrb(mccq, wrb_num);
  3129. free_mcc_tag(&phba->ctrl, tag);
  3130. boot_resp = embedded_payload(wrb);
  3131. if (boot_resp->boot_session_handle < 0) {
  3132. shost_printk(KERN_INFO, phba->shost, "No Boot Session.\n");
  3133. return -ENXIO;
  3134. }
  3135. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3136. sizeof(*session_resp),
  3137. &nonemb_cmd.dma);
  3138. if (nonemb_cmd.va == NULL) {
  3139. SE_DEBUG(DBG_LVL_1,
  3140. "Failed to allocate memory for"
  3141. "beiscsi_get_session_info\n");
  3142. return -ENOMEM;
  3143. }
  3144. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3145. tag = beiscsi_get_session_info(phba,
  3146. boot_resp->boot_session_handle, &nonemb_cmd);
  3147. if (!tag) {
  3148. SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info"
  3149. " Failed\n");
  3150. goto boot_freemem;
  3151. } else
  3152. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3153. phba->ctrl.mcc_numtag[tag]);
  3154. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3155. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3156. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3157. if (status || extd_status) {
  3158. SE_DEBUG(DBG_LVL_1, "beiscsi_get_session_info Failed"
  3159. " status = %d extd_status = %d\n",
  3160. status, extd_status);
  3161. free_mcc_tag(&phba->ctrl, tag);
  3162. goto boot_freemem;
  3163. }
  3164. wrb = queue_get_wrb(mccq, wrb_num);
  3165. free_mcc_tag(&phba->ctrl, tag);
  3166. session_resp = nonemb_cmd.va ;
  3167. memcpy(&phba->boot_sess, &session_resp->session_info,
  3168. sizeof(struct mgmt_session_info));
  3169. ret = 0;
  3170. boot_freemem:
  3171. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3172. nonemb_cmd.va, nonemb_cmd.dma);
  3173. return ret;
  3174. }
  3175. static void beiscsi_boot_release(void *data)
  3176. {
  3177. struct beiscsi_hba *phba = data;
  3178. scsi_host_put(phba->shost);
  3179. }
  3180. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3181. {
  3182. struct iscsi_boot_kobj *boot_kobj;
  3183. /* get boot info using mgmt cmd */
  3184. if (beiscsi_get_boot_info(phba))
  3185. /* Try to see if we can carry on without this */
  3186. return 0;
  3187. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3188. if (!phba->boot_kset)
  3189. return -ENOMEM;
  3190. /* get a ref because the show function will ref the phba */
  3191. if (!scsi_host_get(phba->shost))
  3192. goto free_kset;
  3193. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3194. beiscsi_show_boot_tgt_info,
  3195. beiscsi_tgt_get_attr_visibility,
  3196. beiscsi_boot_release);
  3197. if (!boot_kobj)
  3198. goto put_shost;
  3199. if (!scsi_host_get(phba->shost))
  3200. goto free_kset;
  3201. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3202. beiscsi_show_boot_ini_info,
  3203. beiscsi_ini_get_attr_visibility,
  3204. beiscsi_boot_release);
  3205. if (!boot_kobj)
  3206. goto put_shost;
  3207. if (!scsi_host_get(phba->shost))
  3208. goto free_kset;
  3209. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3210. beiscsi_show_boot_eth_info,
  3211. beiscsi_eth_get_attr_visibility,
  3212. beiscsi_boot_release);
  3213. if (!boot_kobj)
  3214. goto put_shost;
  3215. return 0;
  3216. put_shost:
  3217. scsi_host_put(phba->shost);
  3218. free_kset:
  3219. iscsi_boot_destroy_kset(phba->boot_kset);
  3220. return -ENOMEM;
  3221. }
  3222. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3223. {
  3224. int ret;
  3225. ret = beiscsi_init_controller(phba);
  3226. if (ret < 0) {
  3227. shost_printk(KERN_ERR, phba->shost,
  3228. "beiscsi_dev_probe - Failed in"
  3229. "beiscsi_init_controller\n");
  3230. return ret;
  3231. }
  3232. ret = beiscsi_init_sgl_handle(phba);
  3233. if (ret < 0) {
  3234. shost_printk(KERN_ERR, phba->shost,
  3235. "beiscsi_dev_probe - Failed in"
  3236. "beiscsi_init_sgl_handle\n");
  3237. goto do_cleanup_ctrlr;
  3238. }
  3239. if (hba_setup_cid_tbls(phba)) {
  3240. shost_printk(KERN_ERR, phba->shost,
  3241. "Failed in hba_setup_cid_tbls\n");
  3242. kfree(phba->io_sgl_hndl_base);
  3243. kfree(phba->eh_sgl_hndl_base);
  3244. goto do_cleanup_ctrlr;
  3245. }
  3246. return ret;
  3247. do_cleanup_ctrlr:
  3248. hwi_cleanup(phba);
  3249. return ret;
  3250. }
  3251. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3252. {
  3253. struct hwi_controller *phwi_ctrlr;
  3254. struct hwi_context_memory *phwi_context;
  3255. struct be_queue_info *eq;
  3256. struct be_eq_entry *eqe = NULL;
  3257. int i, eq_msix;
  3258. unsigned int num_processed;
  3259. phwi_ctrlr = phba->phwi_ctrlr;
  3260. phwi_context = phwi_ctrlr->phwi_ctxt;
  3261. if (phba->msix_enabled)
  3262. eq_msix = 1;
  3263. else
  3264. eq_msix = 0;
  3265. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3266. eq = &phwi_context->be_eq[i].q;
  3267. eqe = queue_tail_node(eq);
  3268. num_processed = 0;
  3269. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3270. & EQE_VALID_MASK) {
  3271. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3272. queue_tail_inc(eq);
  3273. eqe = queue_tail_node(eq);
  3274. num_processed++;
  3275. }
  3276. if (num_processed)
  3277. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3278. }
  3279. }
  3280. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3281. {
  3282. int mgmt_status;
  3283. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3284. if (mgmt_status)
  3285. shost_printk(KERN_WARNING, phba->shost,
  3286. "mgmt_epfw_cleanup FAILED\n");
  3287. hwi_purge_eq(phba);
  3288. hwi_cleanup(phba);
  3289. kfree(phba->io_sgl_hndl_base);
  3290. kfree(phba->eh_sgl_hndl_base);
  3291. kfree(phba->cid_array);
  3292. kfree(phba->ep_array);
  3293. }
  3294. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3295. {
  3296. struct beiscsi_io_task *io_task = task->dd_data;
  3297. struct iscsi_conn *conn = task->conn;
  3298. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3299. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3300. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3301. struct hwi_wrb_context *pwrb_context;
  3302. struct hwi_controller *phwi_ctrlr;
  3303. phwi_ctrlr = phba->phwi_ctrlr;
  3304. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3305. - phba->fw_config.iscsi_cid_start];
  3306. if (io_task->cmd_bhs) {
  3307. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3308. io_task->bhs_pa.u.a64.address);
  3309. io_task->cmd_bhs = NULL;
  3310. }
  3311. if (task->sc) {
  3312. if (io_task->pwrb_handle) {
  3313. free_wrb_handle(phba, pwrb_context,
  3314. io_task->pwrb_handle);
  3315. io_task->pwrb_handle = NULL;
  3316. }
  3317. if (io_task->psgl_handle) {
  3318. spin_lock(&phba->io_sgl_lock);
  3319. free_io_sgl_handle(phba, io_task->psgl_handle);
  3320. spin_unlock(&phba->io_sgl_lock);
  3321. io_task->psgl_handle = NULL;
  3322. }
  3323. } else {
  3324. if (!beiscsi_conn->login_in_progress) {
  3325. if (io_task->pwrb_handle) {
  3326. free_wrb_handle(phba, pwrb_context,
  3327. io_task->pwrb_handle);
  3328. io_task->pwrb_handle = NULL;
  3329. }
  3330. if (io_task->psgl_handle) {
  3331. spin_lock(&phba->mgmt_sgl_lock);
  3332. free_mgmt_sgl_handle(phba,
  3333. io_task->psgl_handle);
  3334. spin_unlock(&phba->mgmt_sgl_lock);
  3335. io_task->psgl_handle = NULL;
  3336. }
  3337. }
  3338. }
  3339. }
  3340. void
  3341. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3342. struct beiscsi_offload_params *params)
  3343. {
  3344. struct wrb_handle *pwrb_handle;
  3345. struct iscsi_target_context_update_wrb *pwrb = NULL;
  3346. struct be_mem_descriptor *mem_descr;
  3347. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3348. struct iscsi_task *task = beiscsi_conn->task;
  3349. struct iscsi_session *session = task->conn->session;
  3350. u32 doorbell = 0;
  3351. /*
  3352. * We can always use 0 here because it is reserved by libiscsi for
  3353. * login/startup related tasks.
  3354. */
  3355. beiscsi_conn->login_in_progress = 0;
  3356. spin_lock_bh(&session->lock);
  3357. beiscsi_cleanup_task(task);
  3358. spin_unlock_bh(&session->lock);
  3359. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3360. phba->fw_config.iscsi_cid_start));
  3361. pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
  3362. memset(pwrb, 0, sizeof(*pwrb));
  3363. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3364. max_burst_length, pwrb, params->dw[offsetof
  3365. (struct amap_beiscsi_offload_params,
  3366. max_burst_length) / 32]);
  3367. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3368. max_send_data_segment_length, pwrb,
  3369. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3370. max_send_data_segment_length) / 32]);
  3371. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3372. first_burst_length,
  3373. pwrb,
  3374. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3375. first_burst_length) / 32]);
  3376. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
  3377. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3378. erl) / 32] & OFFLD_PARAMS_ERL));
  3379. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
  3380. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3381. dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
  3382. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
  3383. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3384. hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
  3385. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
  3386. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3387. ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
  3388. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
  3389. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3390. imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
  3391. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
  3392. pwrb,
  3393. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3394. exp_statsn) / 32] + 1));
  3395. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
  3396. 0x7);
  3397. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
  3398. pwrb, pwrb_handle->wrb_index);
  3399. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
  3400. pwrb, pwrb_handle->nxt_wrb_index);
  3401. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3402. session_state, pwrb, 0);
  3403. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
  3404. pwrb, 1);
  3405. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
  3406. pwrb, 0);
  3407. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
  3408. 0);
  3409. mem_descr = phba->init_mem;
  3410. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  3411. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3412. pad_buffer_addr_hi, pwrb,
  3413. mem_descr->mem_array[0].bus_address.u.a32.address_hi);
  3414. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3415. pad_buffer_addr_lo, pwrb,
  3416. mem_descr->mem_array[0].bus_address.u.a32.address_lo);
  3417. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
  3418. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3419. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3420. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3421. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3422. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3423. }
  3424. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3425. int *index, int *age)
  3426. {
  3427. *index = (int)itt;
  3428. if (age)
  3429. *age = conn->session->age;
  3430. }
  3431. /**
  3432. * beiscsi_alloc_pdu - allocates pdu and related resources
  3433. * @task: libiscsi task
  3434. * @opcode: opcode of pdu for task
  3435. *
  3436. * This is called with the session lock held. It will allocate
  3437. * the wrb and sgl if needed for the command. And it will prep
  3438. * the pdu's itt. beiscsi_parse_pdu will later translate
  3439. * the pdu itt to the libiscsi task itt.
  3440. */
  3441. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3442. {
  3443. struct beiscsi_io_task *io_task = task->dd_data;
  3444. struct iscsi_conn *conn = task->conn;
  3445. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3446. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3447. struct hwi_wrb_context *pwrb_context;
  3448. struct hwi_controller *phwi_ctrlr;
  3449. itt_t itt;
  3450. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3451. dma_addr_t paddr;
  3452. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3453. GFP_ATOMIC, &paddr);
  3454. if (!io_task->cmd_bhs)
  3455. return -ENOMEM;
  3456. io_task->bhs_pa.u.a64.address = paddr;
  3457. io_task->libiscsi_itt = (itt_t)task->itt;
  3458. io_task->conn = beiscsi_conn;
  3459. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3460. task->hdr_max = sizeof(struct be_cmd_bhs);
  3461. io_task->psgl_handle = NULL;
  3462. io_task->pwrb_handle = NULL;
  3463. if (task->sc) {
  3464. spin_lock(&phba->io_sgl_lock);
  3465. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3466. spin_unlock(&phba->io_sgl_lock);
  3467. if (!io_task->psgl_handle)
  3468. goto free_hndls;
  3469. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3470. beiscsi_conn->beiscsi_conn_cid -
  3471. phba->fw_config.iscsi_cid_start);
  3472. if (!io_task->pwrb_handle)
  3473. goto free_io_hndls;
  3474. } else {
  3475. io_task->scsi_cmnd = NULL;
  3476. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3477. if (!beiscsi_conn->login_in_progress) {
  3478. spin_lock(&phba->mgmt_sgl_lock);
  3479. io_task->psgl_handle = (struct sgl_handle *)
  3480. alloc_mgmt_sgl_handle(phba);
  3481. spin_unlock(&phba->mgmt_sgl_lock);
  3482. if (!io_task->psgl_handle)
  3483. goto free_hndls;
  3484. beiscsi_conn->login_in_progress = 1;
  3485. beiscsi_conn->plogin_sgl_handle =
  3486. io_task->psgl_handle;
  3487. io_task->pwrb_handle =
  3488. alloc_wrb_handle(phba,
  3489. beiscsi_conn->beiscsi_conn_cid -
  3490. phba->fw_config.iscsi_cid_start);
  3491. if (!io_task->pwrb_handle)
  3492. goto free_io_hndls;
  3493. beiscsi_conn->plogin_wrb_handle =
  3494. io_task->pwrb_handle;
  3495. } else {
  3496. io_task->psgl_handle =
  3497. beiscsi_conn->plogin_sgl_handle;
  3498. io_task->pwrb_handle =
  3499. beiscsi_conn->plogin_wrb_handle;
  3500. }
  3501. beiscsi_conn->task = task;
  3502. } else {
  3503. spin_lock(&phba->mgmt_sgl_lock);
  3504. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3505. spin_unlock(&phba->mgmt_sgl_lock);
  3506. if (!io_task->psgl_handle)
  3507. goto free_hndls;
  3508. io_task->pwrb_handle =
  3509. alloc_wrb_handle(phba,
  3510. beiscsi_conn->beiscsi_conn_cid -
  3511. phba->fw_config.iscsi_cid_start);
  3512. if (!io_task->pwrb_handle)
  3513. goto free_mgmt_hndls;
  3514. }
  3515. }
  3516. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3517. wrb_index << 16) | (unsigned int)
  3518. (io_task->psgl_handle->sgl_index));
  3519. io_task->pwrb_handle->pio_handle = task;
  3520. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3521. return 0;
  3522. free_io_hndls:
  3523. spin_lock(&phba->io_sgl_lock);
  3524. free_io_sgl_handle(phba, io_task->psgl_handle);
  3525. spin_unlock(&phba->io_sgl_lock);
  3526. goto free_hndls;
  3527. free_mgmt_hndls:
  3528. spin_lock(&phba->mgmt_sgl_lock);
  3529. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3530. spin_unlock(&phba->mgmt_sgl_lock);
  3531. free_hndls:
  3532. phwi_ctrlr = phba->phwi_ctrlr;
  3533. pwrb_context = &phwi_ctrlr->wrb_context[
  3534. beiscsi_conn->beiscsi_conn_cid -
  3535. phba->fw_config.iscsi_cid_start];
  3536. if (io_task->pwrb_handle)
  3537. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3538. io_task->pwrb_handle = NULL;
  3539. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3540. io_task->bhs_pa.u.a64.address);
  3541. io_task->cmd_bhs = NULL;
  3542. SE_DEBUG(DBG_LVL_1, "Alloc of SGL_ICD Failed\n");
  3543. return -ENOMEM;
  3544. }
  3545. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3546. unsigned int num_sg, unsigned int xferlen,
  3547. unsigned int writedir)
  3548. {
  3549. struct beiscsi_io_task *io_task = task->dd_data;
  3550. struct iscsi_conn *conn = task->conn;
  3551. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3552. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3553. struct iscsi_wrb *pwrb = NULL;
  3554. unsigned int doorbell = 0;
  3555. pwrb = io_task->pwrb_handle->pwrb;
  3556. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3557. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3558. if (writedir) {
  3559. memset(&io_task->cmd_bhs->iscsi_data_pdu, 0, 48);
  3560. AMAP_SET_BITS(struct amap_pdu_data_out, itt,
  3561. &io_task->cmd_bhs->iscsi_data_pdu,
  3562. (unsigned int)io_task->cmd_bhs->iscsi_hdr.itt);
  3563. AMAP_SET_BITS(struct amap_pdu_data_out, opcode,
  3564. &io_task->cmd_bhs->iscsi_data_pdu,
  3565. ISCSI_OPCODE_SCSI_DATA_OUT);
  3566. AMAP_SET_BITS(struct amap_pdu_data_out, final_bit,
  3567. &io_task->cmd_bhs->iscsi_data_pdu, 1);
  3568. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3569. INI_WR_CMD);
  3570. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3571. } else {
  3572. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3573. INI_RD_CMD);
  3574. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3575. }
  3576. memcpy(&io_task->cmd_bhs->iscsi_data_pdu.
  3577. dw[offsetof(struct amap_pdu_data_out, lun) / 32],
  3578. &io_task->cmd_bhs->iscsi_hdr.lun, sizeof(struct scsi_lun));
  3579. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3580. cpu_to_be16(*(unsigned short *)
  3581. &io_task->cmd_bhs->iscsi_hdr.lun));
  3582. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3583. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3584. io_task->pwrb_handle->wrb_index);
  3585. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3586. be32_to_cpu(task->cmdsn));
  3587. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3588. io_task->psgl_handle->sgl_index);
  3589. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3590. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3591. io_task->pwrb_handle->nxt_wrb_index);
  3592. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3593. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3594. doorbell |= (io_task->pwrb_handle->wrb_index &
  3595. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3596. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3597. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3598. return 0;
  3599. }
  3600. static int beiscsi_mtask(struct iscsi_task *task)
  3601. {
  3602. struct beiscsi_io_task *io_task = task->dd_data;
  3603. struct iscsi_conn *conn = task->conn;
  3604. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3605. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3606. struct iscsi_wrb *pwrb = NULL;
  3607. unsigned int doorbell = 0;
  3608. unsigned int cid;
  3609. cid = beiscsi_conn->beiscsi_conn_cid;
  3610. pwrb = io_task->pwrb_handle->pwrb;
  3611. memset(pwrb, 0, sizeof(*pwrb));
  3612. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3613. be32_to_cpu(task->cmdsn));
  3614. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3615. io_task->pwrb_handle->wrb_index);
  3616. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3617. io_task->psgl_handle->sgl_index);
  3618. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3619. case ISCSI_OP_LOGIN:
  3620. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3621. TGT_DM_CMD);
  3622. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3623. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  3624. hwi_write_buffer(pwrb, task);
  3625. break;
  3626. case ISCSI_OP_NOOP_OUT:
  3627. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  3628. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3629. TGT_DM_CMD);
  3630. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
  3631. pwrb, 0);
  3632. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
  3633. } else {
  3634. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3635. INI_RD_CMD);
  3636. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3637. }
  3638. hwi_write_buffer(pwrb, task);
  3639. break;
  3640. case ISCSI_OP_TEXT:
  3641. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3642. TGT_DM_CMD);
  3643. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3644. hwi_write_buffer(pwrb, task);
  3645. break;
  3646. case ISCSI_OP_SCSI_TMFUNC:
  3647. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3648. INI_TMF_CMD);
  3649. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3650. hwi_write_buffer(pwrb, task);
  3651. break;
  3652. case ISCSI_OP_LOGOUT:
  3653. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3654. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3655. HWH_TYPE_LOGOUT);
  3656. hwi_write_buffer(pwrb, task);
  3657. break;
  3658. default:
  3659. SE_DEBUG(DBG_LVL_1, "opcode =%d Not supported\n",
  3660. task->hdr->opcode & ISCSI_OPCODE_MASK);
  3661. return -EINVAL;
  3662. }
  3663. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3664. task->data_count);
  3665. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3666. io_task->pwrb_handle->nxt_wrb_index);
  3667. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3668. doorbell |= cid & DB_WRB_POST_CID_MASK;
  3669. doorbell |= (io_task->pwrb_handle->wrb_index &
  3670. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3671. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3672. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3673. return 0;
  3674. }
  3675. static int beiscsi_task_xmit(struct iscsi_task *task)
  3676. {
  3677. struct beiscsi_io_task *io_task = task->dd_data;
  3678. struct scsi_cmnd *sc = task->sc;
  3679. struct scatterlist *sg;
  3680. int num_sg;
  3681. unsigned int writedir = 0, xferlen = 0;
  3682. if (!sc)
  3683. return beiscsi_mtask(task);
  3684. io_task->scsi_cmnd = sc;
  3685. num_sg = scsi_dma_map(sc);
  3686. if (num_sg < 0) {
  3687. SE_DEBUG(DBG_LVL_1, " scsi_dma_map Failed\n")
  3688. return num_sg;
  3689. }
  3690. xferlen = scsi_bufflen(sc);
  3691. sg = scsi_sglist(sc);
  3692. if (sc->sc_data_direction == DMA_TO_DEVICE) {
  3693. writedir = 1;
  3694. SE_DEBUG(DBG_LVL_4, "task->imm_count=0x%08x\n",
  3695. task->imm_count);
  3696. } else
  3697. writedir = 0;
  3698. return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
  3699. }
  3700. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  3701. {
  3702. struct hwi_controller *phwi_ctrlr;
  3703. struct hwi_context_memory *phwi_context;
  3704. struct be_eq_obj *pbe_eq;
  3705. unsigned int i, msix_vec;
  3706. u8 *real_offset = 0;
  3707. u32 value = 0;
  3708. phwi_ctrlr = phba->phwi_ctrlr;
  3709. phwi_context = phwi_ctrlr->phwi_ctxt;
  3710. hwi_disable_intr(phba);
  3711. if (phba->msix_enabled) {
  3712. for (i = 0; i <= phba->num_cpus; i++) {
  3713. msix_vec = phba->msix_entries[i].vector;
  3714. free_irq(msix_vec, &phwi_context->be_eq[i]);
  3715. kfree(phba->msi_name[i]);
  3716. }
  3717. } else
  3718. if (phba->pcidev->irq)
  3719. free_irq(phba->pcidev->irq, phba);
  3720. pci_disable_msix(phba->pcidev);
  3721. destroy_workqueue(phba->wq);
  3722. if (blk_iopoll_enabled)
  3723. for (i = 0; i < phba->num_cpus; i++) {
  3724. pbe_eq = &phwi_context->be_eq[i];
  3725. blk_iopoll_disable(&pbe_eq->iopoll);
  3726. }
  3727. beiscsi_clean_port(phba);
  3728. beiscsi_free_mem(phba);
  3729. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3730. value = readl((void *)real_offset);
  3731. if (value & 0x00010000) {
  3732. value &= 0xfffeffff;
  3733. writel(value, (void *)real_offset);
  3734. }
  3735. beiscsi_unmap_pci_function(phba);
  3736. pci_free_consistent(phba->pcidev,
  3737. phba->ctrl.mbox_mem_alloced.size,
  3738. phba->ctrl.mbox_mem_alloced.va,
  3739. phba->ctrl.mbox_mem_alloced.dma);
  3740. }
  3741. static void beiscsi_remove(struct pci_dev *pcidev)
  3742. {
  3743. struct beiscsi_hba *phba = NULL;
  3744. phba = pci_get_drvdata(pcidev);
  3745. if (!phba) {
  3746. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  3747. return;
  3748. }
  3749. beiscsi_quiesce(phba);
  3750. iscsi_boot_destroy_kset(phba->boot_kset);
  3751. iscsi_host_remove(phba->shost);
  3752. pci_dev_put(phba->pcidev);
  3753. iscsi_host_free(phba->shost);
  3754. pci_disable_device(pcidev);
  3755. }
  3756. static void beiscsi_shutdown(struct pci_dev *pcidev)
  3757. {
  3758. struct beiscsi_hba *phba = NULL;
  3759. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  3760. if (!phba) {
  3761. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  3762. return;
  3763. }
  3764. beiscsi_quiesce(phba);
  3765. pci_disable_device(pcidev);
  3766. }
  3767. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  3768. {
  3769. int i, status;
  3770. for (i = 0; i <= phba->num_cpus; i++)
  3771. phba->msix_entries[i].entry = i;
  3772. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  3773. (phba->num_cpus + 1));
  3774. if (!status)
  3775. phba->msix_enabled = true;
  3776. return;
  3777. }
  3778. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  3779. const struct pci_device_id *id)
  3780. {
  3781. struct beiscsi_hba *phba = NULL;
  3782. struct hwi_controller *phwi_ctrlr;
  3783. struct hwi_context_memory *phwi_context;
  3784. struct be_eq_obj *pbe_eq;
  3785. int ret, num_cpus, i;
  3786. u8 *real_offset = 0;
  3787. u32 value = 0;
  3788. ret = beiscsi_enable_pci(pcidev);
  3789. if (ret < 0) {
  3790. dev_err(&pcidev->dev, "beiscsi_dev_probe-"
  3791. " Failed to enable pci device\n");
  3792. return ret;
  3793. }
  3794. phba = beiscsi_hba_alloc(pcidev);
  3795. if (!phba) {
  3796. dev_err(&pcidev->dev, "beiscsi_dev_probe-"
  3797. " Failed in beiscsi_hba_alloc\n");
  3798. goto disable_pci;
  3799. }
  3800. switch (pcidev->device) {
  3801. case BE_DEVICE_ID1:
  3802. case OC_DEVICE_ID1:
  3803. case OC_DEVICE_ID2:
  3804. phba->generation = BE_GEN2;
  3805. break;
  3806. case BE_DEVICE_ID2:
  3807. case OC_DEVICE_ID3:
  3808. phba->generation = BE_GEN3;
  3809. break;
  3810. default:
  3811. phba->generation = 0;
  3812. }
  3813. if (enable_msix)
  3814. num_cpus = find_num_cpus();
  3815. else
  3816. num_cpus = 1;
  3817. phba->num_cpus = num_cpus;
  3818. SE_DEBUG(DBG_LVL_8, "num_cpus = %d\n", phba->num_cpus);
  3819. if (enable_msix) {
  3820. beiscsi_msix_enable(phba);
  3821. if (!phba->msix_enabled)
  3822. phba->num_cpus = 1;
  3823. }
  3824. ret = be_ctrl_init(phba, pcidev);
  3825. if (ret) {
  3826. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3827. "Failed in be_ctrl_init\n");
  3828. goto hba_free;
  3829. }
  3830. if (!num_hba) {
  3831. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3832. value = readl((void *)real_offset);
  3833. if (value & 0x00010000) {
  3834. gcrashmode++;
  3835. shost_printk(KERN_ERR, phba->shost,
  3836. "Loading Driver in crashdump mode\n");
  3837. ret = beiscsi_cmd_reset_function(phba);
  3838. if (ret) {
  3839. shost_printk(KERN_ERR, phba->shost,
  3840. "Reset Failed. Aborting Crashdump\n");
  3841. goto hba_free;
  3842. }
  3843. ret = be_chk_reset_complete(phba);
  3844. if (ret) {
  3845. shost_printk(KERN_ERR, phba->shost,
  3846. "Failed to get out of reset."
  3847. "Aborting Crashdump\n");
  3848. goto hba_free;
  3849. }
  3850. } else {
  3851. value |= 0x00010000;
  3852. writel(value, (void *)real_offset);
  3853. num_hba++;
  3854. }
  3855. }
  3856. spin_lock_init(&phba->io_sgl_lock);
  3857. spin_lock_init(&phba->mgmt_sgl_lock);
  3858. spin_lock_init(&phba->isr_lock);
  3859. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  3860. if (ret != 0) {
  3861. shost_printk(KERN_ERR, phba->shost,
  3862. "Error getting fw config\n");
  3863. goto free_port;
  3864. }
  3865. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  3866. beiscsi_get_params(phba);
  3867. phba->shost->can_queue = phba->params.ios_per_ctrl;
  3868. ret = beiscsi_init_port(phba);
  3869. if (ret < 0) {
  3870. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3871. "Failed in beiscsi_init_port\n");
  3872. goto free_port;
  3873. }
  3874. for (i = 0; i < MAX_MCC_CMD ; i++) {
  3875. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  3876. phba->ctrl.mcc_tag[i] = i + 1;
  3877. phba->ctrl.mcc_numtag[i + 1] = 0;
  3878. phba->ctrl.mcc_tag_available++;
  3879. }
  3880. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  3881. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_q_irq%u",
  3882. phba->shost->host_no);
  3883. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  3884. if (!phba->wq) {
  3885. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3886. "Failed to allocate work queue\n");
  3887. goto free_twq;
  3888. }
  3889. INIT_WORK(&phba->work_cqs, beiscsi_process_all_cqs);
  3890. phwi_ctrlr = phba->phwi_ctrlr;
  3891. phwi_context = phwi_ctrlr->phwi_ctxt;
  3892. if (blk_iopoll_enabled) {
  3893. for (i = 0; i < phba->num_cpus; i++) {
  3894. pbe_eq = &phwi_context->be_eq[i];
  3895. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  3896. be_iopoll);
  3897. blk_iopoll_enable(&pbe_eq->iopoll);
  3898. }
  3899. }
  3900. ret = beiscsi_init_irqs(phba);
  3901. if (ret < 0) {
  3902. shost_printk(KERN_ERR, phba->shost, "beiscsi_dev_probe-"
  3903. "Failed to beiscsi_init_irqs\n");
  3904. goto free_blkenbld;
  3905. }
  3906. hwi_enable_intr(phba);
  3907. if (beiscsi_setup_boot_info(phba))
  3908. /*
  3909. * log error but continue, because we may not be using
  3910. * iscsi boot.
  3911. */
  3912. shost_printk(KERN_ERR, phba->shost, "Could not set up "
  3913. "iSCSI boot info.");
  3914. SE_DEBUG(DBG_LVL_8, "\n\n\n SUCCESS - DRIVER LOADED\n\n\n");
  3915. return 0;
  3916. free_blkenbld:
  3917. destroy_workqueue(phba->wq);
  3918. if (blk_iopoll_enabled)
  3919. for (i = 0; i < phba->num_cpus; i++) {
  3920. pbe_eq = &phwi_context->be_eq[i];
  3921. blk_iopoll_disable(&pbe_eq->iopoll);
  3922. }
  3923. free_twq:
  3924. beiscsi_clean_port(phba);
  3925. beiscsi_free_mem(phba);
  3926. free_port:
  3927. real_offset = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
  3928. value = readl((void *)real_offset);
  3929. if (value & 0x00010000) {
  3930. value &= 0xfffeffff;
  3931. writel(value, (void *)real_offset);
  3932. }
  3933. pci_free_consistent(phba->pcidev,
  3934. phba->ctrl.mbox_mem_alloced.size,
  3935. phba->ctrl.mbox_mem_alloced.va,
  3936. phba->ctrl.mbox_mem_alloced.dma);
  3937. beiscsi_unmap_pci_function(phba);
  3938. hba_free:
  3939. if (phba->msix_enabled)
  3940. pci_disable_msix(phba->pcidev);
  3941. iscsi_host_remove(phba->shost);
  3942. pci_dev_put(phba->pcidev);
  3943. iscsi_host_free(phba->shost);
  3944. disable_pci:
  3945. pci_disable_device(pcidev);
  3946. return ret;
  3947. }
  3948. struct iscsi_transport beiscsi_iscsi_transport = {
  3949. .owner = THIS_MODULE,
  3950. .name = DRV_NAME,
  3951. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  3952. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  3953. .create_session = beiscsi_session_create,
  3954. .destroy_session = beiscsi_session_destroy,
  3955. .create_conn = beiscsi_conn_create,
  3956. .bind_conn = beiscsi_conn_bind,
  3957. .destroy_conn = iscsi_conn_teardown,
  3958. .attr_is_visible = be2iscsi_attr_is_visible,
  3959. .set_param = beiscsi_set_param,
  3960. .get_conn_param = iscsi_conn_get_param,
  3961. .get_session_param = iscsi_session_get_param,
  3962. .get_host_param = beiscsi_get_host_param,
  3963. .start_conn = beiscsi_conn_start,
  3964. .stop_conn = iscsi_conn_stop,
  3965. .send_pdu = iscsi_conn_send_pdu,
  3966. .xmit_task = beiscsi_task_xmit,
  3967. .cleanup_task = beiscsi_cleanup_task,
  3968. .alloc_pdu = beiscsi_alloc_pdu,
  3969. .parse_pdu_itt = beiscsi_parse_pdu,
  3970. .get_stats = beiscsi_conn_get_stats,
  3971. .get_ep_param = beiscsi_ep_get_param,
  3972. .ep_connect = beiscsi_ep_connect,
  3973. .ep_poll = beiscsi_ep_poll,
  3974. .ep_disconnect = beiscsi_ep_disconnect,
  3975. .session_recovery_timedout = iscsi_session_recovery_timedout,
  3976. };
  3977. static struct pci_driver beiscsi_pci_driver = {
  3978. .name = DRV_NAME,
  3979. .probe = beiscsi_dev_probe,
  3980. .remove = beiscsi_remove,
  3981. .shutdown = beiscsi_shutdown,
  3982. .id_table = beiscsi_pci_id_table
  3983. };
  3984. static int __init beiscsi_module_init(void)
  3985. {
  3986. int ret;
  3987. beiscsi_scsi_transport =
  3988. iscsi_register_transport(&beiscsi_iscsi_transport);
  3989. if (!beiscsi_scsi_transport) {
  3990. SE_DEBUG(DBG_LVL_1,
  3991. "beiscsi_module_init - Unable to register beiscsi"
  3992. "transport.\n");
  3993. return -ENOMEM;
  3994. }
  3995. SE_DEBUG(DBG_LVL_8, "In beiscsi_module_init, tt=%p\n",
  3996. &beiscsi_iscsi_transport);
  3997. ret = pci_register_driver(&beiscsi_pci_driver);
  3998. if (ret) {
  3999. SE_DEBUG(DBG_LVL_1,
  4000. "beiscsi_module_init - Unable to register"
  4001. "beiscsi pci driver.\n");
  4002. goto unregister_iscsi_transport;
  4003. }
  4004. return 0;
  4005. unregister_iscsi_transport:
  4006. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4007. return ret;
  4008. }
  4009. static void __exit beiscsi_module_exit(void)
  4010. {
  4011. pci_unregister_driver(&beiscsi_pci_driver);
  4012. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4013. }
  4014. module_init(beiscsi_module_init);
  4015. module_exit(beiscsi_module_exit);