atmel_usba_udc.c 49 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/device.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/list.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/usb/ch9.h>
  20. #include <linux/usb/gadget.h>
  21. #include <linux/usb/atmel_usba_udc.h>
  22. #include <linux/delay.h>
  23. #include <asm/gpio.h>
  24. #include <asm/arch/board.h>
  25. #include "atmel_usba_udc.h"
  26. static struct usba_udc the_udc;
  27. static struct usba_ep *usba_ep;
  28. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  29. #include <linux/debugfs.h>
  30. #include <linux/uaccess.h>
  31. static int queue_dbg_open(struct inode *inode, struct file *file)
  32. {
  33. struct usba_ep *ep = inode->i_private;
  34. struct usba_request *req, *req_copy;
  35. struct list_head *queue_data;
  36. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  37. if (!queue_data)
  38. return -ENOMEM;
  39. INIT_LIST_HEAD(queue_data);
  40. spin_lock_irq(&ep->udc->lock);
  41. list_for_each_entry(req, &ep->queue, queue) {
  42. req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
  43. if (!req_copy)
  44. goto fail;
  45. memcpy(req_copy, req, sizeof(*req_copy));
  46. list_add_tail(&req_copy->queue, queue_data);
  47. }
  48. spin_unlock_irq(&ep->udc->lock);
  49. file->private_data = queue_data;
  50. return 0;
  51. fail:
  52. spin_unlock_irq(&ep->udc->lock);
  53. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  54. list_del(&req->queue);
  55. kfree(req);
  56. }
  57. kfree(queue_data);
  58. return -ENOMEM;
  59. }
  60. /*
  61. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  62. *
  63. * b: buffer address
  64. * l: buffer length
  65. * I/i: interrupt/no interrupt
  66. * Z/z: zero/no zero
  67. * S/s: short ok/short not ok
  68. * s: status
  69. * n: nr_packets
  70. * F/f: submitted/not submitted to FIFO
  71. * D/d: using/not using DMA
  72. * L/l: last transaction/not last transaction
  73. */
  74. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  75. size_t nbytes, loff_t *ppos)
  76. {
  77. struct list_head *queue = file->private_data;
  78. struct usba_request *req, *tmp_req;
  79. size_t len, remaining, actual = 0;
  80. char tmpbuf[38];
  81. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  82. return -EFAULT;
  83. mutex_lock(&file->f_dentry->d_inode->i_mutex);
  84. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  85. len = snprintf(tmpbuf, sizeof(tmpbuf),
  86. "%8p %08x %c%c%c %5d %c%c%c\n",
  87. req->req.buf, req->req.length,
  88. req->req.no_interrupt ? 'i' : 'I',
  89. req->req.zero ? 'Z' : 'z',
  90. req->req.short_not_ok ? 's' : 'S',
  91. req->req.status,
  92. req->submitted ? 'F' : 'f',
  93. req->using_dma ? 'D' : 'd',
  94. req->last_transaction ? 'L' : 'l');
  95. len = min(len, sizeof(tmpbuf));
  96. if (len > nbytes)
  97. break;
  98. list_del(&req->queue);
  99. kfree(req);
  100. remaining = __copy_to_user(buf, tmpbuf, len);
  101. actual += len - remaining;
  102. if (remaining)
  103. break;
  104. nbytes -= len;
  105. buf += len;
  106. }
  107. mutex_unlock(&file->f_dentry->d_inode->i_mutex);
  108. return actual;
  109. }
  110. static int queue_dbg_release(struct inode *inode, struct file *file)
  111. {
  112. struct list_head *queue_data = file->private_data;
  113. struct usba_request *req, *tmp_req;
  114. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  115. list_del(&req->queue);
  116. kfree(req);
  117. }
  118. kfree(queue_data);
  119. return 0;
  120. }
  121. static int regs_dbg_open(struct inode *inode, struct file *file)
  122. {
  123. struct usba_udc *udc;
  124. unsigned int i;
  125. u32 *data;
  126. int ret = -ENOMEM;
  127. mutex_lock(&inode->i_mutex);
  128. udc = inode->i_private;
  129. data = kmalloc(inode->i_size, GFP_KERNEL);
  130. if (!data)
  131. goto out;
  132. spin_lock_irq(&udc->lock);
  133. for (i = 0; i < inode->i_size / 4; i++)
  134. data[i] = __raw_readl(udc->regs + i * 4);
  135. spin_unlock_irq(&udc->lock);
  136. file->private_data = data;
  137. ret = 0;
  138. out:
  139. mutex_unlock(&inode->i_mutex);
  140. return ret;
  141. }
  142. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  143. size_t nbytes, loff_t *ppos)
  144. {
  145. struct inode *inode = file->f_dentry->d_inode;
  146. int ret;
  147. mutex_lock(&inode->i_mutex);
  148. ret = simple_read_from_buffer(buf, nbytes, ppos,
  149. file->private_data,
  150. file->f_dentry->d_inode->i_size);
  151. mutex_unlock(&inode->i_mutex);
  152. return ret;
  153. }
  154. static int regs_dbg_release(struct inode *inode, struct file *file)
  155. {
  156. kfree(file->private_data);
  157. return 0;
  158. }
  159. const struct file_operations queue_dbg_fops = {
  160. .owner = THIS_MODULE,
  161. .open = queue_dbg_open,
  162. .llseek = no_llseek,
  163. .read = queue_dbg_read,
  164. .release = queue_dbg_release,
  165. };
  166. const struct file_operations regs_dbg_fops = {
  167. .owner = THIS_MODULE,
  168. .open = regs_dbg_open,
  169. .llseek = generic_file_llseek,
  170. .read = regs_dbg_read,
  171. .release = regs_dbg_release,
  172. };
  173. static void usba_ep_init_debugfs(struct usba_udc *udc,
  174. struct usba_ep *ep)
  175. {
  176. struct dentry *ep_root;
  177. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  178. if (!ep_root)
  179. goto err_root;
  180. ep->debugfs_dir = ep_root;
  181. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  182. ep, &queue_dbg_fops);
  183. if (!ep->debugfs_queue)
  184. goto err_queue;
  185. if (ep->can_dma) {
  186. ep->debugfs_dma_status
  187. = debugfs_create_u32("dma_status", 0400, ep_root,
  188. &ep->last_dma_status);
  189. if (!ep->debugfs_dma_status)
  190. goto err_dma_status;
  191. }
  192. if (ep_is_control(ep)) {
  193. ep->debugfs_state
  194. = debugfs_create_u32("state", 0400, ep_root,
  195. &ep->state);
  196. if (!ep->debugfs_state)
  197. goto err_state;
  198. }
  199. return;
  200. err_state:
  201. if (ep->can_dma)
  202. debugfs_remove(ep->debugfs_dma_status);
  203. err_dma_status:
  204. debugfs_remove(ep->debugfs_queue);
  205. err_queue:
  206. debugfs_remove(ep_root);
  207. err_root:
  208. dev_err(&ep->udc->pdev->dev,
  209. "failed to create debugfs directory for %s\n", ep->ep.name);
  210. }
  211. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  212. {
  213. debugfs_remove(ep->debugfs_queue);
  214. debugfs_remove(ep->debugfs_dma_status);
  215. debugfs_remove(ep->debugfs_state);
  216. debugfs_remove(ep->debugfs_dir);
  217. ep->debugfs_dma_status = NULL;
  218. ep->debugfs_dir = NULL;
  219. }
  220. static void usba_init_debugfs(struct usba_udc *udc)
  221. {
  222. struct dentry *root, *regs;
  223. struct resource *regs_resource;
  224. root = debugfs_create_dir(udc->gadget.name, NULL);
  225. if (IS_ERR(root) || !root)
  226. goto err_root;
  227. udc->debugfs_root = root;
  228. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  229. if (!regs)
  230. goto err_regs;
  231. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  232. CTRL_IOMEM_ID);
  233. regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
  234. udc->debugfs_regs = regs;
  235. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  236. return;
  237. err_regs:
  238. debugfs_remove(root);
  239. err_root:
  240. udc->debugfs_root = NULL;
  241. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  242. }
  243. static void usba_cleanup_debugfs(struct usba_udc *udc)
  244. {
  245. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  246. debugfs_remove(udc->debugfs_regs);
  247. debugfs_remove(udc->debugfs_root);
  248. udc->debugfs_regs = NULL;
  249. udc->debugfs_root = NULL;
  250. }
  251. #else
  252. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  253. struct usba_ep *ep)
  254. {
  255. }
  256. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  257. {
  258. }
  259. static inline void usba_init_debugfs(struct usba_udc *udc)
  260. {
  261. }
  262. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  263. {
  264. }
  265. #endif
  266. static int vbus_is_present(struct usba_udc *udc)
  267. {
  268. if (udc->vbus_pin != -1)
  269. return gpio_get_value(udc->vbus_pin);
  270. /* No Vbus detection: Assume always present */
  271. return 1;
  272. }
  273. #if defined(CONFIG_AVR32)
  274. static void toggle_bias(int is_on)
  275. {
  276. }
  277. #elif defined(CONFIG_ARCH_AT91)
  278. #include <asm/arch/at91_pmc.h>
  279. static void toggle_bias(int is_on)
  280. {
  281. unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
  282. if (is_on)
  283. at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
  284. else
  285. at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
  286. }
  287. #endif /* CONFIG_ARCH_AT91 */
  288. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  289. {
  290. unsigned int transaction_len;
  291. transaction_len = req->req.length - req->req.actual;
  292. req->last_transaction = 1;
  293. if (transaction_len > ep->ep.maxpacket) {
  294. transaction_len = ep->ep.maxpacket;
  295. req->last_transaction = 0;
  296. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  297. req->last_transaction = 0;
  298. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  299. ep->ep.name, req, transaction_len,
  300. req->last_transaction ? ", done" : "");
  301. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  302. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  303. req->req.actual += transaction_len;
  304. }
  305. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  306. {
  307. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  308. ep->ep.name, req, req->req.length);
  309. req->req.actual = 0;
  310. req->submitted = 1;
  311. if (req->using_dma) {
  312. if (req->req.length == 0) {
  313. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  314. return;
  315. }
  316. if (req->req.zero)
  317. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  318. else
  319. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  320. usba_dma_writel(ep, ADDRESS, req->req.dma);
  321. usba_dma_writel(ep, CONTROL, req->ctrl);
  322. } else {
  323. next_fifo_transaction(ep, req);
  324. if (req->last_transaction) {
  325. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  326. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  327. } else {
  328. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  329. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  330. }
  331. }
  332. }
  333. static void submit_next_request(struct usba_ep *ep)
  334. {
  335. struct usba_request *req;
  336. if (list_empty(&ep->queue)) {
  337. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  338. return;
  339. }
  340. req = list_entry(ep->queue.next, struct usba_request, queue);
  341. if (!req->submitted)
  342. submit_request(ep, req);
  343. }
  344. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  345. {
  346. ep->state = STATUS_STAGE_IN;
  347. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  348. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  349. }
  350. static void receive_data(struct usba_ep *ep)
  351. {
  352. struct usba_udc *udc = ep->udc;
  353. struct usba_request *req;
  354. unsigned long status;
  355. unsigned int bytecount, nr_busy;
  356. int is_complete = 0;
  357. status = usba_ep_readl(ep, STA);
  358. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  359. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  360. while (nr_busy > 0) {
  361. if (list_empty(&ep->queue)) {
  362. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  363. break;
  364. }
  365. req = list_entry(ep->queue.next,
  366. struct usba_request, queue);
  367. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  368. if (status & (1 << 31))
  369. is_complete = 1;
  370. if (req->req.actual + bytecount >= req->req.length) {
  371. is_complete = 1;
  372. bytecount = req->req.length - req->req.actual;
  373. }
  374. memcpy_fromio(req->req.buf + req->req.actual,
  375. ep->fifo, bytecount);
  376. req->req.actual += bytecount;
  377. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  378. if (is_complete) {
  379. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  380. req->req.status = 0;
  381. list_del_init(&req->queue);
  382. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  383. spin_unlock(&udc->lock);
  384. req->req.complete(&ep->ep, &req->req);
  385. spin_lock(&udc->lock);
  386. }
  387. status = usba_ep_readl(ep, STA);
  388. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  389. if (is_complete && ep_is_control(ep)) {
  390. send_status(udc, ep);
  391. break;
  392. }
  393. }
  394. }
  395. static void
  396. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  397. {
  398. struct usba_udc *udc = ep->udc;
  399. WARN_ON(!list_empty(&req->queue));
  400. if (req->req.status == -EINPROGRESS)
  401. req->req.status = status;
  402. if (req->mapped) {
  403. dma_unmap_single(
  404. &udc->pdev->dev, req->req.dma, req->req.length,
  405. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  406. req->req.dma = DMA_ADDR_INVALID;
  407. req->mapped = 0;
  408. }
  409. DBG(DBG_GADGET | DBG_REQ,
  410. "%s: req %p complete: status %d, actual %u\n",
  411. ep->ep.name, req, req->req.status, req->req.actual);
  412. spin_unlock(&udc->lock);
  413. req->req.complete(&ep->ep, &req->req);
  414. spin_lock(&udc->lock);
  415. }
  416. static void
  417. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  418. {
  419. struct usba_request *req, *tmp_req;
  420. list_for_each_entry_safe(req, tmp_req, list, queue) {
  421. list_del_init(&req->queue);
  422. request_complete(ep, req, status);
  423. }
  424. }
  425. static int
  426. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  427. {
  428. struct usba_ep *ep = to_usba_ep(_ep);
  429. struct usba_udc *udc = ep->udc;
  430. unsigned long flags, ept_cfg, maxpacket;
  431. unsigned int nr_trans;
  432. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  433. maxpacket = le16_to_cpu(desc->wMaxPacketSize) & 0x7ff;
  434. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  435. || ep->index == 0
  436. || desc->bDescriptorType != USB_DT_ENDPOINT
  437. || maxpacket == 0
  438. || maxpacket > ep->fifo_size) {
  439. DBG(DBG_ERR, "ep_enable: Invalid argument");
  440. return -EINVAL;
  441. }
  442. ep->is_isoc = 0;
  443. ep->is_in = 0;
  444. if (maxpacket <= 8)
  445. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  446. else
  447. /* LSB is bit 1, not 0 */
  448. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  449. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  450. ep->ep.name, ept_cfg, maxpacket);
  451. if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
  452. ep->is_in = 1;
  453. ept_cfg |= USBA_EPT_DIR_IN;
  454. }
  455. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  456. case USB_ENDPOINT_XFER_CONTROL:
  457. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  458. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  459. break;
  460. case USB_ENDPOINT_XFER_ISOC:
  461. if (!ep->can_isoc) {
  462. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  463. ep->ep.name);
  464. return -EINVAL;
  465. }
  466. /*
  467. * Bits 11:12 specify number of _additional_
  468. * transactions per microframe.
  469. */
  470. nr_trans = ((le16_to_cpu(desc->wMaxPacketSize) >> 11) & 3) + 1;
  471. if (nr_trans > 3)
  472. return -EINVAL;
  473. ep->is_isoc = 1;
  474. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  475. /*
  476. * Do triple-buffering on high-bandwidth iso endpoints.
  477. */
  478. if (nr_trans > 1 && ep->nr_banks == 3)
  479. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  480. else
  481. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  482. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  483. break;
  484. case USB_ENDPOINT_XFER_BULK:
  485. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  486. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  487. break;
  488. case USB_ENDPOINT_XFER_INT:
  489. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  490. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  491. break;
  492. }
  493. spin_lock_irqsave(&ep->udc->lock, flags);
  494. if (ep->desc) {
  495. spin_unlock_irqrestore(&ep->udc->lock, flags);
  496. DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
  497. return -EBUSY;
  498. }
  499. ep->desc = desc;
  500. ep->ep.maxpacket = maxpacket;
  501. usba_ep_writel(ep, CFG, ept_cfg);
  502. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  503. if (ep->can_dma) {
  504. u32 ctrl;
  505. usba_writel(udc, INT_ENB,
  506. (usba_readl(udc, INT_ENB)
  507. | USBA_BF(EPT_INT, 1 << ep->index)
  508. | USBA_BF(DMA_INT, 1 << ep->index)));
  509. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  510. usba_ep_writel(ep, CTL_ENB, ctrl);
  511. } else {
  512. usba_writel(udc, INT_ENB,
  513. (usba_readl(udc, INT_ENB)
  514. | USBA_BF(EPT_INT, 1 << ep->index)));
  515. }
  516. spin_unlock_irqrestore(&udc->lock, flags);
  517. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  518. (unsigned long)usba_ep_readl(ep, CFG));
  519. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  520. (unsigned long)usba_readl(udc, INT_ENB));
  521. return 0;
  522. }
  523. static int usba_ep_disable(struct usb_ep *_ep)
  524. {
  525. struct usba_ep *ep = to_usba_ep(_ep);
  526. struct usba_udc *udc = ep->udc;
  527. LIST_HEAD(req_list);
  528. unsigned long flags;
  529. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  530. spin_lock_irqsave(&udc->lock, flags);
  531. if (!ep->desc) {
  532. spin_unlock_irqrestore(&udc->lock, flags);
  533. DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name);
  534. return -EINVAL;
  535. }
  536. ep->desc = NULL;
  537. list_splice_init(&ep->queue, &req_list);
  538. if (ep->can_dma) {
  539. usba_dma_writel(ep, CONTROL, 0);
  540. usba_dma_writel(ep, ADDRESS, 0);
  541. usba_dma_readl(ep, STATUS);
  542. }
  543. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  544. usba_writel(udc, INT_ENB,
  545. usba_readl(udc, INT_ENB)
  546. & ~USBA_BF(EPT_INT, 1 << ep->index));
  547. request_complete_list(ep, &req_list, -ESHUTDOWN);
  548. spin_unlock_irqrestore(&udc->lock, flags);
  549. return 0;
  550. }
  551. static struct usb_request *
  552. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  553. {
  554. struct usba_request *req;
  555. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  556. req = kzalloc(sizeof(*req), gfp_flags);
  557. if (!req)
  558. return NULL;
  559. INIT_LIST_HEAD(&req->queue);
  560. req->req.dma = DMA_ADDR_INVALID;
  561. return &req->req;
  562. }
  563. static void
  564. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  565. {
  566. struct usba_request *req = to_usba_req(_req);
  567. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  568. kfree(req);
  569. }
  570. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  571. struct usba_request *req, gfp_t gfp_flags)
  572. {
  573. unsigned long flags;
  574. int ret;
  575. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  576. ep->ep.name, req->req.length, req->req.dma,
  577. req->req.zero ? 'Z' : 'z',
  578. req->req.short_not_ok ? 'S' : 's',
  579. req->req.no_interrupt ? 'I' : 'i');
  580. if (req->req.length > 0x10000) {
  581. /* Lengths from 0 to 65536 (inclusive) are supported */
  582. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  583. return -EINVAL;
  584. }
  585. req->using_dma = 1;
  586. if (req->req.dma == DMA_ADDR_INVALID) {
  587. req->req.dma = dma_map_single(
  588. &udc->pdev->dev, req->req.buf, req->req.length,
  589. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  590. req->mapped = 1;
  591. } else {
  592. dma_sync_single_for_device(
  593. &udc->pdev->dev, req->req.dma, req->req.length,
  594. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  595. req->mapped = 0;
  596. }
  597. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  598. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  599. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  600. if (ep->is_in)
  601. req->ctrl |= USBA_DMA_END_BUF_EN;
  602. /*
  603. * Add this request to the queue and submit for DMA if
  604. * possible. Check if we're still alive first -- we may have
  605. * received a reset since last time we checked.
  606. */
  607. ret = -ESHUTDOWN;
  608. spin_lock_irqsave(&udc->lock, flags);
  609. if (ep->desc) {
  610. if (list_empty(&ep->queue))
  611. submit_request(ep, req);
  612. list_add_tail(&req->queue, &ep->queue);
  613. ret = 0;
  614. }
  615. spin_unlock_irqrestore(&udc->lock, flags);
  616. return ret;
  617. }
  618. static int
  619. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  620. {
  621. struct usba_request *req = to_usba_req(_req);
  622. struct usba_ep *ep = to_usba_ep(_ep);
  623. struct usba_udc *udc = ep->udc;
  624. unsigned long flags;
  625. int ret;
  626. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  627. ep->ep.name, req, _req->length);
  628. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || !ep->desc)
  629. return -ESHUTDOWN;
  630. req->submitted = 0;
  631. req->using_dma = 0;
  632. req->last_transaction = 0;
  633. _req->status = -EINPROGRESS;
  634. _req->actual = 0;
  635. if (ep->can_dma)
  636. return queue_dma(udc, ep, req, gfp_flags);
  637. /* May have received a reset since last time we checked */
  638. ret = -ESHUTDOWN;
  639. spin_lock_irqsave(&udc->lock, flags);
  640. if (ep->desc) {
  641. list_add_tail(&req->queue, &ep->queue);
  642. if (ep->is_in || (ep_is_control(ep)
  643. && (ep->state == DATA_STAGE_IN
  644. || ep->state == STATUS_STAGE_IN)))
  645. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  646. else
  647. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  648. ret = 0;
  649. }
  650. spin_unlock_irqrestore(&udc->lock, flags);
  651. return ret;
  652. }
  653. static void
  654. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  655. {
  656. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  657. }
  658. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  659. {
  660. unsigned int timeout;
  661. u32 status;
  662. /*
  663. * Stop the DMA controller. When writing both CH_EN
  664. * and LINK to 0, the other bits are not affected.
  665. */
  666. usba_dma_writel(ep, CONTROL, 0);
  667. /* Wait for the FIFO to empty */
  668. for (timeout = 40; timeout; --timeout) {
  669. status = usba_dma_readl(ep, STATUS);
  670. if (!(status & USBA_DMA_CH_EN))
  671. break;
  672. udelay(1);
  673. }
  674. if (pstatus)
  675. *pstatus = status;
  676. if (timeout == 0) {
  677. dev_err(&ep->udc->pdev->dev,
  678. "%s: timed out waiting for DMA FIFO to empty\n",
  679. ep->ep.name);
  680. return -ETIMEDOUT;
  681. }
  682. return 0;
  683. }
  684. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  685. {
  686. struct usba_ep *ep = to_usba_ep(_ep);
  687. struct usba_udc *udc = ep->udc;
  688. struct usba_request *req = to_usba_req(_req);
  689. unsigned long flags;
  690. u32 status;
  691. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  692. ep->ep.name, req);
  693. spin_lock_irqsave(&udc->lock, flags);
  694. if (req->using_dma) {
  695. /*
  696. * If this request is currently being transferred,
  697. * stop the DMA controller and reset the FIFO.
  698. */
  699. if (ep->queue.next == &req->queue) {
  700. status = usba_dma_readl(ep, STATUS);
  701. if (status & USBA_DMA_CH_EN)
  702. stop_dma(ep, &status);
  703. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  704. ep->last_dma_status = status;
  705. #endif
  706. usba_writel(udc, EPT_RST, 1 << ep->index);
  707. usba_update_req(ep, req, status);
  708. }
  709. }
  710. /*
  711. * Errors should stop the queue from advancing until the
  712. * completion function returns.
  713. */
  714. list_del_init(&req->queue);
  715. request_complete(ep, req, -ECONNRESET);
  716. /* Process the next request if any */
  717. submit_next_request(ep);
  718. spin_unlock_irqrestore(&udc->lock, flags);
  719. return 0;
  720. }
  721. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  722. {
  723. struct usba_ep *ep = to_usba_ep(_ep);
  724. struct usba_udc *udc = ep->udc;
  725. unsigned long flags;
  726. int ret = 0;
  727. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  728. value ? "set" : "clear");
  729. if (!ep->desc) {
  730. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  731. ep->ep.name);
  732. return -ENODEV;
  733. }
  734. if (ep->is_isoc) {
  735. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  736. ep->ep.name);
  737. return -ENOTTY;
  738. }
  739. spin_lock_irqsave(&udc->lock, flags);
  740. /*
  741. * We can't halt IN endpoints while there are still data to be
  742. * transferred
  743. */
  744. if (!list_empty(&ep->queue)
  745. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  746. & USBA_BF(BUSY_BANKS, -1L))))) {
  747. ret = -EAGAIN;
  748. } else {
  749. if (value)
  750. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  751. else
  752. usba_ep_writel(ep, CLR_STA,
  753. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  754. usba_ep_readl(ep, STA);
  755. }
  756. spin_unlock_irqrestore(&udc->lock, flags);
  757. return ret;
  758. }
  759. static int usba_ep_fifo_status(struct usb_ep *_ep)
  760. {
  761. struct usba_ep *ep = to_usba_ep(_ep);
  762. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  763. }
  764. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  765. {
  766. struct usba_ep *ep = to_usba_ep(_ep);
  767. struct usba_udc *udc = ep->udc;
  768. usba_writel(udc, EPT_RST, 1 << ep->index);
  769. }
  770. static const struct usb_ep_ops usba_ep_ops = {
  771. .enable = usba_ep_enable,
  772. .disable = usba_ep_disable,
  773. .alloc_request = usba_ep_alloc_request,
  774. .free_request = usba_ep_free_request,
  775. .queue = usba_ep_queue,
  776. .dequeue = usba_ep_dequeue,
  777. .set_halt = usba_ep_set_halt,
  778. .fifo_status = usba_ep_fifo_status,
  779. .fifo_flush = usba_ep_fifo_flush,
  780. };
  781. static int usba_udc_get_frame(struct usb_gadget *gadget)
  782. {
  783. struct usba_udc *udc = to_usba_udc(gadget);
  784. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  785. }
  786. static int usba_udc_wakeup(struct usb_gadget *gadget)
  787. {
  788. struct usba_udc *udc = to_usba_udc(gadget);
  789. unsigned long flags;
  790. u32 ctrl;
  791. int ret = -EINVAL;
  792. spin_lock_irqsave(&udc->lock, flags);
  793. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  794. ctrl = usba_readl(udc, CTRL);
  795. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  796. ret = 0;
  797. }
  798. spin_unlock_irqrestore(&udc->lock, flags);
  799. return ret;
  800. }
  801. static int
  802. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  803. {
  804. struct usba_udc *udc = to_usba_udc(gadget);
  805. unsigned long flags;
  806. spin_lock_irqsave(&udc->lock, flags);
  807. if (is_selfpowered)
  808. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  809. else
  810. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  811. spin_unlock_irqrestore(&udc->lock, flags);
  812. return 0;
  813. }
  814. static const struct usb_gadget_ops usba_udc_ops = {
  815. .get_frame = usba_udc_get_frame,
  816. .wakeup = usba_udc_wakeup,
  817. .set_selfpowered = usba_udc_set_selfpowered,
  818. };
  819. static struct usb_endpoint_descriptor usba_ep0_desc = {
  820. .bLength = USB_DT_ENDPOINT_SIZE,
  821. .bDescriptorType = USB_DT_ENDPOINT,
  822. .bEndpointAddress = 0,
  823. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  824. .wMaxPacketSize = __constant_cpu_to_le16(64),
  825. /* FIXME: I have no idea what to put here */
  826. .bInterval = 1,
  827. };
  828. static void nop_release(struct device *dev)
  829. {
  830. }
  831. static struct usba_udc the_udc = {
  832. .gadget = {
  833. .ops = &usba_udc_ops,
  834. .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
  835. .is_dualspeed = 1,
  836. .name = "atmel_usba_udc",
  837. .dev = {
  838. .bus_id = "gadget",
  839. .release = nop_release,
  840. },
  841. },
  842. .lock = SPIN_LOCK_UNLOCKED,
  843. };
  844. /*
  845. * Called with interrupts disabled and udc->lock held.
  846. */
  847. static void reset_all_endpoints(struct usba_udc *udc)
  848. {
  849. struct usba_ep *ep;
  850. struct usba_request *req, *tmp_req;
  851. usba_writel(udc, EPT_RST, ~0UL);
  852. ep = to_usba_ep(udc->gadget.ep0);
  853. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  854. list_del_init(&req->queue);
  855. request_complete(ep, req, -ECONNRESET);
  856. }
  857. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  858. if (ep->desc) {
  859. spin_unlock(&udc->lock);
  860. usba_ep_disable(&ep->ep);
  861. spin_lock(&udc->lock);
  862. }
  863. }
  864. }
  865. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  866. {
  867. struct usba_ep *ep;
  868. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  869. return to_usba_ep(udc->gadget.ep0);
  870. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  871. u8 bEndpointAddress;
  872. if (!ep->desc)
  873. continue;
  874. bEndpointAddress = ep->desc->bEndpointAddress;
  875. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  876. continue;
  877. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  878. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  879. return ep;
  880. }
  881. return NULL;
  882. }
  883. /* Called with interrupts disabled and udc->lock held */
  884. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  885. {
  886. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  887. ep->state = WAIT_FOR_SETUP;
  888. }
  889. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  890. {
  891. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  892. return 1;
  893. return 0;
  894. }
  895. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  896. {
  897. u32 regval;
  898. DBG(DBG_BUS, "setting address %u...\n", addr);
  899. regval = usba_readl(udc, CTRL);
  900. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  901. usba_writel(udc, CTRL, regval);
  902. }
  903. static int do_test_mode(struct usba_udc *udc)
  904. {
  905. static const char test_packet_buffer[] = {
  906. /* JKJKJKJK * 9 */
  907. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  908. /* JJKKJJKK * 8 */
  909. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  910. /* JJKKJJKK * 8 */
  911. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  912. /* JJJJJJJKKKKKKK * 8 */
  913. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  914. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  915. /* JJJJJJJK * 8 */
  916. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  917. /* {JKKKKKKK * 10}, JK */
  918. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  919. };
  920. struct usba_ep *ep;
  921. struct device *dev = &udc->pdev->dev;
  922. int test_mode;
  923. test_mode = udc->test_mode;
  924. /* Start from a clean slate */
  925. reset_all_endpoints(udc);
  926. switch (test_mode) {
  927. case 0x0100:
  928. /* Test_J */
  929. usba_writel(udc, TST, USBA_TST_J_MODE);
  930. dev_info(dev, "Entering Test_J mode...\n");
  931. break;
  932. case 0x0200:
  933. /* Test_K */
  934. usba_writel(udc, TST, USBA_TST_K_MODE);
  935. dev_info(dev, "Entering Test_K mode...\n");
  936. break;
  937. case 0x0300:
  938. /*
  939. * Test_SE0_NAK: Force high-speed mode and set up ep0
  940. * for Bulk IN transfers
  941. */
  942. ep = &usba_ep[0];
  943. usba_writel(udc, TST,
  944. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  945. usba_ep_writel(ep, CFG,
  946. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  947. | USBA_EPT_DIR_IN
  948. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  949. | USBA_BF(BK_NUMBER, 1));
  950. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  951. set_protocol_stall(udc, ep);
  952. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  953. } else {
  954. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  955. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  956. }
  957. break;
  958. case 0x0400:
  959. /* Test_Packet */
  960. ep = &usba_ep[0];
  961. usba_ep_writel(ep, CFG,
  962. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  963. | USBA_EPT_DIR_IN
  964. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  965. | USBA_BF(BK_NUMBER, 1));
  966. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  967. set_protocol_stall(udc, ep);
  968. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  969. } else {
  970. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  971. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  972. memcpy_toio(ep->fifo, test_packet_buffer,
  973. sizeof(test_packet_buffer));
  974. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  975. dev_info(dev, "Entering Test_Packet mode...\n");
  976. }
  977. break;
  978. default:
  979. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  980. return -EINVAL;
  981. }
  982. return 0;
  983. }
  984. /* Avoid overly long expressions */
  985. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  986. {
  987. if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  988. return true;
  989. return false;
  990. }
  991. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  992. {
  993. if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_TEST_MODE))
  994. return true;
  995. return false;
  996. }
  997. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  998. {
  999. if (crq->wValue == __constant_cpu_to_le16(USB_ENDPOINT_HALT))
  1000. return true;
  1001. return false;
  1002. }
  1003. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1004. struct usb_ctrlrequest *crq)
  1005. {
  1006. int retval = 0;;
  1007. switch (crq->bRequest) {
  1008. case USB_REQ_GET_STATUS: {
  1009. u16 status;
  1010. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1011. status = cpu_to_le16(udc->devstatus);
  1012. } else if (crq->bRequestType
  1013. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1014. status = __constant_cpu_to_le16(0);
  1015. } else if (crq->bRequestType
  1016. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1017. struct usba_ep *target;
  1018. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1019. if (!target)
  1020. goto stall;
  1021. status = 0;
  1022. if (is_stalled(udc, target))
  1023. status |= __constant_cpu_to_le16(1);
  1024. } else
  1025. goto delegate;
  1026. /* Write directly to the FIFO. No queueing is done. */
  1027. if (crq->wLength != __constant_cpu_to_le16(sizeof(status)))
  1028. goto stall;
  1029. ep->state = DATA_STAGE_IN;
  1030. __raw_writew(status, ep->fifo);
  1031. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1032. break;
  1033. }
  1034. case USB_REQ_CLEAR_FEATURE: {
  1035. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1036. if (feature_is_dev_remote_wakeup(crq))
  1037. udc->devstatus
  1038. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1039. else
  1040. /* Can't CLEAR_FEATURE TEST_MODE */
  1041. goto stall;
  1042. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1043. struct usba_ep *target;
  1044. if (crq->wLength != __constant_cpu_to_le16(0)
  1045. || !feature_is_ep_halt(crq))
  1046. goto stall;
  1047. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1048. if (!target)
  1049. goto stall;
  1050. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1051. if (target->index != 0)
  1052. usba_ep_writel(target, CLR_STA,
  1053. USBA_TOGGLE_CLR);
  1054. } else {
  1055. goto delegate;
  1056. }
  1057. send_status(udc, ep);
  1058. break;
  1059. }
  1060. case USB_REQ_SET_FEATURE: {
  1061. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1062. if (feature_is_dev_test_mode(crq)) {
  1063. send_status(udc, ep);
  1064. ep->state = STATUS_STAGE_TEST;
  1065. udc->test_mode = le16_to_cpu(crq->wIndex);
  1066. return 0;
  1067. } else if (feature_is_dev_remote_wakeup(crq)) {
  1068. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1069. } else {
  1070. goto stall;
  1071. }
  1072. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1073. struct usba_ep *target;
  1074. if (crq->wLength != __constant_cpu_to_le16(0)
  1075. || !feature_is_ep_halt(crq))
  1076. goto stall;
  1077. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1078. if (!target)
  1079. goto stall;
  1080. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1081. } else
  1082. goto delegate;
  1083. send_status(udc, ep);
  1084. break;
  1085. }
  1086. case USB_REQ_SET_ADDRESS:
  1087. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1088. goto delegate;
  1089. set_address(udc, le16_to_cpu(crq->wValue));
  1090. send_status(udc, ep);
  1091. ep->state = STATUS_STAGE_ADDR;
  1092. break;
  1093. default:
  1094. delegate:
  1095. spin_unlock(&udc->lock);
  1096. retval = udc->driver->setup(&udc->gadget, crq);
  1097. spin_lock(&udc->lock);
  1098. }
  1099. return retval;
  1100. stall:
  1101. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1102. "halting endpoint...\n",
  1103. ep->ep.name, crq->bRequestType, crq->bRequest,
  1104. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1105. le16_to_cpu(crq->wLength));
  1106. set_protocol_stall(udc, ep);
  1107. return -1;
  1108. }
  1109. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1110. {
  1111. struct usba_request *req;
  1112. u32 epstatus;
  1113. u32 epctrl;
  1114. restart:
  1115. epstatus = usba_ep_readl(ep, STA);
  1116. epctrl = usba_ep_readl(ep, CTL);
  1117. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1118. ep->ep.name, ep->state, epstatus, epctrl);
  1119. req = NULL;
  1120. if (!list_empty(&ep->queue))
  1121. req = list_entry(ep->queue.next,
  1122. struct usba_request, queue);
  1123. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1124. if (req->submitted)
  1125. next_fifo_transaction(ep, req);
  1126. else
  1127. submit_request(ep, req);
  1128. if (req->last_transaction) {
  1129. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1130. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1131. }
  1132. goto restart;
  1133. }
  1134. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1135. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1136. switch (ep->state) {
  1137. case DATA_STAGE_IN:
  1138. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1139. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1140. ep->state = STATUS_STAGE_OUT;
  1141. break;
  1142. case STATUS_STAGE_ADDR:
  1143. /* Activate our new address */
  1144. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1145. | USBA_FADDR_EN));
  1146. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1147. ep->state = WAIT_FOR_SETUP;
  1148. break;
  1149. case STATUS_STAGE_IN:
  1150. if (req) {
  1151. list_del_init(&req->queue);
  1152. request_complete(ep, req, 0);
  1153. submit_next_request(ep);
  1154. }
  1155. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1156. ep->state = WAIT_FOR_SETUP;
  1157. break;
  1158. case STATUS_STAGE_TEST:
  1159. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1160. ep->state = WAIT_FOR_SETUP;
  1161. if (do_test_mode(udc))
  1162. set_protocol_stall(udc, ep);
  1163. break;
  1164. default:
  1165. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1166. "halting endpoint...\n",
  1167. ep->ep.name, ep->state);
  1168. set_protocol_stall(udc, ep);
  1169. break;
  1170. }
  1171. goto restart;
  1172. }
  1173. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1174. switch (ep->state) {
  1175. case STATUS_STAGE_OUT:
  1176. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1177. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1178. if (req) {
  1179. list_del_init(&req->queue);
  1180. request_complete(ep, req, 0);
  1181. }
  1182. ep->state = WAIT_FOR_SETUP;
  1183. break;
  1184. case DATA_STAGE_OUT:
  1185. receive_data(ep);
  1186. break;
  1187. default:
  1188. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1189. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1190. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1191. "halting endpoint...\n",
  1192. ep->ep.name, ep->state);
  1193. set_protocol_stall(udc, ep);
  1194. break;
  1195. }
  1196. goto restart;
  1197. }
  1198. if (epstatus & USBA_RX_SETUP) {
  1199. union {
  1200. struct usb_ctrlrequest crq;
  1201. unsigned long data[2];
  1202. } crq;
  1203. unsigned int pkt_len;
  1204. int ret;
  1205. if (ep->state != WAIT_FOR_SETUP) {
  1206. /*
  1207. * Didn't expect a SETUP packet at this
  1208. * point. Clean up any pending requests (which
  1209. * may be successful).
  1210. */
  1211. int status = -EPROTO;
  1212. /*
  1213. * RXRDY and TXCOMP are dropped when SETUP
  1214. * packets arrive. Just pretend we received
  1215. * the status packet.
  1216. */
  1217. if (ep->state == STATUS_STAGE_OUT
  1218. || ep->state == STATUS_STAGE_IN) {
  1219. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1220. status = 0;
  1221. }
  1222. if (req) {
  1223. list_del_init(&req->queue);
  1224. request_complete(ep, req, status);
  1225. }
  1226. }
  1227. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1228. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1229. if (pkt_len != sizeof(crq)) {
  1230. pr_warning("udc: Invalid packet length %u "
  1231. "(expected %zu)\n", pkt_len, sizeof(crq));
  1232. set_protocol_stall(udc, ep);
  1233. return;
  1234. }
  1235. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1236. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1237. /* Free up one bank in the FIFO so that we can
  1238. * generate or receive a reply right away. */
  1239. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1240. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1241. ep->state, crq.crq.bRequestType,
  1242. crq.crq.bRequest); */
  1243. if (crq.crq.bRequestType & USB_DIR_IN) {
  1244. /*
  1245. * The USB 2.0 spec states that "if wLength is
  1246. * zero, there is no data transfer phase."
  1247. * However, testusb #14 seems to actually
  1248. * expect a data phase even if wLength = 0...
  1249. */
  1250. ep->state = DATA_STAGE_IN;
  1251. } else {
  1252. if (crq.crq.wLength != __constant_cpu_to_le16(0))
  1253. ep->state = DATA_STAGE_OUT;
  1254. else
  1255. ep->state = STATUS_STAGE_IN;
  1256. }
  1257. ret = -1;
  1258. if (ep->index == 0)
  1259. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1260. else {
  1261. spin_unlock(&udc->lock);
  1262. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1263. spin_lock(&udc->lock);
  1264. }
  1265. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1266. crq.crq.bRequestType, crq.crq.bRequest,
  1267. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1268. if (ret < 0) {
  1269. /* Let the host know that we failed */
  1270. set_protocol_stall(udc, ep);
  1271. }
  1272. }
  1273. }
  1274. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1275. {
  1276. struct usba_request *req;
  1277. u32 epstatus;
  1278. u32 epctrl;
  1279. epstatus = usba_ep_readl(ep, STA);
  1280. epctrl = usba_ep_readl(ep, CTL);
  1281. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1282. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1283. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1284. if (list_empty(&ep->queue)) {
  1285. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1286. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1287. return;
  1288. }
  1289. req = list_entry(ep->queue.next, struct usba_request, queue);
  1290. if (req->using_dma) {
  1291. /* Send a zero-length packet */
  1292. usba_ep_writel(ep, SET_STA,
  1293. USBA_TX_PK_RDY);
  1294. usba_ep_writel(ep, CTL_DIS,
  1295. USBA_TX_PK_RDY);
  1296. list_del_init(&req->queue);
  1297. submit_next_request(ep);
  1298. request_complete(ep, req, 0);
  1299. } else {
  1300. if (req->submitted)
  1301. next_fifo_transaction(ep, req);
  1302. else
  1303. submit_request(ep, req);
  1304. if (req->last_transaction) {
  1305. list_del_init(&req->queue);
  1306. submit_next_request(ep);
  1307. request_complete(ep, req, 0);
  1308. }
  1309. }
  1310. epstatus = usba_ep_readl(ep, STA);
  1311. epctrl = usba_ep_readl(ep, CTL);
  1312. }
  1313. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1314. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1315. receive_data(ep);
  1316. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1317. }
  1318. }
  1319. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1320. {
  1321. struct usba_request *req;
  1322. u32 status, control, pending;
  1323. status = usba_dma_readl(ep, STATUS);
  1324. control = usba_dma_readl(ep, CONTROL);
  1325. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1326. ep->last_dma_status = status;
  1327. #endif
  1328. pending = status & control;
  1329. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1330. if (status & USBA_DMA_CH_EN) {
  1331. dev_err(&udc->pdev->dev,
  1332. "DMA_CH_EN is set after transfer is finished!\n");
  1333. dev_err(&udc->pdev->dev,
  1334. "status=%#08x, pending=%#08x, control=%#08x\n",
  1335. status, pending, control);
  1336. /*
  1337. * try to pretend nothing happened. We might have to
  1338. * do something here...
  1339. */
  1340. }
  1341. if (list_empty(&ep->queue))
  1342. /* Might happen if a reset comes along at the right moment */
  1343. return;
  1344. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1345. req = list_entry(ep->queue.next, struct usba_request, queue);
  1346. usba_update_req(ep, req, status);
  1347. list_del_init(&req->queue);
  1348. submit_next_request(ep);
  1349. request_complete(ep, req, 0);
  1350. }
  1351. }
  1352. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1353. {
  1354. struct usba_udc *udc = devid;
  1355. u32 status;
  1356. u32 dma_status;
  1357. u32 ep_status;
  1358. spin_lock(&udc->lock);
  1359. status = usba_readl(udc, INT_STA);
  1360. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1361. if (status & USBA_DET_SUSPEND) {
  1362. toggle_bias(0);
  1363. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1364. DBG(DBG_BUS, "Suspend detected\n");
  1365. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1366. && udc->driver && udc->driver->suspend) {
  1367. spin_unlock(&udc->lock);
  1368. udc->driver->suspend(&udc->gadget);
  1369. spin_lock(&udc->lock);
  1370. }
  1371. }
  1372. if (status & USBA_WAKE_UP) {
  1373. toggle_bias(1);
  1374. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1375. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1376. }
  1377. if (status & USBA_END_OF_RESUME) {
  1378. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1379. DBG(DBG_BUS, "Resume detected\n");
  1380. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1381. && udc->driver && udc->driver->resume) {
  1382. spin_unlock(&udc->lock);
  1383. udc->driver->resume(&udc->gadget);
  1384. spin_lock(&udc->lock);
  1385. }
  1386. }
  1387. dma_status = USBA_BFEXT(DMA_INT, status);
  1388. if (dma_status) {
  1389. int i;
  1390. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1391. if (dma_status & (1 << i))
  1392. usba_dma_irq(udc, &usba_ep[i]);
  1393. }
  1394. ep_status = USBA_BFEXT(EPT_INT, status);
  1395. if (ep_status) {
  1396. int i;
  1397. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1398. if (ep_status & (1 << i)) {
  1399. if (ep_is_control(&usba_ep[i]))
  1400. usba_control_irq(udc, &usba_ep[i]);
  1401. else
  1402. usba_ep_irq(udc, &usba_ep[i]);
  1403. }
  1404. }
  1405. if (status & USBA_END_OF_RESET) {
  1406. struct usba_ep *ep0;
  1407. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1408. reset_all_endpoints(udc);
  1409. if (status & USBA_HIGH_SPEED) {
  1410. DBG(DBG_BUS, "High-speed bus reset detected\n");
  1411. udc->gadget.speed = USB_SPEED_HIGH;
  1412. } else {
  1413. DBG(DBG_BUS, "Full-speed bus reset detected\n");
  1414. udc->gadget.speed = USB_SPEED_FULL;
  1415. }
  1416. ep0 = &usba_ep[0];
  1417. ep0->desc = &usba_ep0_desc;
  1418. ep0->state = WAIT_FOR_SETUP;
  1419. usba_ep_writel(ep0, CFG,
  1420. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1421. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1422. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1423. usba_ep_writel(ep0, CTL_ENB,
  1424. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1425. usba_writel(udc, INT_ENB,
  1426. (usba_readl(udc, INT_ENB)
  1427. | USBA_BF(EPT_INT, 1)
  1428. | USBA_DET_SUSPEND
  1429. | USBA_END_OF_RESUME));
  1430. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1431. dev_warn(&udc->pdev->dev,
  1432. "WARNING: EP0 configuration is invalid!\n");
  1433. }
  1434. spin_unlock(&udc->lock);
  1435. return IRQ_HANDLED;
  1436. }
  1437. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1438. {
  1439. struct usba_udc *udc = devid;
  1440. int vbus;
  1441. /* debounce */
  1442. udelay(10);
  1443. spin_lock(&udc->lock);
  1444. /* May happen if Vbus pin toggles during probe() */
  1445. if (!udc->driver)
  1446. goto out;
  1447. vbus = gpio_get_value(udc->vbus_pin);
  1448. if (vbus != udc->vbus_prev) {
  1449. if (vbus) {
  1450. toggle_bias(1);
  1451. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1452. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1453. } else {
  1454. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1455. reset_all_endpoints(udc);
  1456. toggle_bias(0);
  1457. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1458. spin_unlock(&udc->lock);
  1459. udc->driver->disconnect(&udc->gadget);
  1460. spin_lock(&udc->lock);
  1461. }
  1462. udc->vbus_prev = vbus;
  1463. }
  1464. out:
  1465. spin_unlock(&udc->lock);
  1466. return IRQ_HANDLED;
  1467. }
  1468. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1469. {
  1470. struct usba_udc *udc = &the_udc;
  1471. unsigned long flags;
  1472. int ret;
  1473. if (!udc->pdev)
  1474. return -ENODEV;
  1475. spin_lock_irqsave(&udc->lock, flags);
  1476. if (udc->driver) {
  1477. spin_unlock_irqrestore(&udc->lock, flags);
  1478. return -EBUSY;
  1479. }
  1480. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1481. udc->driver = driver;
  1482. udc->gadget.dev.driver = &driver->driver;
  1483. spin_unlock_irqrestore(&udc->lock, flags);
  1484. clk_enable(udc->pclk);
  1485. clk_enable(udc->hclk);
  1486. ret = driver->bind(&udc->gadget);
  1487. if (ret) {
  1488. DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
  1489. driver->driver.name, ret);
  1490. goto err_driver_bind;
  1491. }
  1492. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1493. udc->vbus_prev = 0;
  1494. if (udc->vbus_pin != -1)
  1495. enable_irq(gpio_to_irq(udc->vbus_pin));
  1496. /* If Vbus is present, enable the controller and wait for reset */
  1497. spin_lock_irqsave(&udc->lock, flags);
  1498. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1499. toggle_bias(1);
  1500. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1501. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1502. }
  1503. spin_unlock_irqrestore(&udc->lock, flags);
  1504. return 0;
  1505. err_driver_bind:
  1506. udc->driver = NULL;
  1507. udc->gadget.dev.driver = NULL;
  1508. return ret;
  1509. }
  1510. EXPORT_SYMBOL(usb_gadget_register_driver);
  1511. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1512. {
  1513. struct usba_udc *udc = &the_udc;
  1514. unsigned long flags;
  1515. if (!udc->pdev)
  1516. return -ENODEV;
  1517. if (driver != udc->driver)
  1518. return -EINVAL;
  1519. if (udc->vbus_pin != -1)
  1520. disable_irq(gpio_to_irq(udc->vbus_pin));
  1521. spin_lock_irqsave(&udc->lock, flags);
  1522. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1523. reset_all_endpoints(udc);
  1524. spin_unlock_irqrestore(&udc->lock, flags);
  1525. /* This will also disable the DP pullup */
  1526. toggle_bias(0);
  1527. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1528. driver->unbind(&udc->gadget);
  1529. udc->gadget.dev.driver = NULL;
  1530. udc->driver = NULL;
  1531. clk_disable(udc->hclk);
  1532. clk_disable(udc->pclk);
  1533. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1534. return 0;
  1535. }
  1536. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1537. static int __init usba_udc_probe(struct platform_device *pdev)
  1538. {
  1539. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1540. struct resource *regs, *fifo;
  1541. struct clk *pclk, *hclk;
  1542. struct usba_udc *udc = &the_udc;
  1543. int irq, ret, i;
  1544. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1545. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1546. if (!regs || !fifo || !pdata)
  1547. return -ENXIO;
  1548. irq = platform_get_irq(pdev, 0);
  1549. if (irq < 0)
  1550. return irq;
  1551. pclk = clk_get(&pdev->dev, "pclk");
  1552. if (IS_ERR(pclk))
  1553. return PTR_ERR(pclk);
  1554. hclk = clk_get(&pdev->dev, "hclk");
  1555. if (IS_ERR(hclk)) {
  1556. ret = PTR_ERR(hclk);
  1557. goto err_get_hclk;
  1558. }
  1559. udc->pdev = pdev;
  1560. udc->pclk = pclk;
  1561. udc->hclk = hclk;
  1562. udc->vbus_pin = -1;
  1563. ret = -ENOMEM;
  1564. udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
  1565. if (!udc->regs) {
  1566. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1567. goto err_map_regs;
  1568. }
  1569. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1570. (unsigned long)regs->start, udc->regs);
  1571. udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
  1572. if (!udc->fifo) {
  1573. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1574. goto err_map_fifo;
  1575. }
  1576. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1577. (unsigned long)fifo->start, udc->fifo);
  1578. device_initialize(&udc->gadget.dev);
  1579. udc->gadget.dev.parent = &pdev->dev;
  1580. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1581. platform_set_drvdata(pdev, udc);
  1582. /* Make sure we start from a clean slate */
  1583. clk_enable(pclk);
  1584. toggle_bias(0);
  1585. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1586. clk_disable(pclk);
  1587. usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
  1588. GFP_KERNEL);
  1589. if (!usba_ep)
  1590. goto err_alloc_ep;
  1591. the_udc.gadget.ep0 = &usba_ep[0].ep;
  1592. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1593. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1594. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1595. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1596. usba_ep[0].ep.ops = &usba_ep_ops;
  1597. usba_ep[0].ep.name = pdata->ep[0].name;
  1598. usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
  1599. usba_ep[0].udc = &the_udc;
  1600. INIT_LIST_HEAD(&usba_ep[0].queue);
  1601. usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
  1602. usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
  1603. usba_ep[0].index = pdata->ep[0].index;
  1604. usba_ep[0].can_dma = pdata->ep[0].can_dma;
  1605. usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
  1606. for (i = 1; i < pdata->num_ep; i++) {
  1607. struct usba_ep *ep = &usba_ep[i];
  1608. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1609. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1610. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1611. ep->ep.ops = &usba_ep_ops;
  1612. ep->ep.name = pdata->ep[i].name;
  1613. ep->ep.maxpacket = pdata->ep[i].fifo_size;
  1614. ep->udc = &the_udc;
  1615. INIT_LIST_HEAD(&ep->queue);
  1616. ep->fifo_size = pdata->ep[i].fifo_size;
  1617. ep->nr_banks = pdata->ep[i].nr_banks;
  1618. ep->index = pdata->ep[i].index;
  1619. ep->can_dma = pdata->ep[i].can_dma;
  1620. ep->can_isoc = pdata->ep[i].can_isoc;
  1621. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1622. }
  1623. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1624. if (ret) {
  1625. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1626. irq, ret);
  1627. goto err_request_irq;
  1628. }
  1629. udc->irq = irq;
  1630. ret = device_add(&udc->gadget.dev);
  1631. if (ret) {
  1632. dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
  1633. goto err_device_add;
  1634. }
  1635. if (pdata->vbus_pin >= 0) {
  1636. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1637. udc->vbus_pin = pdata->vbus_pin;
  1638. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1639. usba_vbus_irq, 0,
  1640. "atmel_usba_udc", udc);
  1641. if (ret) {
  1642. gpio_free(udc->vbus_pin);
  1643. udc->vbus_pin = -1;
  1644. dev_warn(&udc->pdev->dev,
  1645. "failed to request vbus irq; "
  1646. "assuming always on\n");
  1647. } else {
  1648. disable_irq(gpio_to_irq(udc->vbus_pin));
  1649. }
  1650. }
  1651. }
  1652. usba_init_debugfs(udc);
  1653. for (i = 1; i < pdata->num_ep; i++)
  1654. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1655. return 0;
  1656. err_device_add:
  1657. free_irq(irq, udc);
  1658. err_request_irq:
  1659. kfree(usba_ep);
  1660. err_alloc_ep:
  1661. iounmap(udc->fifo);
  1662. err_map_fifo:
  1663. iounmap(udc->regs);
  1664. err_map_regs:
  1665. clk_put(hclk);
  1666. err_get_hclk:
  1667. clk_put(pclk);
  1668. platform_set_drvdata(pdev, NULL);
  1669. return ret;
  1670. }
  1671. static int __exit usba_udc_remove(struct platform_device *pdev)
  1672. {
  1673. struct usba_udc *udc;
  1674. int i;
  1675. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1676. udc = platform_get_drvdata(pdev);
  1677. for (i = 1; i < pdata->num_ep; i++)
  1678. usba_ep_cleanup_debugfs(&usba_ep[i]);
  1679. usba_cleanup_debugfs(udc);
  1680. if (udc->vbus_pin != -1)
  1681. gpio_free(udc->vbus_pin);
  1682. free_irq(udc->irq, udc);
  1683. kfree(usba_ep);
  1684. iounmap(udc->fifo);
  1685. iounmap(udc->regs);
  1686. clk_put(udc->hclk);
  1687. clk_put(udc->pclk);
  1688. device_unregister(&udc->gadget.dev);
  1689. return 0;
  1690. }
  1691. static struct platform_driver udc_driver = {
  1692. .remove = __exit_p(usba_udc_remove),
  1693. .driver = {
  1694. .name = "atmel_usba_udc",
  1695. .owner = THIS_MODULE,
  1696. },
  1697. };
  1698. static int __init udc_init(void)
  1699. {
  1700. return platform_driver_probe(&udc_driver, usba_udc_probe);
  1701. }
  1702. module_init(udc_init);
  1703. static void __exit udc_exit(void)
  1704. {
  1705. platform_driver_unregister(&udc_driver);
  1706. }
  1707. module_exit(udc_exit);
  1708. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1709. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
  1710. MODULE_LICENSE("GPL");
  1711. MODULE_ALIAS("platform:atmel_usba_udc");