microcode_amd.c 8.0 KB

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  1. /*
  2. * AMD CPU Microcode Update Driver for Linux
  3. * Copyright (C) 2008 Advanced Micro Devices Inc.
  4. *
  5. * Author: Peter Oruba <peter.oruba@amd.com>
  6. *
  7. * Based on work by:
  8. * Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
  9. *
  10. * This driver allows to upgrade microcode on AMD
  11. * family 0x10 and 0x11 processors.
  12. *
  13. * Licensed under the terms of the GNU General Public
  14. * License version 2. See file COPYING for details.
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include <linux/firmware.h>
  18. #include <linux/pci_ids.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/vmalloc.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <asm/microcode.h>
  25. #include <asm/processor.h>
  26. #include <asm/msr.h>
  27. MODULE_DESCRIPTION("AMD Microcode Update Driver");
  28. MODULE_AUTHOR("Peter Oruba");
  29. MODULE_LICENSE("GPL v2");
  30. #define UCODE_MAGIC 0x00414d44
  31. #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
  32. #define UCODE_UCODE_TYPE 0x00000001
  33. struct equiv_cpu_entry {
  34. u32 installed_cpu;
  35. u32 fixed_errata_mask;
  36. u32 fixed_errata_compare;
  37. u16 equiv_cpu;
  38. u16 res;
  39. } __attribute__((packed));
  40. struct microcode_header_amd {
  41. u32 data_code;
  42. u32 patch_id;
  43. u16 mc_patch_data_id;
  44. u8 mc_patch_data_len;
  45. u8 init_flag;
  46. u32 mc_patch_data_checksum;
  47. u32 nb_dev_id;
  48. u32 sb_dev_id;
  49. u16 processor_rev_id;
  50. u8 nb_rev_id;
  51. u8 sb_rev_id;
  52. u8 bios_api_rev;
  53. u8 reserved1[3];
  54. u32 match_reg[8];
  55. } __attribute__((packed));
  56. struct microcode_amd {
  57. struct microcode_header_amd hdr;
  58. unsigned int mpb[0];
  59. };
  60. #define SECTION_HDR_SIZE 8
  61. #define CONTAINER_HDR_SZ 12
  62. static struct equiv_cpu_entry *equiv_cpu_table;
  63. /* page-sized ucode patch buffer */
  64. void *patch;
  65. static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
  66. {
  67. struct cpuinfo_x86 *c = &cpu_data(cpu);
  68. if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
  69. pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
  70. return -1;
  71. }
  72. csig->rev = c->microcode;
  73. pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
  74. return 0;
  75. }
  76. static int get_matching_microcode(int cpu, struct microcode_header_amd *mc_hdr,
  77. int rev)
  78. {
  79. unsigned int current_cpu_id;
  80. u16 equiv_cpu_id = 0;
  81. unsigned int i = 0;
  82. BUG_ON(equiv_cpu_table == NULL);
  83. current_cpu_id = cpuid_eax(0x00000001);
  84. while (equiv_cpu_table[i].installed_cpu != 0) {
  85. if (current_cpu_id == equiv_cpu_table[i].installed_cpu) {
  86. equiv_cpu_id = equiv_cpu_table[i].equiv_cpu;
  87. break;
  88. }
  89. i++;
  90. }
  91. if (!equiv_cpu_id)
  92. return 0;
  93. if (mc_hdr->processor_rev_id != equiv_cpu_id)
  94. return 0;
  95. /* ucode might be chipset specific -- currently we don't support this */
  96. if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
  97. pr_err("CPU%d: chipset specific code not yet supported\n",
  98. cpu);
  99. return 0;
  100. }
  101. if (mc_hdr->patch_id <= rev)
  102. return 0;
  103. return 1;
  104. }
  105. static int apply_microcode_amd(int cpu)
  106. {
  107. u32 rev, dummy;
  108. int cpu_num = raw_smp_processor_id();
  109. struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
  110. struct microcode_amd *mc_amd = uci->mc;
  111. struct cpuinfo_x86 *c = &cpu_data(cpu);
  112. /* We should bind the task to the CPU */
  113. BUG_ON(cpu_num != cpu);
  114. if (mc_amd == NULL)
  115. return 0;
  116. wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
  117. /* get patch id after patching */
  118. rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
  119. /* check current patch id and patch's id for match */
  120. if (rev != mc_amd->hdr.patch_id) {
  121. pr_err("CPU%d: update failed for patch_level=0x%08x\n",
  122. cpu, mc_amd->hdr.patch_id);
  123. return -1;
  124. }
  125. pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
  126. uci->cpu_sig.rev = rev;
  127. c->microcode = rev;
  128. return 0;
  129. }
  130. static unsigned int verify_ucode_size(int cpu, const u8 *buf, unsigned int size)
  131. {
  132. struct cpuinfo_x86 *c = &cpu_data(cpu);
  133. u32 max_size, actual_size;
  134. #define F1XH_MPB_MAX_SIZE 2048
  135. #define F14H_MPB_MAX_SIZE 1824
  136. #define F15H_MPB_MAX_SIZE 4096
  137. switch (c->x86) {
  138. case 0x14:
  139. max_size = F14H_MPB_MAX_SIZE;
  140. break;
  141. case 0x15:
  142. max_size = F15H_MPB_MAX_SIZE;
  143. break;
  144. default:
  145. max_size = F1XH_MPB_MAX_SIZE;
  146. break;
  147. }
  148. actual_size = *(u32 *)(buf + 4);
  149. if (actual_size + SECTION_HDR_SIZE > size || actual_size > max_size) {
  150. pr_err("section size mismatch\n");
  151. return 0;
  152. }
  153. return actual_size;
  154. }
  155. static struct microcode_header_amd *
  156. get_next_ucode(int cpu, const u8 *buf, unsigned int size, unsigned int *mc_size)
  157. {
  158. struct microcode_header_amd *mc = NULL;
  159. unsigned int actual_size = 0;
  160. if (*(u32 *)buf != UCODE_UCODE_TYPE) {
  161. pr_err("invalid type field in container file section header\n");
  162. goto out;
  163. }
  164. actual_size = verify_ucode_size(cpu, buf, size);
  165. if (!actual_size)
  166. goto out;
  167. mc = vzalloc(actual_size);
  168. if (!mc)
  169. goto out;
  170. get_ucode_data(mc, buf + SECTION_HDR_SIZE, actual_size);
  171. *mc_size = actual_size + SECTION_HDR_SIZE;
  172. out:
  173. return mc;
  174. }
  175. static int install_equiv_cpu_table(const u8 *buf)
  176. {
  177. unsigned int *ibuf = (unsigned int *)buf;
  178. unsigned int type = ibuf[1];
  179. unsigned int size = ibuf[2];
  180. if (type != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
  181. pr_err("empty section/"
  182. "invalid type field in container file section header\n");
  183. return -EINVAL;
  184. }
  185. equiv_cpu_table = vmalloc(size);
  186. if (!equiv_cpu_table) {
  187. pr_err("failed to allocate equivalent CPU table\n");
  188. return -ENOMEM;
  189. }
  190. get_ucode_data(equiv_cpu_table, buf + CONTAINER_HDR_SZ, size);
  191. /* add header length */
  192. return size + CONTAINER_HDR_SZ;
  193. }
  194. static void free_equiv_cpu_table(void)
  195. {
  196. vfree(equiv_cpu_table);
  197. equiv_cpu_table = NULL;
  198. }
  199. static enum ucode_state
  200. generic_load_microcode(int cpu, const u8 *data, size_t size)
  201. {
  202. struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
  203. struct microcode_header_amd *mc_hdr = NULL;
  204. unsigned int mc_size, leftover;
  205. int offset;
  206. const u8 *ucode_ptr = data;
  207. void *new_mc = NULL;
  208. unsigned int new_rev = uci->cpu_sig.rev;
  209. enum ucode_state state = UCODE_OK;
  210. offset = install_equiv_cpu_table(ucode_ptr);
  211. if (offset < 0) {
  212. pr_err("failed to create equivalent cpu table\n");
  213. return UCODE_ERROR;
  214. }
  215. ucode_ptr += offset;
  216. leftover = size - offset;
  217. while (leftover) {
  218. mc_hdr = get_next_ucode(cpu, ucode_ptr, leftover, &mc_size);
  219. if (!mc_hdr)
  220. break;
  221. if (get_matching_microcode(cpu, mc_hdr, new_rev)) {
  222. vfree(new_mc);
  223. new_rev = mc_hdr->patch_id;
  224. new_mc = mc_hdr;
  225. } else
  226. vfree(mc_hdr);
  227. ucode_ptr += mc_size;
  228. leftover -= mc_size;
  229. }
  230. if (!new_mc) {
  231. state = UCODE_NFOUND;
  232. goto free_table;
  233. }
  234. if (!leftover) {
  235. vfree(uci->mc);
  236. uci->mc = new_mc;
  237. pr_debug("CPU%d update ucode (0x%08x -> 0x%08x)\n",
  238. cpu, uci->cpu_sig.rev, new_rev);
  239. } else {
  240. vfree(new_mc);
  241. state = UCODE_ERROR;
  242. }
  243. free_table:
  244. free_equiv_cpu_table();
  245. return state;
  246. }
  247. static enum ucode_state request_microcode_amd(int cpu, struct device *device)
  248. {
  249. const char *fw_name = "amd-ucode/microcode_amd.bin";
  250. const struct firmware *fw;
  251. enum ucode_state ret = UCODE_NFOUND;
  252. if (request_firmware(&fw, fw_name, device)) {
  253. pr_err("failed to load file %s\n", fw_name);
  254. goto out;
  255. }
  256. ret = UCODE_ERROR;
  257. if (*(u32 *)fw->data != UCODE_MAGIC) {
  258. pr_err("invalid magic value (0x%08x)\n", *(u32 *)fw->data);
  259. goto fw_release;
  260. }
  261. ret = generic_load_microcode(cpu, fw->data, fw->size);
  262. fw_release:
  263. release_firmware(fw);
  264. out:
  265. return ret;
  266. }
  267. static enum ucode_state
  268. request_microcode_user(int cpu, const void __user *buf, size_t size)
  269. {
  270. pr_info("AMD microcode update via /dev/cpu/microcode not supported\n");
  271. return UCODE_ERROR;
  272. }
  273. static void microcode_fini_cpu_amd(int cpu)
  274. {
  275. struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
  276. vfree(uci->mc);
  277. uci->mc = NULL;
  278. }
  279. static struct microcode_ops microcode_amd_ops = {
  280. .request_microcode_user = request_microcode_user,
  281. .request_microcode_fw = request_microcode_amd,
  282. .collect_cpu_info = collect_cpu_info_amd,
  283. .apply_microcode = apply_microcode_amd,
  284. .microcode_fini_cpu = microcode_fini_cpu_amd,
  285. };
  286. struct microcode_ops * __init init_amd_microcode(void)
  287. {
  288. patch = (void *)get_zeroed_page(GFP_KERNEL);
  289. if (!patch)
  290. return NULL;
  291. return &microcode_amd_ops;
  292. }
  293. void __exit exit_amd_microcode(void)
  294. {
  295. free_page((unsigned long)patch);
  296. }