netxen_nic_init.c 40 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551
  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. unsigned long last_schedule_time;
  43. #define NETXEN_MAX_CRB_XFORM 60
  44. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  45. #define NETXEN_ADDR_ERROR (0xffffffff)
  46. #define crb_addr_transform(name) \
  47. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  48. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  49. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  50. static inline void
  51. netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  52. unsigned long off, int *data)
  53. {
  54. void __iomem *addr = pci_base_offset(adapter, off);
  55. writel(*data, addr);
  56. }
  57. static void crb_addr_transform_setup(void)
  58. {
  59. crb_addr_transform(XDMA);
  60. crb_addr_transform(TIMR);
  61. crb_addr_transform(SRE);
  62. crb_addr_transform(SQN3);
  63. crb_addr_transform(SQN2);
  64. crb_addr_transform(SQN1);
  65. crb_addr_transform(SQN0);
  66. crb_addr_transform(SQS3);
  67. crb_addr_transform(SQS2);
  68. crb_addr_transform(SQS1);
  69. crb_addr_transform(SQS0);
  70. crb_addr_transform(RPMX7);
  71. crb_addr_transform(RPMX6);
  72. crb_addr_transform(RPMX5);
  73. crb_addr_transform(RPMX4);
  74. crb_addr_transform(RPMX3);
  75. crb_addr_transform(RPMX2);
  76. crb_addr_transform(RPMX1);
  77. crb_addr_transform(RPMX0);
  78. crb_addr_transform(ROMUSB);
  79. crb_addr_transform(SN);
  80. crb_addr_transform(QMN);
  81. crb_addr_transform(QMS);
  82. crb_addr_transform(PGNI);
  83. crb_addr_transform(PGND);
  84. crb_addr_transform(PGN3);
  85. crb_addr_transform(PGN2);
  86. crb_addr_transform(PGN1);
  87. crb_addr_transform(PGN0);
  88. crb_addr_transform(PGSI);
  89. crb_addr_transform(PGSD);
  90. crb_addr_transform(PGS3);
  91. crb_addr_transform(PGS2);
  92. crb_addr_transform(PGS1);
  93. crb_addr_transform(PGS0);
  94. crb_addr_transform(PS);
  95. crb_addr_transform(PH);
  96. crb_addr_transform(NIU);
  97. crb_addr_transform(I2Q);
  98. crb_addr_transform(EG);
  99. crb_addr_transform(MN);
  100. crb_addr_transform(MS);
  101. crb_addr_transform(CAS2);
  102. crb_addr_transform(CAS1);
  103. crb_addr_transform(CAS0);
  104. crb_addr_transform(CAM);
  105. crb_addr_transform(C2C1);
  106. crb_addr_transform(C2C0);
  107. crb_addr_transform(SMB);
  108. }
  109. int netxen_init_firmware(struct netxen_adapter *adapter)
  110. {
  111. u32 state = 0, loops = 0, err = 0;
  112. /* Window 1 call */
  113. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  114. if (state == PHAN_INITIALIZE_ACK)
  115. return 0;
  116. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  117. udelay(100);
  118. /* Window 1 call */
  119. state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  120. loops++;
  121. }
  122. if (loops >= 2000) {
  123. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  124. state);
  125. err = -EIO;
  126. return err;
  127. }
  128. /* Window 1 call */
  129. writel(INTR_SCHEME_PERPORT,
  130. NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_HOST));
  131. writel(MPORT_MULTI_FUNCTION_MODE,
  132. NETXEN_CRB_NORMALIZE(adapter, CRB_MPORT_MODE));
  133. writel(PHAN_INITIALIZE_ACK,
  134. NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_STATE));
  135. return err;
  136. }
  137. #define NETXEN_ADDR_LIMIT 0xffffffffULL
  138. void *netxen_alloc(struct pci_dev *pdev, size_t sz, dma_addr_t * ptr,
  139. struct pci_dev **used_dev)
  140. {
  141. void *addr;
  142. addr = pci_alloc_consistent(pdev, sz, ptr);
  143. if ((unsigned long long)(*ptr) < NETXEN_ADDR_LIMIT) {
  144. *used_dev = pdev;
  145. return addr;
  146. }
  147. pci_free_consistent(pdev, sz, addr, *ptr);
  148. addr = pci_alloc_consistent(NULL, sz, ptr);
  149. *used_dev = NULL;
  150. return addr;
  151. }
  152. void netxen_initialize_adapter_sw(struct netxen_adapter *adapter)
  153. {
  154. int ctxid, ring;
  155. u32 i;
  156. u32 num_rx_bufs = 0;
  157. struct netxen_rcv_desc_ctx *rcv_desc;
  158. DPRINTK(INFO, "initializing some queues: %p\n", adapter);
  159. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  160. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  161. struct netxen_rx_buffer *rx_buf;
  162. rcv_desc = &adapter->recv_ctx[ctxid].rcv_desc[ring];
  163. rcv_desc->rcv_free = rcv_desc->max_rx_desc_count;
  164. rcv_desc->begin_alloc = 0;
  165. rx_buf = rcv_desc->rx_buf_arr;
  166. num_rx_bufs = rcv_desc->max_rx_desc_count;
  167. /*
  168. * Now go through all of them, set reference handles
  169. * and put them in the queues.
  170. */
  171. for (i = 0; i < num_rx_bufs; i++) {
  172. rx_buf->ref_handle = i;
  173. rx_buf->state = NETXEN_BUFFER_FREE;
  174. DPRINTK(INFO, "Rx buf:ctx%d i(%d) rx_buf:"
  175. "%p\n", ctxid, i, rx_buf);
  176. rx_buf++;
  177. }
  178. }
  179. }
  180. }
  181. void netxen_initialize_adapter_hw(struct netxen_adapter *adapter)
  182. {
  183. int ports = 0;
  184. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  185. if (netxen_nic_get_board_info(adapter) != 0)
  186. printk("%s: Error getting board config info.\n",
  187. netxen_nic_driver_name);
  188. get_brd_port_by_type(board_info->board_type, &ports);
  189. if (ports == 0)
  190. printk(KERN_ERR "%s: Unknown board type\n",
  191. netxen_nic_driver_name);
  192. adapter->ahw.max_ports = ports;
  193. }
  194. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  195. {
  196. switch (adapter->ahw.board_type) {
  197. case NETXEN_NIC_GBE:
  198. adapter->enable_phy_interrupts =
  199. netxen_niu_gbe_enable_phy_interrupts;
  200. adapter->disable_phy_interrupts =
  201. netxen_niu_gbe_disable_phy_interrupts;
  202. adapter->handle_phy_intr = netxen_nic_gbe_handle_phy_intr;
  203. adapter->macaddr_set = netxen_niu_macaddr_set;
  204. adapter->set_mtu = netxen_nic_set_mtu_gb;
  205. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  206. adapter->unset_promisc = netxen_niu_set_promiscuous_mode;
  207. adapter->phy_read = netxen_niu_gbe_phy_read;
  208. adapter->phy_write = netxen_niu_gbe_phy_write;
  209. adapter->init_niu = netxen_nic_init_niu_gb;
  210. adapter->stop_port = netxen_niu_disable_gbe_port;
  211. break;
  212. case NETXEN_NIC_XGBE:
  213. adapter->enable_phy_interrupts =
  214. netxen_niu_xgbe_enable_phy_interrupts;
  215. adapter->disable_phy_interrupts =
  216. netxen_niu_xgbe_disable_phy_interrupts;
  217. adapter->handle_phy_intr = netxen_nic_xgbe_handle_phy_intr;
  218. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  219. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  220. adapter->init_port = netxen_niu_xg_init_port;
  221. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  222. adapter->unset_promisc = netxen_niu_xg_set_promiscuous_mode;
  223. adapter->stop_port = netxen_niu_disable_xg_port;
  224. break;
  225. default:
  226. break;
  227. }
  228. }
  229. /*
  230. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  231. * address to external PCI CRB address.
  232. */
  233. u32 netxen_decode_crb_addr(u32 addr)
  234. {
  235. int i;
  236. u32 base_addr, offset, pci_base;
  237. crb_addr_transform_setup();
  238. pci_base = NETXEN_ADDR_ERROR;
  239. base_addr = addr & 0xfff00000;
  240. offset = addr & 0x000fffff;
  241. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  242. if (crb_addr_xform[i] == base_addr) {
  243. pci_base = i << 20;
  244. break;
  245. }
  246. }
  247. if (pci_base == NETXEN_ADDR_ERROR)
  248. return pci_base;
  249. else
  250. return (pci_base + offset);
  251. }
  252. static long rom_max_timeout = 100;
  253. static long rom_lock_timeout = 10000;
  254. static long rom_write_timeout = 700;
  255. static inline int rom_lock(struct netxen_adapter *adapter)
  256. {
  257. int iter;
  258. u32 done = 0;
  259. int timeout = 0;
  260. while (!done) {
  261. /* acquire semaphore2 from PCI HW block */
  262. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  263. &done);
  264. if (done == 1)
  265. break;
  266. if (timeout >= rom_lock_timeout)
  267. return -EIO;
  268. timeout++;
  269. /*
  270. * Yield CPU
  271. */
  272. if (!in_atomic())
  273. schedule();
  274. else {
  275. for (iter = 0; iter < 20; iter++)
  276. cpu_relax(); /*This a nop instr on i386 */
  277. }
  278. }
  279. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  280. return 0;
  281. }
  282. int netxen_wait_rom_done(struct netxen_adapter *adapter)
  283. {
  284. long timeout = 0;
  285. long done = 0;
  286. while (done == 0) {
  287. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  288. done &= 2;
  289. timeout++;
  290. if (timeout >= rom_max_timeout) {
  291. printk("Timeout reached waiting for rom done");
  292. return -EIO;
  293. }
  294. }
  295. return 0;
  296. }
  297. static inline int netxen_rom_wren(struct netxen_adapter *adapter)
  298. {
  299. /* Set write enable latch in ROM status register */
  300. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  301. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  302. M25P_INSTR_WREN);
  303. if (netxen_wait_rom_done(adapter)) {
  304. return -1;
  305. }
  306. return 0;
  307. }
  308. static inline unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  309. unsigned int addr)
  310. {
  311. unsigned int data = 0xdeaddead;
  312. data = netxen_nic_reg_read(adapter, addr);
  313. return data;
  314. }
  315. static inline int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  316. {
  317. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  318. M25P_INSTR_RDSR);
  319. if (netxen_wait_rom_done(adapter)) {
  320. return -1;
  321. }
  322. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  323. }
  324. static inline void netxen_rom_unlock(struct netxen_adapter *adapter)
  325. {
  326. u32 val;
  327. /* release semaphore2 */
  328. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  329. }
  330. int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  331. {
  332. long timeout = 0;
  333. long wip = 1;
  334. int val;
  335. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  336. while (wip != 0) {
  337. val = netxen_do_rom_rdsr(adapter);
  338. wip = val & 1;
  339. timeout++;
  340. if (timeout > rom_max_timeout) {
  341. return -1;
  342. }
  343. }
  344. return 0;
  345. }
  346. static inline int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  347. int data)
  348. {
  349. if (netxen_rom_wren(adapter)) {
  350. return -1;
  351. }
  352. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  353. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  354. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  355. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  356. M25P_INSTR_PP);
  357. if (netxen_wait_rom_done(adapter)) {
  358. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  359. return -1;
  360. }
  361. return netxen_rom_wip_poll(adapter);
  362. }
  363. static inline int
  364. do_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  365. {
  366. cond_resched();
  367. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  368. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  369. udelay(100); /* prevent bursting on CRB */
  370. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  371. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  372. if (netxen_wait_rom_done(adapter)) {
  373. printk("Error waiting for rom done\n");
  374. return -EIO;
  375. }
  376. /* reset abyte_cnt and dummy_byte_cnt */
  377. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  378. udelay(100); /* prevent bursting on CRB */
  379. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  380. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  381. return 0;
  382. }
  383. static inline int
  384. do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  385. u8 *bytes, size_t size)
  386. {
  387. int addridx;
  388. int ret = 0;
  389. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  390. ret = do_rom_fast_read(adapter, addridx, (int *)bytes);
  391. if (ret != 0)
  392. break;
  393. *(int *)bytes = cpu_to_le32(*(int *)bytes);
  394. bytes += 4;
  395. }
  396. return ret;
  397. }
  398. int
  399. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  400. u8 *bytes, size_t size)
  401. {
  402. int ret;
  403. ret = rom_lock(adapter);
  404. if (ret < 0)
  405. return ret;
  406. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  407. netxen_rom_unlock(adapter);
  408. return ret;
  409. }
  410. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  411. {
  412. int ret;
  413. if (rom_lock(adapter) != 0)
  414. return -EIO;
  415. ret = do_rom_fast_read(adapter, addr, valp);
  416. netxen_rom_unlock(adapter);
  417. return ret;
  418. }
  419. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  420. {
  421. int ret = 0;
  422. if (rom_lock(adapter) != 0) {
  423. return -1;
  424. }
  425. ret = do_rom_fast_write(adapter, addr, data);
  426. netxen_rom_unlock(adapter);
  427. return ret;
  428. }
  429. static inline int do_rom_fast_write_words(struct netxen_adapter *adapter,
  430. int addr, u8 *bytes, size_t size)
  431. {
  432. int addridx = addr;
  433. int ret = 0;
  434. while (addridx < (addr + size)) {
  435. int last_attempt = 0;
  436. int timeout = 0;
  437. int data;
  438. data = le32_to_cpu((*(u32*)bytes));
  439. ret = do_rom_fast_write(adapter, addridx, data);
  440. if (ret < 0)
  441. return ret;
  442. while(1) {
  443. int data1;
  444. ret = do_rom_fast_read(adapter, addridx, &data1);
  445. if (ret < 0)
  446. return ret;
  447. if (data1 == data)
  448. break;
  449. if (timeout++ >= rom_write_timeout) {
  450. if (last_attempt++ < 4) {
  451. ret = do_rom_fast_write(adapter,
  452. addridx, data);
  453. if (ret < 0)
  454. return ret;
  455. }
  456. else {
  457. printk(KERN_INFO "Data write did not "
  458. "succeed at address 0x%x\n", addridx);
  459. break;
  460. }
  461. }
  462. }
  463. bytes += 4;
  464. addridx += 4;
  465. }
  466. return ret;
  467. }
  468. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  469. u8 *bytes, size_t size)
  470. {
  471. int ret = 0;
  472. ret = rom_lock(adapter);
  473. if (ret < 0)
  474. return ret;
  475. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  476. netxen_rom_unlock(adapter);
  477. return ret;
  478. }
  479. int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  480. {
  481. int ret;
  482. ret = netxen_rom_wren(adapter);
  483. if (ret < 0)
  484. return ret;
  485. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  486. netxen_crb_writelit_adapter(adapter,
  487. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  488. ret = netxen_wait_rom_done(adapter);
  489. if (ret < 0)
  490. return ret;
  491. return netxen_rom_wip_poll(adapter);
  492. }
  493. int netxen_rom_rdsr(struct netxen_adapter *adapter)
  494. {
  495. int ret;
  496. ret = rom_lock(adapter);
  497. if (ret < 0)
  498. return ret;
  499. ret = netxen_do_rom_rdsr(adapter);
  500. netxen_rom_unlock(adapter);
  501. return ret;
  502. }
  503. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  504. {
  505. int ret = FLASH_SUCCESS;
  506. int val;
  507. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  508. if (!buffer)
  509. return -ENOMEM;
  510. /* unlock sector 63 */
  511. val = netxen_rom_rdsr(adapter);
  512. val = val & 0xe3;
  513. ret = netxen_rom_wrsr(adapter, val);
  514. if (ret != FLASH_SUCCESS)
  515. goto out_kfree;
  516. ret = netxen_rom_wip_poll(adapter);
  517. if (ret != FLASH_SUCCESS)
  518. goto out_kfree;
  519. /* copy sector 0 to sector 63 */
  520. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  521. buffer, NETXEN_FLASH_SECTOR_SIZE);
  522. if (ret != FLASH_SUCCESS)
  523. goto out_kfree;
  524. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  525. buffer, NETXEN_FLASH_SECTOR_SIZE);
  526. if (ret != FLASH_SUCCESS)
  527. goto out_kfree;
  528. /* lock sector 63 */
  529. val = netxen_rom_rdsr(adapter);
  530. if (!(val & 0x8)) {
  531. val |= (0x1 << 2);
  532. /* lock sector 63 */
  533. if (netxen_rom_wrsr(adapter, val) == 0) {
  534. ret = netxen_rom_wip_poll(adapter);
  535. if (ret != FLASH_SUCCESS)
  536. goto out_kfree;
  537. /* lock SR writes */
  538. ret = netxen_rom_wip_poll(adapter);
  539. if (ret != FLASH_SUCCESS)
  540. goto out_kfree;
  541. }
  542. }
  543. out_kfree:
  544. kfree(buffer);
  545. return ret;
  546. }
  547. int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  548. {
  549. netxen_rom_wren(adapter);
  550. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  551. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  552. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  553. M25P_INSTR_SE);
  554. if (netxen_wait_rom_done(adapter)) {
  555. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  556. return -1;
  557. }
  558. return netxen_rom_wip_poll(adapter);
  559. }
  560. void check_erased_flash(struct netxen_adapter *adapter, int addr)
  561. {
  562. int i;
  563. int val;
  564. int count = 0, erased_errors = 0;
  565. int range;
  566. range = (addr == NETXEN_USER_START) ?
  567. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  568. for (i = addr; i < range; i += 4) {
  569. netxen_rom_fast_read(adapter, i, &val);
  570. if (val != 0xffffffff)
  571. erased_errors++;
  572. count++;
  573. }
  574. if (erased_errors)
  575. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  576. "for sector address: %x\n", erased_errors, count, addr);
  577. }
  578. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  579. {
  580. int ret = 0;
  581. if (rom_lock(adapter) != 0) {
  582. return -1;
  583. }
  584. ret = netxen_do_rom_se(adapter, addr);
  585. netxen_rom_unlock(adapter);
  586. msleep(30);
  587. check_erased_flash(adapter, addr);
  588. return ret;
  589. }
  590. int
  591. netxen_flash_erase_sections(struct netxen_adapter *adapter, int start, int end)
  592. {
  593. int ret = FLASH_SUCCESS;
  594. int i;
  595. for (i = start; i < end; i++) {
  596. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  597. if (ret)
  598. break;
  599. ret = netxen_rom_wip_poll(adapter);
  600. if (ret < 0)
  601. return ret;
  602. }
  603. return ret;
  604. }
  605. int
  606. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  607. {
  608. int ret = FLASH_SUCCESS;
  609. int start, end;
  610. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  611. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  612. ret = netxen_flash_erase_sections(adapter, start, end);
  613. return ret;
  614. }
  615. int
  616. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  617. {
  618. int ret = FLASH_SUCCESS;
  619. int start, end;
  620. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  621. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  622. ret = netxen_flash_erase_sections(adapter, start, end);
  623. return ret;
  624. }
  625. void netxen_halt_pegs(struct netxen_adapter *adapter)
  626. {
  627. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  628. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  629. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  630. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  631. }
  632. int netxen_flash_unlock(struct netxen_adapter *adapter)
  633. {
  634. int ret = 0;
  635. ret = netxen_rom_wrsr(adapter, 0);
  636. if (ret < 0)
  637. return ret;
  638. ret = netxen_rom_wren(adapter);
  639. if (ret < 0)
  640. return ret;
  641. return ret;
  642. }
  643. #define NETXEN_BOARDTYPE 0x4008
  644. #define NETXEN_BOARDNUM 0x400c
  645. #define NETXEN_CHIPNUM 0x4010
  646. #define NETXEN_ROMBUS_RESET 0xFFFFFFFF
  647. #define NETXEN_ROM_FIRST_BARRIER 0x800000000ULL
  648. #define NETXEN_ROM_FOUND_INIT 0x400
  649. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  650. {
  651. int addr, val, status;
  652. int n, i;
  653. int init_delay = 0;
  654. struct crb_addr_pair *buf;
  655. u32 off;
  656. /* resetall */
  657. status = netxen_nic_get_board_info(adapter);
  658. if (status)
  659. printk("%s: netxen_pinit_from_rom: Error getting board info\n",
  660. netxen_nic_driver_name);
  661. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  662. NETXEN_ROMBUS_RESET);
  663. if (verbose) {
  664. int val;
  665. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  666. printk("P2 ROM board type: 0x%08x\n", val);
  667. else
  668. printk("Could not read board type\n");
  669. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  670. printk("P2 ROM board num: 0x%08x\n", val);
  671. else
  672. printk("Could not read board number\n");
  673. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  674. printk("P2 ROM chip num: 0x%08x\n", val);
  675. else
  676. printk("Could not read chip number\n");
  677. }
  678. if (netxen_rom_fast_read(adapter, 0, &n) == 0
  679. && (n & NETXEN_ROM_FIRST_BARRIER)) {
  680. n &= ~NETXEN_ROM_ROUNDUP;
  681. if (n < NETXEN_ROM_FOUND_INIT) {
  682. if (verbose)
  683. printk("%s: %d CRB init values found"
  684. " in ROM.\n", netxen_nic_driver_name, n);
  685. } else {
  686. printk("%s:n=0x%x Error! NetXen card flash not"
  687. " initialized.\n", __FUNCTION__, n);
  688. return -EIO;
  689. }
  690. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  691. if (buf == NULL) {
  692. printk("%s: netxen_pinit_from_rom: Unable to calloc "
  693. "memory.\n", netxen_nic_driver_name);
  694. return -ENOMEM;
  695. }
  696. for (i = 0; i < n; i++) {
  697. if (netxen_rom_fast_read(adapter, 8 * i + 4, &val) != 0
  698. || netxen_rom_fast_read(adapter, 8 * i + 8,
  699. &addr) != 0)
  700. return -EIO;
  701. buf[i].addr = addr;
  702. buf[i].data = val;
  703. if (verbose)
  704. printk("%s: PCI: 0x%08x == 0x%08x\n",
  705. netxen_nic_driver_name, (unsigned int)
  706. netxen_decode_crb_addr(addr), val);
  707. }
  708. for (i = 0; i < n; i++) {
  709. off = netxen_decode_crb_addr(buf[i].addr);
  710. if (off == NETXEN_ADDR_ERROR) {
  711. printk(KERN_ERR"CRB init value out of range %x\n",
  712. buf[i].addr);
  713. continue;
  714. }
  715. off += NETXEN_PCI_CRBSPACE;
  716. /* skipping cold reboot MAGIC */
  717. if (off == NETXEN_CAM_RAM(0x1fc))
  718. continue;
  719. /* After writing this register, HW needs time for CRB */
  720. /* to quiet down (else crb_window returns 0xffffffff) */
  721. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  722. init_delay = 1;
  723. /* hold xdma in reset also */
  724. buf[i].data = NETXEN_NIC_XDMA_RESET;
  725. }
  726. if (ADDR_IN_WINDOW1(off)) {
  727. writel(buf[i].data,
  728. NETXEN_CRB_NORMALIZE(adapter, off));
  729. } else {
  730. netxen_nic_pci_change_crbwindow(adapter, 0);
  731. writel(buf[i].data,
  732. pci_base_offset(adapter, off));
  733. netxen_nic_pci_change_crbwindow(adapter, 1);
  734. }
  735. if (init_delay == 1) {
  736. msleep(2000);
  737. init_delay = 0;
  738. }
  739. msleep(20);
  740. }
  741. kfree(buf);
  742. /* disable_peg_cache_all */
  743. /* unreset_net_cache */
  744. netxen_nic_hw_read_wx(adapter, NETXEN_ROMUSB_GLB_SW_RESET, &val,
  745. 4);
  746. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  747. (val & 0xffffff0f));
  748. /* p2dn replyCount */
  749. netxen_crb_writelit_adapter(adapter,
  750. NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  751. /* disable_peg_cache 0 */
  752. netxen_crb_writelit_adapter(adapter,
  753. NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  754. /* disable_peg_cache 1 */
  755. netxen_crb_writelit_adapter(adapter,
  756. NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  757. /* peg_clr_all */
  758. /* peg_clr 0 */
  759. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8,
  760. 0);
  761. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc,
  762. 0);
  763. /* peg_clr 1 */
  764. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8,
  765. 0);
  766. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc,
  767. 0);
  768. /* peg_clr 2 */
  769. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8,
  770. 0);
  771. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc,
  772. 0);
  773. /* peg_clr 3 */
  774. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8,
  775. 0);
  776. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc,
  777. 0);
  778. }
  779. return 0;
  780. }
  781. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  782. {
  783. uint64_t addr;
  784. uint32_t hi;
  785. uint32_t lo;
  786. adapter->dummy_dma.addr =
  787. pci_alloc_consistent(adapter->ahw.pdev,
  788. NETXEN_HOST_DUMMY_DMA_SIZE,
  789. &adapter->dummy_dma.phys_addr);
  790. if (adapter->dummy_dma.addr == NULL) {
  791. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  792. __FUNCTION__);
  793. return -ENOMEM;
  794. }
  795. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  796. hi = (addr >> 32) & 0xffffffff;
  797. lo = addr & 0xffffffff;
  798. writel(hi, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI));
  799. writel(lo, NETXEN_CRB_NORMALIZE(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO));
  800. return 0;
  801. }
  802. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  803. {
  804. if (adapter->dummy_dma.addr) {
  805. pci_free_consistent(adapter->ahw.pdev,
  806. NETXEN_HOST_DUMMY_DMA_SIZE,
  807. adapter->dummy_dma.addr,
  808. adapter->dummy_dma.phys_addr);
  809. adapter->dummy_dma.addr = NULL;
  810. }
  811. }
  812. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  813. {
  814. u32 val = 0;
  815. int retries = 30;
  816. if (!pegtune_val) {
  817. do {
  818. val = readl(NETXEN_CRB_NORMALIZE
  819. (adapter, CRB_CMDPEG_STATE));
  820. pegtune_val = readl(NETXEN_CRB_NORMALIZE
  821. (adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE));
  822. if (val == PHAN_INITIALIZE_COMPLETE ||
  823. val == PHAN_INITIALIZE_ACK)
  824. return 0;
  825. msleep(1000);
  826. } while (--retries);
  827. if (!retries) {
  828. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  829. "pegtune_val=%x\n", pegtune_val);
  830. return -1;
  831. }
  832. }
  833. return 0;
  834. }
  835. int netxen_nic_rx_has_work(struct netxen_adapter *adapter)
  836. {
  837. int ctx;
  838. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  839. struct netxen_recv_context *recv_ctx =
  840. &(adapter->recv_ctx[ctx]);
  841. u32 consumer;
  842. struct status_desc *desc_head;
  843. struct status_desc *desc;
  844. consumer = recv_ctx->status_rx_consumer;
  845. desc_head = recv_ctx->rcv_status_desc_head;
  846. desc = &desc_head[consumer];
  847. if (netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)
  848. return 1;
  849. }
  850. return 0;
  851. }
  852. static inline int netxen_nic_check_temp(struct netxen_adapter *adapter)
  853. {
  854. struct net_device *netdev = adapter->netdev;
  855. uint32_t temp, temp_state, temp_val;
  856. int rv = 0;
  857. temp = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_TEMP_STATE));
  858. temp_state = nx_get_temp_state(temp);
  859. temp_val = nx_get_temp_val(temp);
  860. if (temp_state == NX_TEMP_PANIC) {
  861. printk(KERN_ALERT
  862. "%s: Device temperature %d degrees C exceeds"
  863. " maximum allowed. Hardware has been shut down.\n",
  864. netxen_nic_driver_name, temp_val);
  865. netif_carrier_off(netdev);
  866. netif_stop_queue(netdev);
  867. rv = 1;
  868. } else if (temp_state == NX_TEMP_WARN) {
  869. if (adapter->temp == NX_TEMP_NORMAL) {
  870. printk(KERN_ALERT
  871. "%s: Device temperature %d degrees C "
  872. "exceeds operating range."
  873. " Immediate action needed.\n",
  874. netxen_nic_driver_name, temp_val);
  875. }
  876. } else {
  877. if (adapter->temp == NX_TEMP_WARN) {
  878. printk(KERN_INFO
  879. "%s: Device temperature is now %d degrees C"
  880. " in normal range.\n", netxen_nic_driver_name,
  881. temp_val);
  882. }
  883. }
  884. adapter->temp = temp_state;
  885. return rv;
  886. }
  887. void netxen_watchdog_task(struct work_struct *work)
  888. {
  889. struct net_device *netdev;
  890. struct netxen_adapter *adapter =
  891. container_of(work, struct netxen_adapter, watchdog_task);
  892. if ((adapter->portnum == 0) && netxen_nic_check_temp(adapter))
  893. return;
  894. if (adapter->handle_phy_intr)
  895. adapter->handle_phy_intr(adapter);
  896. netdev = adapter->netdev;
  897. if ((netif_running(netdev)) && !netif_carrier_ok(netdev) &&
  898. netxen_nic_link_ok(adapter) ) {
  899. printk(KERN_INFO "%s %s (port %d), Link is up\n",
  900. netxen_nic_driver_name, netdev->name, adapter->portnum);
  901. netif_carrier_on(netdev);
  902. netif_wake_queue(netdev);
  903. } else if(!(netif_running(netdev)) && netif_carrier_ok(netdev)) {
  904. printk(KERN_ERR "%s %s Link is Down\n",
  905. netxen_nic_driver_name, netdev->name);
  906. netif_carrier_off(netdev);
  907. netif_stop_queue(netdev);
  908. }
  909. mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
  910. }
  911. /*
  912. * netxen_process_rcv() send the received packet to the protocol stack.
  913. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  914. * invoke the routine to send more rx buffers to the Phantom...
  915. */
  916. void
  917. netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  918. struct status_desc *desc)
  919. {
  920. struct pci_dev *pdev = adapter->pdev;
  921. struct net_device *netdev = adapter->netdev;
  922. int index = netxen_get_sts_refhandle(desc);
  923. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  924. struct netxen_rx_buffer *buffer;
  925. struct sk_buff *skb;
  926. u32 length = netxen_get_sts_totallength(desc);
  927. u32 desc_ctx;
  928. struct netxen_rcv_desc_ctx *rcv_desc;
  929. int ret;
  930. desc_ctx = netxen_get_sts_type(desc);
  931. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  932. printk("%s: %s Bad Rcv descriptor ring\n",
  933. netxen_nic_driver_name, netdev->name);
  934. return;
  935. }
  936. rcv_desc = &recv_ctx->rcv_desc[desc_ctx];
  937. if (unlikely(index > rcv_desc->max_rx_desc_count)) {
  938. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  939. index, rcv_desc->max_rx_desc_count);
  940. return;
  941. }
  942. buffer = &rcv_desc->rx_buf_arr[index];
  943. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  944. buffer->lro_current_frags++;
  945. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  946. buffer->lro_expected_frags =
  947. netxen_get_sts_desc_lro_cnt(desc);
  948. buffer->lro_length = length;
  949. }
  950. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  951. if (buffer->lro_expected_frags != 0) {
  952. printk("LRO: (refhandle:%x) recv frag."
  953. "wait for last. flags: %x expected:%d"
  954. "have:%d\n", index,
  955. netxen_get_sts_desc_lro_last_frag(desc),
  956. buffer->lro_expected_frags,
  957. buffer->lro_current_frags);
  958. }
  959. return;
  960. }
  961. }
  962. pci_unmap_single(pdev, buffer->dma, rcv_desc->dma_size,
  963. PCI_DMA_FROMDEVICE);
  964. skb = (struct sk_buff *)buffer->skb;
  965. if (likely(netxen_get_sts_status(desc) == STATUS_CKSUM_OK)) {
  966. adapter->stats.csummed++;
  967. skb->ip_summed = CHECKSUM_UNNECESSARY;
  968. }
  969. skb->dev = netdev;
  970. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  971. /* True length was only available on the last pkt */
  972. skb_put(skb, buffer->lro_length);
  973. } else {
  974. skb_put(skb, length);
  975. }
  976. skb->protocol = eth_type_trans(skb, netdev);
  977. ret = netif_receive_skb(skb);
  978. /*
  979. * RH: Do we need these stats on a regular basis. Can we get it from
  980. * Linux stats.
  981. */
  982. switch (ret) {
  983. case NET_RX_SUCCESS:
  984. adapter->stats.uphappy++;
  985. break;
  986. case NET_RX_CN_LOW:
  987. adapter->stats.uplcong++;
  988. break;
  989. case NET_RX_CN_MOD:
  990. adapter->stats.upmcong++;
  991. break;
  992. case NET_RX_CN_HIGH:
  993. adapter->stats.uphcong++;
  994. break;
  995. case NET_RX_DROP:
  996. adapter->stats.updropped++;
  997. break;
  998. default:
  999. adapter->stats.updunno++;
  1000. break;
  1001. }
  1002. netdev->last_rx = jiffies;
  1003. rcv_desc->rcv_free++;
  1004. rcv_desc->rcv_pending--;
  1005. /*
  1006. * We just consumed one buffer so post a buffer.
  1007. */
  1008. buffer->skb = NULL;
  1009. buffer->state = NETXEN_BUFFER_FREE;
  1010. buffer->lro_current_frags = 0;
  1011. buffer->lro_expected_frags = 0;
  1012. adapter->stats.no_rcv++;
  1013. adapter->stats.rxbytes += length;
  1014. }
  1015. /* Process Receive status ring */
  1016. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1017. {
  1018. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1019. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1020. struct status_desc *desc; /* used to read status desc here */
  1021. u32 consumer = recv_ctx->status_rx_consumer;
  1022. u32 producer = 0;
  1023. int count = 0, ring;
  1024. DPRINTK(INFO, "procesing receive\n");
  1025. /*
  1026. * we assume in this case that there is only one port and that is
  1027. * port #1...changes need to be done in firmware to indicate port
  1028. * number as part of the descriptor. This way we will be able to get
  1029. * the netdev which is associated with that device.
  1030. */
  1031. while (count < max) {
  1032. desc = &desc_head[consumer];
  1033. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1034. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1035. netxen_get_sts_owner(desc));
  1036. break;
  1037. }
  1038. netxen_process_rcv(adapter, ctxid, desc);
  1039. netxen_clear_sts_owner(desc);
  1040. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1041. consumer = (consumer + 1) & (adapter->max_rx_desc_count - 1);
  1042. count++;
  1043. }
  1044. if (count) {
  1045. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  1046. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1047. }
  1048. }
  1049. /* update the consumer index in phantom */
  1050. if (count) {
  1051. recv_ctx->status_rx_consumer = consumer;
  1052. recv_ctx->status_rx_producer = producer;
  1053. /* Window = 1 */
  1054. writel(consumer,
  1055. NETXEN_CRB_NORMALIZE(adapter,
  1056. recv_crb_registers[adapter->portnum].
  1057. crb_rcv_status_consumer));
  1058. wmb();
  1059. }
  1060. return count;
  1061. }
  1062. /* Process Command status ring */
  1063. int netxen_process_cmd_ring(unsigned long data)
  1064. {
  1065. u32 last_consumer;
  1066. u32 consumer;
  1067. struct netxen_adapter *adapter = (struct netxen_adapter *)data;
  1068. int count1 = 0;
  1069. int count2 = 0;
  1070. struct netxen_cmd_buffer *buffer;
  1071. struct pci_dev *pdev;
  1072. struct netxen_skb_frag *frag;
  1073. u32 i;
  1074. struct sk_buff *skb = NULL;
  1075. int done;
  1076. spin_lock(&adapter->tx_lock);
  1077. last_consumer = adapter->last_cmd_consumer;
  1078. DPRINTK(INFO, "procesing xmit complete\n");
  1079. /* we assume in this case that there is only one port and that is
  1080. * port #1...changes need to be done in firmware to indicate port
  1081. * number as part of the descriptor. This way we will be able to get
  1082. * the netdev which is associated with that device.
  1083. */
  1084. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1085. if (last_consumer == consumer) { /* Ring is empty */
  1086. DPRINTK(INFO, "last_consumer %d == consumer %d\n",
  1087. last_consumer, consumer);
  1088. spin_unlock(&adapter->tx_lock);
  1089. return 1;
  1090. }
  1091. adapter->proc_cmd_buf_counter++;
  1092. /*
  1093. * Not needed - does not seem to be used anywhere.
  1094. * adapter->cmd_consumer = consumer;
  1095. */
  1096. spin_unlock(&adapter->tx_lock);
  1097. while ((last_consumer != consumer) && (count1 < MAX_STATUS_HANDLE)) {
  1098. buffer = &adapter->cmd_buf_arr[last_consumer];
  1099. pdev = adapter->pdev;
  1100. frag = &buffer->frag_array[0];
  1101. skb = buffer->skb;
  1102. if (skb && (cmpxchg(&buffer->skb, skb, 0) == skb)) {
  1103. pci_unmap_single(pdev, frag->dma, frag->length,
  1104. PCI_DMA_TODEVICE);
  1105. frag->dma = 0ULL;
  1106. for (i = 1; i < buffer->frag_count; i++) {
  1107. DPRINTK(INFO, "getting fragment no %d\n", i);
  1108. frag++; /* Get the next frag */
  1109. pci_unmap_page(pdev, frag->dma, frag->length,
  1110. PCI_DMA_TODEVICE);
  1111. frag->dma = 0ULL;
  1112. }
  1113. adapter->stats.skbfreed++;
  1114. dev_kfree_skb_any(skb);
  1115. skb = NULL;
  1116. } else if (adapter->proc_cmd_buf_counter == 1) {
  1117. adapter->stats.txnullskb++;
  1118. }
  1119. if (unlikely(netif_queue_stopped(adapter->netdev)
  1120. && netif_carrier_ok(adapter->netdev))
  1121. && ((jiffies - adapter->netdev->trans_start) >
  1122. adapter->netdev->watchdog_timeo)) {
  1123. SCHEDULE_WORK(&adapter->tx_timeout_task);
  1124. }
  1125. last_consumer = get_next_index(last_consumer,
  1126. adapter->max_tx_desc_count);
  1127. count1++;
  1128. }
  1129. count2 = 0;
  1130. spin_lock(&adapter->tx_lock);
  1131. if ((--adapter->proc_cmd_buf_counter) == 0) {
  1132. adapter->last_cmd_consumer = last_consumer;
  1133. while ((adapter->last_cmd_consumer != consumer)
  1134. && (count2 < MAX_STATUS_HANDLE)) {
  1135. buffer =
  1136. &adapter->cmd_buf_arr[adapter->last_cmd_consumer];
  1137. count2++;
  1138. if (buffer->skb)
  1139. break;
  1140. else
  1141. adapter->last_cmd_consumer =
  1142. get_next_index(adapter->last_cmd_consumer,
  1143. adapter->max_tx_desc_count);
  1144. }
  1145. }
  1146. if (count1 || count2) {
  1147. if (netif_queue_stopped(adapter->netdev)
  1148. && (adapter->flags & NETXEN_NETDEV_STATUS)) {
  1149. netif_wake_queue(adapter->netdev);
  1150. adapter->flags &= ~NETXEN_NETDEV_STATUS;
  1151. }
  1152. }
  1153. /*
  1154. * If everything is freed up to consumer then check if the ring is full
  1155. * If the ring is full then check if more needs to be freed and
  1156. * schedule the call back again.
  1157. *
  1158. * This happens when there are 2 CPUs. One could be freeing and the
  1159. * other filling it. If the ring is full when we get out of here and
  1160. * the card has already interrupted the host then the host can miss the
  1161. * interrupt.
  1162. *
  1163. * There is still a possible race condition and the host could miss an
  1164. * interrupt. The card has to take care of this.
  1165. */
  1166. if (adapter->last_cmd_consumer == consumer &&
  1167. (((adapter->cmd_producer + 1) %
  1168. adapter->max_tx_desc_count) == adapter->last_cmd_consumer)) {
  1169. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1170. }
  1171. done = (adapter->last_cmd_consumer == consumer);
  1172. spin_unlock(&adapter->tx_lock);
  1173. DPRINTK(INFO, "last consumer is %d in %s\n", last_consumer,
  1174. __FUNCTION__);
  1175. return (done);
  1176. }
  1177. /*
  1178. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1179. */
  1180. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1181. {
  1182. struct pci_dev *pdev = adapter->ahw.pdev;
  1183. struct sk_buff *skb;
  1184. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1185. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1186. uint producer;
  1187. struct rcv_desc *pdesc;
  1188. struct netxen_rx_buffer *buffer;
  1189. int count = 0;
  1190. int index = 0;
  1191. netxen_ctx_msg msg = 0;
  1192. dma_addr_t dma;
  1193. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1194. producer = rcv_desc->producer;
  1195. index = rcv_desc->begin_alloc;
  1196. buffer = &rcv_desc->rx_buf_arr[index];
  1197. /* We can start writing rx descriptors into the phantom memory. */
  1198. while (buffer->state == NETXEN_BUFFER_FREE) {
  1199. skb = dev_alloc_skb(rcv_desc->skb_size);
  1200. if (unlikely(!skb)) {
  1201. /*
  1202. * TODO
  1203. * We need to schedule the posting of buffers to the pegs.
  1204. */
  1205. rcv_desc->begin_alloc = index;
  1206. DPRINTK(ERR, "netxen_post_rx_buffers: "
  1207. " allocated only %d buffers\n", count);
  1208. break;
  1209. }
  1210. count++; /* now there should be no failure */
  1211. pdesc = &rcv_desc->desc_head[producer];
  1212. #if defined(XGB_DEBUG)
  1213. *(unsigned long *)(skb->head) = 0xc0debabe;
  1214. if (skb_is_nonlinear(skb)) {
  1215. printk("Allocated SKB @%p is nonlinear\n");
  1216. }
  1217. #endif
  1218. skb_reserve(skb, 2);
  1219. /* This will be setup when we receive the
  1220. * buffer after it has been filled FSL TBD TBD
  1221. * skb->dev = netdev;
  1222. */
  1223. dma = pci_map_single(pdev, skb->data, rcv_desc->dma_size,
  1224. PCI_DMA_FROMDEVICE);
  1225. pdesc->addr_buffer = cpu_to_le64(dma);
  1226. buffer->skb = skb;
  1227. buffer->state = NETXEN_BUFFER_BUSY;
  1228. buffer->dma = dma;
  1229. /* make a rcv descriptor */
  1230. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1231. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1232. DPRINTK(INFO, "done writing descripter\n");
  1233. producer =
  1234. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1235. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1236. buffer = &rcv_desc->rx_buf_arr[index];
  1237. }
  1238. /* if we did allocate buffers, then write the count to Phantom */
  1239. if (count) {
  1240. rcv_desc->begin_alloc = index;
  1241. rcv_desc->rcv_pending += count;
  1242. rcv_desc->producer = producer;
  1243. if (rcv_desc->rcv_free >= 32) {
  1244. rcv_desc->rcv_free = 0;
  1245. /* Window = 1 */
  1246. writel((producer - 1) &
  1247. (rcv_desc->max_rx_desc_count - 1),
  1248. NETXEN_CRB_NORMALIZE(adapter,
  1249. recv_crb_registers[
  1250. adapter->portnum].
  1251. rcv_desc_crb[ringid].
  1252. crb_rcv_producer_offset));
  1253. /*
  1254. * Write a doorbell msg to tell phanmon of change in
  1255. * receive ring producer
  1256. */
  1257. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1258. netxen_set_msg_privid(msg);
  1259. netxen_set_msg_count(msg,
  1260. ((producer -
  1261. 1) & (rcv_desc->
  1262. max_rx_desc_count - 1)));
  1263. netxen_set_msg_ctxid(msg, adapter->portnum);
  1264. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1265. writel(msg,
  1266. DB_NORMALIZE(adapter,
  1267. NETXEN_RCV_PRODUCER_OFFSET));
  1268. wmb();
  1269. }
  1270. }
  1271. }
  1272. void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter, uint32_t ctx,
  1273. uint32_t ringid)
  1274. {
  1275. struct pci_dev *pdev = adapter->ahw.pdev;
  1276. struct sk_buff *skb;
  1277. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1278. struct netxen_rcv_desc_ctx *rcv_desc = NULL;
  1279. u32 producer;
  1280. struct rcv_desc *pdesc;
  1281. struct netxen_rx_buffer *buffer;
  1282. int count = 0;
  1283. int index = 0;
  1284. rcv_desc = &recv_ctx->rcv_desc[ringid];
  1285. producer = rcv_desc->producer;
  1286. index = rcv_desc->begin_alloc;
  1287. buffer = &rcv_desc->rx_buf_arr[index];
  1288. /* We can start writing rx descriptors into the phantom memory. */
  1289. while (buffer->state == NETXEN_BUFFER_FREE) {
  1290. skb = dev_alloc_skb(rcv_desc->skb_size);
  1291. if (unlikely(!skb)) {
  1292. /*
  1293. * We need to schedule the posting of buffers to the pegs.
  1294. */
  1295. rcv_desc->begin_alloc = index;
  1296. DPRINTK(ERR, "netxen_post_rx_buffers_nodb: "
  1297. " allocated only %d buffers\n", count);
  1298. break;
  1299. }
  1300. count++; /* now there should be no failure */
  1301. pdesc = &rcv_desc->desc_head[producer];
  1302. skb_reserve(skb, 2);
  1303. /*
  1304. * This will be setup when we receive the
  1305. * buffer after it has been filled
  1306. * skb->dev = netdev;
  1307. */
  1308. buffer->skb = skb;
  1309. buffer->state = NETXEN_BUFFER_BUSY;
  1310. buffer->dma = pci_map_single(pdev, skb->data,
  1311. rcv_desc->dma_size,
  1312. PCI_DMA_FROMDEVICE);
  1313. /* make a rcv descriptor */
  1314. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1315. pdesc->buffer_length = cpu_to_le32(rcv_desc->dma_size);
  1316. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1317. DPRINTK(INFO, "done writing descripter\n");
  1318. producer =
  1319. get_next_index(producer, rcv_desc->max_rx_desc_count);
  1320. index = get_next_index(index, rcv_desc->max_rx_desc_count);
  1321. buffer = &rcv_desc->rx_buf_arr[index];
  1322. }
  1323. /* if we did allocate buffers, then write the count to Phantom */
  1324. if (count) {
  1325. rcv_desc->begin_alloc = index;
  1326. rcv_desc->rcv_pending += count;
  1327. rcv_desc->producer = producer;
  1328. if (rcv_desc->rcv_free >= 32) {
  1329. rcv_desc->rcv_free = 0;
  1330. /* Window = 1 */
  1331. writel((producer - 1) &
  1332. (rcv_desc->max_rx_desc_count - 1),
  1333. NETXEN_CRB_NORMALIZE(adapter,
  1334. recv_crb_registers[
  1335. adapter->portnum].
  1336. rcv_desc_crb[ringid].
  1337. crb_rcv_producer_offset));
  1338. wmb();
  1339. }
  1340. }
  1341. }
  1342. int netxen_nic_tx_has_work(struct netxen_adapter *adapter)
  1343. {
  1344. if (find_diff_among(adapter->last_cmd_consumer,
  1345. adapter->cmd_producer,
  1346. adapter->max_tx_desc_count) > 0)
  1347. return 1;
  1348. return 0;
  1349. }
  1350. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1351. {
  1352. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1353. return;
  1354. }