apic.h 2.8 KB

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  1. #ifndef __ASM_MACH_APIC_H
  2. #define __ASM_MACH_APIC_H
  3. #define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
  4. #define esr_disable (1)
  5. static inline int apic_id_registered(void)
  6. {
  7. return (1);
  8. }
  9. static inline cpumask_t target_cpus(void)
  10. {
  11. #ifdef CONFIG_SMP
  12. return cpu_online_map;
  13. #else
  14. return cpumask_of_cpu(0);
  15. #endif
  16. }
  17. #undef APIC_DEST_LOGICAL
  18. #define APIC_DEST_LOGICAL 0
  19. #define APIC_DFR_VALUE (APIC_DFR_FLAT)
  20. #define INT_DELIVERY_MODE (dest_Fixed)
  21. #define INT_DEST_MODE (0) /* phys delivery to target proc */
  22. #define NO_BALANCE_IRQ (0)
  23. static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  24. {
  25. return (0);
  26. }
  27. static inline unsigned long check_apicid_present(int bit)
  28. {
  29. return (1);
  30. }
  31. static inline unsigned long calculate_ldr(int cpu)
  32. {
  33. unsigned long val, id;
  34. val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  35. id = xapic_phys_to_log_apicid(cpu);
  36. val |= SET_APIC_LOGICAL_ID(id);
  37. return val;
  38. }
  39. /*
  40. * Set up the logical destination ID.
  41. *
  42. * Intel recommends to set DFR, LDR and TPR before enabling
  43. * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
  44. * document number 292116). So here it goes...
  45. */
  46. static inline void init_apic_ldr(void)
  47. {
  48. unsigned long val;
  49. int cpu = smp_processor_id();
  50. apic_write(APIC_DFR, APIC_DFR_VALUE);
  51. val = calculate_ldr(cpu);
  52. apic_write(APIC_LDR, val);
  53. }
  54. static inline void setup_apic_routing(void)
  55. {
  56. printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
  57. "Physflat", nr_ioapics);
  58. }
  59. static inline int multi_timer_check(int apic, int irq)
  60. {
  61. return (0);
  62. }
  63. static inline int apicid_to_node(int logical_apicid)
  64. {
  65. return apicid_2_node[hard_smp_processor_id()];
  66. }
  67. static inline int cpu_present_to_apicid(int mps_cpu)
  68. {
  69. if (mps_cpu < NR_CPUS)
  70. return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
  71. return BAD_APICID;
  72. }
  73. static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
  74. {
  75. return physid_mask_of_physid(phys_apicid);
  76. }
  77. extern u8 cpu_2_logical_apicid[];
  78. /* Mapping from cpu number to logical apicid */
  79. static inline int cpu_to_logical_apicid(int cpu)
  80. {
  81. if (cpu >= NR_CPUS)
  82. return BAD_APICID;
  83. return cpu_physical_id(cpu);
  84. }
  85. static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
  86. {
  87. /* For clustered we don't have a good way to do this yet - hack */
  88. return physids_promote(0xFFL);
  89. }
  90. static inline void setup_portio_remap(void)
  91. {
  92. }
  93. static inline void enable_apic_mode(void)
  94. {
  95. }
  96. static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
  97. {
  98. return (1);
  99. }
  100. /* As we are using single CPU as destination, pick only one CPU here */
  101. static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
  102. {
  103. int cpu;
  104. int apicid;
  105. cpu = first_cpu(cpumask);
  106. apicid = cpu_to_logical_apicid(cpu);
  107. return apicid;
  108. }
  109. static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
  110. {
  111. return cpuid_apic >> index_msb;
  112. }
  113. #endif /* __ASM_MACH_APIC_H */