sysregs.h 1.9 KB

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  1. /*
  2. * Copyright 2011 Calxeda, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #ifndef _MACH_HIGHBANK__SYSREGS_H_
  17. #define _MACH_HIGHBANK__SYSREGS_H_
  18. #include <linux/io.h>
  19. #include <linux/smp.h>
  20. #include <asm/smp_plat.h>
  21. #include <asm/smp_scu.h>
  22. #include "core.h"
  23. extern void __iomem *sregs_base;
  24. #define HB_SREG_A9_PWR_REQ 0xf00
  25. #define HB_SREG_A9_BOOT_STAT 0xf04
  26. #define HB_SREG_A9_BOOT_DATA 0xf08
  27. #define HB_PWR_SUSPEND 0
  28. #define HB_PWR_SOFT_RESET 1
  29. #define HB_PWR_HARD_RESET 2
  30. #define HB_PWR_SHUTDOWN 3
  31. #define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
  32. static inline void highbank_set_core_pwr(void)
  33. {
  34. int cpu = cpu_logical_map(smp_processor_id());
  35. if (scu_base_addr)
  36. scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
  37. else
  38. writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
  39. }
  40. static inline void hignbank_set_pwr_suspend(void)
  41. {
  42. writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
  43. highbank_set_core_pwr();
  44. }
  45. static inline void hignbank_set_pwr_shutdown(void)
  46. {
  47. writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
  48. highbank_set_core_pwr();
  49. }
  50. static inline void hignbank_set_pwr_soft_reset(void)
  51. {
  52. writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
  53. highbank_set_core_pwr();
  54. }
  55. static inline void hignbank_set_pwr_hard_reset(void)
  56. {
  57. writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
  58. highbank_set_core_pwr();
  59. }
  60. #endif