xilinx_hwicap.h 6.1 KB

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  1. /*****************************************************************************
  2. *
  3. * Author: Xilinx, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
  11. * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
  12. * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
  13. * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
  14. * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
  15. * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
  16. * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
  17. * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
  18. * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
  19. * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
  20. * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
  21. * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  22. * FOR A PARTICULAR PURPOSE.
  23. *
  24. * Xilinx products are not intended for use in life support appliances,
  25. * devices, or systems. Use in such applications is expressly prohibited.
  26. *
  27. * (c) Copyright 2003-2007 Xilinx Inc.
  28. * All rights reserved.
  29. *
  30. * You should have received a copy of the GNU General Public License along
  31. * with this program; if not, write to the Free Software Foundation, Inc.,
  32. * 675 Mass Ave, Cambridge, MA 02139, USA.
  33. *
  34. *****************************************************************************/
  35. #ifndef XILINX_HWICAP_H_ /* prevent circular inclusions */
  36. #define XILINX_HWICAP_H_ /* by using protection macros */
  37. #include <linux/types.h>
  38. #include <linux/cdev.h>
  39. #include <linux/version.h>
  40. #include <linux/platform_device.h>
  41. #include <asm/io.h>
  42. struct hwicap_drvdata {
  43. u32 write_buffer_in_use; /* Always in [0,3] */
  44. u8 write_buffer[4];
  45. u32 read_buffer_in_use; /* Always in [0,3] */
  46. u8 read_buffer[4];
  47. resource_size_t mem_start;/* phys. address of the control registers */
  48. resource_size_t mem_end; /* phys. address of the control registers */
  49. resource_size_t mem_size;
  50. void __iomem *base_address;/* virt. address of the control registers */
  51. struct device *dev;
  52. struct cdev cdev; /* Char device structure */
  53. dev_t devt;
  54. const struct hwicap_driver_config *config;
  55. const struct config_registers *config_regs;
  56. void *private_data;
  57. bool is_open;
  58. struct mutex sem;
  59. };
  60. struct hwicap_driver_config {
  61. int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
  62. u32 size);
  63. int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data,
  64. u32 size);
  65. void (*reset)(struct hwicap_drvdata *drvdata);
  66. };
  67. /* Number of times to poll the done regsiter */
  68. #define XHI_MAX_RETRIES 10
  69. /************ Constant Definitions *************/
  70. #define XHI_PAD_FRAMES 0x1
  71. /* Mask for calculating configuration packet headers */
  72. #define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL
  73. #define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL
  74. #define XHI_TYPE_MASK 0x7
  75. #define XHI_REGISTER_MASK 0xF
  76. #define XHI_OP_MASK 0x3
  77. #define XHI_TYPE_SHIFT 29
  78. #define XHI_REGISTER_SHIFT 13
  79. #define XHI_OP_SHIFT 27
  80. #define XHI_TYPE_1 1
  81. #define XHI_TYPE_2 2
  82. #define XHI_OP_WRITE 2
  83. #define XHI_OP_READ 1
  84. /* Address Block Types */
  85. #define XHI_FAR_CLB_BLOCK 0
  86. #define XHI_FAR_BRAM_BLOCK 1
  87. #define XHI_FAR_BRAM_INT_BLOCK 2
  88. struct config_registers {
  89. u32 CRC;
  90. u32 FAR;
  91. u32 FDRI;
  92. u32 FDRO;
  93. u32 CMD;
  94. u32 CTL;
  95. u32 MASK;
  96. u32 STAT;
  97. u32 LOUT;
  98. u32 COR;
  99. u32 MFWR;
  100. u32 FLR;
  101. u32 KEY;
  102. u32 CBC;
  103. u32 IDCODE;
  104. u32 AXSS;
  105. u32 C0R_1;
  106. u32 CSOB;
  107. u32 WBSTAR;
  108. u32 TIMER;
  109. u32 BOOTSTS;
  110. u32 CTL_1;
  111. };
  112. /* Configuration Commands */
  113. #define XHI_CMD_NULL 0
  114. #define XHI_CMD_WCFG 1
  115. #define XHI_CMD_MFW 2
  116. #define XHI_CMD_DGHIGH 3
  117. #define XHI_CMD_RCFG 4
  118. #define XHI_CMD_START 5
  119. #define XHI_CMD_RCAP 6
  120. #define XHI_CMD_RCRC 7
  121. #define XHI_CMD_AGHIGH 8
  122. #define XHI_CMD_SWITCH 9
  123. #define XHI_CMD_GRESTORE 10
  124. #define XHI_CMD_SHUTDOWN 11
  125. #define XHI_CMD_GCAPTURE 12
  126. #define XHI_CMD_DESYNCH 13
  127. #define XHI_CMD_IPROG 15 /* Only in Virtex5 */
  128. #define XHI_CMD_CRCC 16 /* Only in Virtex5 */
  129. #define XHI_CMD_LTIMER 17 /* Only in Virtex5 */
  130. /* Packet constants */
  131. #define XHI_SYNC_PACKET 0xAA995566UL
  132. #define XHI_DUMMY_PACKET 0xFFFFFFFFUL
  133. #define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT)
  134. #define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
  135. (XHI_OP_READ << XHI_OP_SHIFT))
  136. #define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \
  137. (XHI_OP_WRITE << XHI_OP_SHIFT))
  138. #define XHI_TYPE2_CNT_MASK 0x07FFFFFF
  139. #define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL
  140. #define XHI_TYPE_1_HEADER_BYTES 4
  141. #define XHI_TYPE_2_HEADER_BYTES 8
  142. /* Constant to use for CRC check when CRC has been disabled */
  143. #define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL
  144. /**
  145. * hwicap_type_1_read - Generates a Type 1 read packet header.
  146. * @reg: is the address of the register to be read back.
  147. *
  148. * Generates a Type 1 read packet header, which is used to indirectly
  149. * read registers in the configuration logic. This packet must then
  150. * be sent through the icap device, and a return packet received with
  151. * the information.
  152. **/
  153. static inline u32 hwicap_type_1_read(u32 reg)
  154. {
  155. return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
  156. (reg << XHI_REGISTER_SHIFT) |
  157. (XHI_OP_READ << XHI_OP_SHIFT);
  158. }
  159. /**
  160. * hwicap_type_1_write - Generates a Type 1 write packet header
  161. * @reg: is the address of the register to be read back.
  162. **/
  163. static inline u32 hwicap_type_1_write(u32 reg)
  164. {
  165. return (XHI_TYPE_1 << XHI_TYPE_SHIFT) |
  166. (reg << XHI_REGISTER_SHIFT) |
  167. (XHI_OP_WRITE << XHI_OP_SHIFT);
  168. }
  169. #endif