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imx6dl.dtsi

imx6dl.dtsi 12 KB
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  1. 

  2. /*
    3. 

  3.  * Copyright 2013 Freescale Semiconductor, Inc.
    4. 

  4.  *
    5. 

  5.  * This program is free software; you can redistribute it and/or modify
    6. 

  6.  * it under the terms of the GNU General Public License version 2 as
    7. 

  7.  * published by the Free Software Foundation.
    8. 

  8.  *
    9. 

  9.  */
    10. 

  10. 

  11. #include "imx6qdl.dtsi"
    12. 

  12. #include "imx6dl-pinfunc.h"
    13. 

  13. 

  14. / {
    15. 

  15. 	cpus {
    16. 

  16. 		#address-cells = <1>;
    17. 

  17. 		#size-cells = <0>;
    18. 

  18. 

  19. 		cpu@0 {
    20. 

  20. 			compatible = "arm,cortex-a9";
    21. 

  21. 			device_type = "cpu";
    22. 

  22. 			reg = <0>;
    23. 

  23. 			next-level-cache = <&L2>;
    24. 

  24. 		};
    25. 

  25. 

  26. 		cpu@1 {
    27. 

  27. 			compatible = "arm,cortex-a9";
    28. 

  28. 			device_type = "cpu";
    29. 

  29. 			reg = <1>;
    30. 

  30. 			next-level-cache = <&L2>;
    31. 

  31. 		};
    32. 

  32. 	};
    33. 

  33. 

  34. 	soc {
    35. 

  35. 		aips1: aips-bus@02000000 {
    36. 

  36. 			iomuxc: iomuxc@020e0000 {
    37. 

  37. 				compatible = "fsl,imx6dl-iomuxc";
    38. 

  38. 				reg = <0x020e0000 0x4000>;
    39. 

  39. 

  40. 				audmux {
    41. 

  41. 					pinctrl_audmux_1: audmux-1 {
    42. 

  42. 						fsl,pins = <
    43. 

  43. 							MX6DL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
    44. 

  44. 							MX6DL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
    45. 

  45. 							MX6DL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
    46. 

  46. 							MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
    47. 

  47. 						>;
    48. 

  48. 					};
    49. 

  49. 

  50. 					pinctrl_audmux_2: audmux-2 {
    51. 

  51. 						fsl,pins = <
    52. 

  52. 							MX6DL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
    53. 

  53. 							MX6DL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
    54. 

  54. 							MX6DL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
    55. 

  55. 							MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
    56. 

  56. 						>;
    57. 

  57. 					};
    58. 

  58. 				};
    59. 

  59. 

  60. 				ecspi1 {
    61. 

  61. 					pinctrl_ecspi1_1: ecspi1grp-1 {
    62. 

  62. 						fsl,pins = <
    63. 

  63. 							MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
    64. 

  64. 							MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
    65. 

  65. 							MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
    66. 

  66. 						>;
    67. 

  67. 					};
    68. 

  68. 

  69. 					pinctrl_ecspi1_2: ecspi1grp-2 {
    70. 

  70. 						fsl,pins = <
    71. 

  71. 							MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
    72. 

  72. 							MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
    73. 

  73. 							MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
    74. 

  74. 						>;
    75. 

  75. 					};
    76. 

  76. 				};
    77. 

  77. 

  78. 				ecspi3 {
    79. 

  79. 					pinctrl_ecspi3_1: ecspi3grp-1 {
    80. 

  80. 						fsl,pins = <
    81. 

  81. 							MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
    82. 

  82. 							MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
    83. 

  83. 							MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
    84. 

  84. 						>;
    85. 

  85. 					};
    86. 

  86. 				};
    87. 

  87. 

  88. 				enet {
    89. 

  89. 					pinctrl_enet_1: enetgrp-1 {
    90. 

  90. 						fsl,pins = <
    91. 

  91. 							MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
    92. 

  92. 							MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
    93. 

  93. 							MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
    94. 

  94. 							MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
    95. 

  95. 							MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
    96. 

  96. 							MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
    97. 

  97. 							MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
    98. 

  98. 							MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
    99. 

  99. 							MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
    100. 

  100. 							MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
    101. 

  101. 							MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
    102. 

  102. 							MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
    103. 

  103. 							MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
    104. 

  104. 							MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
    105. 

  105. 							MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
    106. 

  106. 							MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
    107. 

  107. 						>;
    108. 

  108. 					};
    109. 

  109. 

  110. 					pinctrl_enet_2: enetgrp-2 {
    111. 

  111. 						fsl,pins = <
    112. 

  112. 							MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
    113. 

  113. 							MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
    114. 

  114. 							MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
    115. 

  115. 							MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
    116. 

  116. 							MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
    117. 

  117. 							MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
    118. 

  118. 							MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
    119. 

  119. 							MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
    120. 

  120. 							MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
    121. 

  121. 							MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
    122. 

  122. 							MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
    123. 

  123. 							MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
    124. 

  124. 							MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
    125. 

  125. 							MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
    126. 

  126. 							MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
    127. 

  127. 						>;
    128. 

  128. 					};
    129. 

  129. 

  130. 					pinctrl_enet_3: enetgrp-3 {
    131. 

  131. 						fsl,pins = <
    132. 

  132. 							MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
    133. 

  133. 							MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
    134. 

  134. 							MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
    135. 

  135. 							MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
    136. 

  136. 							MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
    137. 

  137. 							MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
    138. 

  138. 							MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
    139. 

  139. 							MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
    140. 

  140. 							MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
    141. 

  141. 							MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
    142. 

  142. 							MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
    143. 

  143. 							MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
    144. 

  144. 							MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
    145. 

  145. 							MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
    146. 

  146. 							MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
    147. 

  147. 							MX6DL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
    148. 

  148. 						>;
    149. 

  149. 					};
    150. 

  150. 				};
    151. 

  151. 

  152. 				gpmi-nand {
    153. 

  153. 					pinctrl_gpmi_nand_1: gpmi-nand-1 {
    154. 

  154. 						fsl,pins = <
    155. 

  155. 							MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
    156. 

  156. 							MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
    157. 

  157. 							MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
    158. 

  158. 							MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
    159. 

  159. 							MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
    160. 

  160. 							MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
    161. 

  161. 							MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
    162. 

  162. 							MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
    163. 

  163. 							MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
    164. 

  164. 							MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
    165. 

  165. 							MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
    166. 

  166. 							MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
    167. 

  167. 							MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
    168. 

  168. 							MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
    169. 

  169. 							MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
    170. 

  170. 							MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
    171. 

  171. 							MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
    172. 

  172. 						>;
    173. 

  173. 					};
    174. 

  174. 				};
    175. 

  175. 

  176. 				i2c1 {
    177. 

  177. 					pinctrl_i2c1_1: i2c1grp-1 {
    178. 

  178. 						fsl,pins = <
    179. 

  179. 							MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
    180. 

  180. 							MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
    181. 

  181. 						>;
    182. 

  182. 					};
    183. 

  183. 

  184. 					pinctrl_i2c1_2: i2c1grp-2 {
    185. 

  185. 						fsl,pins = <
    186. 

  186. 							MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
    187. 

  187. 							MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
    188. 

  188. 						>;
    189. 

  189. 					};
    190. 

  190. 				};
    191. 

  191. 

  192. 				i2c2 {
    193. 

  193. 					pinctrl_i2c2_1: i2c2grp-1 {
    194. 

  194. 						fsl,pins = <
    195. 

  195. 							MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
    196. 

  196. 							MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
    197. 

  197. 						>;
    198. 

  198. 					};
    199. 

  199. 				};
    200. 

  200. 

  201. 				i2c3 {
    202. 

  202. 					pinctrl_i2c3_1: i2c3grp-1 {
    203. 

  203. 						fsl,pins = <
    204. 

  204. 							MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
    205. 

  205. 							MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
    206. 

  206. 						>;
    207. 

  207. 					};
    208. 

  208. 				};
    209. 

  209. 

  210. 				uart1 {
    211. 

  211. 					pinctrl_uart1_1: uart1grp-1 {
    212. 

  212. 						fsl,pins = <
    213. 

  213. 							MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
    214. 

  214. 							MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
    215. 

  215. 						>;
    216. 

  216. 					};
    217. 

  217. 				};
    218. 

  218. 

  219. 				uart2 {
    220. 

  220. 					pinctrl_uart2_1: uart2grp-1 {
    221. 

  221. 						fsl,pins = <
    222. 

  222. 							MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
    223. 

  223. 							MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
    224. 

  224. 						>;
    225. 

  225. 					};
    226. 

  226. 				};
    227. 

  227. 

  228. 				uart4 {
    229. 

  229. 					pinctrl_uart4_1: uart4grp-1 {
    230. 

  230. 						fsl,pins = <
    231. 

  231. 							MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
    232. 

  232. 							MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
    233. 

  233. 						>;
    234. 

  234. 					};
    235. 

  235. 				};
    236. 

  236. 

  237. 				usbotg {
    238. 

  238. 					pinctrl_usbotg_1: usbotggrp-1 {
    239. 

  239. 						fsl,pins = <
    240. 

  240. 							MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
    241. 

  241. 						>;
    242. 

  242. 					};
    243. 

  243. 

  244. 					pinctrl_usbotg_2: usbotggrp-2 {
    245. 

  245. 						fsl,pins = <
    246. 

  246. 							MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
    247. 

  247. 						>;
    248. 

  248. 					};
    249. 

  249. 				};
    250. 

  250. 

  251. 				usdhc2 {
    252. 

  252. 					pinctrl_usdhc2_1: usdhc2grp-1 {
    253. 

  253. 						fsl,pins = <
    254. 

  254. 							MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
    255. 

  255. 							MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
    256. 

  256. 							MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
    257. 

  257. 							MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
    258. 

  258. 							MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
    259. 

  259. 							MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
    260. 

  260. 							MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
    261. 

  261. 							MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
    262. 

  262. 							MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
    263. 

  263. 							MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
    264. 

  264. 						>;
    265. 

  265. 					};
    266. 

  266. 

  267. 					pinctrl_usdhc2_2: usdhc2grp-2 {
    268. 

  268. 						fsl,pins = <
    269. 

  269. 							MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
    270. 

  270. 							MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
    271. 

  271. 							MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
    272. 

  272. 							MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
    273. 

  273. 							MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
    274. 

  274. 							MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
    275. 

  275. 						>;
    276. 

  276. 					};
    277. 

  277. 				};
    278. 

  278. 

  279. 				usdhc3 {
    280. 

  280. 					pinctrl_usdhc3_1: usdhc3grp-1 {
    281. 

  281. 						fsl,pins = <
    282. 

  282. 							MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
    283. 

  283. 							MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
    284. 

  284. 							MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
    285. 

  285. 							MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
    286. 

  286. 							MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
    287. 

  287. 							MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
    288. 

  288. 							MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
    289. 

  289. 							MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
    290. 

  290. 							MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
    291. 

  291. 							MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
    292. 

  292. 						>;
    293. 

  293. 					};
    294. 

  294. 

  295. 					pinctrl_usdhc3_2: usdhc3grp-2 {
    296. 

  296. 						fsl,pins = <
    297. 

  297. 							MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
    298. 

  298. 							MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
    299. 

  299. 							MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
    300. 

  300. 							MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
    301. 

  301. 							MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
    302. 

  302. 							MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
    303. 

  303. 						>;
    304. 

  304. 					};
    305. 

  305. 				};
    306. 

  306. 

  307. 				usdhc4 {
    308. 

  308. 					pinctrl_usdhc4_1: usdhc4grp-1 {
    309. 

  309. 						fsl,pins = <
    310. 

  310. 							MX6DL_PAD_SD4_CMD__SD4_CMD    0x17059
    311. 

  311. 							MX6DL_PAD_SD4_CLK__SD4_CLK    0x10059
    312. 

  312. 							MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
    313. 

  313. 							MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
    314. 

  314. 							MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
    315. 

  315. 							MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
    316. 

  316. 							MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x17059
    317. 

  317. 							MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x17059
    318. 

  318. 							MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x17059
    319. 

  319. 							MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x17059
    320. 

  320. 						>;
    321. 

  321. 					};
    322. 

  322. 

  323. 					pinctrl_usdhc4_2: usdhc4grp-2 {
    324. 

  324. 						fsl,pins = <
    325. 

  325. 							MX6DL_PAD_SD4_CMD__SD4_CMD    0x17059
    326. 

  326. 							MX6DL_PAD_SD4_CLK__SD4_CLK    0x10059
    327. 

  327. 							MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
    328. 

  328. 							MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
    329. 

  329. 							MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
    330. 

  330. 							MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
    331. 

  331. 						>;
    332. 

  332. 					};
    333. 

  333. 				};
    334. 

  334. 

  335. 				weim {
    336. 

  336. 					pinctrl_weim_cs0_1: weim_cs0grp-1 {
    337. 

  337. 						fsl,pins = <
    338. 

  338. 							MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
    339. 

  339. 						>;
    340. 

  340. 					};
    341. 

  341. 

  342. 					pinctrl_weim_nor_1: weim_norgrp-1 {
    343. 

  343. 						fsl,pins = <
    344. 

  344. 							MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
    345. 

  345. 							MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
    346. 

  346. 							MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
    347. 

  347. 							/* data */
    348. 

  348. 							MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
    349. 

  349. 							MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
    350. 

  350. 							MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
    351. 

  351. 							MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
    352. 

  352. 							MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
    353. 

  353. 							MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
    354. 

  354. 							MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
    355. 

  355. 							MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
    356. 

  356. 							MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
    357. 

  357. 							MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
    358. 

  358. 							MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
    359. 

  359. 							MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
    360. 

  360. 							MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
    361. 

  361. 							MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
    362. 

  362. 							MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
    363. 

  363. 							MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
    364. 

  364. 							/* address */
    365. 

  365. 							MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
    366. 

  366. 							MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
    367. 

  367. 							MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
    368. 

  368. 							MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
    369. 

  369. 							MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
    370. 

  370. 							MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
    371. 

  371. 							MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
    372. 

  372. 							MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
    373. 

  373. 							MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
    374. 

  374. 							MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
    375. 

  375. 							MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
    376. 

  376. 							MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
    377. 

  377. 							MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
    378. 

  378. 							MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
    379. 

  379. 							MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
    380. 

  380. 							MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
    381. 

  381. 							MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
    382. 

  382. 							MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
    383. 

  383. 							MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
    384. 

  384. 							MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
    385. 

  385. 							MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
    386. 

  386. 							MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
    387. 

  387. 							MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
    388. 

  388. 							MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
    389. 

  389. 						>;
    390. 

  390. 					};
    391. 

  391. 				};
    392. 

  392. 			};
    393. 

  393. 

  394. 			pxp: pxp@020f0000 {
    395. 

  395. 				reg = <0x020f0000 0x4000>;
    396. 

  396. 				interrupts = <0 98 0x04>;
    397. 

  397. 			};
    398. 

  398. 

  399. 			epdc: epdc@020f4000 {
    400. 

  400. 				reg = <0x020f4000 0x4000>;
    401. 

  401. 				interrupts = <0 97 0x04>;
    402. 

  402. 			};
    403. 

  403. 

  404. 			lcdif: lcdif@020f8000 {
    405. 

  405. 				reg = <0x020f8000 0x4000>;
    406. 

  406. 				interrupts = <0 39 0x04>;
    407. 

  407. 			};
    408. 

  408. 		};
    409. 

  409. 

  410. 		aips2: aips-bus@02100000 {
    411. 

  411. 			i2c4: i2c@021f8000 {
    412. 

  412. 				#address-cells = <1>;
    413. 

  413. 				#size-cells = <0>;
    414. 

  414. 				compatible = "fsl,imx1-i2c";
    415. 

  415. 				reg = <0x021f8000 0x4000>;
    416. 

  416. 				interrupts = <0 35 0x04>;
    417. 

  417. 				status = "disabled";
    418. 

  418. 			};
    419. 

  419. 		};
    420. 

  420. 	};
    421. 

  421. };
    422. 

  422. 

  423. &ldb {
    424. 

  424. 	clocks = <&clks 33>, <&clks 34>,
    425. 

  425. 		 <&clks 39>, <&clks 40>,
    426. 

  426. 		 <&clks 135>, <&clks 136>;
    427. 

  427. 	clock-names = "di0_pll", "di1_pll",
    428. 

  428. 		      "di0_sel", "di1_sel",
    429. 

  429. 		      "di0", "di1";
    430. 

  430. 

  431. 	lvds-channel@0 {
    432. 

  432. 		crtcs = <&ipu1 0>, <&ipu1 1>;
    433. 

  433. 	};
    434. 

  434. 

  435. 	lvds-channel@1 {
    436. 

  436. 		crtcs = <&ipu1 0>, <&ipu1 1>;
    437. 

  437. 	};
    438. 

  438. };
    439.