stv090x.c 112 KB

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  1. /*
  2. STV0900/0903 Multistandard Broadcast Frontend driver
  3. Copyright (C) Manu Abraham <abraham.manu@gmail.com>
  4. Copyright (C) ST Microelectronics
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/string.h>
  21. #include <linux/mutex.h>
  22. #include <linux/dvb/frontend.h>
  23. #include "dvb_frontend.h"
  24. #include "stv6110x.h" /* for demodulator internal modes */
  25. #include "stv090x_reg.h"
  26. #include "stv090x.h"
  27. #include "stv090x_priv.h"
  28. static unsigned int verbose;
  29. module_param(verbose, int, 0644);
  30. struct mutex demod_lock;
  31. /* DVBS1 and DSS C/N Lookup table */
  32. static const struct stv090x_tab stv090x_s1cn_tab[] = {
  33. { 0, 8917 }, /* 0.0dB */
  34. { 5, 8801 }, /* 0.5dB */
  35. { 10, 8667 }, /* 1.0dB */
  36. { 15, 8522 }, /* 1.5dB */
  37. { 20, 8355 }, /* 2.0dB */
  38. { 25, 8175 }, /* 2.5dB */
  39. { 30, 7979 }, /* 3.0dB */
  40. { 35, 7763 }, /* 3.5dB */
  41. { 40, 7530 }, /* 4.0dB */
  42. { 45, 7282 }, /* 4.5dB */
  43. { 50, 7026 }, /* 5.0dB */
  44. { 55, 6781 }, /* 5.5dB */
  45. { 60, 6514 }, /* 6.0dB */
  46. { 65, 6241 }, /* 6.5dB */
  47. { 70, 5965 }, /* 7.0dB */
  48. { 75, 5690 }, /* 7.5dB */
  49. { 80, 5424 }, /* 8.0dB */
  50. { 85, 5161 }, /* 8.5dB */
  51. { 90, 4902 }, /* 9.0dB */
  52. { 95, 4654 }, /* 9.5dB */
  53. { 100, 4417 }, /* 10.0dB */
  54. { 105, 4186 }, /* 10.5dB */
  55. { 110, 3968 }, /* 11.0dB */
  56. { 115, 3757 }, /* 11.5dB */
  57. { 120, 3558 }, /* 12.0dB */
  58. { 125, 3366 }, /* 12.5dB */
  59. { 130, 3185 }, /* 13.0dB */
  60. { 135, 3012 }, /* 13.5dB */
  61. { 140, 2850 }, /* 14.0dB */
  62. { 145, 2698 }, /* 14.5dB */
  63. { 150, 2550 }, /* 15.0dB */
  64. { 160, 2283 }, /* 16.0dB */
  65. { 170, 2042 }, /* 17.0dB */
  66. { 180, 1827 }, /* 18.0dB */
  67. { 190, 1636 }, /* 19.0dB */
  68. { 200, 1466 }, /* 20.0dB */
  69. { 210, 1315 }, /* 21.0dB */
  70. { 220, 1181 }, /* 22.0dB */
  71. { 230, 1064 }, /* 23.0dB */
  72. { 240, 960 }, /* 24.0dB */
  73. { 250, 869 }, /* 25.0dB */
  74. { 260, 792 }, /* 26.0dB */
  75. { 270, 724 }, /* 27.0dB */
  76. { 280, 665 }, /* 28.0dB */
  77. { 290, 616 }, /* 29.0dB */
  78. { 300, 573 }, /* 30.0dB */
  79. { 310, 537 }, /* 31.0dB */
  80. { 320, 507 }, /* 32.0dB */
  81. { 330, 483 }, /* 33.0dB */
  82. { 400, 398 }, /* 40.0dB */
  83. { 450, 381 }, /* 45.0dB */
  84. { 500, 377 } /* 50.0dB */
  85. };
  86. /* DVBS2 C/N Lookup table */
  87. static const struct stv090x_tab stv090x_s2cn_tab[] = {
  88. { -30, 13348 }, /* -3.0dB */
  89. { -20, 12640 }, /* -2d.0B */
  90. { -10, 11883 }, /* -1.0dB */
  91. { 0, 11101 }, /* -0.0dB */
  92. { 5, 10718 }, /* 0.5dB */
  93. { 10, 10339 }, /* 1.0dB */
  94. { 15, 9947 }, /* 1.5dB */
  95. { 20, 9552 }, /* 2.0dB */
  96. { 25, 9183 }, /* 2.5dB */
  97. { 30, 8799 }, /* 3.0dB */
  98. { 35, 8422 }, /* 3.5dB */
  99. { 40, 8062 }, /* 4.0dB */
  100. { 45, 7707 }, /* 4.5dB */
  101. { 50, 7353 }, /* 5.0dB */
  102. { 55, 7025 }, /* 5.5dB */
  103. { 60, 6684 }, /* 6.0dB */
  104. { 65, 6331 }, /* 6.5dB */
  105. { 70, 6036 }, /* 7.0dB */
  106. { 75, 5727 }, /* 7.5dB */
  107. { 80, 5437 }, /* 8.0dB */
  108. { 85, 5164 }, /* 8.5dB */
  109. { 90, 4902 }, /* 9.0dB */
  110. { 95, 4653 }, /* 9.5dB */
  111. { 100, 4408 }, /* 10.0dB */
  112. { 105, 4187 }, /* 10.5dB */
  113. { 110, 3961 }, /* 11.0dB */
  114. { 115, 3751 }, /* 11.5dB */
  115. { 120, 3558 }, /* 12.0dB */
  116. { 125, 3368 }, /* 12.5dB */
  117. { 130, 3191 }, /* 13.0dB */
  118. { 135, 3017 }, /* 13.5dB */
  119. { 140, 2862 }, /* 14.0dB */
  120. { 145, 2710 }, /* 14.5dB */
  121. { 150, 2565 }, /* 15.0dB */
  122. { 160, 2300 }, /* 16.0dB */
  123. { 170, 2058 }, /* 17.0dB */
  124. { 180, 1849 }, /* 18.0dB */
  125. { 190, 1663 }, /* 19.0dB */
  126. { 200, 1495 }, /* 20.0dB */
  127. { 210, 1349 }, /* 21.0dB */
  128. { 220, 1222 }, /* 22.0dB */
  129. { 230, 1110 }, /* 23.0dB */
  130. { 240, 1011 }, /* 24.0dB */
  131. { 250, 925 }, /* 25.0dB */
  132. { 260, 853 }, /* 26.0dB */
  133. { 270, 789 }, /* 27.0dB */
  134. { 280, 734 }, /* 28.0dB */
  135. { 290, 690 }, /* 29.0dB */
  136. { 300, 650 }, /* 30.0dB */
  137. { 310, 619 }, /* 31.0dB */
  138. { 320, 593 }, /* 32.0dB */
  139. { 330, 571 }, /* 33.0dB */
  140. { 400, 498 }, /* 40.0dB */
  141. { 450, 484 }, /* 45.0dB */
  142. { 500, 481 } /* 50.0dB */
  143. };
  144. /* RF level C/N lookup table */
  145. static const struct stv090x_tab stv090x_rf_tab[] = {
  146. { -5, 0xcaa1 }, /* -5dBm */
  147. { -10, 0xc229 }, /* -10dBm */
  148. { -15, 0xbb08 }, /* -15dBm */
  149. { -20, 0xb4bc }, /* -20dBm */
  150. { -25, 0xad5a }, /* -25dBm */
  151. { -30, 0xa298 }, /* -30dBm */
  152. { -35, 0x98a8 }, /* -35dBm */
  153. { -40, 0x8389 }, /* -40dBm */
  154. { -45, 0x59be }, /* -45dBm */
  155. { -50, 0x3a14 }, /* -50dBm */
  156. { -55, 0x2d11 }, /* -55dBm */
  157. { -60, 0x210d }, /* -60dBm */
  158. { -65, 0xa14f }, /* -65dBm */
  159. { -70, 0x07aa } /* -70dBm */
  160. };
  161. static struct stv090x_reg stv0900_initval[] = {
  162. { STV090x_OUTCFG, 0x00 },
  163. { STV090x_MODECFG, 0xff },
  164. { STV090x_AGCRF1CFG, 0x11 },
  165. { STV090x_AGCRF2CFG, 0x13 },
  166. { STV090x_TSGENERAL1X, 0x14 },
  167. { STV090x_TSTTNR2, 0x21 },
  168. { STV090x_TSTTNR4, 0x21 },
  169. { STV090x_P2_DISTXCTL, 0x22 },
  170. { STV090x_P2_F22TX, 0xc0 },
  171. { STV090x_P2_F22RX, 0xc0 },
  172. { STV090x_P2_DISRXCTL, 0x00 },
  173. { STV090x_P2_DMDCFGMD, 0xF9 },
  174. { STV090x_P2_DEMOD, 0x08 },
  175. { STV090x_P2_DMDCFG3, 0xc4 },
  176. { STV090x_P2_CARFREQ, 0xed },
  177. { STV090x_P2_LDT, 0xd0 },
  178. { STV090x_P2_LDT2, 0xb8 },
  179. { STV090x_P2_TMGCFG, 0xd2 },
  180. { STV090x_P2_TMGTHRISE, 0x20 },
  181. { STV090x_P1_TMGCFG, 0xd2 },
  182. { STV090x_P2_TMGTHFALL, 0x00 },
  183. { STV090x_P2_FECSPY, 0x88 },
  184. { STV090x_P2_FSPYDATA, 0x3a },
  185. { STV090x_P2_FBERCPT4, 0x00 },
  186. { STV090x_P2_FSPYBER, 0x10 },
  187. { STV090x_P2_ERRCTRL1, 0x35 },
  188. { STV090x_P2_ERRCTRL2, 0xc1 },
  189. { STV090x_P2_CFRICFG, 0xf8 },
  190. { STV090x_P2_NOSCFG, 0x1c },
  191. { STV090x_P2_DMDTOM, 0x20 },
  192. { STV090x_P2_CORRELMANT, 0x70 },
  193. { STV090x_P2_CORRELABS, 0x88 },
  194. { STV090x_P2_AGC2O, 0x5b },
  195. { STV090x_P2_AGC2REF, 0x38 },
  196. { STV090x_P2_CARCFG, 0xe4 },
  197. { STV090x_P2_ACLC, 0x1A },
  198. { STV090x_P2_BCLC, 0x09 },
  199. { STV090x_P2_CARHDR, 0x08 },
  200. { STV090x_P2_KREFTMG, 0xc1 },
  201. { STV090x_P2_SFRUPRATIO, 0xf0 },
  202. { STV090x_P2_SFRLOWRATIO, 0x70 },
  203. { STV090x_P2_SFRSTEP, 0x58 },
  204. { STV090x_P2_TMGCFG2, 0x01 },
  205. { STV090x_P2_CAR2CFG, 0x26 },
  206. { STV090x_P2_BCLC2S2Q, 0x86 },
  207. { STV090x_P2_BCLC2S28, 0x86 },
  208. { STV090x_P2_SMAPCOEF7, 0x77 },
  209. { STV090x_P2_SMAPCOEF6, 0x85 },
  210. { STV090x_P2_SMAPCOEF5, 0x77 },
  211. { STV090x_P2_TSCFGL, 0x20 },
  212. { STV090x_P2_DMDCFG2, 0x3b },
  213. { STV090x_P2_MODCODLST0, 0xff },
  214. { STV090x_P2_MODCODLST1, 0xff },
  215. { STV090x_P2_MODCODLST2, 0xff },
  216. { STV090x_P2_MODCODLST3, 0xff },
  217. { STV090x_P2_MODCODLST4, 0xff },
  218. { STV090x_P2_MODCODLST5, 0xff },
  219. { STV090x_P2_MODCODLST6, 0xff },
  220. { STV090x_P2_MODCODLST7, 0xcc },
  221. { STV090x_P2_MODCODLST8, 0xcc },
  222. { STV090x_P2_MODCODLST9, 0xcc },
  223. { STV090x_P2_MODCODLSTA, 0xcc },
  224. { STV090x_P2_MODCODLSTB, 0xcc },
  225. { STV090x_P2_MODCODLSTC, 0xcc },
  226. { STV090x_P2_MODCODLSTD, 0xcc },
  227. { STV090x_P2_MODCODLSTE, 0xcc },
  228. { STV090x_P2_MODCODLSTF, 0xcf },
  229. { STV090x_P1_DISTXCTL, 0x22 },
  230. { STV090x_P1_F22TX, 0xc0 },
  231. { STV090x_P1_F22RX, 0xc0 },
  232. { STV090x_P1_DISRXCTL, 0x00 },
  233. { STV090x_P1_DMDCFGMD, 0xf9 },
  234. { STV090x_P1_DEMOD, 0x08 },
  235. { STV090x_P1_DMDCFG3, 0xc4 },
  236. { STV090x_P1_DMDTOM, 0x20 },
  237. { STV090x_P1_CARFREQ, 0xed },
  238. { STV090x_P1_LDT, 0xd0 },
  239. { STV090x_P1_LDT2, 0xb8 },
  240. { STV090x_P1_TMGCFG, 0xd2 },
  241. { STV090x_P1_TMGTHRISE, 0x20 },
  242. { STV090x_P1_TMGTHFALL, 0x00 },
  243. { STV090x_P1_SFRUPRATIO, 0xf0 },
  244. { STV090x_P1_SFRLOWRATIO, 0x70 },
  245. { STV090x_P1_TSCFGL, 0x20 },
  246. { STV090x_P1_FECSPY, 0x88 },
  247. { STV090x_P1_FSPYDATA, 0x3a },
  248. { STV090x_P1_FBERCPT4, 0x00 },
  249. { STV090x_P1_FSPYBER, 0x10 },
  250. { STV090x_P1_ERRCTRL1, 0x35 },
  251. { STV090x_P1_ERRCTRL2, 0xc1 },
  252. { STV090x_P1_CFRICFG, 0xf8 },
  253. { STV090x_P1_NOSCFG, 0x1c },
  254. { STV090x_P1_CORRELMANT, 0x70 },
  255. { STV090x_P1_CORRELABS, 0x88 },
  256. { STV090x_P1_AGC2O, 0x5b },
  257. { STV090x_P1_AGC2REF, 0x38 },
  258. { STV090x_P1_CARCFG, 0xe4 },
  259. { STV090x_P1_ACLC, 0x1A },
  260. { STV090x_P1_BCLC, 0x09 },
  261. { STV090x_P1_CARHDR, 0x08 },
  262. { STV090x_P1_KREFTMG, 0xc1 },
  263. { STV090x_P1_SFRSTEP, 0x58 },
  264. { STV090x_P1_TMGCFG2, 0x01 },
  265. { STV090x_P1_CAR2CFG, 0x26 },
  266. { STV090x_P1_BCLC2S2Q, 0x86 },
  267. { STV090x_P1_BCLC2S28, 0x86 },
  268. { STV090x_P1_SMAPCOEF7, 0x77 },
  269. { STV090x_P1_SMAPCOEF6, 0x85 },
  270. { STV090x_P1_SMAPCOEF5, 0x77 },
  271. { STV090x_P1_DMDCFG2, 0x3b },
  272. { STV090x_P1_MODCODLST0, 0xff },
  273. { STV090x_P1_MODCODLST1, 0xff },
  274. { STV090x_P1_MODCODLST2, 0xff },
  275. { STV090x_P1_MODCODLST3, 0xff },
  276. { STV090x_P1_MODCODLST4, 0xff },
  277. { STV090x_P1_MODCODLST5, 0xff },
  278. { STV090x_P1_MODCODLST6, 0xff },
  279. { STV090x_P1_MODCODLST7, 0xcc },
  280. { STV090x_P1_MODCODLST8, 0xcc },
  281. { STV090x_P1_MODCODLST9, 0xcc },
  282. { STV090x_P1_MODCODLSTA, 0xcc },
  283. { STV090x_P1_MODCODLSTB, 0xcc },
  284. { STV090x_P1_MODCODLSTC, 0xcc },
  285. { STV090x_P1_MODCODLSTD, 0xcc },
  286. { STV090x_P1_MODCODLSTE, 0xcc },
  287. { STV090x_P1_MODCODLSTF, 0xcf },
  288. { STV090x_GENCFG, 0x1d },
  289. { STV090x_NBITER_NF4, 0x37 },
  290. { STV090x_NBITER_NF5, 0x29 },
  291. { STV090x_NBITER_NF6, 0x37 },
  292. { STV090x_NBITER_NF7, 0x33 },
  293. { STV090x_NBITER_NF8, 0x31 },
  294. { STV090x_NBITER_NF9, 0x2f },
  295. { STV090x_NBITER_NF10, 0x39 },
  296. { STV090x_NBITER_NF11, 0x3a },
  297. { STV090x_NBITER_NF12, 0x29 },
  298. { STV090x_NBITER_NF13, 0x37 },
  299. { STV090x_NBITER_NF14, 0x33 },
  300. { STV090x_NBITER_NF15, 0x2f },
  301. { STV090x_NBITER_NF16, 0x39 },
  302. { STV090x_NBITER_NF17, 0x3a },
  303. { STV090x_NBITERNOERR, 0x04 },
  304. { STV090x_GAINLLR_NF4, 0x0C },
  305. { STV090x_GAINLLR_NF5, 0x0F },
  306. { STV090x_GAINLLR_NF6, 0x11 },
  307. { STV090x_GAINLLR_NF7, 0x14 },
  308. { STV090x_GAINLLR_NF8, 0x17 },
  309. { STV090x_GAINLLR_NF9, 0x19 },
  310. { STV090x_GAINLLR_NF10, 0x20 },
  311. { STV090x_GAINLLR_NF11, 0x21 },
  312. { STV090x_GAINLLR_NF12, 0x0D },
  313. { STV090x_GAINLLR_NF13, 0x0F },
  314. { STV090x_GAINLLR_NF14, 0x13 },
  315. { STV090x_GAINLLR_NF15, 0x1A },
  316. { STV090x_GAINLLR_NF16, 0x1F },
  317. { STV090x_GAINLLR_NF17, 0x21 },
  318. { STV090x_RCCFGH, 0x20 },
  319. { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
  320. { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
  321. { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
  322. { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
  323. };
  324. static struct stv090x_reg stv0903_initval[] = {
  325. { STV090x_OUTCFG, 0x00 },
  326. { STV090x_AGCRF1CFG, 0x11 },
  327. { STV090x_STOPCLK1, 0x48 },
  328. { STV090x_STOPCLK2, 0x14 },
  329. { STV090x_TSTTNR1, 0x27 },
  330. { STV090x_TSTTNR2, 0x21 },
  331. { STV090x_P1_DISTXCTL, 0x22 },
  332. { STV090x_P1_F22TX, 0xc0 },
  333. { STV090x_P1_F22RX, 0xc0 },
  334. { STV090x_P1_DISRXCTL, 0x00 },
  335. { STV090x_P1_DMDCFGMD, 0xF9 },
  336. { STV090x_P1_DEMOD, 0x08 },
  337. { STV090x_P1_DMDCFG3, 0xc4 },
  338. { STV090x_P1_CARFREQ, 0xed },
  339. { STV090x_P1_TNRCFG2, 0x82 },
  340. { STV090x_P1_LDT, 0xd0 },
  341. { STV090x_P1_LDT2, 0xb8 },
  342. { STV090x_P1_TMGCFG, 0xd2 },
  343. { STV090x_P1_TMGTHRISE, 0x20 },
  344. { STV090x_P1_TMGTHFALL, 0x00 },
  345. { STV090x_P1_SFRUPRATIO, 0xf0 },
  346. { STV090x_P1_SFRLOWRATIO, 0x70 },
  347. { STV090x_P1_TSCFGL, 0x20 },
  348. { STV090x_P1_FECSPY, 0x88 },
  349. { STV090x_P1_FSPYDATA, 0x3a },
  350. { STV090x_P1_FBERCPT4, 0x00 },
  351. { STV090x_P1_FSPYBER, 0x10 },
  352. { STV090x_P1_ERRCTRL1, 0x35 },
  353. { STV090x_P1_ERRCTRL2, 0xc1 },
  354. { STV090x_P1_CFRICFG, 0xf8 },
  355. { STV090x_P1_NOSCFG, 0x1c },
  356. { STV090x_P1_DMDTOM, 0x20 },
  357. { STV090x_P1_CORRELMANT, 0x70 },
  358. { STV090x_P1_CORRELABS, 0x88 },
  359. { STV090x_P1_AGC2O, 0x5b },
  360. { STV090x_P1_AGC2REF, 0x38 },
  361. { STV090x_P1_CARCFG, 0xe4 },
  362. { STV090x_P1_ACLC, 0x1A },
  363. { STV090x_P1_BCLC, 0x09 },
  364. { STV090x_P1_CARHDR, 0x08 },
  365. { STV090x_P1_KREFTMG, 0xc1 },
  366. { STV090x_P1_SFRSTEP, 0x58 },
  367. { STV090x_P1_TMGCFG2, 0x01 },
  368. { STV090x_P1_CAR2CFG, 0x26 },
  369. { STV090x_P1_BCLC2S2Q, 0x86 },
  370. { STV090x_P1_BCLC2S28, 0x86 },
  371. { STV090x_P1_SMAPCOEF7, 0x77 },
  372. { STV090x_P1_SMAPCOEF6, 0x85 },
  373. { STV090x_P1_SMAPCOEF5, 0x77 },
  374. { STV090x_P1_DMDCFG2, 0x3b },
  375. { STV090x_P1_MODCODLST0, 0xff },
  376. { STV090x_P1_MODCODLST1, 0xff },
  377. { STV090x_P1_MODCODLST2, 0xff },
  378. { STV090x_P1_MODCODLST3, 0xff },
  379. { STV090x_P1_MODCODLST4, 0xff },
  380. { STV090x_P1_MODCODLST5, 0xff },
  381. { STV090x_P1_MODCODLST6, 0xff },
  382. { STV090x_P1_MODCODLST7, 0xcc },
  383. { STV090x_P1_MODCODLST8, 0xcc },
  384. { STV090x_P1_MODCODLST9, 0xcc },
  385. { STV090x_P1_MODCODLSTA, 0xcc },
  386. { STV090x_P1_MODCODLSTB, 0xcc },
  387. { STV090x_P1_MODCODLSTC, 0xcc },
  388. { STV090x_P1_MODCODLSTD, 0xcc },
  389. { STV090x_P1_MODCODLSTE, 0xcc },
  390. { STV090x_P1_MODCODLSTF, 0xcf },
  391. { STV090x_GENCFG, 0x1c },
  392. { STV090x_NBITER_NF4, 0x37 },
  393. { STV090x_NBITER_NF5, 0x29 },
  394. { STV090x_NBITER_NF6, 0x37 },
  395. { STV090x_NBITER_NF7, 0x33 },
  396. { STV090x_NBITER_NF8, 0x31 },
  397. { STV090x_NBITER_NF9, 0x2f },
  398. { STV090x_NBITER_NF10, 0x39 },
  399. { STV090x_NBITER_NF11, 0x3a },
  400. { STV090x_NBITER_NF12, 0x29 },
  401. { STV090x_NBITER_NF13, 0x37 },
  402. { STV090x_NBITER_NF14, 0x33 },
  403. { STV090x_NBITER_NF15, 0x2f },
  404. { STV090x_NBITER_NF16, 0x39 },
  405. { STV090x_NBITER_NF17, 0x3a },
  406. { STV090x_NBITERNOERR, 0x04 },
  407. { STV090x_GAINLLR_NF4, 0x0C },
  408. { STV090x_GAINLLR_NF5, 0x0F },
  409. { STV090x_GAINLLR_NF6, 0x11 },
  410. { STV090x_GAINLLR_NF7, 0x14 },
  411. { STV090x_GAINLLR_NF8, 0x17 },
  412. { STV090x_GAINLLR_NF9, 0x19 },
  413. { STV090x_GAINLLR_NF10, 0x20 },
  414. { STV090x_GAINLLR_NF11, 0x21 },
  415. { STV090x_GAINLLR_NF12, 0x0D },
  416. { STV090x_GAINLLR_NF13, 0x0F },
  417. { STV090x_GAINLLR_NF14, 0x13 },
  418. { STV090x_GAINLLR_NF15, 0x1A },
  419. { STV090x_GAINLLR_NF16, 0x1F },
  420. { STV090x_GAINLLR_NF17, 0x21 },
  421. { STV090x_RCCFGH, 0x20 },
  422. { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
  423. { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
  424. };
  425. static struct stv090x_reg stv0900_cut20_val[] = {
  426. { STV090x_P2_DMDCFG3, 0xe8 },
  427. { STV090x_P2_DMDCFG4, 0x10 },
  428. { STV090x_P2_CARFREQ, 0x38 },
  429. { STV090x_P2_CARHDR, 0x20 },
  430. { STV090x_P2_KREFTMG, 0x5a },
  431. { STV090x_P2_SMAPCOEF7, 0x06 },
  432. { STV090x_P2_SMAPCOEF6, 0x00 },
  433. { STV090x_P2_SMAPCOEF5, 0x04 },
  434. { STV090x_P2_NOSCFG, 0x0c },
  435. { STV090x_P1_DMDCFG3, 0xe8 },
  436. { STV090x_P1_DMDCFG4, 0x10 },
  437. { STV090x_P1_CARFREQ, 0x38 },
  438. { STV090x_P1_CARHDR, 0x20 },
  439. { STV090x_P1_KREFTMG, 0x5a },
  440. { STV090x_P1_SMAPCOEF7, 0x06 },
  441. { STV090x_P1_SMAPCOEF6, 0x00 },
  442. { STV090x_P1_SMAPCOEF5, 0x04 },
  443. { STV090x_P1_NOSCFG, 0x0c },
  444. { STV090x_GAINLLR_NF4, 0x21 },
  445. { STV090x_GAINLLR_NF5, 0x21 },
  446. { STV090x_GAINLLR_NF6, 0x20 },
  447. { STV090x_GAINLLR_NF7, 0x1F },
  448. { STV090x_GAINLLR_NF8, 0x1E },
  449. { STV090x_GAINLLR_NF9, 0x1E },
  450. { STV090x_GAINLLR_NF10, 0x1D },
  451. { STV090x_GAINLLR_NF11, 0x1B },
  452. { STV090x_GAINLLR_NF12, 0x20 },
  453. { STV090x_GAINLLR_NF13, 0x20 },
  454. { STV090x_GAINLLR_NF14, 0x20 },
  455. { STV090x_GAINLLR_NF15, 0x20 },
  456. { STV090x_GAINLLR_NF16, 0x20 },
  457. { STV090x_GAINLLR_NF17, 0x21 },
  458. };
  459. static struct stv090x_reg stv0903_cut20_val[] = {
  460. { STV090x_P1_DMDCFG3, 0xe8 },
  461. { STV090x_P1_DMDCFG4, 0x10 },
  462. { STV090x_P1_CARFREQ, 0x38 },
  463. { STV090x_P1_CARHDR, 0x20 },
  464. { STV090x_P1_KREFTMG, 0x5a },
  465. { STV090x_P1_SMAPCOEF7, 0x06 },
  466. { STV090x_P1_SMAPCOEF6, 0x00 },
  467. { STV090x_P1_SMAPCOEF5, 0x04 },
  468. { STV090x_P1_NOSCFG, 0x0c },
  469. { STV090x_GAINLLR_NF4, 0x21 },
  470. { STV090x_GAINLLR_NF5, 0x21 },
  471. { STV090x_GAINLLR_NF6, 0x20 },
  472. { STV090x_GAINLLR_NF7, 0x1F },
  473. { STV090x_GAINLLR_NF8, 0x1E },
  474. { STV090x_GAINLLR_NF9, 0x1E },
  475. { STV090x_GAINLLR_NF10, 0x1D },
  476. { STV090x_GAINLLR_NF11, 0x1B },
  477. { STV090x_GAINLLR_NF12, 0x20 },
  478. { STV090x_GAINLLR_NF13, 0x20 },
  479. { STV090x_GAINLLR_NF14, 0x20 },
  480. { STV090x_GAINLLR_NF15, 0x20 },
  481. { STV090x_GAINLLR_NF16, 0x20 },
  482. { STV090x_GAINLLR_NF17, 0x21 }
  483. };
  484. /* Cut 1.x Long Frame Tracking CR loop */
  485. static struct stv090x_long_frame_crloop stv090x_s2_crl[] = {
  486. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  487. { STV090x_QPSK_12, 0x1c, 0x0d, 0x1b, 0x2c, 0x3a, 0x1c, 0x2a, 0x3b, 0x2a, 0x1b },
  488. { STV090x_QPSK_35, 0x2c, 0x0d, 0x2b, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b, 0x2a, 0x0b },
  489. { STV090x_QPSK_23, 0x2c, 0x0d, 0x2b, 0x2c, 0x0b, 0x0c, 0x3a, 0x1b, 0x2a, 0x3a },
  490. { STV090x_QPSK_34, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  491. { STV090x_QPSK_45, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  492. { STV090x_QPSK_56, 0x0d, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  493. { STV090x_QPSK_89, 0x0d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  494. { STV090x_QPSK_910, 0x1d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  495. { STV090x_8PSK_35, 0x29, 0x3b, 0x09, 0x2b, 0x38, 0x0b, 0x18, 0x1a, 0x08, 0x0a },
  496. { STV090x_8PSK_23, 0x0a, 0x3b, 0x29, 0x2b, 0x19, 0x0b, 0x38, 0x1a, 0x18, 0x0a },
  497. { STV090x_8PSK_34, 0x3a, 0x3b, 0x2a, 0x2b, 0x39, 0x0b, 0x19, 0x1a, 0x38, 0x0a },
  498. { STV090x_8PSK_56, 0x1b, 0x3b, 0x0b, 0x2b, 0x1a, 0x0b, 0x39, 0x1a, 0x19, 0x0a },
  499. { STV090x_8PSK_89, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 },
  500. { STV090x_8PSK_910, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 }
  501. };
  502. /* Cut 2.0 Long Frame Tracking CR loop */
  503. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
  504. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  505. { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
  506. { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
  507. { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
  508. { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  509. { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  510. { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  511. { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  512. { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  513. { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
  514. { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
  515. { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
  516. { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
  517. { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
  518. { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
  519. };
  520. /* Cut 2.0 Long Frame Tracking CR Loop */
  521. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
  522. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  523. { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
  524. { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
  525. { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  526. { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  527. { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  528. { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  529. { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  530. { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  531. { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  532. { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  533. { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
  534. };
  535. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
  536. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  537. { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
  538. { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
  539. { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
  540. };
  541. /* Cut 1.2 & 2.0 Short Frame Tracking CR Loop */
  542. static struct stv090x_short_frame_crloop stv090x_s2_short_crl[] = {
  543. /* MODCOD 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
  544. { STV090x_QPSK, 0x3c, 0x2f, 0x2b, 0x2e, 0x0b, 0x0e, 0x3a, 0x0e, 0x2a, 0x3d },
  545. { STV090x_8PSK, 0x0b, 0x3e, 0x2a, 0x0e, 0x0a, 0x2d, 0x19, 0x0d, 0x09, 0x3c },
  546. { STV090x_16APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d },
  547. { STV090x_32APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d }
  548. };
  549. static inline s32 comp2(s32 __x, s32 __width)
  550. {
  551. if (__width == 32)
  552. return __x;
  553. else
  554. return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
  555. }
  556. static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
  557. {
  558. const struct stv090x_config *config = state->config;
  559. int ret;
  560. u8 b0[] = { reg >> 8, reg & 0xff };
  561. u8 buf;
  562. struct i2c_msg msg[] = {
  563. { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
  564. { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
  565. };
  566. ret = i2c_transfer(state->i2c, msg, 2);
  567. if (ret != 2) {
  568. if (ret != -ERESTARTSYS)
  569. dprintk(FE_ERROR, 1,
  570. "Read error, Reg=[0x%02x], Status=%d",
  571. reg, ret);
  572. return ret < 0 ? ret : -EREMOTEIO;
  573. }
  574. if (unlikely(*state->verbose >= FE_DEBUGREG))
  575. dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
  576. reg, buf);
  577. return (unsigned int) buf;
  578. }
  579. static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
  580. {
  581. const struct stv090x_config *config = state->config;
  582. int ret;
  583. u8 buf[2 + count];
  584. struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
  585. buf[0] = reg >> 8;
  586. buf[1] = reg & 0xff;
  587. memcpy(&buf[2], data, count);
  588. if (unlikely(*state->verbose >= FE_DEBUGREG)) {
  589. int i;
  590. printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
  591. for (i = 0; i < count; i++)
  592. printk(" %02x", data[i]);
  593. printk("\n");
  594. }
  595. ret = i2c_transfer(state->i2c, &i2c_msg, 1);
  596. if (ret != 1) {
  597. if (ret != -ERESTARTSYS)
  598. dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
  599. reg, data[0], count, ret);
  600. return ret < 0 ? ret : -EREMOTEIO;
  601. }
  602. return 0;
  603. }
  604. static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
  605. {
  606. return stv090x_write_regs(state, reg, &data, 1);
  607. }
  608. static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  609. {
  610. struct stv090x_state *state = fe->demodulator_priv;
  611. u32 reg;
  612. reg = STV090x_READ_DEMOD(state, I2CRPT);
  613. if (enable) {
  614. dprintk(FE_DEBUG, 1, "Enable Gate");
  615. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
  616. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
  617. goto err;
  618. } else {
  619. dprintk(FE_DEBUG, 1, "Disable Gate");
  620. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
  621. if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
  622. goto err;
  623. }
  624. return 0;
  625. err:
  626. dprintk(FE_ERROR, 1, "I/O error");
  627. return -1;
  628. }
  629. static void stv090x_get_lock_tmg(struct stv090x_state *state)
  630. {
  631. switch (state->algo) {
  632. case STV090x_BLIND_SEARCH:
  633. dprintk(FE_DEBUG, 1, "Blind Search");
  634. if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
  635. state->DemodTimeout = 1500;
  636. state->FecTimeout = 400;
  637. } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
  638. state->DemodTimeout = 1000;
  639. state->FecTimeout = 300;
  640. } else { /*SR >20Msps*/
  641. state->DemodTimeout = 700;
  642. state->FecTimeout = 100;
  643. }
  644. break;
  645. case STV090x_COLD_SEARCH:
  646. case STV090x_WARM_SEARCH:
  647. default:
  648. dprintk(FE_DEBUG, 1, "Normal Search");
  649. if (state->srate <= 1000000) { /*SR <=1Msps*/
  650. state->DemodTimeout = 4500;
  651. state->FecTimeout = 1700;
  652. } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
  653. state->DemodTimeout = 2500;
  654. state->FecTimeout = 1100;
  655. } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
  656. state->DemodTimeout = 1000;
  657. state->FecTimeout = 550;
  658. } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
  659. state->DemodTimeout = 700;
  660. state->FecTimeout = 250;
  661. } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
  662. state->DemodTimeout = 400;
  663. state->FecTimeout = 130;
  664. } else { /*SR >20Msps*/
  665. state->DemodTimeout = 300;
  666. state->FecTimeout = 100;
  667. }
  668. break;
  669. }
  670. if (state->algo == STV090x_WARM_SEARCH)
  671. state->DemodTimeout /= 2;
  672. }
  673. static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
  674. {
  675. u32 sym;
  676. if (srate > 60000000) {
  677. sym = (srate << 4); /* SR * 2^16 / master_clk */
  678. sym /= (state->mclk >> 12);
  679. } else if (srate > 6000000) {
  680. sym = (srate << 6);
  681. sym /= (state->mclk >> 10);
  682. } else {
  683. sym = (srate << 9);
  684. sym /= (state->mclk >> 7);
  685. }
  686. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
  687. goto err;
  688. if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
  689. goto err;
  690. return 0;
  691. err:
  692. dprintk(FE_ERROR, 1, "I/O error");
  693. return -1;
  694. }
  695. static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
  696. {
  697. u32 sym;
  698. srate = 105 * (srate / 100);
  699. if (srate > 60000000) {
  700. sym = (srate << 4); /* SR * 2^16 / master_clk */
  701. sym /= (state->mclk >> 12);
  702. } else if (srate > 6000000) {
  703. sym = (srate << 6);
  704. sym /= (state->mclk >> 10);
  705. } else {
  706. sym = (srate << 9);
  707. sym /= (state->mclk >> 7);
  708. }
  709. if (sym < 0x7fff) {
  710. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
  711. goto err;
  712. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
  713. goto err;
  714. } else {
  715. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
  716. goto err;
  717. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
  718. goto err;
  719. }
  720. return 0;
  721. err:
  722. dprintk(FE_ERROR, 1, "I/O error");
  723. return -1;
  724. }
  725. static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
  726. {
  727. u32 sym;
  728. srate = 95 * (srate / 100);
  729. if (srate > 60000000) {
  730. sym = (srate << 4); /* SR * 2^16 / master_clk */
  731. sym /= (state->mclk >> 12);
  732. } else if (srate > 6000000) {
  733. sym = (srate << 6);
  734. sym /= (state->mclk >> 10);
  735. } else {
  736. sym = (srate << 9);
  737. sym /= (state->mclk >> 7);
  738. }
  739. if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
  740. goto err;
  741. if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
  742. goto err;
  743. return 0;
  744. err:
  745. dprintk(FE_ERROR, 1, "I/O error");
  746. return -1;
  747. }
  748. static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
  749. {
  750. u32 ro;
  751. switch (rolloff) {
  752. case STV090x_RO_20:
  753. ro = 20;
  754. break;
  755. case STV090x_RO_25:
  756. ro = 25;
  757. break;
  758. case STV090x_RO_35:
  759. default:
  760. ro = 35;
  761. break;
  762. }
  763. return srate + (srate * ro) / 100;
  764. }
  765. static int stv090x_set_vit_thacq(struct stv090x_state *state)
  766. {
  767. if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
  768. goto err;
  769. if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
  770. goto err;
  771. if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
  772. goto err;
  773. if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
  774. goto err;
  775. if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
  776. goto err;
  777. if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
  778. goto err;
  779. return 0;
  780. err:
  781. dprintk(FE_ERROR, 1, "I/O error");
  782. return -1;
  783. }
  784. static int stv090x_set_vit_thtracq(struct stv090x_state *state)
  785. {
  786. if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
  787. goto err;
  788. if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
  789. goto err;
  790. if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
  791. goto err;
  792. if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
  793. goto err;
  794. if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
  795. goto err;
  796. if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
  797. goto err;
  798. return 0;
  799. err:
  800. dprintk(FE_ERROR, 1, "I/O error");
  801. return -1;
  802. }
  803. static int stv090x_set_viterbi(struct stv090x_state *state)
  804. {
  805. switch (state->search_mode) {
  806. case STV090x_SEARCH_AUTO:
  807. if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
  808. goto err;
  809. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
  810. goto err;
  811. break;
  812. case STV090x_SEARCH_DVBS1:
  813. if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
  814. goto err;
  815. switch (state->fec) {
  816. case STV090x_PR12:
  817. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  818. goto err;
  819. break;
  820. case STV090x_PR23:
  821. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  822. goto err;
  823. break;
  824. case STV090x_PR34:
  825. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
  826. goto err;
  827. break;
  828. case STV090x_PR56:
  829. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
  830. goto err;
  831. break;
  832. case STV090x_PR78:
  833. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
  834. goto err;
  835. break;
  836. default:
  837. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
  838. goto err;
  839. break;
  840. }
  841. break;
  842. case STV090x_SEARCH_DSS:
  843. if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
  844. goto err;
  845. switch (state->fec) {
  846. case STV090x_PR12:
  847. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  848. goto err;
  849. break;
  850. case STV090x_PR23:
  851. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  852. goto err;
  853. break;
  854. case STV090x_PR67:
  855. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
  856. goto err;
  857. break;
  858. default:
  859. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
  860. goto err;
  861. break;
  862. }
  863. break;
  864. default:
  865. break;
  866. }
  867. return 0;
  868. err:
  869. dprintk(FE_ERROR, 1, "I/O error");
  870. return -1;
  871. }
  872. static int stv090x_stop_modcod(struct stv090x_state *state)
  873. {
  874. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  875. goto err;
  876. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  877. goto err;
  878. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  879. goto err;
  880. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  881. goto err;
  882. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  883. goto err;
  884. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  885. goto err;
  886. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  887. goto err;
  888. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
  889. goto err;
  890. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
  891. goto err;
  892. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
  893. goto err;
  894. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
  895. goto err;
  896. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
  897. goto err;
  898. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
  899. goto err;
  900. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
  901. goto err;
  902. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  903. goto err;
  904. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
  905. goto err;
  906. return 0;
  907. err:
  908. dprintk(FE_ERROR, 1, "I/O error");
  909. return -1;
  910. }
  911. static int stv090x_activate_modcod(struct stv090x_state *state)
  912. {
  913. u32 matype, modcod, f_mod, index;
  914. if (state->dev_ver <= 0x11) {
  915. msleep(5);
  916. modcod = STV090x_READ_DEMOD(state, PLHMODCOD);
  917. matype = modcod & 0x03;
  918. modcod = (modcod & 0x7f) >> 2;
  919. index = STV090x_ADDR_OFFST(state, MODCODLSTF) - (modcod / 2);
  920. switch (matype) {
  921. default:
  922. case 0:
  923. f_mod = 14;
  924. break;
  925. case 1:
  926. f_mod = 13;
  927. break;
  928. case 2:
  929. f_mod = 11;
  930. break;
  931. case 3:
  932. f_mod = 7;
  933. break;
  934. }
  935. if (matype <= 1) {
  936. if (modcod % 2) {
  937. if (stv090x_write_reg(state, index, 0xf0 | f_mod) < 0)
  938. goto err;
  939. } else {
  940. if (stv090x_write_reg(state, index, (f_mod << 4) | 0x0f) < 0)
  941. goto err;
  942. }
  943. }
  944. } else if (state->dev_ver >= 0x12) {
  945. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  946. goto err;
  947. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
  948. goto err;
  949. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
  950. goto err;
  951. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
  952. goto err;
  953. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
  954. goto err;
  955. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
  956. goto err;
  957. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
  958. goto err;
  959. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  960. goto err;
  961. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  962. goto err;
  963. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  964. goto err;
  965. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  966. goto err;
  967. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  968. goto err;
  969. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  970. goto err;
  971. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  972. goto err;
  973. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
  974. goto err;
  975. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  976. goto err;
  977. }
  978. return 0;
  979. err:
  980. dprintk(FE_ERROR, 1, "I/O error");
  981. return -1;
  982. }
  983. static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
  984. {
  985. u32 reg;
  986. switch (state->demod) {
  987. case STV090x_DEMODULATOR_0:
  988. mutex_lock(&demod_lock);
  989. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  990. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
  991. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  992. goto err;
  993. mutex_unlock(&demod_lock);
  994. break;
  995. case STV090x_DEMODULATOR_1:
  996. mutex_lock(&demod_lock);
  997. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  998. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
  999. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  1000. goto err;
  1001. mutex_unlock(&demod_lock);
  1002. break;
  1003. default:
  1004. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  1005. break;
  1006. }
  1007. return 0;
  1008. err:
  1009. mutex_unlock(&demod_lock);
  1010. dprintk(FE_ERROR, 1, "I/O error");
  1011. return -1;
  1012. }
  1013. static int stv090x_delivery_search(struct stv090x_state *state)
  1014. {
  1015. u32 reg;
  1016. switch (state->search_mode) {
  1017. case STV090x_SEARCH_DVBS1:
  1018. case STV090x_SEARCH_DSS:
  1019. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1020. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1021. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1022. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1023. goto err;
  1024. /* Activate Viterbi decoder in legacy search, do not use FRESVIT1, might impact VITERBI2 */
  1025. if (stv090x_vitclk_ctl(state, 0) < 0)
  1026. goto err;
  1027. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  1028. goto err;
  1029. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1030. goto err;
  1031. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
  1032. goto err;
  1033. stv090x_set_vit_thacq(state);
  1034. stv090x_set_viterbi(state);
  1035. break;
  1036. case STV090x_SEARCH_DVBS2:
  1037. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1038. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1039. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1040. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1041. goto err;
  1042. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1043. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1044. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1045. goto err;
  1046. if (stv090x_vitclk_ctl(state, 1) < 0)
  1047. goto err;
  1048. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
  1049. goto err;
  1050. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1051. goto err;
  1052. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1053. goto err;
  1054. if (state->demod_mode != STV090x_SINGLE) {
  1055. if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
  1056. stv090x_stop_modcod(state);
  1057. else
  1058. stv090x_activate_modcod(state);
  1059. }
  1060. break;
  1061. case STV090x_SEARCH_AUTO:
  1062. default:
  1063. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1064. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1065. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1066. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1067. goto err;
  1068. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1069. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1070. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1071. goto err;
  1072. if (stv090x_vitclk_ctl(state, 0) < 0)
  1073. goto err;
  1074. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  1075. goto err;
  1076. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1077. goto err;
  1078. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1079. goto err;
  1080. if (state->demod_mode != STV090x_SINGLE) {
  1081. if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
  1082. stv090x_stop_modcod(state);
  1083. else
  1084. stv090x_activate_modcod(state);
  1085. }
  1086. stv090x_set_vit_thacq(state);
  1087. stv090x_set_viterbi(state);
  1088. break;
  1089. }
  1090. return 0;
  1091. err:
  1092. dprintk(FE_ERROR, 1, "I/O error");
  1093. return -1;
  1094. }
  1095. static int stv090x_start_search(struct stv090x_state *state)
  1096. {
  1097. u32 reg;
  1098. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1099. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
  1100. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1101. goto err;
  1102. if (state->dev_ver == 0x10) {
  1103. if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
  1104. goto err;
  1105. }
  1106. if (state->dev_ver < 0x20) {
  1107. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
  1108. goto err;
  1109. }
  1110. if (state->srate <= 5000000) {
  1111. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
  1112. goto err;
  1113. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
  1114. goto err;
  1115. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
  1116. goto err;
  1117. if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
  1118. goto err;
  1119. if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
  1120. goto err;
  1121. /*enlarge the timing bandwith for Low SR*/
  1122. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
  1123. goto err;
  1124. } else {
  1125. /* If the symbol rate is >5 Msps
  1126. Set The carrier search up and low to auto mode */
  1127. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1128. goto err;
  1129. /*reduce the timing bandwith for high SR*/
  1130. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1131. goto err;
  1132. }
  1133. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
  1134. goto err;
  1135. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
  1136. goto err;
  1137. if (state->dev_ver >= 0x20) {
  1138. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1139. goto err;
  1140. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1141. goto err;
  1142. if ((state->search_mode == STV090x_DVBS1) ||
  1143. (state->search_mode == STV090x_DSS) ||
  1144. (state->search_mode == STV090x_SEARCH_AUTO)) {
  1145. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1146. goto err;
  1147. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
  1148. goto err;
  1149. }
  1150. }
  1151. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
  1152. goto err;
  1153. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
  1154. goto err;
  1155. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
  1156. goto err;
  1157. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1158. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1159. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1160. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1161. goto err;
  1162. reg = STV090x_READ_DEMOD(state, DMDCFG2);
  1163. STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
  1164. if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
  1165. goto err;
  1166. if (state->dev_ver >= 0x20) { /*Frequency offset detector setting*/
  1167. if (state->srate < 10000000) {
  1168. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
  1169. goto err;
  1170. } else {
  1171. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
  1172. goto err;
  1173. }
  1174. } else {
  1175. if (state->srate < 10000000) {
  1176. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1177. goto err;
  1178. } else {
  1179. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1180. goto err;
  1181. }
  1182. }
  1183. switch (state->algo) {
  1184. case STV090x_WARM_SEARCH:/*The symbol rate and the exact carrier Frequency are known */
  1185. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1186. goto err;
  1187. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1188. goto err;
  1189. break;
  1190. case STV090x_COLD_SEARCH:/*The symbol rate is known*/
  1191. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1192. goto err;
  1193. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1194. goto err;
  1195. break;
  1196. default:
  1197. break;
  1198. }
  1199. return 0;
  1200. err:
  1201. dprintk(FE_ERROR, 1, "I/O error");
  1202. return -1;
  1203. }
  1204. static int stv090x_get_agc2_min_level(struct stv090x_state *state)
  1205. {
  1206. u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
  1207. s32 i, j, steps, dir;
  1208. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1209. goto err;
  1210. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1211. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1212. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
  1213. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1214. goto err;
  1215. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
  1216. goto err;
  1217. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1218. goto err;
  1219. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
  1220. goto err;
  1221. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1222. goto err;
  1223. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
  1224. goto err;
  1225. stv090x_set_srate(state, 1000000);
  1226. steps = -1 + state->search_range / 1000000;
  1227. steps /= 2;
  1228. steps = (2 * steps) + 1;
  1229. if (steps < 0)
  1230. steps = 1;
  1231. dir = 1;
  1232. freq_step = (1000000 * 256) / (state->mclk / 256);
  1233. freq_init = 0;
  1234. for (i = 0; i < steps; i++) {
  1235. if (dir > 0)
  1236. freq_init = freq_init + (freq_step * i);
  1237. else
  1238. freq_init = freq_init - (freq_step * i);
  1239. dir = -1;
  1240. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
  1241. goto err;
  1242. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
  1243. goto err;
  1244. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
  1245. goto err;
  1246. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
  1247. goto err;
  1248. msleep(10);
  1249. for (j = 0; j < 10; j++) {
  1250. agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1251. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1252. }
  1253. agc2 /= 10;
  1254. agc2_min = 0xffff;
  1255. if (agc2 < 0xffff)
  1256. agc2_min = agc2;
  1257. }
  1258. return agc2_min;
  1259. err:
  1260. dprintk(FE_ERROR, 1, "I/O error");
  1261. return -1;
  1262. }
  1263. static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
  1264. {
  1265. u8 r3, r2, r1, r0;
  1266. s32 srate, int_1, int_2, tmp_1, tmp_2;
  1267. r3 = STV090x_READ_DEMOD(state, SFR3);
  1268. r2 = STV090x_READ_DEMOD(state, SFR2);
  1269. r1 = STV090x_READ_DEMOD(state, SFR1);
  1270. r0 = STV090x_READ_DEMOD(state, SFR0);
  1271. srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
  1272. int_1 = clk >> 16;
  1273. int_2 = srate >> 16;
  1274. tmp_1 = clk % 0x10000;
  1275. tmp_2 = srate % 0x10000;
  1276. srate = (int_1 * int_2) +
  1277. ((int_1 * tmp_2) >> 16) +
  1278. ((int_2 * tmp_1) >> 16);
  1279. return srate;
  1280. }
  1281. static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
  1282. {
  1283. struct dvb_frontend *fe = &state->frontend;
  1284. int tmg_lock = 0, i;
  1285. s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
  1286. u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
  1287. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1288. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
  1289. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1290. goto err;
  1291. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
  1292. goto err;
  1293. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
  1294. goto err;
  1295. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
  1296. goto err;
  1297. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1298. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1299. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
  1300. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1301. goto err;
  1302. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
  1303. goto err;
  1304. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1305. goto err;
  1306. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
  1307. goto err;
  1308. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1309. goto err;
  1310. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
  1311. goto err;
  1312. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
  1313. goto err;
  1314. if (state->dev_ver >= 0x20) {
  1315. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
  1316. goto err;
  1317. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
  1318. goto err;
  1319. } else {
  1320. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1321. goto err;
  1322. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x73) < 0)
  1323. goto err;
  1324. }
  1325. if (state->srate <= 2000000)
  1326. car_step = 1000;
  1327. else if (state->srate <= 5000000)
  1328. car_step = 2000;
  1329. else if (state->srate <= 12000000)
  1330. car_step = 3000;
  1331. else
  1332. car_step = 5000;
  1333. steps = -1 + ((state->search_range / 1000) / car_step);
  1334. steps /= 2;
  1335. steps = (2 * steps) + 1;
  1336. if (steps < 0)
  1337. steps = 1;
  1338. else if (steps > 10) {
  1339. steps = 11;
  1340. car_step = (state->search_range / 1000) / 10;
  1341. }
  1342. cur_step = 0;
  1343. dir = 1;
  1344. freq = state->frequency;
  1345. while ((!tmg_lock) && (cur_step < steps)) {
  1346. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
  1347. goto err;
  1348. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1349. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
  1350. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1351. goto err;
  1352. msleep(50);
  1353. for (i = 0; i < 10; i++) {
  1354. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1355. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1356. tmg_cpt++;
  1357. agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1358. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1359. }
  1360. agc2 /= 10;
  1361. srate_coarse = stv090x_get_srate(state, state->mclk);
  1362. cur_step++;
  1363. dir *= -1;
  1364. if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
  1365. tmg_lock = 1;
  1366. else if (cur_step < steps) {
  1367. if (dir > 0)
  1368. freq += cur_step * car_step;
  1369. else
  1370. freq -= cur_step * car_step;
  1371. /* Setup tuner */
  1372. stv090x_i2c_gate_ctrl(fe, 1);
  1373. if (state->config->tuner_set_frequency)
  1374. state->config->tuner_set_frequency(fe, state->frequency);
  1375. if (state->config->tuner_set_bandwidth)
  1376. state->config->tuner_set_bandwidth(fe, state->tuner_bw);
  1377. stv090x_i2c_gate_ctrl(fe, 0);
  1378. msleep(50);
  1379. stv090x_i2c_gate_ctrl(fe, 1);
  1380. if (state->config->tuner_get_status)
  1381. state->config->tuner_get_status(fe, &reg);
  1382. if (reg)
  1383. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1384. else
  1385. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1386. stv090x_i2c_gate_ctrl(fe, 0);
  1387. }
  1388. }
  1389. if (!tmg_lock)
  1390. srate_coarse = 0;
  1391. else
  1392. srate_coarse = stv090x_get_srate(state, state->mclk);
  1393. return srate_coarse;
  1394. err:
  1395. dprintk(FE_ERROR, 1, "I/O error");
  1396. return -1;
  1397. }
  1398. static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
  1399. {
  1400. u32 srate_coarse, freq_coarse, sym, reg;
  1401. srate_coarse = stv090x_get_srate(state, state->mclk);
  1402. freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
  1403. freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
  1404. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1405. if (sym < state->srate)
  1406. srate_coarse = 0;
  1407. else {
  1408. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
  1409. goto err;
  1410. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
  1411. goto err;
  1412. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1413. goto err;
  1414. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1415. goto err;
  1416. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  1417. goto err;
  1418. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1419. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  1420. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1421. goto err;
  1422. if (state->dev_ver >= 0x20) {
  1423. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1424. goto err;
  1425. } else {
  1426. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1427. goto err;
  1428. }
  1429. if (srate_coarse > 3000000) {
  1430. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1431. sym = (sym / 1000) * 65536;
  1432. sym /= (state->mclk / 1000);
  1433. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1434. goto err;
  1435. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1436. goto err;
  1437. sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
  1438. sym = (sym / 1000) * 65536;
  1439. sym /= (state->mclk / 1000);
  1440. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1441. goto err;
  1442. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1443. goto err;
  1444. sym = (srate_coarse / 1000) * 65536;
  1445. sym /= (state->mclk / 1000);
  1446. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1447. goto err;
  1448. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1449. goto err;
  1450. } else {
  1451. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1452. sym = (sym / 100) * 65536;
  1453. sym /= (state->mclk / 100);
  1454. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1455. goto err;
  1456. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1457. goto err;
  1458. sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
  1459. sym = (sym / 100) * 65536;
  1460. sym /= (state->mclk / 100);
  1461. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1462. goto err;
  1463. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1464. goto err;
  1465. sym = (srate_coarse / 100) * 65536;
  1466. sym /= (state->mclk / 100);
  1467. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1468. goto err;
  1469. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1470. goto err;
  1471. }
  1472. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  1473. goto err;
  1474. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
  1475. goto err;
  1476. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
  1477. goto err;
  1478. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
  1479. goto err;
  1480. }
  1481. return srate_coarse;
  1482. err:
  1483. dprintk(FE_ERROR, 1, "I/O error");
  1484. return -1;
  1485. }
  1486. static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
  1487. {
  1488. s32 timer = 0, lock = 0;
  1489. u32 reg;
  1490. u8 stat;
  1491. while ((timer < timeout) && (!lock)) {
  1492. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1493. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  1494. switch (stat) {
  1495. case 0: /* searching */
  1496. case 1: /* first PLH detected */
  1497. default:
  1498. dprintk(FE_DEBUG, 1, "Demodulator searching ..");
  1499. lock = 0;
  1500. break;
  1501. case 2: /* DVB-S2 mode */
  1502. case 3: /* DVB-S1/legacy mode */
  1503. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1504. lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  1505. break;
  1506. }
  1507. if (!lock)
  1508. msleep(10);
  1509. else
  1510. dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
  1511. timer += 10;
  1512. }
  1513. return lock;
  1514. }
  1515. static int stv090x_blind_search(struct stv090x_state *state)
  1516. {
  1517. u32 agc2, reg, srate_coarse;
  1518. s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
  1519. u8 k_ref, k_max, k_min;
  1520. int coarse_fail, lock;
  1521. if (state->dev_ver < 0x20) {
  1522. k_max = 233;
  1523. k_min = 143;
  1524. } else {
  1525. k_max = 120;
  1526. k_min = 30;
  1527. }
  1528. agc2 = stv090x_get_agc2_min_level(state);
  1529. if (agc2 > STV090x_SEARCH_AGC2_TH) {
  1530. lock = 0;
  1531. } else {
  1532. if (state->dev_ver == 0x10) {
  1533. if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
  1534. goto err;
  1535. }
  1536. if (state->dev_ver < 0x20) {
  1537. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
  1538. goto err;
  1539. }
  1540. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1541. goto err;
  1542. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1543. goto err;
  1544. if (state->dev_ver >= 0x20) {
  1545. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1546. goto err;
  1547. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1548. goto err;
  1549. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1550. goto err;
  1551. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
  1552. goto err;
  1553. }
  1554. k_ref = k_max;
  1555. do {
  1556. if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
  1557. goto err;
  1558. if (stv090x_srate_srch_coarse(state) != 0) {
  1559. srate_coarse = stv090x_srate_srch_fine(state);
  1560. if (srate_coarse != 0) {
  1561. stv090x_get_lock_tmg(state);
  1562. lock = stv090x_get_dmdlock(state, timeout_dmd);
  1563. } else {
  1564. lock = 0;
  1565. }
  1566. } else {
  1567. cpt_fail = 0;
  1568. agc2_ovflw = 0;
  1569. for (i = 0; i < 10; i++) {
  1570. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1571. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1572. if (agc2 >= 0xff00)
  1573. agc2_ovflw++;
  1574. reg = STV090x_READ_DEMOD(state, DSTATUS2);
  1575. if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
  1576. (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
  1577. cpt_fail++;
  1578. }
  1579. if ((cpt_fail > 7) || (agc2_ovflw > 7))
  1580. coarse_fail = 1;
  1581. lock = 0;
  1582. }
  1583. k_ref -= 30;
  1584. } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
  1585. }
  1586. return lock;
  1587. err:
  1588. dprintk(FE_ERROR, 1, "I/O error");
  1589. return -1;
  1590. }
  1591. static int stv090x_chk_tmg(struct stv090x_state *state)
  1592. {
  1593. u32 reg;
  1594. s32 tmg_cpt, i;
  1595. u8 freq, tmg_thh, tmg_thl;
  1596. int tmg_lock;
  1597. freq = STV090x_READ_DEMOD(state, CARFREQ);
  1598. tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
  1599. tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
  1600. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1601. goto err;
  1602. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1603. goto err;
  1604. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1605. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
  1606. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1607. goto err;
  1608. if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
  1609. goto err;
  1610. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
  1611. goto err;
  1612. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
  1613. goto err;
  1614. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
  1615. goto err;
  1616. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1617. goto err;
  1618. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
  1619. goto err;
  1620. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
  1621. goto err;
  1622. msleep(10);
  1623. for (i = 0; i < 10; i++) {
  1624. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1625. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1626. tmg_cpt++;
  1627. msleep(1);
  1628. }
  1629. if (tmg_cpt >= 3)
  1630. tmg_lock = 1;
  1631. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1632. goto err;
  1633. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
  1634. goto err;
  1635. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
  1636. goto err;
  1637. if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
  1638. goto err;
  1639. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
  1640. goto err;
  1641. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
  1642. goto err;
  1643. return tmg_lock;
  1644. err:
  1645. dprintk(FE_ERROR, 1, "I/O error");
  1646. return -1;
  1647. }
  1648. static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
  1649. {
  1650. struct dvb_frontend *fe = &state->frontend;
  1651. u32 reg;
  1652. s32 car_step, steps, cur_step, dir, freq, timeout_lock;
  1653. int lock = 0;
  1654. if (state->srate >= 10000000)
  1655. timeout_lock = timeout_dmd / 3;
  1656. else
  1657. timeout_lock = timeout_dmd / 2;
  1658. lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
  1659. if (!lock) {
  1660. if (state->srate >= 10000000) {
  1661. if (stv090x_chk_tmg(state)) {
  1662. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1663. goto err;
  1664. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1665. goto err;
  1666. lock = stv090x_get_dmdlock(state, timeout_dmd);
  1667. } else {
  1668. lock = 0;
  1669. }
  1670. } else {
  1671. if (state->srate <= 4000000)
  1672. car_step = 1000;
  1673. else if (state->srate <= 7000000)
  1674. car_step = 2000;
  1675. else if (state->srate <= 10000000)
  1676. car_step = 3000;
  1677. else
  1678. car_step = 5000;
  1679. steps = (state->search_range / 1000) / car_step;
  1680. steps /= 2;
  1681. steps = 2 * (steps + 1);
  1682. if (steps < 0)
  1683. steps = 2;
  1684. else if (steps > 12)
  1685. steps = 12;
  1686. cur_step = 1;
  1687. dir = 1;
  1688. if (!lock) {
  1689. freq = state->frequency;
  1690. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
  1691. while ((cur_step <= steps) && (!lock)) {
  1692. if (dir > 0)
  1693. freq += cur_step * car_step;
  1694. else
  1695. freq -= cur_step * car_step;
  1696. /* Setup tuner */
  1697. stv090x_i2c_gate_ctrl(fe, 1);
  1698. if (state->config->tuner_set_frequency)
  1699. state->config->tuner_set_frequency(fe, state->frequency);
  1700. if (state->config->tuner_set_bandwidth)
  1701. state->config->tuner_set_bandwidth(fe, state->tuner_bw);
  1702. stv090x_i2c_gate_ctrl(fe, 0);
  1703. msleep(50);
  1704. stv090x_i2c_gate_ctrl(fe, 1);
  1705. if (state->config->tuner_get_status)
  1706. state->config->tuner_get_status(fe, &reg);
  1707. if (reg)
  1708. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1709. else
  1710. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1711. stv090x_i2c_gate_ctrl(fe, 0);
  1712. STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
  1713. if (state->delsys == STV090x_DVBS2) {
  1714. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1715. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1716. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1717. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1718. goto err;
  1719. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1720. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1721. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1722. goto err;
  1723. }
  1724. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1725. goto err;
  1726. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1727. goto err;
  1728. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1729. goto err;
  1730. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1731. goto err;
  1732. lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
  1733. dir *= -1;
  1734. cur_step++;
  1735. }
  1736. }
  1737. }
  1738. }
  1739. return lock;
  1740. err:
  1741. dprintk(FE_ERROR, 1, "I/O error");
  1742. return -1;
  1743. }
  1744. static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
  1745. {
  1746. s32 timeout, inc, steps_max, srate, car_max;
  1747. srate = state->srate;
  1748. car_max = state->search_range / 1000;
  1749. car_max += car_max / 10;
  1750. car_max = 65536 * (car_max / 2);
  1751. car_max /= (state->mclk / 1000);
  1752. if (car_max > 0x4000)
  1753. car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
  1754. inc = srate;
  1755. inc /= state->mclk / 1000;
  1756. inc *= 256;
  1757. inc *= 256;
  1758. inc /= 1000;
  1759. switch (state->search_mode) {
  1760. case STV090x_SEARCH_DVBS1:
  1761. case STV090x_SEARCH_DSS:
  1762. inc *= 3; /* freq step = 3% of srate */
  1763. timeout = 20;
  1764. break;
  1765. case STV090x_SEARCH_DVBS2:
  1766. inc *= 4;
  1767. timeout = 25;
  1768. break;
  1769. case STV090x_SEARCH_AUTO:
  1770. default:
  1771. inc *= 3;
  1772. timeout = 25;
  1773. break;
  1774. }
  1775. inc /= 100;
  1776. if ((inc > car_max) || (inc < 0))
  1777. inc = car_max / 2; /* increment <= 1/8 Mclk */
  1778. timeout *= 27500; /* 27.5 Msps reference */
  1779. if (srate > 0)
  1780. timeout /= (srate / 1000);
  1781. if ((timeout > 100) || (timeout < 0))
  1782. timeout = 100;
  1783. steps_max = (car_max / inc) + 1; /* min steps = 3 */
  1784. if ((steps_max > 100) || (steps_max < 0)) {
  1785. steps_max = 100; /* max steps <= 100 */
  1786. inc = car_max / steps_max;
  1787. }
  1788. *freq_inc = inc;
  1789. *timeout_sw = timeout;
  1790. *steps = steps_max;
  1791. return 0;
  1792. }
  1793. static int stv090x_chk_signal(struct stv090x_state *state)
  1794. {
  1795. s32 offst_car, agc2, car_max;
  1796. int no_signal;
  1797. offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
  1798. offst_car |= STV090x_READ_DEMOD(state, CFR1);
  1799. offst_car = comp2(offst_car, 16);
  1800. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1801. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1802. car_max = state->search_range / 1000;
  1803. car_max += (car_max / 10); /* 10% margin */
  1804. car_max = (65536 * car_max / 2);
  1805. car_max /= state->mclk / 1000;
  1806. if (car_max > 0x4000)
  1807. car_max = 0x4000;
  1808. if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
  1809. no_signal = 1;
  1810. dprintk(FE_DEBUG, 1, "No Signal");
  1811. } else {
  1812. no_signal = 0;
  1813. dprintk(FE_DEBUG, 1, "Found Signal");
  1814. }
  1815. return no_signal;
  1816. }
  1817. static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
  1818. {
  1819. int no_signal, lock = 0;
  1820. s32 cpt_step, offst_freq, car_max;
  1821. u32 reg;
  1822. car_max = state->search_range / 1000;
  1823. car_max += (car_max / 10);
  1824. car_max = (65536 * car_max / 2);
  1825. car_max /= (state->mclk / 1000);
  1826. if (car_max > 0x4000)
  1827. car_max = 0x4000;
  1828. if (zigzag)
  1829. offst_freq = 0;
  1830. else
  1831. offst_freq = -car_max + inc;
  1832. cpt_step = 0;
  1833. do {
  1834. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  1835. goto err;
  1836. if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
  1837. goto err;
  1838. if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
  1839. goto err;
  1840. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1841. goto err;
  1842. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  1843. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
  1844. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  1845. goto err;
  1846. if (state->dev_ver == 0x12) {
  1847. reg = STV090x_READ_DEMOD(state, TSCFGH);
  1848. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x1);
  1849. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  1850. goto err;
  1851. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x0);
  1852. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  1853. goto err;
  1854. }
  1855. if (zigzag) {
  1856. if (offst_freq >= 0)
  1857. offst_freq = -offst_freq - 2 * inc;
  1858. else
  1859. offst_freq = -offst_freq;
  1860. } else {
  1861. offst_freq += 2 * inc;
  1862. }
  1863. cpt_step++;
  1864. lock = stv090x_get_dmdlock(state, timeout);
  1865. no_signal = stv090x_chk_signal(state);
  1866. } while ((!lock) &&
  1867. (!no_signal) &&
  1868. ((offst_freq - inc) < car_max) &&
  1869. ((offst_freq + inc) > -car_max) &&
  1870. (cpt_step < steps_max));
  1871. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  1872. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
  1873. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  1874. goto err;
  1875. return lock;
  1876. err:
  1877. dprintk(FE_ERROR, 1, "I/O error");
  1878. return -1;
  1879. }
  1880. static int stv090x_sw_algo(struct stv090x_state *state)
  1881. {
  1882. int no_signal, zigzag, lock = 0;
  1883. u32 reg;
  1884. s32 dvbs2_fly_wheel;
  1885. s32 inc, timeout_step, trials, steps_max;
  1886. stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); /* get params */
  1887. switch (state->search_mode) {
  1888. case STV090x_SEARCH_DVBS1:
  1889. case STV090x_SEARCH_DSS:
  1890. /* accelerate the frequency detector */
  1891. if (state->dev_ver >= 0x20) {
  1892. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
  1893. goto err;
  1894. } else {
  1895. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1896. goto err;
  1897. }
  1898. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
  1899. goto err;
  1900. zigzag = 0;
  1901. break;
  1902. case STV090x_SEARCH_DVBS2:
  1903. if (state->dev_ver >= 0x20) {
  1904. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  1905. goto err;
  1906. } else {
  1907. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
  1908. goto err;
  1909. }
  1910. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  1911. goto err;
  1912. zigzag = 1;
  1913. break;
  1914. case STV090x_SEARCH_AUTO:
  1915. default:
  1916. /* accelerate the frequency detector */
  1917. if (state->dev_ver >= 0x20) {
  1918. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
  1919. goto err;
  1920. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  1921. goto err;
  1922. } else {
  1923. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1924. goto err;
  1925. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
  1926. goto err;
  1927. }
  1928. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
  1929. goto err;
  1930. zigzag = 0;
  1931. break;
  1932. }
  1933. trials = 0;
  1934. do {
  1935. lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
  1936. no_signal = stv090x_chk_signal(state);
  1937. trials++;
  1938. /*run the SW search 2 times maximum*/
  1939. if (lock || no_signal || (trials == 2)) {
  1940. /*Check if the demod is not losing lock in DVBS2*/
  1941. if (state->dev_ver >= 0x20) {
  1942. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1943. goto err;
  1944. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  1945. goto err;
  1946. } else {
  1947. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1948. goto err;
  1949. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0)
  1950. goto err;
  1951. }
  1952. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1953. if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
  1954. /*Check if the demod is not losing lock in DVBS2*/
  1955. msleep(timeout_step);
  1956. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  1957. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  1958. if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
  1959. msleep(timeout_step);
  1960. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  1961. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  1962. }
  1963. if (dvbs2_fly_wheel < 0xd) {
  1964. /*FALSE lock, The demod is loosing lock */
  1965. lock = 0;
  1966. if (trials < 2) {
  1967. if (state->dev_ver >= 0x20) {
  1968. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  1969. goto err;
  1970. } else {
  1971. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
  1972. goto err;
  1973. }
  1974. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  1975. goto err;
  1976. }
  1977. }
  1978. }
  1979. }
  1980. } while ((!lock) && (trials < 2) && (!no_signal));
  1981. return lock;
  1982. err:
  1983. dprintk(FE_ERROR, 1, "I/O error");
  1984. return -1;
  1985. }
  1986. static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
  1987. {
  1988. u32 reg;
  1989. enum stv090x_delsys delsys;
  1990. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1991. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
  1992. delsys = STV090x_DVBS2;
  1993. else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
  1994. reg = STV090x_READ_DEMOD(state, FECM);
  1995. if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
  1996. delsys = STV090x_DSS;
  1997. else
  1998. delsys = STV090x_DVBS1;
  1999. } else {
  2000. delsys = STV090x_ERROR;
  2001. }
  2002. return delsys;
  2003. }
  2004. /* in Hz */
  2005. static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
  2006. {
  2007. s32 derot, int_1, int_2, tmp_1, tmp_2;
  2008. derot = STV090x_READ_DEMOD(state, CFR2) << 16;
  2009. derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
  2010. derot |= STV090x_READ_DEMOD(state, CFR0);
  2011. derot = comp2(derot, 24);
  2012. int_1 = state->mclk >> 12;
  2013. int_2 = derot >> 12;
  2014. /* carrier_frequency = MasterClock * Reg / 2^24 */
  2015. tmp_1 = state->mclk % 0x1000;
  2016. tmp_2 = derot % 0x1000;
  2017. derot = (int_1 * int_2) +
  2018. ((int_1 * tmp_2) >> 12) +
  2019. ((int_1 * tmp_1) >> 12);
  2020. return derot;
  2021. }
  2022. static int stv090x_get_viterbi(struct stv090x_state *state)
  2023. {
  2024. u32 reg, rate;
  2025. reg = STV090x_READ_DEMOD(state, VITCURPUN);
  2026. rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
  2027. switch (rate) {
  2028. case 13:
  2029. state->fec = STV090x_PR12;
  2030. break;
  2031. case 18:
  2032. state->fec = STV090x_PR23;
  2033. break;
  2034. case 21:
  2035. state->fec = STV090x_PR34;
  2036. break;
  2037. case 24:
  2038. state->fec = STV090x_PR56;
  2039. break;
  2040. case 25:
  2041. state->fec = STV090x_PR67;
  2042. break;
  2043. case 26:
  2044. state->fec = STV090x_PR78;
  2045. break;
  2046. default:
  2047. state->fec = STV090x_PRERR;
  2048. break;
  2049. }
  2050. return 0;
  2051. }
  2052. static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
  2053. {
  2054. struct dvb_frontend *fe = &state->frontend;
  2055. u8 tmg;
  2056. u32 reg;
  2057. s32 i = 0, offst_freq;
  2058. msleep(5);
  2059. if (state->algo == STV090x_BLIND_SEARCH) {
  2060. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2061. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
  2062. while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
  2063. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2064. msleep(5);
  2065. i += 5;
  2066. }
  2067. }
  2068. state->delsys = stv090x_get_std(state);
  2069. stv090x_i2c_gate_ctrl(fe, 1);
  2070. if (state->config->tuner_get_frequency)
  2071. state->config->tuner_get_frequency(fe, &state->frequency);
  2072. stv090x_i2c_gate_ctrl(fe, 0);
  2073. offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
  2074. state->frequency += offst_freq;
  2075. stv090x_get_viterbi(state);
  2076. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2077. state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2078. state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2079. state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
  2080. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2081. state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2082. reg = STV090x_READ_DEMOD(state, FECM);
  2083. state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
  2084. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
  2085. stv090x_i2c_gate_ctrl(fe, 1);
  2086. if (state->config->tuner_get_frequency)
  2087. state->config->tuner_get_frequency(fe, &state->frequency);
  2088. stv090x_i2c_gate_ctrl(fe, 0);
  2089. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2090. return STV090x_RANGEOK;
  2091. else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
  2092. return STV090x_RANGEOK;
  2093. else
  2094. return STV090x_OUTOFRANGE; /* Out of Range */
  2095. } else {
  2096. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2097. return STV090x_RANGEOK;
  2098. else
  2099. return STV090x_OUTOFRANGE;
  2100. }
  2101. return STV090x_OUTOFRANGE;
  2102. }
  2103. static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
  2104. {
  2105. s32 offst_tmg;
  2106. offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
  2107. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
  2108. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
  2109. offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
  2110. if (!offst_tmg)
  2111. offst_tmg = 1;
  2112. offst_tmg = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
  2113. offst_tmg /= 320;
  2114. return offst_tmg;
  2115. }
  2116. static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
  2117. {
  2118. u8 aclc = 0x29;
  2119. s32 i;
  2120. struct stv090x_long_frame_crloop *car_loop;
  2121. if (state->dev_ver <= 0x12)
  2122. car_loop = stv090x_s2_crl;
  2123. else if (state->dev_ver == 0x20)
  2124. car_loop = stv090x_s2_crl_cut20;
  2125. else
  2126. car_loop = stv090x_s2_crl;
  2127. if (modcod < STV090x_QPSK_12) {
  2128. i = 0;
  2129. while ((i < 3) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
  2130. i++;
  2131. if (i >= 3)
  2132. i = 2;
  2133. } else {
  2134. i = 0;
  2135. while ((i < 14) && (modcod != car_loop[i].modcod))
  2136. i++;
  2137. if (i >= 14) {
  2138. i = 0;
  2139. while ((i < 11) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
  2140. i++;
  2141. if (i >= 11)
  2142. i = 10;
  2143. }
  2144. }
  2145. if (modcod <= STV090x_QPSK_25) {
  2146. if (pilots) {
  2147. if (state->srate <= 3000000)
  2148. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_2;
  2149. else if (state->srate <= 7000000)
  2150. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_5;
  2151. else if (state->srate <= 15000000)
  2152. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_10;
  2153. else if (state->srate <= 25000000)
  2154. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_20;
  2155. else
  2156. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_30;
  2157. } else {
  2158. if (state->srate <= 3000000)
  2159. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_2;
  2160. else if (state->srate <= 7000000)
  2161. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_5;
  2162. else if (state->srate <= 15000000)
  2163. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_10;
  2164. else if (state->srate <= 25000000)
  2165. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_20;
  2166. else
  2167. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_30;
  2168. }
  2169. } else if (modcod <= STV090x_8PSK_910) {
  2170. if (pilots) {
  2171. if (state->srate <= 3000000)
  2172. aclc = car_loop[i].crl_pilots_on_2;
  2173. else if (state->srate <= 7000000)
  2174. aclc = car_loop[i].crl_pilots_on_5;
  2175. else if (state->srate <= 15000000)
  2176. aclc = car_loop[i].crl_pilots_on_10;
  2177. else if (state->srate <= 25000000)
  2178. aclc = car_loop[i].crl_pilots_on_20;
  2179. else
  2180. aclc = car_loop[i].crl_pilots_on_30;
  2181. } else {
  2182. if (state->srate <= 3000000)
  2183. aclc = car_loop[i].crl_pilots_off_2;
  2184. else if (state->srate <= 7000000)
  2185. aclc = car_loop[i].crl_pilots_off_5;
  2186. else if (state->srate <= 15000000)
  2187. aclc = car_loop[i].crl_pilots_off_10;
  2188. else if (state->srate <= 25000000)
  2189. aclc = car_loop[i].crl_pilots_off_20;
  2190. else
  2191. aclc = car_loop[i].crl_pilots_off_30;
  2192. }
  2193. } else { /* 16APSK and 32APSK */
  2194. if (state->srate <= 3000000)
  2195. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_2;
  2196. else if (state->srate <= 7000000)
  2197. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_5;
  2198. else if (state->srate <= 15000000)
  2199. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_10;
  2200. else if (state->srate <= 25000000)
  2201. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_20;
  2202. else
  2203. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_30;
  2204. }
  2205. return aclc;
  2206. }
  2207. static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
  2208. {
  2209. s32 index = 0;
  2210. u8 aclc = 0x0b;
  2211. switch (state->modulation) {
  2212. case STV090x_QPSK:
  2213. default:
  2214. index = 0;
  2215. break;
  2216. case STV090x_8PSK:
  2217. index = 1;
  2218. break;
  2219. case STV090x_16APSK:
  2220. index = 2;
  2221. break;
  2222. case STV090x_32APSK:
  2223. index = 3;
  2224. break;
  2225. }
  2226. switch (state->dev_ver) {
  2227. case 0x20:
  2228. if (state->srate <= 3000000)
  2229. aclc = stv090x_s2_short_crl[index].crl_cut20_2;
  2230. else if (state->srate <= 7000000)
  2231. aclc = stv090x_s2_short_crl[index].crl_cut20_5;
  2232. else if (state->srate <= 15000000)
  2233. aclc = stv090x_s2_short_crl[index].crl_cut20_10;
  2234. else if (state->srate <= 25000000)
  2235. aclc = stv090x_s2_short_crl[index].crl_cut20_20;
  2236. else
  2237. aclc = stv090x_s2_short_crl[index].crl_cut20_30;
  2238. break;
  2239. case 0x12:
  2240. default:
  2241. if (state->srate <= 3000000)
  2242. aclc = stv090x_s2_short_crl[index].crl_cut12_2;
  2243. else if (state->srate <= 7000000)
  2244. aclc = stv090x_s2_short_crl[index].crl_cut12_5;
  2245. else if (state->srate <= 15000000)
  2246. aclc = stv090x_s2_short_crl[index].crl_cut12_10;
  2247. else if (state->srate <= 25000000)
  2248. aclc = stv090x_s2_short_crl[index].crl_cut12_20;
  2249. else
  2250. aclc = stv090x_s2_short_crl[index].crl_cut12_30;
  2251. break;
  2252. }
  2253. return aclc;
  2254. }
  2255. static int stv090x_optimize_track(struct stv090x_state *state)
  2256. {
  2257. struct dvb_frontend *fe = &state->frontend;
  2258. enum stv090x_rolloff rolloff;
  2259. enum stv090x_modcod modcod;
  2260. s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
  2261. u32 reg;
  2262. srate = stv090x_get_srate(state, state->mclk);
  2263. srate += stv090x_get_tmgoffst(state, srate);
  2264. switch (state->delsys) {
  2265. case STV090x_DVBS1:
  2266. case STV090x_DSS:
  2267. if (state->algo == STV090x_SEARCH_AUTO) {
  2268. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2269. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2270. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  2271. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2272. goto err;
  2273. }
  2274. reg = STV090x_READ_DEMOD(state, DEMOD);
  2275. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  2276. STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
  2277. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2278. goto err;
  2279. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2280. goto err;
  2281. break;
  2282. case STV090x_DVBS2:
  2283. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2284. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  2285. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2286. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2287. goto err;
  2288. if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
  2289. goto err;
  2290. if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
  2291. goto err;
  2292. if (state->frame_len == STV090x_LONG_FRAME) {
  2293. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2294. modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2295. pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2296. aclc = stv090x_optimize_carloop(state, modcod, pilots);
  2297. if (modcod <= STV090x_QPSK_910) {
  2298. STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
  2299. } else if (modcod <= STV090x_8PSK_910) {
  2300. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2301. goto err;
  2302. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2303. goto err;
  2304. }
  2305. if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
  2306. if (modcod <= STV090x_16APSK_910) {
  2307. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2308. goto err;
  2309. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2310. goto err;
  2311. } else {
  2312. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2313. goto err;
  2314. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2315. goto err;
  2316. }
  2317. }
  2318. } else {
  2319. /*Carrier loop setting for short frame*/
  2320. aclc = stv090x_optimize_carloop_short(state);
  2321. if (state->modulation == STV090x_QPSK) {
  2322. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
  2323. goto err;
  2324. } else if (state->modulation == STV090x_8PSK) {
  2325. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2326. goto err;
  2327. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2328. goto err;
  2329. } else if (state->modulation == STV090x_16APSK) {
  2330. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2331. goto err;
  2332. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2333. goto err;
  2334. } else if (state->modulation == STV090x_32APSK) {
  2335. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2336. goto err;
  2337. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2338. goto err;
  2339. }
  2340. }
  2341. if (state->dev_ver <= 0x11) {
  2342. if (state->demod_mode != STV090x_SINGLE)
  2343. stv090x_activate_modcod(state); /* link to LDPC after demod LOCK */
  2344. }
  2345. STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
  2346. break;
  2347. case STV090x_UNKNOWN:
  2348. default:
  2349. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2350. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2351. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2352. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2353. goto err;
  2354. break;
  2355. }
  2356. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2357. f_0 = STV090x_READ_DEMOD(state, CFR1);
  2358. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2359. rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2360. if (state->algo == STV090x_BLIND_SEARCH) {
  2361. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
  2362. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2363. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
  2364. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  2365. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2366. goto err;
  2367. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
  2368. goto err;
  2369. stv090x_set_srate(state, srate);
  2370. stv090x_set_max_srate(state, state->mclk, srate);
  2371. stv090x_set_min_srate(state, state->mclk, srate);
  2372. blind_tune = 1;
  2373. }
  2374. if (state->dev_ver >= 0x20) {
  2375. if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
  2376. (state->search_mode == STV090x_SEARCH_DSS) ||
  2377. (state->search_mode == STV090x_SEARCH_AUTO)) {
  2378. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
  2379. goto err;
  2380. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
  2381. goto err;
  2382. }
  2383. }
  2384. if (state->dev_ver < 0x20) {
  2385. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x08) < 0)
  2386. goto err;
  2387. }
  2388. if (state->dev_ver == 0x10) {
  2389. if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0x0a) < 0)
  2390. goto err;
  2391. }
  2392. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2393. goto err;
  2394. if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
  2395. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2396. goto err;
  2397. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2398. goto err;
  2399. state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
  2400. if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
  2401. if (state->algo != STV090x_WARM_SEARCH) {
  2402. stv090x_i2c_gate_ctrl(fe, 1);
  2403. if (state->config->tuner_set_bandwidth)
  2404. state->config->tuner_set_bandwidth(fe, state->tuner_bw);
  2405. stv090x_i2c_gate_ctrl(fe, 0);
  2406. }
  2407. }
  2408. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
  2409. msleep(50); /* blind search: wait 50ms for SR stabilization */
  2410. else
  2411. msleep(5);
  2412. stv090x_get_lock_tmg(state);
  2413. if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
  2414. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2415. goto err;
  2416. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2417. goto err;
  2418. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2419. goto err;
  2420. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2421. goto err;
  2422. i = 0;
  2423. while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
  2424. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2425. goto err;
  2426. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2427. goto err;
  2428. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2429. goto err;
  2430. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2431. goto err;
  2432. i++;
  2433. }
  2434. }
  2435. }
  2436. if (state->dev_ver >= 0x20) {
  2437. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2438. goto err;
  2439. }
  2440. if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
  2441. stv090x_set_vit_thtracq(state);
  2442. return 0;
  2443. err:
  2444. dprintk(FE_ERROR, 1, "I/O error");
  2445. return -1;
  2446. }
  2447. static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
  2448. {
  2449. s32 timer = 0, lock = 0, stat;
  2450. u32 reg;
  2451. while ((timer < timeout) && (!lock)) {
  2452. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2453. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2454. switch (stat) {
  2455. case 0: /* searching */
  2456. case 1: /* first PLH detected */
  2457. default:
  2458. lock = 0;
  2459. break;
  2460. case 2: /* DVB-S2 mode */
  2461. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  2462. lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
  2463. break;
  2464. case 3: /* DVB-S1/legacy mode */
  2465. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2466. lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
  2467. break;
  2468. }
  2469. if (!lock) {
  2470. msleep(10);
  2471. timer += 10;
  2472. }
  2473. }
  2474. return lock;
  2475. }
  2476. static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
  2477. {
  2478. u32 reg;
  2479. s32 timer = 0;
  2480. int lock;
  2481. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2482. if (lock)
  2483. lock = stv090x_get_feclock(state, timeout_fec);
  2484. if (lock) {
  2485. lock = 0;
  2486. while ((timer < timeout_fec) && (!lock)) {
  2487. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2488. lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
  2489. msleep(1);
  2490. timer++;
  2491. }
  2492. }
  2493. return lock;
  2494. }
  2495. static int stv090x_set_s2rolloff(struct stv090x_state *state)
  2496. {
  2497. s32 rolloff;
  2498. u32 reg;
  2499. if (state->dev_ver == 0x10) {
  2500. reg = STV090x_READ_DEMOD(state, DEMOD);
  2501. STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
  2502. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2503. goto err;
  2504. rolloff = STV090x_READ_DEMOD(state, MATSTR1) & 0x03;
  2505. reg = STV090x_READ_DEMOD(state, DEMOD);
  2506. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, reg);
  2507. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2508. goto err;
  2509. } else {
  2510. reg = STV090x_READ_DEMOD(state, DEMOD);
  2511. STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x00);
  2512. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2513. goto err;
  2514. }
  2515. return 0;
  2516. err:
  2517. dprintk(FE_ERROR, 1, "I/O error");
  2518. return -1;
  2519. }
  2520. static enum stv090x_signal_state stv090x_acq_fixs1(struct stv090x_state *state)
  2521. {
  2522. s32 srate, f_1, f_2;
  2523. enum stv090x_signal_state signal_state = STV090x_NODATA;
  2524. u32 reg;
  2525. int lock;
  2526. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2527. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { /* DVB-S mode */
  2528. srate = stv090x_get_srate(state, state->mclk);
  2529. srate += stv090x_get_tmgoffst(state, state->srate);
  2530. if (state->algo == STV090x_BLIND_SEARCH)
  2531. stv090x_set_srate(state, state->srate);
  2532. stv090x_get_lock_tmg(state);
  2533. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2534. f_2 = STV090x_READ_DEMOD(state, CFR1);
  2535. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2536. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  2537. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2538. goto err;
  2539. reg = STV090x_READ_DEMOD(state, DEMOD);
  2540. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_SWAP);
  2541. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2542. goto err;
  2543. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) /* stop demod */
  2544. goto err;
  2545. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2546. goto err;
  2547. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
  2548. goto err;
  2549. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
  2550. goto err;
  2551. if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
  2552. lock = 1;
  2553. stv090x_get_sig_params(state);
  2554. stv090x_optimize_track(state);
  2555. } else {
  2556. reg = STV090x_READ_DEMOD(state, DEMOD);
  2557. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_NORMAL);
  2558. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2559. goto err;
  2560. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  2561. goto err;
  2562. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2563. goto err;
  2564. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
  2565. goto err;
  2566. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
  2567. goto err;
  2568. if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
  2569. lock = 1;
  2570. signal_state = stv090x_get_sig_params(state);
  2571. stv090x_optimize_track(state);
  2572. }
  2573. }
  2574. } else {
  2575. lock = 0;
  2576. }
  2577. return signal_state;
  2578. err:
  2579. dprintk(FE_ERROR, 1, "I/O error");
  2580. return -1;
  2581. }
  2582. static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
  2583. {
  2584. struct dvb_frontend *fe = &state->frontend;
  2585. enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
  2586. u32 reg;
  2587. s32 timeout_dmd = 500, timeout_fec = 50;
  2588. int lock = 0, low_sr = 0, no_signal = 0;
  2589. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2590. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
  2591. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2592. goto err;
  2593. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
  2594. goto err;
  2595. if (state->dev_ver >= 0x20) {
  2596. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
  2597. goto err;
  2598. } else {
  2599. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0) /* cut 1.x */
  2600. goto err;
  2601. }
  2602. stv090x_get_lock_tmg(state);
  2603. if (state->algo == STV090x_BLIND_SEARCH) {
  2604. state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
  2605. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x00) < 0) /* wider srate scan */
  2606. goto err;
  2607. stv090x_set_srate(state, 1000000); /* inital srate = 1Msps */
  2608. } else {
  2609. /* known srate */
  2610. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  2611. goto err;
  2612. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  2613. goto err;
  2614. if (state->srate >= 10000000) {
  2615. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) /* High SR */
  2616. goto err;
  2617. } else {
  2618. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) /* Low SR */
  2619. goto err;
  2620. }
  2621. if (state->dev_ver >= 0x20) {
  2622. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
  2623. goto err;
  2624. if (state->algo == STV090x_COLD_SEARCH)
  2625. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
  2626. else if (state->algo == STV090x_WARM_SEARCH)
  2627. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
  2628. } else {
  2629. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0xc1) < 0)
  2630. goto err;
  2631. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
  2632. }
  2633. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) /* narrow srate scan */
  2634. goto err;
  2635. stv090x_set_srate(state, state->srate);
  2636. stv090x_set_max_srate(state, state->mclk, state->srate);
  2637. stv090x_set_min_srate(state, state->mclk, state->srate);
  2638. if (state->srate >= 10000000)
  2639. low_sr = 0;
  2640. else
  2641. low_sr = 1;
  2642. }
  2643. /* Setup tuner */
  2644. stv090x_i2c_gate_ctrl(fe, 1);
  2645. if (state->config->tuner_set_bbgain)
  2646. state->config->tuner_set_bbgain(fe, 10); /* 10dB */
  2647. if (state->config->tuner_set_frequency)
  2648. state->config->tuner_set_frequency(fe, state->frequency);
  2649. if (state->config->tuner_set_bandwidth)
  2650. state->config->tuner_set_bandwidth(fe, state->tuner_bw);
  2651. stv090x_i2c_gate_ctrl(fe, 0);
  2652. msleep(50);
  2653. stv090x_i2c_gate_ctrl(fe, 1);
  2654. if (state->config->tuner_get_status)
  2655. state->config->tuner_get_status(fe, &reg);
  2656. if (reg)
  2657. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  2658. else
  2659. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  2660. stv090x_i2c_gate_ctrl(fe, 0);
  2661. reg = STV090x_READ_DEMOD(state, DEMOD);
  2662. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
  2663. STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 1);
  2664. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2665. goto err;
  2666. stv090x_delivery_search(state);
  2667. if (state->algo != STV090x_BLIND_SEARCH)
  2668. stv090x_start_search(state);
  2669. if (state->dev_ver == 0x12) {
  2670. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2671. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2672. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2673. goto err;
  2674. msleep(3);
  2675. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2676. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2677. goto err;
  2678. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2679. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2680. goto err;
  2681. }
  2682. if (state->algo == STV090x_BLIND_SEARCH)
  2683. lock = stv090x_blind_search(state);
  2684. else if (state->algo == STV090x_COLD_SEARCH)
  2685. lock = stv090x_get_coldlock(state, timeout_dmd);
  2686. else if (state->algo == STV090x_WARM_SEARCH)
  2687. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2688. if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
  2689. if (!low_sr) {
  2690. if (stv090x_chk_tmg(state))
  2691. lock = stv090x_sw_algo(state);
  2692. }
  2693. }
  2694. if (lock)
  2695. signal_state = stv090x_get_sig_params(state);
  2696. if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
  2697. stv090x_optimize_track(state);
  2698. if (state->dev_ver <= 0x11) { /*workaround for dual DVBS1 cut 1.1 and 1.0 only*/
  2699. if (stv090x_get_std(state) == STV090x_DVBS1) {
  2700. msleep(20);
  2701. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2702. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2703. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2704. goto err;
  2705. } else {
  2706. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2707. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2708. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2709. goto err;
  2710. msleep(3);
  2711. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2712. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2713. goto err;
  2714. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2715. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2716. goto err;
  2717. }
  2718. } else if (state->dev_ver == 0x20) { /*cut 2.0 :release TS reset after demod lock and TrackingOptimization*/
  2719. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2720. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2721. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2722. goto err;
  2723. msleep(3);
  2724. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2725. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2726. goto err;
  2727. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2728. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2729. goto err;
  2730. }
  2731. if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
  2732. lock = 1;
  2733. if (state->delsys == STV090x_DVBS2) {
  2734. stv090x_set_s2rolloff(state);
  2735. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x40) < 0)
  2736. goto err;
  2737. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x00) < 0) /* RESET counter */
  2738. goto err;
  2739. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
  2740. goto err;
  2741. } else {
  2742. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2743. goto err;
  2744. }
  2745. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
  2746. goto err;
  2747. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2748. goto err;
  2749. } else {
  2750. lock = 0;
  2751. signal_state = STV090x_NODATA;
  2752. no_signal = stv090x_chk_signal(state);
  2753. }
  2754. }
  2755. if ((signal_state == STV090x_NODATA) && (!no_signal)) {
  2756. if (state->dev_ver <= 0x11) {
  2757. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2758. if (((STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD)) == STV090x_DVBS1) && (state->inversion == INVERSION_AUTO))
  2759. signal_state = stv090x_acq_fixs1(state);
  2760. }
  2761. }
  2762. return signal_state;
  2763. err:
  2764. dprintk(FE_ERROR, 1, "I/O error");
  2765. return -1;
  2766. }
  2767. static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
  2768. {
  2769. struct stv090x_state *state = fe->demodulator_priv;
  2770. struct dtv_frontend_properties *props = &fe->dtv_property_cache;
  2771. state->delsys = props->delivery_system;
  2772. state->frequency = p->frequency;
  2773. state->srate = p->u.qpsk.symbol_rate;
  2774. state->search_mode = STV090x_SEARCH_AUTO;
  2775. state->algo = STV090x_COLD_SEARCH;
  2776. state->fec = STV090x_PRERR;
  2777. state->search_range = 2000000;
  2778. if (stv090x_algo(state) == STV090x_RANGEOK) {
  2779. dprintk(FE_DEBUG, 1, "Search success!");
  2780. return DVBFE_ALGO_SEARCH_SUCCESS;
  2781. } else {
  2782. dprintk(FE_DEBUG, 1, "Search failed!");
  2783. return DVBFE_ALGO_SEARCH_FAILED;
  2784. }
  2785. return DVBFE_ALGO_SEARCH_ERROR;
  2786. }
  2787. /* FIXME! */
  2788. static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  2789. {
  2790. struct stv090x_state *state = fe->demodulator_priv;
  2791. u32 reg;
  2792. u8 search_state;
  2793. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2794. search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2795. switch (search_state) {
  2796. case 0: /* searching */
  2797. case 1: /* first PLH detected */
  2798. default:
  2799. dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
  2800. *status = 0;
  2801. break;
  2802. case 2: /* DVB-S2 mode */
  2803. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
  2804. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2805. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  2806. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2807. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  2808. *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
  2809. }
  2810. }
  2811. break;
  2812. case 3: /* DVB-S1/legacy mode */
  2813. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
  2814. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2815. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  2816. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2817. if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
  2818. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2819. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  2820. *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
  2821. }
  2822. }
  2823. }
  2824. break;
  2825. }
  2826. return 0;
  2827. }
  2828. static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
  2829. {
  2830. struct stv090x_state *state = fe->demodulator_priv;
  2831. s32 count_4, count_3, count_2, count_1, count_0, count;
  2832. u32 reg, h, m, l;
  2833. enum fe_status status;
  2834. stv090x_read_status(fe, &status);
  2835. if (!(status & FE_HAS_LOCK)) {
  2836. *per = 1 << 23; /* Max PER */
  2837. } else {
  2838. /* Counter 2 */
  2839. reg = STV090x_READ_DEMOD(state, ERRCNT22);
  2840. h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
  2841. reg = STV090x_READ_DEMOD(state, ERRCNT21);
  2842. m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
  2843. reg = STV090x_READ_DEMOD(state, ERRCNT20);
  2844. l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
  2845. *per = ((h << 16) | (m << 8) | l);
  2846. count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
  2847. count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
  2848. count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
  2849. count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
  2850. count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
  2851. if ((!count_4) && (!count_3)) {
  2852. count = (count_2 & 0xff) << 16;
  2853. count |= (count_1 & 0xff) << 8;
  2854. count |= count_0 & 0xff;
  2855. } else {
  2856. count = 1 << 24;
  2857. }
  2858. if (count == 0)
  2859. *per = 1;
  2860. }
  2861. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
  2862. goto err;
  2863. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2864. goto err;
  2865. return 0;
  2866. err:
  2867. dprintk(FE_ERROR, 1, "I/O error");
  2868. return -1;
  2869. }
  2870. static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
  2871. {
  2872. int res = 0;
  2873. int min = 0, med;
  2874. if (val < tab[min].read)
  2875. res = tab[min].real;
  2876. else if (val >= tab[max].read)
  2877. res = tab[max].real;
  2878. else {
  2879. while ((max - min) > 1) {
  2880. med = (max + min) / 2;
  2881. if (val >= tab[min].read && val < tab[med].read)
  2882. max = med;
  2883. else
  2884. min = med;
  2885. }
  2886. res = ((val - tab[min].read) *
  2887. (tab[max].real - tab[min].real) /
  2888. (tab[max].read - tab[min].read)) +
  2889. tab[min].real;
  2890. }
  2891. return res;
  2892. }
  2893. static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  2894. {
  2895. struct stv090x_state *state = fe->demodulator_priv;
  2896. u32 reg;
  2897. s32 agc;
  2898. reg = STV090x_READ_DEMOD(state, AGCIQIN1);
  2899. agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  2900. *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
  2901. if (agc > stv090x_rf_tab[0].read)
  2902. *strength = 5;
  2903. else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
  2904. *strength = -100;
  2905. return 0;
  2906. }
  2907. static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
  2908. {
  2909. struct stv090x_state *state = fe->demodulator_priv;
  2910. u32 reg_0, reg_1, reg, i;
  2911. s32 val_0, val_1, val = 0;
  2912. u8 lock_f;
  2913. switch (state->delsys) {
  2914. case STV090x_DVBS2:
  2915. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2916. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  2917. if (lock_f) {
  2918. msleep(5);
  2919. for (i = 0; i < 16; i++) {
  2920. reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
  2921. val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  2922. reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
  2923. val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  2924. val += MAKEWORD16(val_1, val_0);
  2925. msleep(1);
  2926. }
  2927. val /= 16;
  2928. *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
  2929. if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
  2930. *cnr = 1000;
  2931. }
  2932. break;
  2933. case STV090x_DVBS1:
  2934. case STV090x_DSS:
  2935. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2936. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  2937. if (lock_f) {
  2938. msleep(5);
  2939. for (i = 0; i < 16; i++) {
  2940. reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
  2941. val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  2942. reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
  2943. val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  2944. val += MAKEWORD16(val_1, val_0);
  2945. msleep(1);
  2946. }
  2947. val /= 16;
  2948. *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
  2949. if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
  2950. *cnr = 1000;
  2951. }
  2952. break;
  2953. default:
  2954. break;
  2955. }
  2956. return 0;
  2957. }
  2958. static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
  2959. {
  2960. struct stv090x_state *state = fe->demodulator_priv;
  2961. u32 reg;
  2962. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  2963. switch (tone) {
  2964. case SEC_TONE_ON:
  2965. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  2966. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  2967. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  2968. goto err;
  2969. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  2970. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  2971. goto err;
  2972. break;
  2973. case SEC_TONE_OFF:
  2974. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  2975. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  2976. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  2977. goto err;
  2978. break;
  2979. default:
  2980. return -EINVAL;
  2981. }
  2982. return 0;
  2983. err:
  2984. dprintk(FE_ERROR, 1, "I/O error");
  2985. return -1;
  2986. }
  2987. static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
  2988. {
  2989. return DVBFE_ALGO_CUSTOM;
  2990. }
  2991. static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
  2992. {
  2993. struct stv090x_state *state = fe->demodulator_priv;
  2994. u32 reg, idle = 0, fifo_full = 1;
  2995. int i;
  2996. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  2997. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 2);
  2998. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  2999. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3000. goto err;
  3001. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3002. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3003. goto err;
  3004. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3005. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3006. goto err;
  3007. for (i = 0; i < cmd->msg_len; i++) {
  3008. while (fifo_full) {
  3009. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3010. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3011. }
  3012. if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
  3013. goto err;
  3014. }
  3015. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3016. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3017. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3018. goto err;
  3019. i = 0;
  3020. while ((!idle) && (i < 10)) {
  3021. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3022. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3023. msleep(10);
  3024. i++;
  3025. }
  3026. return 0;
  3027. err:
  3028. dprintk(FE_ERROR, 1, "I/O error");
  3029. return -1;
  3030. }
  3031. static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
  3032. {
  3033. struct stv090x_state *state = fe->demodulator_priv;
  3034. u32 reg, idle = 0, fifo_full = 1;
  3035. u8 mode, value;
  3036. int i;
  3037. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3038. if (burst == SEC_MINI_A) {
  3039. mode = 3;
  3040. value = 0x00;
  3041. } else {
  3042. mode = 2;
  3043. value = 0xFF;
  3044. }
  3045. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
  3046. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  3047. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3048. goto err;
  3049. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  3050. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3051. goto err;
  3052. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  3053. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3054. goto err;
  3055. while (fifo_full) {
  3056. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3057. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  3058. }
  3059. if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
  3060. goto err;
  3061. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  3062. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  3063. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  3064. goto err;
  3065. i = 0;
  3066. while ((!idle) && (i < 10)) {
  3067. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  3068. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  3069. msleep(10);
  3070. i++;
  3071. }
  3072. return 0;
  3073. err:
  3074. dprintk(FE_ERROR, 1, "I/O error");
  3075. return -1;
  3076. }
  3077. static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
  3078. {
  3079. struct stv090x_state *state = fe->demodulator_priv;
  3080. u32 reg = 0, i = 0, rx_end = 0;
  3081. while ((rx_end != 1) && (i < 10)) {
  3082. msleep(10);
  3083. i++;
  3084. reg = STV090x_READ_DEMOD(state, DISRX_ST0);
  3085. rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
  3086. }
  3087. if (rx_end) {
  3088. reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
  3089. for (i = 0; i < reply->msg_len; i++)
  3090. reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
  3091. }
  3092. return 0;
  3093. }
  3094. static int stv090x_sleep(struct dvb_frontend *fe)
  3095. {
  3096. struct stv090x_state *state = fe->demodulator_priv;
  3097. u32 reg;
  3098. dprintk(FE_DEBUG, 1, "Set %s to sleep",
  3099. state->device == STV0900 ? "STV0900" : "STV0903");
  3100. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3101. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
  3102. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3103. goto err;
  3104. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3105. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
  3106. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3107. goto err;
  3108. return 0;
  3109. err:
  3110. dprintk(FE_ERROR, 1, "I/O error");
  3111. return -1;
  3112. }
  3113. static int stv090x_wakeup(struct dvb_frontend *fe)
  3114. {
  3115. struct stv090x_state *state = fe->demodulator_priv;
  3116. u32 reg;
  3117. dprintk(FE_DEBUG, 1, "Wake %s from standby",
  3118. state->device == STV0900 ? "STV0900" : "STV0903");
  3119. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3120. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
  3121. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3122. goto err;
  3123. reg = stv090x_read_reg(state, STV090x_TSTTNR1);
  3124. STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
  3125. if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
  3126. goto err;
  3127. return 0;
  3128. err:
  3129. dprintk(FE_ERROR, 1, "I/O error");
  3130. return -1;
  3131. }
  3132. static void stv090x_release(struct dvb_frontend *fe)
  3133. {
  3134. struct stv090x_state *state = fe->demodulator_priv;
  3135. kfree(state);
  3136. }
  3137. static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
  3138. {
  3139. u32 reg;
  3140. switch (ldpc_mode) {
  3141. case STV090x_DUAL:
  3142. default:
  3143. reg = stv090x_read_reg(state, STV090x_GENCFG);
  3144. if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
  3145. /* follow LDPC default state */
  3146. if (stv090x_write_reg(state, STV090x_GENCFG, reg) < 0)
  3147. goto err;
  3148. state->demod_mode = STV090x_DUAL;
  3149. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3150. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3151. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3152. goto err;
  3153. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3154. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3155. goto err;
  3156. }
  3157. break;
  3158. case STV090x_SINGLE:
  3159. if (state->demod == STV090x_DEMODULATOR_1) {
  3160. if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
  3161. goto err;
  3162. } else {
  3163. if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
  3164. goto err;
  3165. }
  3166. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3167. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3168. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3169. goto err;
  3170. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3171. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3172. goto err;
  3173. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3174. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
  3175. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3176. goto err;
  3177. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
  3178. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3179. goto err;
  3180. break;
  3181. }
  3182. return 0;
  3183. err:
  3184. dprintk(FE_ERROR, 1, "I/O error");
  3185. return -1;
  3186. }
  3187. /* return (Hz), clk in Hz*/
  3188. static u32 stv090x_get_mclk(struct stv090x_state *state)
  3189. {
  3190. const struct stv090x_config *config = state->config;
  3191. u32 div, reg;
  3192. u8 ratio;
  3193. div = stv090x_read_reg(state, STV090x_NCOARSE);
  3194. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3195. ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
  3196. return (div + 1) * config->xtal / ratio; /* kHz */
  3197. }
  3198. static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
  3199. {
  3200. const struct stv090x_config *config = state->config;
  3201. u32 reg, div, clk_sel;
  3202. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3203. clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
  3204. div = ((clk_sel * mclk) / config->xtal) - 1;
  3205. reg = stv090x_read_reg(state, STV090x_NCOARSE);
  3206. STV090x_SETFIELD(reg, M_DIV_FIELD, div);
  3207. if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
  3208. goto err;
  3209. state->mclk = stv090x_get_mclk(state);
  3210. /*Set the DiseqC frequency to 22KHz */
  3211. div = state->mclk / 704000;
  3212. if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
  3213. goto err;
  3214. if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
  3215. goto err;
  3216. return 0;
  3217. err:
  3218. dprintk(FE_ERROR, 1, "I/O error");
  3219. return -1;
  3220. }
  3221. static int stv090x_set_tspath(struct stv090x_state *state)
  3222. {
  3223. u32 reg;
  3224. if (state->dev_ver >= 0x20) {
  3225. switch (state->config->ts1_mode) {
  3226. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3227. case STV090x_TSMODE_DVBCI:
  3228. switch (state->config->ts2_mode) {
  3229. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3230. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3231. default:
  3232. stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
  3233. break;
  3234. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3235. case STV090x_TSMODE_DVBCI:
  3236. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
  3237. goto err;
  3238. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3239. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3240. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3241. goto err;
  3242. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3243. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3244. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3245. goto err;
  3246. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3247. goto err;
  3248. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3249. goto err;
  3250. break;
  3251. }
  3252. break;
  3253. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3254. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3255. default:
  3256. switch (state->config->ts2_mode) {
  3257. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3258. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3259. default:
  3260. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3261. goto err;
  3262. break;
  3263. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3264. case STV090x_TSMODE_DVBCI:
  3265. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
  3266. goto err;
  3267. break;
  3268. }
  3269. break;
  3270. }
  3271. } else {
  3272. switch (state->config->ts1_mode) {
  3273. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3274. case STV090x_TSMODE_DVBCI:
  3275. switch (state->config->ts2_mode) {
  3276. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3277. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3278. default:
  3279. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
  3280. break;
  3281. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3282. case STV090x_TSMODE_DVBCI:
  3283. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
  3284. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3285. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3286. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3287. goto err;
  3288. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3289. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
  3290. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3291. goto err;
  3292. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3293. goto err;
  3294. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3295. goto err;
  3296. break;
  3297. }
  3298. break;
  3299. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3300. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3301. default:
  3302. switch (state->config->ts2_mode) {
  3303. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3304. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3305. default:
  3306. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
  3307. break;
  3308. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3309. case STV090x_TSMODE_DVBCI:
  3310. stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
  3311. break;
  3312. }
  3313. break;
  3314. }
  3315. }
  3316. switch (state->config->ts1_mode) {
  3317. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3318. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3319. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3320. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3321. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3322. goto err;
  3323. break;
  3324. case STV090x_TSMODE_DVBCI:
  3325. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3326. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3327. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3328. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3329. goto err;
  3330. break;
  3331. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3332. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3333. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3334. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3335. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3336. goto err;
  3337. break;
  3338. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3339. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3340. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3341. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3342. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3343. goto err;
  3344. break;
  3345. default:
  3346. break;
  3347. }
  3348. switch (state->config->ts2_mode) {
  3349. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3350. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3351. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3352. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3353. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3354. goto err;
  3355. break;
  3356. case STV090x_TSMODE_DVBCI:
  3357. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3358. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3359. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3360. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3361. goto err;
  3362. break;
  3363. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3364. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3365. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3366. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3367. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3368. goto err;
  3369. break;
  3370. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3371. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3372. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3373. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3374. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3375. goto err;
  3376. break;
  3377. default:
  3378. break;
  3379. }
  3380. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3381. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3382. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3383. goto err;
  3384. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3385. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3386. goto err;
  3387. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3388. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3389. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3390. goto err;
  3391. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3392. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3393. goto err;
  3394. return 0;
  3395. err:
  3396. dprintk(FE_ERROR, 1, "I/O error");
  3397. return -1;
  3398. }
  3399. static int stv090x_init(struct dvb_frontend *fe)
  3400. {
  3401. struct stv090x_state *state = fe->demodulator_priv;
  3402. const struct stv090x_config *config = state->config;
  3403. u32 reg;
  3404. stv090x_ldpc_mode(state, state->demod_mode);
  3405. reg = STV090x_READ_DEMOD(state, TNRCFG2);
  3406. STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
  3407. if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
  3408. goto err;
  3409. reg = STV090x_READ_DEMOD(state, DEMOD);
  3410. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  3411. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  3412. goto err;
  3413. stv090x_i2c_gate_ctrl(fe, 1);
  3414. if (config->tuner_init)
  3415. config->tuner_init(fe);
  3416. stv090x_i2c_gate_ctrl(fe, 0);
  3417. stv090x_set_tspath(state);
  3418. return 0;
  3419. err:
  3420. dprintk(FE_ERROR, 1, "I/O error");
  3421. return -1;
  3422. }
  3423. static int stv090x_setup(struct dvb_frontend *fe)
  3424. {
  3425. struct stv090x_state *state = fe->demodulator_priv;
  3426. const struct stv090x_config *config = state->config;
  3427. const struct stv090x_reg *stv090x_initval = NULL;
  3428. const struct stv090x_reg *stv090x_cut20_val = NULL;
  3429. unsigned long t1_size = 0, t2_size = 0;
  3430. u32 reg = 0;
  3431. int i;
  3432. if (state->device == STV0900) {
  3433. dprintk(FE_DEBUG, 1, "Initializing STV0900");
  3434. stv090x_initval = stv0900_initval;
  3435. t1_size = ARRAY_SIZE(stv0900_initval);
  3436. stv090x_cut20_val = stv0900_cut20_val;
  3437. t2_size = ARRAY_SIZE(stv0900_cut20_val);
  3438. } else if (state->device == STV0903) {
  3439. dprintk(FE_DEBUG, 1, "Initializing STV0903");
  3440. stv090x_initval = stv0903_initval;
  3441. t1_size = ARRAY_SIZE(stv0903_initval);
  3442. stv090x_cut20_val = stv0903_cut20_val;
  3443. t2_size = ARRAY_SIZE(stv0903_cut20_val);
  3444. }
  3445. /* STV090x init */
  3446. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
  3447. goto err;
  3448. msleep(5);
  3449. if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
  3450. goto err;
  3451. STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
  3452. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
  3453. goto err;
  3454. if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
  3455. goto err;
  3456. msleep(5);
  3457. if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
  3458. goto err;
  3459. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
  3460. goto err;
  3461. msleep(5);
  3462. /* write initval */
  3463. dprintk(FE_DEBUG, 1, "Setting up initial values");
  3464. for (i = 0; i < t1_size; i++) {
  3465. if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
  3466. goto err;
  3467. }
  3468. state->dev_ver = stv090x_read_reg(state, STV090x_MID);
  3469. if (state->dev_ver >= 0x20) {
  3470. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3471. goto err;
  3472. /* write cut20_val*/
  3473. dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
  3474. for (i = 0; i < t2_size; i++) {
  3475. if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
  3476. goto err;
  3477. }
  3478. }
  3479. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
  3480. goto err;
  3481. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
  3482. goto err;
  3483. stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
  3484. msleep(5);
  3485. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
  3486. goto err;
  3487. stv090x_get_mclk(state);
  3488. return 0;
  3489. err:
  3490. dprintk(FE_ERROR, 1, "I/O error");
  3491. return -1;
  3492. }
  3493. static struct dvb_frontend_ops stv090x_ops = {
  3494. .info = {
  3495. .name = "STV090x Multistandard",
  3496. },
  3497. .release = stv090x_release,
  3498. .init = stv090x_init,
  3499. .sleep = stv090x_sleep,
  3500. .get_frontend_algo = stv090x_frontend_algo,
  3501. .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
  3502. .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
  3503. .diseqc_send_burst = stv090x_send_diseqc_burst,
  3504. .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
  3505. .set_tone = stv090x_set_tone,
  3506. .search = stv090x_search,
  3507. .read_status = stv090x_read_status,
  3508. .read_ber = stv090x_read_per,
  3509. .read_signal_strength = stv090x_read_signal_strength,
  3510. .read_snr = stv090x_read_cnr
  3511. };
  3512. struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
  3513. struct i2c_adapter *i2c,
  3514. enum stv090x_demodulator demod)
  3515. {
  3516. struct stv090x_state *state = NULL;
  3517. state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
  3518. if (state == NULL)
  3519. goto error;
  3520. state->verbose = &verbose;
  3521. state->config = config;
  3522. state->i2c = i2c;
  3523. state->frontend.ops = stv090x_ops;
  3524. state->frontend.demodulator_priv = state;
  3525. state->demod = demod;
  3526. state->demod_mode = config->demod_mode; /* Single or Dual mode */
  3527. state->device = config->device;
  3528. state->rolloff = STV090x_RO_35; /* default */
  3529. if (state->demod == STV090x_DEMODULATOR_0)
  3530. mutex_init(&demod_lock);
  3531. if (stv090x_sleep(&state->frontend) < 0) {
  3532. dprintk(FE_ERROR, 1, "Error putting device to sleep");
  3533. goto error;
  3534. }
  3535. if (stv090x_setup(&state->frontend) < 0) {
  3536. dprintk(FE_ERROR, 1, "Error setting up device");
  3537. goto error;
  3538. }
  3539. if (stv090x_wakeup(&state->frontend) < 0) {
  3540. dprintk(FE_ERROR, 1, "Error waking device");
  3541. goto error;
  3542. }
  3543. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
  3544. state->device == STV0900 ? "STV0900" : "STV0903",
  3545. demod,
  3546. state->dev_ver);
  3547. return &state->frontend;
  3548. error:
  3549. kfree(state);
  3550. return NULL;
  3551. }
  3552. EXPORT_SYMBOL(stv090x_attach);
  3553. MODULE_PARM_DESC(verbose, "Set Verbosity level");
  3554. MODULE_AUTHOR("Manu Abraham");
  3555. MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
  3556. MODULE_LICENSE("GPL");