dove.dtsi 11 KB

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  1. /include/ "skeleton.dtsi"
  2. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  3. / {
  4. compatible = "marvell,dove";
  5. model = "Marvell Armada 88AP510 SoC";
  6. aliases {
  7. gpio0 = &gpio0;
  8. gpio1 = &gpio1;
  9. gpio2 = &gpio2;
  10. };
  11. cpus {
  12. #address-cells = <1>;
  13. #size-cells = <0>;
  14. cpu0: cpu@0 {
  15. compatible = "marvell,pj4a", "marvell,sheeva-v7";
  16. device_type = "cpu";
  17. next-level-cache = <&l2>;
  18. reg = <0>;
  19. };
  20. };
  21. l2: l2-cache {
  22. compatible = "marvell,tauros2-cache";
  23. marvell,tauros2-cache-features = <0>;
  24. };
  25. mbus {
  26. compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
  27. #address-cells = <2>;
  28. #size-cells = <1>;
  29. controller = <&mbusc>;
  30. pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
  31. pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
  32. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
  33. MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
  34. MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
  35. MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
  36. MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
  37. };
  38. soc@f1000000 {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. interrupt-parent = <&intc>;
  43. ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
  44. 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
  45. 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
  46. 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
  47. 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
  48. 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
  49. 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
  50. 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
  51. mbusc: mbus-ctrl@20000 {
  52. compatible = "marvell,mbus-controller";
  53. reg = <0x20000 0x80>, <0x800100 0x8>;
  54. };
  55. timer: timer@20300 {
  56. compatible = "marvell,orion-timer";
  57. reg = <0x20300 0x20>;
  58. interrupt-parent = <&bridge_intc>;
  59. interrupts = <1>, <2>;
  60. clocks = <&core_clk 0>;
  61. };
  62. intc: main-interrupt-ctrl@20200 {
  63. compatible = "marvell,orion-intc";
  64. interrupt-controller;
  65. #interrupt-cells = <1>;
  66. reg = <0x20200 0x10>, <0x20210 0x10>;
  67. };
  68. bridge_intc: bridge-interrupt-ctrl@20110 {
  69. compatible = "marvell,orion-bridge-intc";
  70. interrupt-controller;
  71. #interrupt-cells = <1>;
  72. reg = <0x20110 0x8>;
  73. interrupts = <0>;
  74. marvell,#interrupts = <5>;
  75. };
  76. core_clk: core-clocks@d0214 {
  77. compatible = "marvell,dove-core-clock";
  78. reg = <0xd0214 0x4>;
  79. #clock-cells = <1>;
  80. };
  81. gate_clk: clock-gating-ctrl@d0038 {
  82. compatible = "marvell,dove-gating-clock";
  83. reg = <0xd0038 0x4>;
  84. clocks = <&core_clk 0>;
  85. #clock-cells = <1>;
  86. };
  87. thermal: thermal-diode@d001c {
  88. compatible = "marvell,dove-thermal";
  89. reg = <0xd001c 0x0c>, <0xd005c 0x08>;
  90. };
  91. uart0: serial@12000 {
  92. compatible = "ns16550a";
  93. reg = <0x12000 0x100>;
  94. reg-shift = <2>;
  95. interrupts = <7>;
  96. clocks = <&core_clk 0>;
  97. status = "disabled";
  98. };
  99. uart1: serial@12100 {
  100. compatible = "ns16550a";
  101. reg = <0x12100 0x100>;
  102. reg-shift = <2>;
  103. interrupts = <8>;
  104. clocks = <&core_clk 0>;
  105. pinctrl-0 = <&pmx_uart1>;
  106. pinctrl-names = "default";
  107. status = "disabled";
  108. };
  109. uart2: serial@12200 {
  110. compatible = "ns16550a";
  111. reg = <0x12000 0x100>;
  112. reg-shift = <2>;
  113. interrupts = <9>;
  114. clocks = <&core_clk 0>;
  115. status = "disabled";
  116. };
  117. uart3: serial@12300 {
  118. compatible = "ns16550a";
  119. reg = <0x12100 0x100>;
  120. reg-shift = <2>;
  121. interrupts = <10>;
  122. clocks = <&core_clk 0>;
  123. status = "disabled";
  124. };
  125. gpio0: gpio-ctrl@d0400 {
  126. compatible = "marvell,orion-gpio";
  127. #gpio-cells = <2>;
  128. gpio-controller;
  129. reg = <0xd0400 0x20>;
  130. ngpios = <32>;
  131. interrupt-controller;
  132. #interrupt-cells = <2>;
  133. interrupts = <12>, <13>, <14>, <60>;
  134. };
  135. gpio1: gpio-ctrl@d0420 {
  136. compatible = "marvell,orion-gpio";
  137. #gpio-cells = <2>;
  138. gpio-controller;
  139. reg = <0xd0420 0x20>;
  140. ngpios = <32>;
  141. interrupt-controller;
  142. #interrupt-cells = <2>;
  143. interrupts = <61>;
  144. };
  145. gpio2: gpio-ctrl@e8400 {
  146. compatible = "marvell,orion-gpio";
  147. #gpio-cells = <2>;
  148. gpio-controller;
  149. reg = <0xe8400 0x0c>;
  150. ngpios = <8>;
  151. };
  152. pinctrl: pin-ctrl@d0200 {
  153. compatible = "marvell,dove-pinctrl";
  154. reg = <0xd0200 0x10>;
  155. clocks = <&gate_clk 22>;
  156. pmx_gpio_0: pmx-gpio-0 {
  157. marvell,pins = "mpp0";
  158. marvell,function = "gpio";
  159. };
  160. pmx_gpio_1: pmx-gpio-1 {
  161. marvell,pins = "mpp1";
  162. marvell,function = "gpio";
  163. };
  164. pmx_gpio_2: pmx-gpio-2 {
  165. marvell,pins = "mpp2";
  166. marvell,function = "gpio";
  167. };
  168. pmx_gpio_3: pmx-gpio-3 {
  169. marvell,pins = "mpp3";
  170. marvell,function = "gpio";
  171. };
  172. pmx_gpio_4: pmx-gpio-4 {
  173. marvell,pins = "mpp4";
  174. marvell,function = "gpio";
  175. };
  176. pmx_gpio_5: pmx-gpio-5 {
  177. marvell,pins = "mpp5";
  178. marvell,function = "gpio";
  179. };
  180. pmx_gpio_6: pmx-gpio-6 {
  181. marvell,pins = "mpp6";
  182. marvell,function = "gpio";
  183. };
  184. pmx_gpio_7: pmx-gpio-7 {
  185. marvell,pins = "mpp7";
  186. marvell,function = "gpio";
  187. };
  188. pmx_gpio_8: pmx-gpio-8 {
  189. marvell,pins = "mpp8";
  190. marvell,function = "gpio";
  191. };
  192. pmx_gpio_9: pmx-gpio-9 {
  193. marvell,pins = "mpp9";
  194. marvell,function = "gpio";
  195. };
  196. pmx_gpio_10: pmx-gpio-10 {
  197. marvell,pins = "mpp10";
  198. marvell,function = "gpio";
  199. };
  200. pmx_gpio_11: pmx-gpio-11 {
  201. marvell,pins = "mpp11";
  202. marvell,function = "gpio";
  203. };
  204. pmx_gpio_12: pmx-gpio-12 {
  205. marvell,pins = "mpp12";
  206. marvell,function = "gpio";
  207. };
  208. pmx_gpio_13: pmx-gpio-13 {
  209. marvell,pins = "mpp13";
  210. marvell,function = "gpio";
  211. };
  212. pmx_gpio_14: pmx-gpio-14 {
  213. marvell,pins = "mpp14";
  214. marvell,function = "gpio";
  215. };
  216. pmx_gpio_15: pmx-gpio-15 {
  217. marvell,pins = "mpp15";
  218. marvell,function = "gpio";
  219. };
  220. pmx_gpio_16: pmx-gpio-16 {
  221. marvell,pins = "mpp16";
  222. marvell,function = "gpio";
  223. };
  224. pmx_gpio_17: pmx-gpio-17 {
  225. marvell,pins = "mpp17";
  226. marvell,function = "gpio";
  227. };
  228. pmx_gpio_18: pmx-gpio-18 {
  229. marvell,pins = "mpp18";
  230. marvell,function = "gpio";
  231. };
  232. pmx_gpio_19: pmx-gpio-19 {
  233. marvell,pins = "mpp19";
  234. marvell,function = "gpio";
  235. };
  236. pmx_gpio_20: pmx-gpio-20 {
  237. marvell,pins = "mpp20";
  238. marvell,function = "gpio";
  239. };
  240. pmx_gpio_21: pmx-gpio-21 {
  241. marvell,pins = "mpp21";
  242. marvell,function = "gpio";
  243. };
  244. pmx_camera: pmx-camera {
  245. marvell,pins = "mpp_camera";
  246. marvell,function = "camera";
  247. };
  248. pmx_camera_gpio: pmx-camera-gpio {
  249. marvell,pins = "mpp_camera";
  250. marvell,function = "gpio";
  251. };
  252. pmx_sdio0: pmx-sdio0 {
  253. marvell,pins = "mpp_sdio0";
  254. marvell,function = "sdio0";
  255. };
  256. pmx_sdio0_gpio: pmx-sdio0-gpio {
  257. marvell,pins = "mpp_sdio0";
  258. marvell,function = "gpio";
  259. };
  260. pmx_sdio1: pmx-sdio1 {
  261. marvell,pins = "mpp_sdio1";
  262. marvell,function = "sdio1";
  263. };
  264. pmx_sdio1_gpio: pmx-sdio1-gpio {
  265. marvell,pins = "mpp_sdio1";
  266. marvell,function = "gpio";
  267. };
  268. pmx_audio1_gpio: pmx-audio1-gpio {
  269. marvell,pins = "mpp_audio1";
  270. marvell,function = "gpio";
  271. };
  272. pmx_spi0: pmx-spi0 {
  273. marvell,pins = "mpp_spi0";
  274. marvell,function = "spi0";
  275. };
  276. pmx_spi0_gpio: pmx-spi0-gpio {
  277. marvell,pins = "mpp_spi0";
  278. marvell,function = "gpio";
  279. };
  280. pmx_uart1: pmx-uart1 {
  281. marvell,pins = "mpp_uart1";
  282. marvell,function = "uart1";
  283. };
  284. pmx_uart1_gpio: pmx-uart1-gpio {
  285. marvell,pins = "mpp_uart1";
  286. marvell,function = "gpio";
  287. };
  288. pmx_nand: pmx-nand {
  289. marvell,pins = "mpp_nand";
  290. marvell,function = "nand";
  291. };
  292. pmx_nand_gpo: pmx-nand-gpo {
  293. marvell,pins = "mpp_nand";
  294. marvell,function = "gpo";
  295. };
  296. };
  297. spi0: spi-ctrl@10600 {
  298. compatible = "marvell,orion-spi";
  299. #address-cells = <1>;
  300. #size-cells = <0>;
  301. cell-index = <0>;
  302. interrupts = <6>;
  303. reg = <0x10600 0x28>;
  304. clocks = <&core_clk 0>;
  305. pinctrl-0 = <&pmx_spi0>;
  306. pinctrl-names = "default";
  307. status = "disabled";
  308. };
  309. spi1: spi-ctrl@14600 {
  310. compatible = "marvell,orion-spi";
  311. #address-cells = <1>;
  312. #size-cells = <0>;
  313. cell-index = <1>;
  314. interrupts = <5>;
  315. reg = <0x14600 0x28>;
  316. clocks = <&core_clk 0>;
  317. status = "disabled";
  318. };
  319. i2c0: i2c-ctrl@11000 {
  320. compatible = "marvell,mv64xxx-i2c";
  321. reg = <0x11000 0x20>;
  322. #address-cells = <1>;
  323. #size-cells = <0>;
  324. interrupts = <11>;
  325. clock-frequency = <400000>;
  326. timeout-ms = <1000>;
  327. clocks = <&core_clk 0>;
  328. status = "disabled";
  329. };
  330. ehci0: usb-host@50000 {
  331. compatible = "marvell,orion-ehci";
  332. reg = <0x50000 0x1000>;
  333. interrupts = <24>;
  334. clocks = <&gate_clk 0>;
  335. status = "okay";
  336. };
  337. ehci1: usb-host@51000 {
  338. compatible = "marvell,orion-ehci";
  339. reg = <0x51000 0x1000>;
  340. interrupts = <25>;
  341. clocks = <&gate_clk 1>;
  342. status = "okay";
  343. };
  344. sdio0: sdio-host@92000 {
  345. compatible = "marvell,dove-sdhci";
  346. reg = <0x92000 0x100>;
  347. interrupts = <35>, <37>;
  348. clocks = <&gate_clk 8>;
  349. pinctrl-0 = <&pmx_sdio0>;
  350. pinctrl-names = "default";
  351. status = "disabled";
  352. };
  353. sdio1: sdio-host@90000 {
  354. compatible = "marvell,dove-sdhci";
  355. reg = <0x90000 0x100>;
  356. interrupts = <36>, <38>;
  357. clocks = <&gate_clk 9>;
  358. pinctrl-0 = <&pmx_sdio1>;
  359. pinctrl-names = "default";
  360. status = "disabled";
  361. };
  362. sata0: sata-host@a0000 {
  363. compatible = "marvell,orion-sata";
  364. reg = <0xa0000 0x2400>;
  365. interrupts = <62>;
  366. clocks = <&gate_clk 3>;
  367. nr-ports = <1>;
  368. status = "disabled";
  369. };
  370. rtc: real-time-clock@d8500 {
  371. compatible = "marvell,orion-rtc";
  372. reg = <0xd8500 0x20>;
  373. };
  374. crypto: crypto-engine@30000 {
  375. compatible = "marvell,orion-crypto";
  376. reg = <0x30000 0x10000>,
  377. <0xc8000000 0x800>;
  378. reg-names = "regs", "sram";
  379. interrupts = <31>;
  380. clocks = <&gate_clk 15>;
  381. status = "okay";
  382. };
  383. xor0: dma-engine@60800 {
  384. compatible = "marvell,orion-xor";
  385. reg = <0x60800 0x100
  386. 0x60a00 0x100>;
  387. clocks = <&gate_clk 23>;
  388. status = "okay";
  389. channel0 {
  390. interrupts = <39>;
  391. dmacap,memcpy;
  392. dmacap,xor;
  393. };
  394. channel1 {
  395. interrupts = <40>;
  396. dmacap,memset;
  397. dmacap,memcpy;
  398. dmacap,xor;
  399. };
  400. };
  401. xor1: dma-engine@60900 {
  402. compatible = "marvell,orion-xor";
  403. reg = <0x60900 0x100
  404. 0x60b00 0x100>;
  405. clocks = <&gate_clk 24>;
  406. status = "okay";
  407. channel0 {
  408. interrupts = <42>;
  409. dmacap,memcpy;
  410. dmacap,xor;
  411. };
  412. channel1 {
  413. interrupts = <43>;
  414. dmacap,memset;
  415. dmacap,memcpy;
  416. dmacap,xor;
  417. };
  418. };
  419. mdio: mdio-bus@72004 {
  420. compatible = "marvell,orion-mdio";
  421. #address-cells = <1>;
  422. #size-cells = <0>;
  423. reg = <0x72004 0x84>;
  424. interrupts = <30>;
  425. clocks = <&gate_clk 2>;
  426. status = "disabled";
  427. ethphy: ethernet-phy {
  428. device-type = "ethernet-phy";
  429. /* set phy address in board file */
  430. };
  431. };
  432. eth: ethernet-controller@72000 {
  433. compatible = "marvell,orion-eth";
  434. #address-cells = <1>;
  435. #size-cells = <0>;
  436. reg = <0x72000 0x4000>;
  437. clocks = <&gate_clk 2>;
  438. marvell,tx-checksum-limit = <1600>;
  439. status = "disabled";
  440. ethernet-port@0 {
  441. device_type = "network";
  442. compatible = "marvell,orion-eth-port";
  443. reg = <0>;
  444. interrupts = <29>;
  445. /* overwrite MAC address in bootloader */
  446. local-mac-address = [00 00 00 00 00 00];
  447. phy-handle = <&ethphy>;
  448. };
  449. };
  450. };
  451. };