aic7xxx_osm_pci.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380
  1. /*
  2. * Linux driver attachment glue for PCI based controllers.
  3. *
  4. * Copyright (c) 2000-2001 Adaptec Inc.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c#47 $
  40. */
  41. #include "aic7xxx_osm.h"
  42. #include "aic7xxx_pci.h"
  43. static int ahc_linux_pci_dev_probe(struct pci_dev *pdev,
  44. const struct pci_device_id *ent);
  45. static int ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc,
  46. u_long *base);
  47. static int ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
  48. u_long *bus_addr,
  49. uint8_t __iomem **maddr);
  50. static void ahc_linux_pci_dev_remove(struct pci_dev *pdev);
  51. /* Define the macro locally since it's different for different class of chips.
  52. */
  53. #define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI)
  54. static struct pci_device_id ahc_linux_pci_id_table[] = {
  55. /* aic7850 based controllers */
  56. ID(ID_AHA_2902_04_10_15_20C_30C),
  57. /* aic7860 based controllers */
  58. ID(ID_AHA_2930CU),
  59. ID(ID_AHA_1480A & ID_DEV_VENDOR_MASK),
  60. ID(ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK),
  61. ID(ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK),
  62. ID(ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK),
  63. /* aic7870 based controllers */
  64. ID(ID_AHA_2940),
  65. ID(ID_AHA_3940),
  66. ID(ID_AHA_398X),
  67. ID(ID_AHA_2944),
  68. ID(ID_AHA_3944),
  69. ID(ID_AHA_4944),
  70. /* aic7880 based controllers */
  71. ID(ID_AHA_2940U & ID_DEV_VENDOR_MASK),
  72. ID(ID_AHA_3940U & ID_DEV_VENDOR_MASK),
  73. ID(ID_AHA_2944U & ID_DEV_VENDOR_MASK),
  74. ID(ID_AHA_3944U & ID_DEV_VENDOR_MASK),
  75. ID(ID_AHA_398XU & ID_DEV_VENDOR_MASK),
  76. ID(ID_AHA_4944U & ID_DEV_VENDOR_MASK),
  77. ID(ID_AHA_2930U & ID_DEV_VENDOR_MASK),
  78. ID(ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK),
  79. ID(ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK),
  80. /* aic7890 based controllers */
  81. ID(ID_AHA_2930U2),
  82. ID(ID_AHA_2940U2B),
  83. ID(ID_AHA_2940U2_OEM),
  84. ID(ID_AHA_2940U2),
  85. ID(ID_AHA_2950U2B),
  86. ID16(ID_AIC7890_ARO & ID_AIC7895_ARO_MASK),
  87. ID(ID_AAA_131U2),
  88. /* aic7890 based controllers */
  89. ID(ID_AHA_29160),
  90. ID(ID_AHA_29160_CPQ),
  91. ID(ID_AHA_29160N),
  92. ID(ID_AHA_29160C),
  93. ID(ID_AHA_29160B),
  94. ID(ID_AHA_19160B),
  95. ID(ID_AIC7892_ARO),
  96. /* aic7892 based controllers */
  97. ID(ID_AHA_2940U_DUAL),
  98. ID(ID_AHA_3940AU),
  99. ID(ID_AHA_3944AU),
  100. ID(ID_AIC7895_ARO),
  101. ID(ID_AHA_3950U2B_0),
  102. ID(ID_AHA_3950U2B_1),
  103. ID(ID_AHA_3950U2D_0),
  104. ID(ID_AHA_3950U2D_1),
  105. ID(ID_AIC7896_ARO),
  106. /* aic7899 based controllers */
  107. ID(ID_AHA_3960D),
  108. ID(ID_AHA_3960D_CPQ),
  109. ID(ID_AIC7899_ARO),
  110. /* Generic chip probes for devices we don't know exactly. */
  111. ID(ID_AIC7850 & ID_DEV_VENDOR_MASK),
  112. ID(ID_AIC7855 & ID_DEV_VENDOR_MASK),
  113. ID(ID_AIC7859 & ID_DEV_VENDOR_MASK),
  114. ID(ID_AIC7860 & ID_DEV_VENDOR_MASK),
  115. ID(ID_AIC7870 & ID_DEV_VENDOR_MASK),
  116. ID(ID_AIC7880 & ID_DEV_VENDOR_MASK),
  117. ID16(ID_AIC7890 & ID_9005_GENERIC_MASK),
  118. ID16(ID_AIC7892 & ID_9005_GENERIC_MASK),
  119. ID(ID_AIC7895 & ID_DEV_VENDOR_MASK),
  120. ID16(ID_AIC7896 & ID_9005_GENERIC_MASK),
  121. ID16(ID_AIC7899 & ID_9005_GENERIC_MASK),
  122. ID(ID_AIC7810 & ID_DEV_VENDOR_MASK),
  123. ID(ID_AIC7815 & ID_DEV_VENDOR_MASK),
  124. { 0 }
  125. };
  126. MODULE_DEVICE_TABLE(pci, ahc_linux_pci_id_table);
  127. struct pci_driver aic7xxx_pci_driver = {
  128. .name = "aic7xxx",
  129. .probe = ahc_linux_pci_dev_probe,
  130. .remove = ahc_linux_pci_dev_remove,
  131. .id_table = ahc_linux_pci_id_table
  132. };
  133. static void
  134. ahc_linux_pci_dev_remove(struct pci_dev *pdev)
  135. {
  136. struct ahc_softc *ahc = pci_get_drvdata(pdev);
  137. u_long s;
  138. ahc_lock(ahc, &s);
  139. ahc_intr_enable(ahc, FALSE);
  140. ahc_unlock(ahc, &s);
  141. ahc_free(ahc);
  142. }
  143. static void
  144. ahc_linux_pci_inherit_flags(struct ahc_softc *ahc)
  145. {
  146. struct pci_dev *pdev = ahc->dev_softc, *master_pdev;
  147. unsigned int master_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
  148. master_pdev = pci_get_slot(pdev->bus, master_devfn);
  149. if (master_pdev) {
  150. struct ahc_softc *master = pci_get_drvdata(master_pdev);
  151. if (master) {
  152. ahc->flags &= ~AHC_BIOS_ENABLED;
  153. ahc->flags |= master->flags & AHC_BIOS_ENABLED;
  154. ahc->flags &= ~AHC_PRIMARY_CHANNEL;
  155. ahc->flags |= master->flags & AHC_PRIMARY_CHANNEL;
  156. } else
  157. printk(KERN_ERR "aic7xxx: no multichannel peer found!\n");
  158. pci_dev_put(master_pdev);
  159. }
  160. }
  161. static int
  162. ahc_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  163. {
  164. char buf[80];
  165. const uint64_t mask_39bit = 0x7FFFFFFFFFULL;
  166. struct ahc_softc *ahc;
  167. ahc_dev_softc_t pci;
  168. struct ahc_pci_identity *entry;
  169. char *name;
  170. int error;
  171. struct device *dev = &pdev->dev;
  172. pci = pdev;
  173. entry = ahc_find_pci_device(pci);
  174. if (entry == NULL)
  175. return (-ENODEV);
  176. /*
  177. * Allocate a softc for this card and
  178. * set it up for attachment by our
  179. * common detect routine.
  180. */
  181. sprintf(buf, "ahc_pci:%d:%d:%d",
  182. ahc_get_pci_bus(pci),
  183. ahc_get_pci_slot(pci),
  184. ahc_get_pci_function(pci));
  185. name = malloc(strlen(buf) + 1, M_DEVBUF, M_NOWAIT);
  186. if (name == NULL)
  187. return (-ENOMEM);
  188. strcpy(name, buf);
  189. ahc = ahc_alloc(NULL, name);
  190. if (ahc == NULL)
  191. return (-ENOMEM);
  192. if (pci_enable_device(pdev)) {
  193. ahc_free(ahc);
  194. return (-ENODEV);
  195. }
  196. pci_set_master(pdev);
  197. if (sizeof(dma_addr_t) > 4
  198. && ahc->features & AHC_LARGE_SCBS
  199. && dma_set_mask(dev, mask_39bit) == 0
  200. && dma_get_required_mask(dev) > DMA_32BIT_MASK) {
  201. ahc->flags |= AHC_39BIT_ADDRESSING;
  202. } else {
  203. if (dma_set_mask(dev, DMA_32BIT_MASK)) {
  204. printk(KERN_WARNING "aic7xxx: No suitable DMA available.\n");
  205. return (-ENODEV);
  206. }
  207. }
  208. ahc->dev_softc = pci;
  209. error = ahc_pci_config(ahc, entry);
  210. if (error != 0) {
  211. ahc_free(ahc);
  212. return (-error);
  213. }
  214. /*
  215. * Second Function PCI devices need to inherit some
  216. * settings from function 0.
  217. */
  218. if ((ahc->features & AHC_MULTI_FUNC) && PCI_FUNC(pdev->devfn) != 0)
  219. ahc_linux_pci_inherit_flags(ahc);
  220. pci_set_drvdata(pdev, ahc);
  221. ahc_linux_register_host(ahc, &aic7xxx_driver_template);
  222. return (0);
  223. }
  224. int
  225. ahc_linux_pci_init(void)
  226. {
  227. /* Translate error or zero return into zero or one */
  228. return pci_module_init(&aic7xxx_pci_driver) ? 0 : 1;
  229. }
  230. void
  231. ahc_linux_pci_exit(void)
  232. {
  233. pci_unregister_driver(&aic7xxx_pci_driver);
  234. }
  235. static int
  236. ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, u_long *base)
  237. {
  238. if (aic7xxx_allow_memio == 0)
  239. return (ENOMEM);
  240. *base = pci_resource_start(ahc->dev_softc, 0);
  241. if (*base == 0)
  242. return (ENOMEM);
  243. if (request_region(*base, 256, "aic7xxx") == 0)
  244. return (ENOMEM);
  245. return (0);
  246. }
  247. static int
  248. ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
  249. u_long *bus_addr,
  250. uint8_t __iomem **maddr)
  251. {
  252. u_long start;
  253. int error;
  254. error = 0;
  255. start = pci_resource_start(ahc->dev_softc, 1);
  256. if (start != 0) {
  257. *bus_addr = start;
  258. if (request_mem_region(start, 0x1000, "aic7xxx") == 0)
  259. error = ENOMEM;
  260. if (error == 0) {
  261. *maddr = ioremap_nocache(start, 256);
  262. if (*maddr == NULL) {
  263. error = ENOMEM;
  264. release_mem_region(start, 0x1000);
  265. }
  266. }
  267. } else
  268. error = ENOMEM;
  269. return (error);
  270. }
  271. int
  272. ahc_pci_map_registers(struct ahc_softc *ahc)
  273. {
  274. uint32_t command;
  275. u_long base;
  276. uint8_t __iomem *maddr;
  277. int error;
  278. /*
  279. * If its allowed, we prefer memory mapped access.
  280. */
  281. command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, 4);
  282. command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
  283. base = 0;
  284. maddr = NULL;
  285. error = ahc_linux_pci_reserve_mem_region(ahc, &base, &maddr);
  286. if (error == 0) {
  287. ahc->platform_data->mem_busaddr = base;
  288. ahc->tag = BUS_SPACE_MEMIO;
  289. ahc->bsh.maddr = maddr;
  290. ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
  291. command | PCIM_CMD_MEMEN, 4);
  292. /*
  293. * Do a quick test to see if memory mapped
  294. * I/O is functioning correctly.
  295. */
  296. if (ahc_pci_test_register_access(ahc) != 0) {
  297. printf("aic7xxx: PCI Device %d:%d:%d "
  298. "failed memory mapped test. Using PIO.\n",
  299. ahc_get_pci_bus(ahc->dev_softc),
  300. ahc_get_pci_slot(ahc->dev_softc),
  301. ahc_get_pci_function(ahc->dev_softc));
  302. iounmap(maddr);
  303. release_mem_region(ahc->platform_data->mem_busaddr,
  304. 0x1000);
  305. ahc->bsh.maddr = NULL;
  306. maddr = NULL;
  307. } else
  308. command |= PCIM_CMD_MEMEN;
  309. } else {
  310. printf("aic7xxx: PCI%d:%d:%d MEM region 0x%lx "
  311. "unavailable. Cannot memory map device.\n",
  312. ahc_get_pci_bus(ahc->dev_softc),
  313. ahc_get_pci_slot(ahc->dev_softc),
  314. ahc_get_pci_function(ahc->dev_softc),
  315. base);
  316. }
  317. /*
  318. * We always prefer memory mapped access.
  319. */
  320. if (maddr == NULL) {
  321. error = ahc_linux_pci_reserve_io_region(ahc, &base);
  322. if (error == 0) {
  323. ahc->tag = BUS_SPACE_PIO;
  324. ahc->bsh.ioport = base;
  325. command |= PCIM_CMD_PORTEN;
  326. } else {
  327. printf("aic7xxx: PCI%d:%d:%d IO region 0x%lx[0..255] "
  328. "unavailable. Cannot map device.\n",
  329. ahc_get_pci_bus(ahc->dev_softc),
  330. ahc_get_pci_slot(ahc->dev_softc),
  331. ahc_get_pci_function(ahc->dev_softc),
  332. base);
  333. }
  334. }
  335. ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
  336. return (error);
  337. }
  338. int
  339. ahc_pci_map_int(struct ahc_softc *ahc)
  340. {
  341. int error;
  342. error = request_irq(ahc->dev_softc->irq, ahc_linux_isr,
  343. SA_SHIRQ, "aic7xxx", ahc);
  344. if (error == 0)
  345. ahc->platform_data->irq = ahc->dev_softc->irq;
  346. return (-error);
  347. }