atl1c_main.c 77 KB

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  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
  26. #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
  27. #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
  28. #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
  29. #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
  30. #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
  31. #define L2CB_V10 0xc0
  32. #define L2CB_V11 0xc1
  33. /*
  34. * atl1c_pci_tbl - PCI Device ID Table
  35. *
  36. * Wildcard entries (PCI_ANY_ID) should come last
  37. * Last entry must be all 0s
  38. *
  39. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  40. * Class, Class Mask, private data (not used) }
  41. */
  42. static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
  43. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  44. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  45. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  46. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  47. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  48. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  49. /* required last entry */
  50. { 0 }
  51. };
  52. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  53. MODULE_AUTHOR("Jie Yang");
  54. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  55. MODULE_DESCRIPTION("Qualcom Atheros 100/1000M Ethernet Network Driver");
  56. MODULE_LICENSE("GPL");
  57. MODULE_VERSION(ATL1C_DRV_VERSION);
  58. static int atl1c_stop_mac(struct atl1c_hw *hw);
  59. static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
  60. static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
  61. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  62. static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup);
  63. static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
  64. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  65. int *work_done, int work_to_do);
  66. static int atl1c_up(struct atl1c_adapter *adapter);
  67. static void atl1c_down(struct atl1c_adapter *adapter);
  68. static const u16 atl1c_pay_load_size[] = {
  69. 128, 256, 512, 1024, 2048, 4096,
  70. };
  71. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  72. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  73. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  74. {
  75. u32 data;
  76. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  77. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  78. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  79. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  80. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  81. data &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK <<
  82. PCIE_PHYMISC2_SERDES_CDR_SHIFT);
  83. data |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
  84. data &= ~(PCIE_PHYMISC2_SERDES_TH_MASK <<
  85. PCIE_PHYMISC2_SERDES_TH_SHIFT);
  86. data |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
  87. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  88. }
  89. }
  90. /* FIXME: no need any more ? */
  91. /*
  92. * atl1c_init_pcie - init PCIE module
  93. */
  94. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  95. {
  96. u32 data;
  97. u32 pci_cmd;
  98. struct pci_dev *pdev = hw->adapter->pdev;
  99. int pos;
  100. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  101. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  102. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  103. PCI_COMMAND_IO);
  104. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  105. /*
  106. * Clear any PowerSaveing Settings
  107. */
  108. pci_enable_wake(pdev, PCI_D3hot, 0);
  109. pci_enable_wake(pdev, PCI_D3cold, 0);
  110. /*
  111. * Mask some pcie error bits
  112. */
  113. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  114. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  115. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  116. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  117. /* clear error status */
  118. pci_write_config_word(pdev, pci_pcie_cap(pdev) + PCI_EXP_DEVSTA,
  119. PCI_EXP_DEVSTA_NFED |
  120. PCI_EXP_DEVSTA_FED |
  121. PCI_EXP_DEVSTA_CED |
  122. PCI_EXP_DEVSTA_URD);
  123. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  124. data &= ~LTSSM_ID_EN_WRO;
  125. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  126. atl1c_pcie_patch(hw);
  127. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  128. atl1c_disable_l0s_l1(hw);
  129. if (flag & ATL1C_PCIE_PHY_RESET)
  130. AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
  131. else
  132. AT_WRITE_REG(hw, REG_GPHY_CTRL,
  133. GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
  134. msleep(5);
  135. }
  136. /*
  137. * atl1c_irq_enable - Enable default interrupt generation settings
  138. * @adapter: board private structure
  139. */
  140. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  141. {
  142. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  143. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  144. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  145. AT_WRITE_FLUSH(&adapter->hw);
  146. }
  147. }
  148. /*
  149. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  150. * @adapter: board private structure
  151. */
  152. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  153. {
  154. atomic_inc(&adapter->irq_sem);
  155. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  156. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  157. AT_WRITE_FLUSH(&adapter->hw);
  158. synchronize_irq(adapter->pdev->irq);
  159. }
  160. /*
  161. * atl1c_irq_reset - reset interrupt confiure on the NIC
  162. * @adapter: board private structure
  163. */
  164. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  165. {
  166. atomic_set(&adapter->irq_sem, 1);
  167. atl1c_irq_enable(adapter);
  168. }
  169. /*
  170. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  171. * of the idle status register until the device is actually idle
  172. */
  173. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  174. {
  175. int timeout;
  176. u32 data;
  177. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  178. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  179. if ((data & modu_ctrl) == 0)
  180. return 0;
  181. msleep(1);
  182. }
  183. return data;
  184. }
  185. /*
  186. * atl1c_phy_config - Timer Call-back
  187. * @data: pointer to netdev cast into an unsigned long
  188. */
  189. static void atl1c_phy_config(unsigned long data)
  190. {
  191. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  192. struct atl1c_hw *hw = &adapter->hw;
  193. unsigned long flags;
  194. spin_lock_irqsave(&adapter->mdio_lock, flags);
  195. atl1c_restart_autoneg(hw);
  196. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  197. }
  198. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  199. {
  200. WARN_ON(in_interrupt());
  201. atl1c_down(adapter);
  202. atl1c_up(adapter);
  203. clear_bit(__AT_RESETTING, &adapter->flags);
  204. }
  205. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  206. {
  207. struct atl1c_hw *hw = &adapter->hw;
  208. struct net_device *netdev = adapter->netdev;
  209. struct pci_dev *pdev = adapter->pdev;
  210. int err;
  211. unsigned long flags;
  212. u16 speed, duplex, phy_data;
  213. spin_lock_irqsave(&adapter->mdio_lock, flags);
  214. /* MII_BMSR must read twise */
  215. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  216. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  217. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  218. if ((phy_data & BMSR_LSTATUS) == 0) {
  219. /* link down */
  220. hw->hibernate = true;
  221. if (atl1c_stop_mac(hw) != 0)
  222. if (netif_msg_hw(adapter))
  223. dev_warn(&pdev->dev, "stop mac failed\n");
  224. atl1c_set_aspm(hw, false);
  225. netif_carrier_off(netdev);
  226. netif_stop_queue(netdev);
  227. atl1c_phy_reset(hw);
  228. atl1c_phy_init(&adapter->hw);
  229. } else {
  230. /* Link Up */
  231. hw->hibernate = false;
  232. spin_lock_irqsave(&adapter->mdio_lock, flags);
  233. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  234. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  235. if (unlikely(err))
  236. return;
  237. /* link result is our setting */
  238. if (adapter->link_speed != speed ||
  239. adapter->link_duplex != duplex) {
  240. adapter->link_speed = speed;
  241. adapter->link_duplex = duplex;
  242. atl1c_set_aspm(hw, true);
  243. atl1c_enable_tx_ctrl(hw);
  244. atl1c_enable_rx_ctrl(hw);
  245. atl1c_setup_mac_ctrl(adapter);
  246. if (netif_msg_link(adapter))
  247. dev_info(&pdev->dev,
  248. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  249. atl1c_driver_name, netdev->name,
  250. adapter->link_speed,
  251. adapter->link_duplex == FULL_DUPLEX ?
  252. "Full Duplex" : "Half Duplex");
  253. }
  254. if (!netif_carrier_ok(netdev))
  255. netif_carrier_on(netdev);
  256. }
  257. }
  258. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  259. {
  260. struct net_device *netdev = adapter->netdev;
  261. struct pci_dev *pdev = adapter->pdev;
  262. u16 phy_data;
  263. u16 link_up;
  264. spin_lock(&adapter->mdio_lock);
  265. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  266. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  267. spin_unlock(&adapter->mdio_lock);
  268. link_up = phy_data & BMSR_LSTATUS;
  269. /* notify upper layer link down ASAP */
  270. if (!link_up) {
  271. if (netif_carrier_ok(netdev)) {
  272. /* old link state: Up */
  273. netif_carrier_off(netdev);
  274. if (netif_msg_link(adapter))
  275. dev_info(&pdev->dev,
  276. "%s: %s NIC Link is Down\n",
  277. atl1c_driver_name, netdev->name);
  278. adapter->link_speed = SPEED_0;
  279. }
  280. }
  281. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  282. schedule_work(&adapter->common_task);
  283. }
  284. static void atl1c_common_task(struct work_struct *work)
  285. {
  286. struct atl1c_adapter *adapter;
  287. struct net_device *netdev;
  288. adapter = container_of(work, struct atl1c_adapter, common_task);
  289. netdev = adapter->netdev;
  290. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  291. netif_device_detach(netdev);
  292. atl1c_down(adapter);
  293. atl1c_up(adapter);
  294. netif_device_attach(netdev);
  295. }
  296. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  297. &adapter->work_event))
  298. atl1c_check_link_status(adapter);
  299. }
  300. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  301. {
  302. del_timer_sync(&adapter->phy_config_timer);
  303. }
  304. /*
  305. * atl1c_tx_timeout - Respond to a Tx Hang
  306. * @netdev: network interface device structure
  307. */
  308. static void atl1c_tx_timeout(struct net_device *netdev)
  309. {
  310. struct atl1c_adapter *adapter = netdev_priv(netdev);
  311. /* Do the reset outside of interrupt context */
  312. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  313. schedule_work(&adapter->common_task);
  314. }
  315. /*
  316. * atl1c_set_multi - Multicast and Promiscuous mode set
  317. * @netdev: network interface device structure
  318. *
  319. * The set_multi entry point is called whenever the multicast address
  320. * list or the network interface flags are updated. This routine is
  321. * responsible for configuring the hardware for proper multicast,
  322. * promiscuous mode, and all-multi behavior.
  323. */
  324. static void atl1c_set_multi(struct net_device *netdev)
  325. {
  326. struct atl1c_adapter *adapter = netdev_priv(netdev);
  327. struct atl1c_hw *hw = &adapter->hw;
  328. struct netdev_hw_addr *ha;
  329. u32 mac_ctrl_data;
  330. u32 hash_value;
  331. /* Check for Promiscuous and All Multicast modes */
  332. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  333. if (netdev->flags & IFF_PROMISC) {
  334. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  335. } else if (netdev->flags & IFF_ALLMULTI) {
  336. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  337. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  338. } else {
  339. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  340. }
  341. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  342. /* clear the old settings from the multicast hash table */
  343. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  344. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  345. /* comoute mc addresses' hash value ,and put it into hash table */
  346. netdev_for_each_mc_addr(ha, netdev) {
  347. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  348. atl1c_hash_set(hw, hash_value);
  349. }
  350. }
  351. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  352. {
  353. if (features & NETIF_F_HW_VLAN_RX) {
  354. /* enable VLAN tag insert/strip */
  355. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  356. } else {
  357. /* disable VLAN tag insert/strip */
  358. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  359. }
  360. }
  361. static void atl1c_vlan_mode(struct net_device *netdev,
  362. netdev_features_t features)
  363. {
  364. struct atl1c_adapter *adapter = netdev_priv(netdev);
  365. struct pci_dev *pdev = adapter->pdev;
  366. u32 mac_ctrl_data = 0;
  367. if (netif_msg_pktdata(adapter))
  368. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  369. atl1c_irq_disable(adapter);
  370. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  371. __atl1c_vlan_mode(features, &mac_ctrl_data);
  372. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  373. atl1c_irq_enable(adapter);
  374. }
  375. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  376. {
  377. struct pci_dev *pdev = adapter->pdev;
  378. if (netif_msg_pktdata(adapter))
  379. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  380. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  381. }
  382. /*
  383. * atl1c_set_mac - Change the Ethernet Address of the NIC
  384. * @netdev: network interface device structure
  385. * @p: pointer to an address structure
  386. *
  387. * Returns 0 on success, negative on failure
  388. */
  389. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  390. {
  391. struct atl1c_adapter *adapter = netdev_priv(netdev);
  392. struct sockaddr *addr = p;
  393. if (!is_valid_ether_addr(addr->sa_data))
  394. return -EADDRNOTAVAIL;
  395. if (netif_running(netdev))
  396. return -EBUSY;
  397. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  398. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  399. netdev->addr_assign_type &= ~NET_ADDR_RANDOM;
  400. atl1c_hw_set_mac_addr(&adapter->hw);
  401. return 0;
  402. }
  403. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  404. struct net_device *dev)
  405. {
  406. int mtu = dev->mtu;
  407. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  408. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  409. }
  410. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  411. netdev_features_t features)
  412. {
  413. /*
  414. * Since there is no support for separate rx/tx vlan accel
  415. * enable/disable make sure tx flag is always in same state as rx.
  416. */
  417. if (features & NETIF_F_HW_VLAN_RX)
  418. features |= NETIF_F_HW_VLAN_TX;
  419. else
  420. features &= ~NETIF_F_HW_VLAN_TX;
  421. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  422. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  423. return features;
  424. }
  425. static int atl1c_set_features(struct net_device *netdev,
  426. netdev_features_t features)
  427. {
  428. netdev_features_t changed = netdev->features ^ features;
  429. if (changed & NETIF_F_HW_VLAN_RX)
  430. atl1c_vlan_mode(netdev, features);
  431. return 0;
  432. }
  433. /*
  434. * atl1c_change_mtu - Change the Maximum Transfer Unit
  435. * @netdev: network interface device structure
  436. * @new_mtu: new value for maximum frame size
  437. *
  438. * Returns 0 on success, negative on failure
  439. */
  440. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  441. {
  442. struct atl1c_adapter *adapter = netdev_priv(netdev);
  443. struct atl1c_hw *hw = &adapter->hw;
  444. int old_mtu = netdev->mtu;
  445. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  446. /* Fast Ethernet controller doesn't support jumbo packet */
  447. if (((hw->nic_type == athr_l2c ||
  448. hw->nic_type == athr_l2c_b ||
  449. hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
  450. max_frame < ETH_ZLEN + ETH_FCS_LEN ||
  451. max_frame > MAX_JUMBO_FRAME_SIZE) {
  452. if (netif_msg_link(adapter))
  453. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  454. return -EINVAL;
  455. }
  456. /* set MTU */
  457. if (old_mtu != new_mtu && netif_running(netdev)) {
  458. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  459. msleep(1);
  460. netdev->mtu = new_mtu;
  461. adapter->hw.max_frame_size = new_mtu;
  462. atl1c_set_rxbufsize(adapter, netdev);
  463. atl1c_down(adapter);
  464. netdev_update_features(netdev);
  465. atl1c_up(adapter);
  466. clear_bit(__AT_RESETTING, &adapter->flags);
  467. if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
  468. u32 phy_data;
  469. AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
  470. phy_data |= 0x10000000;
  471. AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
  472. }
  473. }
  474. return 0;
  475. }
  476. /*
  477. * caller should hold mdio_lock
  478. */
  479. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  480. {
  481. struct atl1c_adapter *adapter = netdev_priv(netdev);
  482. u16 result;
  483. atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
  484. return result;
  485. }
  486. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  487. int reg_num, int val)
  488. {
  489. struct atl1c_adapter *adapter = netdev_priv(netdev);
  490. atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
  491. }
  492. /*
  493. * atl1c_mii_ioctl -
  494. * @netdev:
  495. * @ifreq:
  496. * @cmd:
  497. */
  498. static int atl1c_mii_ioctl(struct net_device *netdev,
  499. struct ifreq *ifr, int cmd)
  500. {
  501. struct atl1c_adapter *adapter = netdev_priv(netdev);
  502. struct pci_dev *pdev = adapter->pdev;
  503. struct mii_ioctl_data *data = if_mii(ifr);
  504. unsigned long flags;
  505. int retval = 0;
  506. if (!netif_running(netdev))
  507. return -EINVAL;
  508. spin_lock_irqsave(&adapter->mdio_lock, flags);
  509. switch (cmd) {
  510. case SIOCGMIIPHY:
  511. data->phy_id = 0;
  512. break;
  513. case SIOCGMIIREG:
  514. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  515. &data->val_out)) {
  516. retval = -EIO;
  517. goto out;
  518. }
  519. break;
  520. case SIOCSMIIREG:
  521. if (data->reg_num & ~(0x1F)) {
  522. retval = -EFAULT;
  523. goto out;
  524. }
  525. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  526. data->reg_num, data->val_in);
  527. if (atl1c_write_phy_reg(&adapter->hw,
  528. data->reg_num, data->val_in)) {
  529. retval = -EIO;
  530. goto out;
  531. }
  532. break;
  533. default:
  534. retval = -EOPNOTSUPP;
  535. break;
  536. }
  537. out:
  538. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  539. return retval;
  540. }
  541. /*
  542. * atl1c_ioctl -
  543. * @netdev:
  544. * @ifreq:
  545. * @cmd:
  546. */
  547. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  548. {
  549. switch (cmd) {
  550. case SIOCGMIIPHY:
  551. case SIOCGMIIREG:
  552. case SIOCSMIIREG:
  553. return atl1c_mii_ioctl(netdev, ifr, cmd);
  554. default:
  555. return -EOPNOTSUPP;
  556. }
  557. }
  558. /*
  559. * atl1c_alloc_queues - Allocate memory for all rings
  560. * @adapter: board private structure to initialize
  561. *
  562. */
  563. static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
  564. {
  565. return 0;
  566. }
  567. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  568. {
  569. switch (hw->device_id) {
  570. case PCI_DEVICE_ID_ATTANSIC_L2C:
  571. hw->nic_type = athr_l2c;
  572. break;
  573. case PCI_DEVICE_ID_ATTANSIC_L1C:
  574. hw->nic_type = athr_l1c;
  575. break;
  576. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  577. hw->nic_type = athr_l2c_b;
  578. break;
  579. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  580. hw->nic_type = athr_l2c_b2;
  581. break;
  582. case PCI_DEVICE_ID_ATHEROS_L1D:
  583. hw->nic_type = athr_l1d;
  584. break;
  585. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  586. hw->nic_type = athr_l1d_2;
  587. break;
  588. default:
  589. break;
  590. }
  591. }
  592. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  593. {
  594. u32 phy_status_data;
  595. u32 link_ctrl_data;
  596. atl1c_set_mac_type(hw);
  597. AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
  598. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  599. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  600. ATL1C_TXQ_MODE_ENHANCE;
  601. if (link_ctrl_data & LINK_CTRL_L0S_EN)
  602. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
  603. if (link_ctrl_data & LINK_CTRL_L1_EN)
  604. hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
  605. if (link_ctrl_data & LINK_CTRL_EXT_SYNC)
  606. hw->ctrl_flags |= ATL1C_LINK_EXT_SYNC;
  607. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  608. if (hw->nic_type == athr_l1c ||
  609. hw->nic_type == athr_l1d ||
  610. hw->nic_type == athr_l1d_2)
  611. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  612. return 0;
  613. }
  614. /*
  615. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  616. * @adapter: board private structure to initialize
  617. *
  618. * atl1c_sw_init initializes the Adapter private data structure.
  619. * Fields are initialized based on PCI device information and
  620. * OS network device settings (MTU size).
  621. */
  622. static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
  623. {
  624. struct atl1c_hw *hw = &adapter->hw;
  625. struct pci_dev *pdev = adapter->pdev;
  626. u32 revision;
  627. adapter->wol = 0;
  628. device_set_wakeup_enable(&pdev->dev, false);
  629. adapter->link_speed = SPEED_0;
  630. adapter->link_duplex = FULL_DUPLEX;
  631. adapter->tpd_ring[0].count = 1024;
  632. adapter->rfd_ring.count = 512;
  633. hw->vendor_id = pdev->vendor;
  634. hw->device_id = pdev->device;
  635. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  636. hw->subsystem_id = pdev->subsystem_device;
  637. AT_READ_REG(hw, PCI_CLASS_REVISION, &revision);
  638. hw->revision_id = revision & 0xFF;
  639. /* before link up, we assume hibernate is true */
  640. hw->hibernate = true;
  641. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  642. if (atl1c_setup_mac_funcs(hw) != 0) {
  643. dev_err(&pdev->dev, "set mac function pointers failed\n");
  644. return -1;
  645. }
  646. hw->intr_mask = IMR_NORMAL_MASK;
  647. hw->phy_configured = false;
  648. hw->preamble_len = 7;
  649. hw->max_frame_size = adapter->netdev->mtu;
  650. hw->autoneg_advertised = ADVERTISED_Autoneg;
  651. hw->indirect_tab = 0xE4E4E4E4;
  652. hw->base_cpu = 0;
  653. hw->ict = 50000; /* 100ms */
  654. hw->smb_timer = 200000; /* 400ms */
  655. hw->rx_imt = 200;
  656. hw->tx_imt = 1000;
  657. hw->tpd_burst = 5;
  658. hw->rfd_burst = 8;
  659. hw->dma_order = atl1c_dma_ord_out;
  660. hw->dmar_block = atl1c_dma_req_1024;
  661. if (atl1c_alloc_queues(adapter)) {
  662. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  663. return -ENOMEM;
  664. }
  665. /* TODO */
  666. atl1c_set_rxbufsize(adapter, adapter->netdev);
  667. atomic_set(&adapter->irq_sem, 1);
  668. spin_lock_init(&adapter->mdio_lock);
  669. spin_lock_init(&adapter->tx_lock);
  670. set_bit(__AT_DOWN, &adapter->flags);
  671. return 0;
  672. }
  673. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  674. struct atl1c_buffer *buffer_info, int in_irq)
  675. {
  676. u16 pci_driection;
  677. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  678. return;
  679. if (buffer_info->dma) {
  680. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  681. pci_driection = PCI_DMA_FROMDEVICE;
  682. else
  683. pci_driection = PCI_DMA_TODEVICE;
  684. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  685. pci_unmap_single(pdev, buffer_info->dma,
  686. buffer_info->length, pci_driection);
  687. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  688. pci_unmap_page(pdev, buffer_info->dma,
  689. buffer_info->length, pci_driection);
  690. }
  691. if (buffer_info->skb) {
  692. if (in_irq)
  693. dev_kfree_skb_irq(buffer_info->skb);
  694. else
  695. dev_kfree_skb(buffer_info->skb);
  696. }
  697. buffer_info->dma = 0;
  698. buffer_info->skb = NULL;
  699. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  700. }
  701. /*
  702. * atl1c_clean_tx_ring - Free Tx-skb
  703. * @adapter: board private structure
  704. */
  705. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  706. enum atl1c_trans_queue type)
  707. {
  708. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  709. struct atl1c_buffer *buffer_info;
  710. struct pci_dev *pdev = adapter->pdev;
  711. u16 index, ring_count;
  712. ring_count = tpd_ring->count;
  713. for (index = 0; index < ring_count; index++) {
  714. buffer_info = &tpd_ring->buffer_info[index];
  715. atl1c_clean_buffer(pdev, buffer_info, 0);
  716. }
  717. /* Zero out Tx-buffers */
  718. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  719. ring_count);
  720. atomic_set(&tpd_ring->next_to_clean, 0);
  721. tpd_ring->next_to_use = 0;
  722. }
  723. /*
  724. * atl1c_clean_rx_ring - Free rx-reservation skbs
  725. * @adapter: board private structure
  726. */
  727. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  728. {
  729. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  730. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  731. struct atl1c_buffer *buffer_info;
  732. struct pci_dev *pdev = adapter->pdev;
  733. int j;
  734. for (j = 0; j < rfd_ring->count; j++) {
  735. buffer_info = &rfd_ring->buffer_info[j];
  736. atl1c_clean_buffer(pdev, buffer_info, 0);
  737. }
  738. /* zero out the descriptor ring */
  739. memset(rfd_ring->desc, 0, rfd_ring->size);
  740. rfd_ring->next_to_clean = 0;
  741. rfd_ring->next_to_use = 0;
  742. rrd_ring->next_to_use = 0;
  743. rrd_ring->next_to_clean = 0;
  744. }
  745. /*
  746. * Read / Write Ptr Initialize:
  747. */
  748. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  749. {
  750. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  751. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  752. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  753. struct atl1c_buffer *buffer_info;
  754. int i, j;
  755. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  756. tpd_ring[i].next_to_use = 0;
  757. atomic_set(&tpd_ring[i].next_to_clean, 0);
  758. buffer_info = tpd_ring[i].buffer_info;
  759. for (j = 0; j < tpd_ring->count; j++)
  760. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  761. ATL1C_BUFFER_FREE);
  762. }
  763. rfd_ring->next_to_use = 0;
  764. rfd_ring->next_to_clean = 0;
  765. rrd_ring->next_to_use = 0;
  766. rrd_ring->next_to_clean = 0;
  767. for (j = 0; j < rfd_ring->count; j++) {
  768. buffer_info = &rfd_ring->buffer_info[j];
  769. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  770. }
  771. }
  772. /*
  773. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  774. * @adapter: board private structure
  775. *
  776. * Free all transmit software resources
  777. */
  778. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  779. {
  780. struct pci_dev *pdev = adapter->pdev;
  781. pci_free_consistent(pdev, adapter->ring_header.size,
  782. adapter->ring_header.desc,
  783. adapter->ring_header.dma);
  784. adapter->ring_header.desc = NULL;
  785. /* Note: just free tdp_ring.buffer_info,
  786. * it contain rfd_ring.buffer_info, do not double free */
  787. if (adapter->tpd_ring[0].buffer_info) {
  788. kfree(adapter->tpd_ring[0].buffer_info);
  789. adapter->tpd_ring[0].buffer_info = NULL;
  790. }
  791. }
  792. /*
  793. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  794. * @adapter: board private structure
  795. *
  796. * Return 0 on success, negative on failure
  797. */
  798. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  799. {
  800. struct pci_dev *pdev = adapter->pdev;
  801. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  802. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  803. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  804. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  805. int size;
  806. int i;
  807. int count = 0;
  808. int rx_desc_count = 0;
  809. u32 offset = 0;
  810. rrd_ring->count = rfd_ring->count;
  811. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  812. tpd_ring[i].count = tpd_ring[0].count;
  813. /* 2 tpd queue, one high priority queue,
  814. * another normal priority queue */
  815. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  816. rfd_ring->count);
  817. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  818. if (unlikely(!tpd_ring->buffer_info)) {
  819. dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
  820. size);
  821. goto err_nomem;
  822. }
  823. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  824. tpd_ring[i].buffer_info =
  825. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  826. count += tpd_ring[i].count;
  827. }
  828. rfd_ring->buffer_info =
  829. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  830. count += rfd_ring->count;
  831. rx_desc_count += rfd_ring->count;
  832. /*
  833. * real ring DMA buffer
  834. * each ring/block may need up to 8 bytes for alignment, hence the
  835. * additional bytes tacked onto the end.
  836. */
  837. ring_header->size = size =
  838. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  839. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  840. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  841. 8 * 4;
  842. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  843. &ring_header->dma);
  844. if (unlikely(!ring_header->desc)) {
  845. dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
  846. goto err_nomem;
  847. }
  848. memset(ring_header->desc, 0, ring_header->size);
  849. /* init TPD ring */
  850. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  851. offset = tpd_ring[0].dma - ring_header->dma;
  852. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  853. tpd_ring[i].dma = ring_header->dma + offset;
  854. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  855. tpd_ring[i].size =
  856. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  857. offset += roundup(tpd_ring[i].size, 8);
  858. }
  859. /* init RFD ring */
  860. rfd_ring->dma = ring_header->dma + offset;
  861. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  862. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  863. offset += roundup(rfd_ring->size, 8);
  864. /* init RRD ring */
  865. rrd_ring->dma = ring_header->dma + offset;
  866. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  867. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  868. rrd_ring->count;
  869. offset += roundup(rrd_ring->size, 8);
  870. return 0;
  871. err_nomem:
  872. kfree(tpd_ring->buffer_info);
  873. return -ENOMEM;
  874. }
  875. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  876. {
  877. struct atl1c_hw *hw = &adapter->hw;
  878. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  879. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  880. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  881. adapter->tpd_ring;
  882. u32 data;
  883. /* TPD */
  884. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  885. (u32)((tpd_ring[atl1c_trans_normal].dma &
  886. AT_DMA_HI_ADDR_MASK) >> 32));
  887. /* just enable normal priority TX queue */
  888. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  889. (u32)(tpd_ring[atl1c_trans_normal].dma &
  890. AT_DMA_LO_ADDR_MASK));
  891. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  892. (u32)(tpd_ring[atl1c_trans_high].dma &
  893. AT_DMA_LO_ADDR_MASK));
  894. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  895. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  896. /* RFD */
  897. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  898. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  899. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  900. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  901. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  902. rfd_ring->count & RFD_RING_SIZE_MASK);
  903. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  904. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  905. /* RRD */
  906. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  907. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  908. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  909. (rrd_ring->count & RRD_RING_SIZE_MASK));
  910. if (hw->nic_type == athr_l2c_b) {
  911. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  912. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  913. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  914. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  915. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  916. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  917. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  918. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  919. }
  920. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d_2) {
  921. /* Power Saving for L2c_B */
  922. AT_READ_REG(hw, REG_SERDES_LOCK, &data);
  923. data |= SERDES_MAC_CLK_SLOWDOWN;
  924. data |= SERDES_PYH_CLK_SLOWDOWN;
  925. AT_WRITE_REG(hw, REG_SERDES_LOCK, data);
  926. }
  927. /* Load all of base address above */
  928. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  929. }
  930. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  931. {
  932. struct atl1c_hw *hw = &adapter->hw;
  933. int max_pay_load;
  934. u16 tx_offload_thresh;
  935. u32 txq_ctrl_data;
  936. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  937. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  938. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  939. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  940. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  941. /*
  942. * if BIOS had changed the dam-read-max-length to an invalid value,
  943. * restore it to default value
  944. */
  945. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  946. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  947. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  948. }
  949. txq_ctrl_data =
  950. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  951. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  952. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  953. }
  954. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  955. {
  956. struct atl1c_hw *hw = &adapter->hw;
  957. u32 rxq_ctrl_data;
  958. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  959. RXQ_RFD_BURST_NUM_SHIFT;
  960. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  961. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  962. /* aspm for gigabit */
  963. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  964. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  965. ASPM_THRUPUT_LIMIT_100M);
  966. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  967. }
  968. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  969. {
  970. struct atl1c_hw *hw = &adapter->hw;
  971. u32 dma_ctrl_data;
  972. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  973. DMA_CTRL_RREQ_PRI_DATA |
  974. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  975. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  976. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  977. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  978. }
  979. /*
  980. * Stop the mac, transmit and receive units
  981. * hw - Struct containing variables accessed by shared code
  982. * return : 0 or idle status (if error)
  983. */
  984. static int atl1c_stop_mac(struct atl1c_hw *hw)
  985. {
  986. u32 data;
  987. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  988. data &= ~RXQ_CTRL_EN;
  989. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  990. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  991. data &= ~TXQ_CTRL_EN;
  992. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  993. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  994. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  995. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  996. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  997. return (int)atl1c_wait_until_idle(hw,
  998. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  999. }
  1000. static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
  1001. {
  1002. u32 data;
  1003. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1004. data |= RXQ_CTRL_EN;
  1005. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1006. }
  1007. static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
  1008. {
  1009. u32 data;
  1010. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1011. data |= TXQ_CTRL_EN;
  1012. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1013. }
  1014. /*
  1015. * Reset the transmit and receive units; mask and clear all interrupts.
  1016. * hw - Struct containing variables accessed by shared code
  1017. * return : 0 or idle status (if error)
  1018. */
  1019. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1020. {
  1021. struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
  1022. struct pci_dev *pdev = adapter->pdev;
  1023. u32 master_ctrl_data = 0;
  1024. AT_WRITE_REG(hw, REG_IMR, 0);
  1025. AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
  1026. atl1c_stop_mac(hw);
  1027. /*
  1028. * Issue Soft Reset to the MAC. This will reset the chip's
  1029. * transmit, receive, DMA. It will not effect
  1030. * the current PCI configuration. The global reset bit is self-
  1031. * clearing, and should clear within a microsecond.
  1032. */
  1033. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1034. master_ctrl_data |= MASTER_CTRL_OOB_DIS_OFF;
  1035. AT_WRITE_REGW(hw, REG_MASTER_CTRL, ((master_ctrl_data | MASTER_CTRL_SOFT_RST)
  1036. & 0xFFFF));
  1037. AT_WRITE_FLUSH(hw);
  1038. msleep(10);
  1039. /* Wait at least 10ms for All module to be Idle */
  1040. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1041. dev_err(&pdev->dev,
  1042. "MAC state machine can't be idle since"
  1043. " disabled for 10ms second\n");
  1044. return -1;
  1045. }
  1046. return 0;
  1047. }
  1048. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1049. {
  1050. u32 pm_ctrl_data;
  1051. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1052. pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
  1053. PM_CTRL_L1_ENTRY_TIMER_SHIFT);
  1054. pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
  1055. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1056. pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
  1057. pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK;
  1058. pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
  1059. pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
  1060. pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
  1061. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
  1062. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1063. }
  1064. /*
  1065. * Set ASPM state.
  1066. * Enable/disable L0s/L1 depend on link state.
  1067. */
  1068. static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
  1069. {
  1070. u32 pm_ctrl_data;
  1071. u32 link_ctrl_data;
  1072. u32 link_l1_timer = 0xF;
  1073. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1074. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  1075. pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
  1076. pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
  1077. PM_CTRL_L1_ENTRY_TIMER_SHIFT);
  1078. pm_ctrl_data &= ~(PM_CTRL_LCKDET_TIMER_MASK <<
  1079. PM_CTRL_LCKDET_TIMER_SHIFT);
  1080. pm_ctrl_data |= AT_LCKDET_TIMER << PM_CTRL_LCKDET_TIMER_SHIFT;
  1081. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1082. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1083. link_ctrl_data &= ~LINK_CTRL_EXT_SYNC;
  1084. if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE)) {
  1085. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10)
  1086. link_ctrl_data |= LINK_CTRL_EXT_SYNC;
  1087. }
  1088. AT_WRITE_REG(hw, REG_LINK_CTRL, link_ctrl_data);
  1089. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER;
  1090. pm_ctrl_data &= ~(PM_CTRL_PM_REQ_TIMER_MASK <<
  1091. PM_CTRL_PM_REQ_TIMER_SHIFT);
  1092. pm_ctrl_data |= AT_ASPM_L1_TIMER <<
  1093. PM_CTRL_PM_REQ_TIMER_SHIFT;
  1094. pm_ctrl_data &= ~PM_CTRL_SA_DLY_EN;
  1095. pm_ctrl_data &= ~PM_CTRL_HOTRST;
  1096. pm_ctrl_data |= 1 << PM_CTRL_L1_ENTRY_TIMER_SHIFT;
  1097. pm_ctrl_data |= PM_CTRL_SERDES_PD_EX_L1;
  1098. }
  1099. pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
  1100. if (linkup) {
  1101. pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
  1102. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1103. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1104. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
  1105. if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
  1106. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
  1107. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1108. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1109. if (hw->nic_type == athr_l2c_b)
  1110. if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE))
  1111. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1112. pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
  1113. pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
  1114. pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
  1115. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1116. if (hw->adapter->link_speed == SPEED_100 ||
  1117. hw->adapter->link_speed == SPEED_1000) {
  1118. pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
  1119. PM_CTRL_L1_ENTRY_TIMER_SHIFT);
  1120. if (hw->nic_type == athr_l2c_b)
  1121. link_l1_timer = 7;
  1122. else if (hw->nic_type == athr_l2c_b2 ||
  1123. hw->nic_type == athr_l1d_2)
  1124. link_l1_timer = 4;
  1125. pm_ctrl_data |= link_l1_timer <<
  1126. PM_CTRL_L1_ENTRY_TIMER_SHIFT;
  1127. }
  1128. } else {
  1129. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
  1130. pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
  1131. pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
  1132. pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
  1133. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1134. pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
  1135. }
  1136. } else {
  1137. pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
  1138. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1139. pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
  1140. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1141. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1142. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
  1143. else
  1144. pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
  1145. }
  1146. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1147. return;
  1148. }
  1149. static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
  1150. {
  1151. struct atl1c_hw *hw = &adapter->hw;
  1152. struct net_device *netdev = adapter->netdev;
  1153. u32 mac_ctrl_data;
  1154. mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
  1155. mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
  1156. if (adapter->link_duplex == FULL_DUPLEX) {
  1157. hw->mac_duplex = true;
  1158. mac_ctrl_data |= MAC_CTRL_DUPLX;
  1159. }
  1160. if (adapter->link_speed == SPEED_1000)
  1161. hw->mac_speed = atl1c_mac_speed_1000;
  1162. else
  1163. hw->mac_speed = atl1c_mac_speed_10_100;
  1164. mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
  1165. MAC_CTRL_SPEED_SHIFT;
  1166. mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
  1167. mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
  1168. MAC_CTRL_PRMLEN_SHIFT);
  1169. __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
  1170. mac_ctrl_data |= MAC_CTRL_BC_EN;
  1171. if (netdev->flags & IFF_PROMISC)
  1172. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  1173. if (netdev->flags & IFF_ALLMULTI)
  1174. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  1175. mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
  1176. if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2 ||
  1177. hw->nic_type == athr_l1d_2) {
  1178. mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
  1179. mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
  1180. }
  1181. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  1182. }
  1183. /*
  1184. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1185. * @adapter: board private structure
  1186. *
  1187. * Configure the Tx /Rx unit of the MAC after a reset.
  1188. */
  1189. static int atl1c_configure(struct atl1c_adapter *adapter)
  1190. {
  1191. struct atl1c_hw *hw = &adapter->hw;
  1192. u32 master_ctrl_data = 0;
  1193. u32 intr_modrt_data;
  1194. u32 data;
  1195. /* clear interrupt status */
  1196. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1197. /* Clear any WOL status */
  1198. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1199. /* set Interrupt Clear Timer
  1200. * HW will enable self to assert interrupt event to system after
  1201. * waiting x-time for software to notify it accept interrupt.
  1202. */
  1203. data = CLK_GATING_EN_ALL;
  1204. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1205. if (hw->nic_type == athr_l2c_b)
  1206. data &= ~CLK_GATING_RXMAC_EN;
  1207. } else
  1208. data = 0;
  1209. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1210. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1211. hw->ict & INT_RETRIG_TIMER_MASK);
  1212. atl1c_configure_des_ring(adapter);
  1213. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1214. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1215. IRQ_MODRT_TX_TIMER_SHIFT;
  1216. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1217. IRQ_MODRT_RX_TIMER_SHIFT;
  1218. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1219. master_ctrl_data |=
  1220. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1221. }
  1222. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1223. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1224. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1225. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1226. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1227. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1228. /* set MTU */
  1229. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1230. VLAN_HLEN + ETH_FCS_LEN);
  1231. atl1c_configure_tx(adapter);
  1232. atl1c_configure_rx(adapter);
  1233. atl1c_configure_dma(adapter);
  1234. return 0;
  1235. }
  1236. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1237. {
  1238. u16 hw_reg_addr = 0;
  1239. unsigned long *stats_item = NULL;
  1240. u32 data;
  1241. /* update rx status */
  1242. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1243. stats_item = &adapter->hw_stats.rx_ok;
  1244. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1245. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1246. *stats_item += data;
  1247. stats_item++;
  1248. hw_reg_addr += 4;
  1249. }
  1250. /* update tx status */
  1251. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1252. stats_item = &adapter->hw_stats.tx_ok;
  1253. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1254. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1255. *stats_item += data;
  1256. stats_item++;
  1257. hw_reg_addr += 4;
  1258. }
  1259. }
  1260. /*
  1261. * atl1c_get_stats - Get System Network Statistics
  1262. * @netdev: network interface device structure
  1263. *
  1264. * Returns the address of the device statistics structure.
  1265. * The statistics are actually updated from the timer callback.
  1266. */
  1267. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1268. {
  1269. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1270. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1271. struct net_device_stats *net_stats = &netdev->stats;
  1272. atl1c_update_hw_stats(adapter);
  1273. net_stats->rx_packets = hw_stats->rx_ok;
  1274. net_stats->tx_packets = hw_stats->tx_ok;
  1275. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1276. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1277. net_stats->multicast = hw_stats->rx_mcast;
  1278. net_stats->collisions = hw_stats->tx_1_col +
  1279. hw_stats->tx_2_col * 2 +
  1280. hw_stats->tx_late_col + hw_stats->tx_abort_col;
  1281. net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
  1282. hw_stats->rx_len_err + hw_stats->rx_sz_ov +
  1283. hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
  1284. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1285. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1286. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1287. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1288. net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1289. net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1290. net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
  1291. hw_stats->tx_underrun + hw_stats->tx_trunc;
  1292. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1293. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1294. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1295. return net_stats;
  1296. }
  1297. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1298. {
  1299. u16 phy_data;
  1300. spin_lock(&adapter->mdio_lock);
  1301. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1302. spin_unlock(&adapter->mdio_lock);
  1303. }
  1304. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1305. enum atl1c_trans_queue type)
  1306. {
  1307. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  1308. &adapter->tpd_ring[type];
  1309. struct atl1c_buffer *buffer_info;
  1310. struct pci_dev *pdev = adapter->pdev;
  1311. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1312. u16 hw_next_to_clean;
  1313. u16 reg;
  1314. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1315. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1316. while (next_to_clean != hw_next_to_clean) {
  1317. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1318. atl1c_clean_buffer(pdev, buffer_info, 1);
  1319. if (++next_to_clean == tpd_ring->count)
  1320. next_to_clean = 0;
  1321. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1322. }
  1323. if (netif_queue_stopped(adapter->netdev) &&
  1324. netif_carrier_ok(adapter->netdev)) {
  1325. netif_wake_queue(adapter->netdev);
  1326. }
  1327. return true;
  1328. }
  1329. /*
  1330. * atl1c_intr - Interrupt Handler
  1331. * @irq: interrupt number
  1332. * @data: pointer to a network interface device structure
  1333. * @pt_regs: CPU registers structure
  1334. */
  1335. static irqreturn_t atl1c_intr(int irq, void *data)
  1336. {
  1337. struct net_device *netdev = data;
  1338. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1339. struct pci_dev *pdev = adapter->pdev;
  1340. struct atl1c_hw *hw = &adapter->hw;
  1341. int max_ints = AT_MAX_INT_WORK;
  1342. int handled = IRQ_NONE;
  1343. u32 status;
  1344. u32 reg_data;
  1345. do {
  1346. AT_READ_REG(hw, REG_ISR, &reg_data);
  1347. status = reg_data & hw->intr_mask;
  1348. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1349. if (max_ints != AT_MAX_INT_WORK)
  1350. handled = IRQ_HANDLED;
  1351. break;
  1352. }
  1353. /* link event */
  1354. if (status & ISR_GPHY)
  1355. atl1c_clear_phy_int(adapter);
  1356. /* Ack ISR */
  1357. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1358. if (status & ISR_RX_PKT) {
  1359. if (likely(napi_schedule_prep(&adapter->napi))) {
  1360. hw->intr_mask &= ~ISR_RX_PKT;
  1361. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1362. __napi_schedule(&adapter->napi);
  1363. }
  1364. }
  1365. if (status & ISR_TX_PKT)
  1366. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1367. handled = IRQ_HANDLED;
  1368. /* check if PCIE PHY Link down */
  1369. if (status & ISR_ERROR) {
  1370. if (netif_msg_hw(adapter))
  1371. dev_err(&pdev->dev,
  1372. "atl1c hardware error (status = 0x%x)\n",
  1373. status & ISR_ERROR);
  1374. /* reset MAC */
  1375. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1376. schedule_work(&adapter->common_task);
  1377. return IRQ_HANDLED;
  1378. }
  1379. if (status & ISR_OVER)
  1380. if (netif_msg_intr(adapter))
  1381. dev_warn(&pdev->dev,
  1382. "TX/RX overflow (status = 0x%x)\n",
  1383. status & ISR_OVER);
  1384. /* link event */
  1385. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1386. netdev->stats.tx_carrier_errors++;
  1387. atl1c_link_chg_event(adapter);
  1388. break;
  1389. }
  1390. } while (--max_ints > 0);
  1391. /* re-enable Interrupt*/
  1392. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1393. return handled;
  1394. }
  1395. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1396. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1397. {
  1398. /*
  1399. * The pid field in RRS in not correct sometimes, so we
  1400. * cannot figure out if the packet is fragmented or not,
  1401. * so we tell the KERNEL CHECKSUM_NONE
  1402. */
  1403. skb_checksum_none_assert(skb);
  1404. }
  1405. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1406. {
  1407. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1408. struct pci_dev *pdev = adapter->pdev;
  1409. struct atl1c_buffer *buffer_info, *next_info;
  1410. struct sk_buff *skb;
  1411. void *vir_addr = NULL;
  1412. u16 num_alloc = 0;
  1413. u16 rfd_next_to_use, next_next;
  1414. struct atl1c_rx_free_desc *rfd_desc;
  1415. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1416. if (++next_next == rfd_ring->count)
  1417. next_next = 0;
  1418. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1419. next_info = &rfd_ring->buffer_info[next_next];
  1420. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1421. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1422. skb = netdev_alloc_skb(adapter->netdev, adapter->rx_buffer_len);
  1423. if (unlikely(!skb)) {
  1424. if (netif_msg_rx_err(adapter))
  1425. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1426. break;
  1427. }
  1428. /*
  1429. * Make buffer alignment 2 beyond a 16 byte boundary
  1430. * this will result in a 16 byte aligned IP header after
  1431. * the 14 byte MAC header is removed
  1432. */
  1433. vir_addr = skb->data;
  1434. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1435. buffer_info->skb = skb;
  1436. buffer_info->length = adapter->rx_buffer_len;
  1437. buffer_info->dma = pci_map_single(pdev, vir_addr,
  1438. buffer_info->length,
  1439. PCI_DMA_FROMDEVICE);
  1440. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1441. ATL1C_PCIMAP_FROMDEVICE);
  1442. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1443. rfd_next_to_use = next_next;
  1444. if (++next_next == rfd_ring->count)
  1445. next_next = 0;
  1446. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1447. next_info = &rfd_ring->buffer_info[next_next];
  1448. num_alloc++;
  1449. }
  1450. if (num_alloc) {
  1451. /* TODO: update mailbox here */
  1452. wmb();
  1453. rfd_ring->next_to_use = rfd_next_to_use;
  1454. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1455. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1456. }
  1457. return num_alloc;
  1458. }
  1459. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1460. struct atl1c_recv_ret_status *rrs, u16 num)
  1461. {
  1462. u16 i;
  1463. /* the relationship between rrd and rfd is one map one */
  1464. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1465. rrd_ring->next_to_clean)) {
  1466. rrs->word3 &= ~RRS_RXD_UPDATED;
  1467. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1468. rrd_ring->next_to_clean = 0;
  1469. }
  1470. }
  1471. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1472. struct atl1c_recv_ret_status *rrs, u16 num)
  1473. {
  1474. u16 i;
  1475. u16 rfd_index;
  1476. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1477. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1478. RRS_RX_RFD_INDEX_MASK;
  1479. for (i = 0; i < num; i++) {
  1480. buffer_info[rfd_index].skb = NULL;
  1481. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1482. ATL1C_BUFFER_FREE);
  1483. if (++rfd_index == rfd_ring->count)
  1484. rfd_index = 0;
  1485. }
  1486. rfd_ring->next_to_clean = rfd_index;
  1487. }
  1488. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1489. int *work_done, int work_to_do)
  1490. {
  1491. u16 rfd_num, rfd_index;
  1492. u16 count = 0;
  1493. u16 length;
  1494. struct pci_dev *pdev = adapter->pdev;
  1495. struct net_device *netdev = adapter->netdev;
  1496. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1497. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1498. struct sk_buff *skb;
  1499. struct atl1c_recv_ret_status *rrs;
  1500. struct atl1c_buffer *buffer_info;
  1501. while (1) {
  1502. if (*work_done >= work_to_do)
  1503. break;
  1504. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1505. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1506. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1507. RRS_RX_RFD_CNT_MASK;
  1508. if (unlikely(rfd_num != 1))
  1509. /* TODO support mul rfd*/
  1510. if (netif_msg_rx_err(adapter))
  1511. dev_warn(&pdev->dev,
  1512. "Multi rfd not support yet!\n");
  1513. goto rrs_checked;
  1514. } else {
  1515. break;
  1516. }
  1517. rrs_checked:
  1518. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1519. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1520. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1521. if (netif_msg_rx_err(adapter))
  1522. dev_warn(&pdev->dev,
  1523. "wrong packet! rrs word3 is %x\n",
  1524. rrs->word3);
  1525. continue;
  1526. }
  1527. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1528. RRS_PKT_SIZE_MASK);
  1529. /* Good Receive */
  1530. if (likely(rfd_num == 1)) {
  1531. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1532. RRS_RX_RFD_INDEX_MASK;
  1533. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1534. pci_unmap_single(pdev, buffer_info->dma,
  1535. buffer_info->length, PCI_DMA_FROMDEVICE);
  1536. skb = buffer_info->skb;
  1537. } else {
  1538. /* TODO */
  1539. if (netif_msg_rx_err(adapter))
  1540. dev_warn(&pdev->dev,
  1541. "Multi rfd not support yet!\n");
  1542. break;
  1543. }
  1544. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1545. skb_put(skb, length - ETH_FCS_LEN);
  1546. skb->protocol = eth_type_trans(skb, netdev);
  1547. atl1c_rx_checksum(adapter, skb, rrs);
  1548. if (rrs->word3 & RRS_VLAN_INS) {
  1549. u16 vlan;
  1550. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1551. vlan = le16_to_cpu(vlan);
  1552. __vlan_hwaccel_put_tag(skb, vlan);
  1553. }
  1554. netif_receive_skb(skb);
  1555. (*work_done)++;
  1556. count++;
  1557. }
  1558. if (count)
  1559. atl1c_alloc_rx_buffer(adapter);
  1560. }
  1561. /*
  1562. * atl1c_clean - NAPI Rx polling callback
  1563. * @adapter: board private structure
  1564. */
  1565. static int atl1c_clean(struct napi_struct *napi, int budget)
  1566. {
  1567. struct atl1c_adapter *adapter =
  1568. container_of(napi, struct atl1c_adapter, napi);
  1569. int work_done = 0;
  1570. /* Keep link state information with original netdev */
  1571. if (!netif_carrier_ok(adapter->netdev))
  1572. goto quit_polling;
  1573. /* just enable one RXQ */
  1574. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1575. if (work_done < budget) {
  1576. quit_polling:
  1577. napi_complete(napi);
  1578. adapter->hw.intr_mask |= ISR_RX_PKT;
  1579. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1580. }
  1581. return work_done;
  1582. }
  1583. #ifdef CONFIG_NET_POLL_CONTROLLER
  1584. /*
  1585. * Polling 'interrupt' - used by things like netconsole to send skbs
  1586. * without having to re-enable interrupts. It's not called while
  1587. * the interrupt routine is executing.
  1588. */
  1589. static void atl1c_netpoll(struct net_device *netdev)
  1590. {
  1591. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1592. disable_irq(adapter->pdev->irq);
  1593. atl1c_intr(adapter->pdev->irq, netdev);
  1594. enable_irq(adapter->pdev->irq);
  1595. }
  1596. #endif
  1597. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1598. {
  1599. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1600. u16 next_to_use = 0;
  1601. u16 next_to_clean = 0;
  1602. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1603. next_to_use = tpd_ring->next_to_use;
  1604. return (u16)(next_to_clean > next_to_use) ?
  1605. (next_to_clean - next_to_use - 1) :
  1606. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1607. }
  1608. /*
  1609. * get next usable tpd
  1610. * Note: should call atl1c_tdp_avail to make sure
  1611. * there is enough tpd to use
  1612. */
  1613. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1614. enum atl1c_trans_queue type)
  1615. {
  1616. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1617. struct atl1c_tpd_desc *tpd_desc;
  1618. u16 next_to_use = 0;
  1619. next_to_use = tpd_ring->next_to_use;
  1620. if (++tpd_ring->next_to_use == tpd_ring->count)
  1621. tpd_ring->next_to_use = 0;
  1622. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1623. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1624. return tpd_desc;
  1625. }
  1626. static struct atl1c_buffer *
  1627. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1628. {
  1629. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1630. return &tpd_ring->buffer_info[tpd -
  1631. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1632. }
  1633. /* Calculate the transmit packet descript needed*/
  1634. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1635. {
  1636. u16 tpd_req;
  1637. u16 proto_hdr_len = 0;
  1638. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1639. if (skb_is_gso(skb)) {
  1640. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1641. if (proto_hdr_len < skb_headlen(skb))
  1642. tpd_req++;
  1643. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1644. tpd_req++;
  1645. }
  1646. return tpd_req;
  1647. }
  1648. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1649. struct sk_buff *skb,
  1650. struct atl1c_tpd_desc **tpd,
  1651. enum atl1c_trans_queue type)
  1652. {
  1653. struct pci_dev *pdev = adapter->pdev;
  1654. u8 hdr_len;
  1655. u32 real_len;
  1656. unsigned short offload_type;
  1657. int err;
  1658. if (skb_is_gso(skb)) {
  1659. if (skb_header_cloned(skb)) {
  1660. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1661. if (unlikely(err))
  1662. return -1;
  1663. }
  1664. offload_type = skb_shinfo(skb)->gso_type;
  1665. if (offload_type & SKB_GSO_TCPV4) {
  1666. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1667. + ntohs(ip_hdr(skb)->tot_len));
  1668. if (real_len < skb->len)
  1669. pskb_trim(skb, real_len);
  1670. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1671. if (unlikely(skb->len == hdr_len)) {
  1672. /* only xsum need */
  1673. if (netif_msg_tx_queued(adapter))
  1674. dev_warn(&pdev->dev,
  1675. "IPV4 tso with zero data??\n");
  1676. goto check_sum;
  1677. } else {
  1678. ip_hdr(skb)->check = 0;
  1679. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1680. ip_hdr(skb)->saddr,
  1681. ip_hdr(skb)->daddr,
  1682. 0, IPPROTO_TCP, 0);
  1683. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1684. }
  1685. }
  1686. if (offload_type & SKB_GSO_TCPV6) {
  1687. struct atl1c_tpd_ext_desc *etpd =
  1688. *(struct atl1c_tpd_ext_desc **)(tpd);
  1689. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1690. *tpd = atl1c_get_tpd(adapter, type);
  1691. ipv6_hdr(skb)->payload_len = 0;
  1692. /* check payload == 0 byte ? */
  1693. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1694. if (unlikely(skb->len == hdr_len)) {
  1695. /* only xsum need */
  1696. if (netif_msg_tx_queued(adapter))
  1697. dev_warn(&pdev->dev,
  1698. "IPV6 tso with zero data??\n");
  1699. goto check_sum;
  1700. } else
  1701. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1702. &ipv6_hdr(skb)->saddr,
  1703. &ipv6_hdr(skb)->daddr,
  1704. 0, IPPROTO_TCP, 0);
  1705. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1706. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1707. etpd->pkt_len = cpu_to_le32(skb->len);
  1708. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1709. }
  1710. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1711. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1712. TPD_TCPHDR_OFFSET_SHIFT;
  1713. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1714. TPD_MSS_SHIFT;
  1715. return 0;
  1716. }
  1717. check_sum:
  1718. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1719. u8 css, cso;
  1720. cso = skb_checksum_start_offset(skb);
  1721. if (unlikely(cso & 0x1)) {
  1722. if (netif_msg_tx_err(adapter))
  1723. dev_err(&adapter->pdev->dev,
  1724. "payload offset should not an event number\n");
  1725. return -1;
  1726. } else {
  1727. css = cso + skb->csum_offset;
  1728. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1729. TPD_PLOADOFFSET_SHIFT;
  1730. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1731. TPD_CCSUM_OFFSET_SHIFT;
  1732. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1733. }
  1734. }
  1735. return 0;
  1736. }
  1737. static void atl1c_tx_map(struct atl1c_adapter *adapter,
  1738. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1739. enum atl1c_trans_queue type)
  1740. {
  1741. struct atl1c_tpd_desc *use_tpd = NULL;
  1742. struct atl1c_buffer *buffer_info = NULL;
  1743. u16 buf_len = skb_headlen(skb);
  1744. u16 map_len = 0;
  1745. u16 mapped_len = 0;
  1746. u16 hdr_len = 0;
  1747. u16 nr_frags;
  1748. u16 f;
  1749. int tso;
  1750. nr_frags = skb_shinfo(skb)->nr_frags;
  1751. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1752. if (tso) {
  1753. /* TSO */
  1754. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1755. use_tpd = tpd;
  1756. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1757. buffer_info->length = map_len;
  1758. buffer_info->dma = pci_map_single(adapter->pdev,
  1759. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1760. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1761. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1762. ATL1C_PCIMAP_TODEVICE);
  1763. mapped_len += map_len;
  1764. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1765. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1766. }
  1767. if (mapped_len < buf_len) {
  1768. /* mapped_len == 0, means we should use the first tpd,
  1769. which is given by caller */
  1770. if (mapped_len == 0)
  1771. use_tpd = tpd;
  1772. else {
  1773. use_tpd = atl1c_get_tpd(adapter, type);
  1774. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1775. }
  1776. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1777. buffer_info->length = buf_len - mapped_len;
  1778. buffer_info->dma =
  1779. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1780. buffer_info->length, PCI_DMA_TODEVICE);
  1781. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1782. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1783. ATL1C_PCIMAP_TODEVICE);
  1784. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1785. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1786. }
  1787. for (f = 0; f < nr_frags; f++) {
  1788. struct skb_frag_struct *frag;
  1789. frag = &skb_shinfo(skb)->frags[f];
  1790. use_tpd = atl1c_get_tpd(adapter, type);
  1791. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1792. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1793. buffer_info->length = skb_frag_size(frag);
  1794. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1795. frag, 0,
  1796. buffer_info->length,
  1797. DMA_TO_DEVICE);
  1798. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1799. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1800. ATL1C_PCIMAP_TODEVICE);
  1801. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1802. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1803. }
  1804. /* The last tpd */
  1805. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1806. /* The last buffer info contain the skb address,
  1807. so it will be free after unmap */
  1808. buffer_info->skb = skb;
  1809. }
  1810. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1811. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1812. {
  1813. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1814. u16 reg;
  1815. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1816. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1817. }
  1818. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1819. struct net_device *netdev)
  1820. {
  1821. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1822. unsigned long flags;
  1823. u16 tpd_req = 1;
  1824. struct atl1c_tpd_desc *tpd;
  1825. enum atl1c_trans_queue type = atl1c_trans_normal;
  1826. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1827. dev_kfree_skb_any(skb);
  1828. return NETDEV_TX_OK;
  1829. }
  1830. tpd_req = atl1c_cal_tpd_req(skb);
  1831. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1832. if (netif_msg_pktdata(adapter))
  1833. dev_info(&adapter->pdev->dev, "tx locked\n");
  1834. return NETDEV_TX_LOCKED;
  1835. }
  1836. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1837. /* no enough descriptor, just stop queue */
  1838. netif_stop_queue(netdev);
  1839. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1840. return NETDEV_TX_BUSY;
  1841. }
  1842. tpd = atl1c_get_tpd(adapter, type);
  1843. /* do TSO and check sum */
  1844. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1845. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1846. dev_kfree_skb_any(skb);
  1847. return NETDEV_TX_OK;
  1848. }
  1849. if (unlikely(vlan_tx_tag_present(skb))) {
  1850. u16 vlan = vlan_tx_tag_get(skb);
  1851. __le16 tag;
  1852. vlan = cpu_to_le16(vlan);
  1853. AT_VLAN_TO_TAG(vlan, tag);
  1854. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1855. tpd->vlan_tag = tag;
  1856. }
  1857. if (skb_network_offset(skb) != ETH_HLEN)
  1858. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1859. atl1c_tx_map(adapter, skb, tpd, type);
  1860. atl1c_tx_queue(adapter, skb, tpd, type);
  1861. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1862. return NETDEV_TX_OK;
  1863. }
  1864. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1865. {
  1866. struct net_device *netdev = adapter->netdev;
  1867. free_irq(adapter->pdev->irq, netdev);
  1868. if (adapter->have_msi)
  1869. pci_disable_msi(adapter->pdev);
  1870. }
  1871. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1872. {
  1873. struct pci_dev *pdev = adapter->pdev;
  1874. struct net_device *netdev = adapter->netdev;
  1875. int flags = 0;
  1876. int err = 0;
  1877. adapter->have_msi = true;
  1878. err = pci_enable_msi(adapter->pdev);
  1879. if (err) {
  1880. if (netif_msg_ifup(adapter))
  1881. dev_err(&pdev->dev,
  1882. "Unable to allocate MSI interrupt Error: %d\n",
  1883. err);
  1884. adapter->have_msi = false;
  1885. }
  1886. if (!adapter->have_msi)
  1887. flags |= IRQF_SHARED;
  1888. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  1889. netdev->name, netdev);
  1890. if (err) {
  1891. if (netif_msg_ifup(adapter))
  1892. dev_err(&pdev->dev,
  1893. "Unable to allocate interrupt Error: %d\n",
  1894. err);
  1895. if (adapter->have_msi)
  1896. pci_disable_msi(adapter->pdev);
  1897. return err;
  1898. }
  1899. if (netif_msg_ifup(adapter))
  1900. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  1901. return err;
  1902. }
  1903. static int atl1c_up(struct atl1c_adapter *adapter)
  1904. {
  1905. struct net_device *netdev = adapter->netdev;
  1906. int num;
  1907. int err;
  1908. netif_carrier_off(netdev);
  1909. atl1c_init_ring_ptrs(adapter);
  1910. atl1c_set_multi(netdev);
  1911. atl1c_restore_vlan(adapter);
  1912. num = atl1c_alloc_rx_buffer(adapter);
  1913. if (unlikely(num == 0)) {
  1914. err = -ENOMEM;
  1915. goto err_alloc_rx;
  1916. }
  1917. if (atl1c_configure(adapter)) {
  1918. err = -EIO;
  1919. goto err_up;
  1920. }
  1921. err = atl1c_request_irq(adapter);
  1922. if (unlikely(err))
  1923. goto err_up;
  1924. clear_bit(__AT_DOWN, &adapter->flags);
  1925. napi_enable(&adapter->napi);
  1926. atl1c_irq_enable(adapter);
  1927. atl1c_check_link_status(adapter);
  1928. netif_start_queue(netdev);
  1929. return err;
  1930. err_up:
  1931. err_alloc_rx:
  1932. atl1c_clean_rx_ring(adapter);
  1933. return err;
  1934. }
  1935. static void atl1c_down(struct atl1c_adapter *adapter)
  1936. {
  1937. struct net_device *netdev = adapter->netdev;
  1938. atl1c_del_timer(adapter);
  1939. adapter->work_event = 0; /* clear all event */
  1940. /* signal that we're down so the interrupt handler does not
  1941. * reschedule our watchdog timer */
  1942. set_bit(__AT_DOWN, &adapter->flags);
  1943. netif_carrier_off(netdev);
  1944. napi_disable(&adapter->napi);
  1945. atl1c_irq_disable(adapter);
  1946. atl1c_free_irq(adapter);
  1947. /* reset MAC to disable all RX/TX */
  1948. atl1c_reset_mac(&adapter->hw);
  1949. msleep(1);
  1950. adapter->link_speed = SPEED_0;
  1951. adapter->link_duplex = -1;
  1952. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  1953. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  1954. atl1c_clean_rx_ring(adapter);
  1955. }
  1956. /*
  1957. * atl1c_open - Called when a network interface is made active
  1958. * @netdev: network interface device structure
  1959. *
  1960. * Returns 0 on success, negative value on failure
  1961. *
  1962. * The open entry point is called when a network interface is made
  1963. * active by the system (IFF_UP). At this point all resources needed
  1964. * for transmit and receive operations are allocated, the interrupt
  1965. * handler is registered with the OS, the watchdog timer is started,
  1966. * and the stack is notified that the interface is ready.
  1967. */
  1968. static int atl1c_open(struct net_device *netdev)
  1969. {
  1970. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1971. int err;
  1972. /* disallow open during test */
  1973. if (test_bit(__AT_TESTING, &adapter->flags))
  1974. return -EBUSY;
  1975. /* allocate rx/tx dma buffer & descriptors */
  1976. err = atl1c_setup_ring_resources(adapter);
  1977. if (unlikely(err))
  1978. return err;
  1979. err = atl1c_up(adapter);
  1980. if (unlikely(err))
  1981. goto err_up;
  1982. if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
  1983. u32 phy_data;
  1984. AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
  1985. phy_data |= MDIO_AP_EN;
  1986. AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
  1987. }
  1988. return 0;
  1989. err_up:
  1990. atl1c_free_irq(adapter);
  1991. atl1c_free_ring_resources(adapter);
  1992. atl1c_reset_mac(&adapter->hw);
  1993. return err;
  1994. }
  1995. /*
  1996. * atl1c_close - Disables a network interface
  1997. * @netdev: network interface device structure
  1998. *
  1999. * Returns 0, this is not allowed to fail
  2000. *
  2001. * The close entry point is called when an interface is de-activated
  2002. * by the OS. The hardware is still under the drivers control, but
  2003. * needs to be disabled. A global MAC reset is issued to stop the
  2004. * hardware, and all transmit and receive resources are freed.
  2005. */
  2006. static int atl1c_close(struct net_device *netdev)
  2007. {
  2008. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2009. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2010. atl1c_down(adapter);
  2011. atl1c_free_ring_resources(adapter);
  2012. return 0;
  2013. }
  2014. static int atl1c_suspend(struct device *dev)
  2015. {
  2016. struct pci_dev *pdev = to_pci_dev(dev);
  2017. struct net_device *netdev = pci_get_drvdata(pdev);
  2018. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2019. struct atl1c_hw *hw = &adapter->hw;
  2020. u32 mac_ctrl_data = 0;
  2021. u32 master_ctrl_data = 0;
  2022. u32 wol_ctrl_data = 0;
  2023. u16 mii_intr_status_data = 0;
  2024. u32 wufc = adapter->wol;
  2025. atl1c_disable_l0s_l1(hw);
  2026. if (netif_running(netdev)) {
  2027. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2028. atl1c_down(adapter);
  2029. }
  2030. netif_device_detach(netdev);
  2031. if (wufc)
  2032. if (atl1c_phy_power_saving(hw) != 0)
  2033. dev_dbg(&pdev->dev, "phy power saving failed");
  2034. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  2035. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  2036. master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  2037. mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
  2038. mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
  2039. MAC_CTRL_PRMLEN_MASK) <<
  2040. MAC_CTRL_PRMLEN_SHIFT);
  2041. mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
  2042. mac_ctrl_data &= ~MAC_CTRL_DUPLX;
  2043. if (wufc) {
  2044. mac_ctrl_data |= MAC_CTRL_RX_EN;
  2045. if (adapter->link_speed == SPEED_1000 ||
  2046. adapter->link_speed == SPEED_0) {
  2047. mac_ctrl_data |= atl1c_mac_speed_1000 <<
  2048. MAC_CTRL_SPEED_SHIFT;
  2049. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2050. } else
  2051. mac_ctrl_data |= atl1c_mac_speed_10_100 <<
  2052. MAC_CTRL_SPEED_SHIFT;
  2053. if (adapter->link_duplex == DUPLEX_FULL)
  2054. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2055. /* turn on magic packet wol */
  2056. if (wufc & AT_WUFC_MAG)
  2057. wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
  2058. if (wufc & AT_WUFC_LNKC) {
  2059. wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
  2060. /* only link up can wake up */
  2061. if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
  2062. dev_dbg(&pdev->dev, "%s: read write phy "
  2063. "register failed.\n",
  2064. atl1c_driver_name);
  2065. }
  2066. }
  2067. /* clear phy interrupt */
  2068. atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
  2069. /* Config MAC Ctrl register */
  2070. __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
  2071. /* magic packet maybe Broadcast&multicast&Unicast frame */
  2072. if (wufc & AT_WUFC_MAG)
  2073. mac_ctrl_data |= MAC_CTRL_BC_EN;
  2074. dev_dbg(&pdev->dev,
  2075. "%s: suspend MAC=0x%x\n",
  2076. atl1c_driver_name, mac_ctrl_data);
  2077. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  2078. AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
  2079. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  2080. AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
  2081. GPHY_CTRL_EXT_RESET);
  2082. } else {
  2083. AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
  2084. master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
  2085. mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
  2086. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2087. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  2088. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  2089. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  2090. hw->phy_configured = false; /* re-init PHY when resume */
  2091. }
  2092. return 0;
  2093. }
  2094. #ifdef CONFIG_PM_SLEEP
  2095. static int atl1c_resume(struct device *dev)
  2096. {
  2097. struct pci_dev *pdev = to_pci_dev(dev);
  2098. struct net_device *netdev = pci_get_drvdata(pdev);
  2099. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2100. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2101. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
  2102. ATL1C_PCIE_PHY_RESET);
  2103. atl1c_phy_reset(&adapter->hw);
  2104. atl1c_reset_mac(&adapter->hw);
  2105. atl1c_phy_init(&adapter->hw);
  2106. #if 0
  2107. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2108. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2109. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2110. #endif
  2111. netif_device_attach(netdev);
  2112. if (netif_running(netdev))
  2113. atl1c_up(adapter);
  2114. return 0;
  2115. }
  2116. #endif
  2117. static void atl1c_shutdown(struct pci_dev *pdev)
  2118. {
  2119. struct net_device *netdev = pci_get_drvdata(pdev);
  2120. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2121. atl1c_suspend(&pdev->dev);
  2122. pci_wake_from_d3(pdev, adapter->wol);
  2123. pci_set_power_state(pdev, PCI_D3hot);
  2124. }
  2125. static const struct net_device_ops atl1c_netdev_ops = {
  2126. .ndo_open = atl1c_open,
  2127. .ndo_stop = atl1c_close,
  2128. .ndo_validate_addr = eth_validate_addr,
  2129. .ndo_start_xmit = atl1c_xmit_frame,
  2130. .ndo_set_mac_address = atl1c_set_mac_addr,
  2131. .ndo_set_rx_mode = atl1c_set_multi,
  2132. .ndo_change_mtu = atl1c_change_mtu,
  2133. .ndo_fix_features = atl1c_fix_features,
  2134. .ndo_set_features = atl1c_set_features,
  2135. .ndo_do_ioctl = atl1c_ioctl,
  2136. .ndo_tx_timeout = atl1c_tx_timeout,
  2137. .ndo_get_stats = atl1c_get_stats,
  2138. #ifdef CONFIG_NET_POLL_CONTROLLER
  2139. .ndo_poll_controller = atl1c_netpoll,
  2140. #endif
  2141. };
  2142. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2143. {
  2144. SET_NETDEV_DEV(netdev, &pdev->dev);
  2145. pci_set_drvdata(pdev, netdev);
  2146. netdev->netdev_ops = &atl1c_netdev_ops;
  2147. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2148. atl1c_set_ethtool_ops(netdev);
  2149. /* TODO: add when ready */
  2150. netdev->hw_features = NETIF_F_SG |
  2151. NETIF_F_HW_CSUM |
  2152. NETIF_F_HW_VLAN_RX |
  2153. NETIF_F_TSO |
  2154. NETIF_F_TSO6;
  2155. netdev->features = netdev->hw_features |
  2156. NETIF_F_HW_VLAN_TX;
  2157. return 0;
  2158. }
  2159. /*
  2160. * atl1c_probe - Device Initialization Routine
  2161. * @pdev: PCI device information struct
  2162. * @ent: entry in atl1c_pci_tbl
  2163. *
  2164. * Returns 0 on success, negative on failure
  2165. *
  2166. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2167. * The OS initialization, configuring of the adapter private structure,
  2168. * and a hardware reset occur.
  2169. */
  2170. static int __devinit atl1c_probe(struct pci_dev *pdev,
  2171. const struct pci_device_id *ent)
  2172. {
  2173. struct net_device *netdev;
  2174. struct atl1c_adapter *adapter;
  2175. static int cards_found;
  2176. int err = 0;
  2177. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2178. err = pci_enable_device_mem(pdev);
  2179. if (err) {
  2180. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2181. return err;
  2182. }
  2183. /*
  2184. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2185. * shared register for the high 32 bits, so only a single, aligned,
  2186. * 4 GB physical address range can be used at a time.
  2187. *
  2188. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2189. * worth. It is far easier to limit to 32-bit DMA than update
  2190. * various kernel subsystems to support the mechanics required by a
  2191. * fixed-high-32-bit system.
  2192. */
  2193. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2194. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2195. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2196. goto err_dma;
  2197. }
  2198. err = pci_request_regions(pdev, atl1c_driver_name);
  2199. if (err) {
  2200. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2201. goto err_pci_reg;
  2202. }
  2203. pci_set_master(pdev);
  2204. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2205. if (netdev == NULL) {
  2206. err = -ENOMEM;
  2207. goto err_alloc_etherdev;
  2208. }
  2209. err = atl1c_init_netdev(netdev, pdev);
  2210. if (err) {
  2211. dev_err(&pdev->dev, "init netdevice failed\n");
  2212. goto err_init_netdev;
  2213. }
  2214. adapter = netdev_priv(netdev);
  2215. adapter->bd_number = cards_found;
  2216. adapter->netdev = netdev;
  2217. adapter->pdev = pdev;
  2218. adapter->hw.adapter = adapter;
  2219. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2220. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2221. if (!adapter->hw.hw_addr) {
  2222. err = -EIO;
  2223. dev_err(&pdev->dev, "cannot map device registers\n");
  2224. goto err_ioremap;
  2225. }
  2226. /* init mii data */
  2227. adapter->mii.dev = netdev;
  2228. adapter->mii.mdio_read = atl1c_mdio_read;
  2229. adapter->mii.mdio_write = atl1c_mdio_write;
  2230. adapter->mii.phy_id_mask = 0x1f;
  2231. adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
  2232. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2233. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2234. (unsigned long)adapter);
  2235. /* setup the private structure */
  2236. err = atl1c_sw_init(adapter);
  2237. if (err) {
  2238. dev_err(&pdev->dev, "net device private data init failed\n");
  2239. goto err_sw_init;
  2240. }
  2241. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
  2242. ATL1C_PCIE_PHY_RESET);
  2243. /* Init GPHY as early as possible due to power saving issue */
  2244. atl1c_phy_reset(&adapter->hw);
  2245. err = atl1c_reset_mac(&adapter->hw);
  2246. if (err) {
  2247. err = -EIO;
  2248. goto err_reset;
  2249. }
  2250. /* reset the controller to
  2251. * put the device in a known good starting state */
  2252. err = atl1c_phy_init(&adapter->hw);
  2253. if (err) {
  2254. err = -EIO;
  2255. goto err_reset;
  2256. }
  2257. if (atl1c_read_mac_addr(&adapter->hw)) {
  2258. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2259. netdev->addr_assign_type |= NET_ADDR_RANDOM;
  2260. }
  2261. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2262. memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
  2263. if (netif_msg_probe(adapter))
  2264. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2265. adapter->hw.mac_addr);
  2266. atl1c_hw_set_mac_addr(&adapter->hw);
  2267. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2268. adapter->work_event = 0;
  2269. err = register_netdev(netdev);
  2270. if (err) {
  2271. dev_err(&pdev->dev, "register netdevice failed\n");
  2272. goto err_register;
  2273. }
  2274. if (netif_msg_probe(adapter))
  2275. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2276. cards_found++;
  2277. return 0;
  2278. err_reset:
  2279. err_register:
  2280. err_sw_init:
  2281. iounmap(adapter->hw.hw_addr);
  2282. err_init_netdev:
  2283. err_ioremap:
  2284. free_netdev(netdev);
  2285. err_alloc_etherdev:
  2286. pci_release_regions(pdev);
  2287. err_pci_reg:
  2288. err_dma:
  2289. pci_disable_device(pdev);
  2290. return err;
  2291. }
  2292. /*
  2293. * atl1c_remove - Device Removal Routine
  2294. * @pdev: PCI device information struct
  2295. *
  2296. * atl1c_remove is called by the PCI subsystem to alert the driver
  2297. * that it should release a PCI device. The could be caused by a
  2298. * Hot-Plug event, or because the driver is going to be removed from
  2299. * memory.
  2300. */
  2301. static void __devexit atl1c_remove(struct pci_dev *pdev)
  2302. {
  2303. struct net_device *netdev = pci_get_drvdata(pdev);
  2304. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2305. unregister_netdev(netdev);
  2306. atl1c_phy_disable(&adapter->hw);
  2307. iounmap(adapter->hw.hw_addr);
  2308. pci_release_regions(pdev);
  2309. pci_disable_device(pdev);
  2310. free_netdev(netdev);
  2311. }
  2312. /*
  2313. * atl1c_io_error_detected - called when PCI error is detected
  2314. * @pdev: Pointer to PCI device
  2315. * @state: The current pci connection state
  2316. *
  2317. * This function is called after a PCI bus error affecting
  2318. * this device has been detected.
  2319. */
  2320. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2321. pci_channel_state_t state)
  2322. {
  2323. struct net_device *netdev = pci_get_drvdata(pdev);
  2324. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2325. netif_device_detach(netdev);
  2326. if (state == pci_channel_io_perm_failure)
  2327. return PCI_ERS_RESULT_DISCONNECT;
  2328. if (netif_running(netdev))
  2329. atl1c_down(adapter);
  2330. pci_disable_device(pdev);
  2331. /* Request a slot slot reset. */
  2332. return PCI_ERS_RESULT_NEED_RESET;
  2333. }
  2334. /*
  2335. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2336. * @pdev: Pointer to PCI device
  2337. *
  2338. * Restart the card from scratch, as if from a cold-boot. Implementation
  2339. * resembles the first-half of the e1000_resume routine.
  2340. */
  2341. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2342. {
  2343. struct net_device *netdev = pci_get_drvdata(pdev);
  2344. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2345. if (pci_enable_device(pdev)) {
  2346. if (netif_msg_hw(adapter))
  2347. dev_err(&pdev->dev,
  2348. "Cannot re-enable PCI device after reset\n");
  2349. return PCI_ERS_RESULT_DISCONNECT;
  2350. }
  2351. pci_set_master(pdev);
  2352. pci_enable_wake(pdev, PCI_D3hot, 0);
  2353. pci_enable_wake(pdev, PCI_D3cold, 0);
  2354. atl1c_reset_mac(&adapter->hw);
  2355. return PCI_ERS_RESULT_RECOVERED;
  2356. }
  2357. /*
  2358. * atl1c_io_resume - called when traffic can start flowing again.
  2359. * @pdev: Pointer to PCI device
  2360. *
  2361. * This callback is called when the error recovery driver tells us that
  2362. * its OK to resume normal operation. Implementation resembles the
  2363. * second-half of the atl1c_resume routine.
  2364. */
  2365. static void atl1c_io_resume(struct pci_dev *pdev)
  2366. {
  2367. struct net_device *netdev = pci_get_drvdata(pdev);
  2368. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2369. if (netif_running(netdev)) {
  2370. if (atl1c_up(adapter)) {
  2371. if (netif_msg_hw(adapter))
  2372. dev_err(&pdev->dev,
  2373. "Cannot bring device back up after reset\n");
  2374. return;
  2375. }
  2376. }
  2377. netif_device_attach(netdev);
  2378. }
  2379. static struct pci_error_handlers atl1c_err_handler = {
  2380. .error_detected = atl1c_io_error_detected,
  2381. .slot_reset = atl1c_io_slot_reset,
  2382. .resume = atl1c_io_resume,
  2383. };
  2384. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2385. static struct pci_driver atl1c_driver = {
  2386. .name = atl1c_driver_name,
  2387. .id_table = atl1c_pci_tbl,
  2388. .probe = atl1c_probe,
  2389. .remove = __devexit_p(atl1c_remove),
  2390. .shutdown = atl1c_shutdown,
  2391. .err_handler = &atl1c_err_handler,
  2392. .driver.pm = &atl1c_pm_ops,
  2393. };
  2394. /*
  2395. * atl1c_init_module - Driver Registration Routine
  2396. *
  2397. * atl1c_init_module is the first routine called when the driver is
  2398. * loaded. All it does is register with the PCI subsystem.
  2399. */
  2400. static int __init atl1c_init_module(void)
  2401. {
  2402. return pci_register_driver(&atl1c_driver);
  2403. }
  2404. /*
  2405. * atl1c_exit_module - Driver Exit Cleanup Routine
  2406. *
  2407. * atl1c_exit_module is called just before the driver is removed
  2408. * from memory.
  2409. */
  2410. static void __exit atl1c_exit_module(void)
  2411. {
  2412. pci_unregister_driver(&atl1c_driver);
  2413. }
  2414. module_init(atl1c_init_module);
  2415. module_exit(atl1c_exit_module);