fw.c 44 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/etherdevice.h>
  35. #include <linux/mlx4/cmd.h>
  36. #include <linux/module.h>
  37. #include <linux/cache.h>
  38. #include "fw.h"
  39. #include "icm.h"
  40. enum {
  41. MLX4_COMMAND_INTERFACE_MIN_REV = 2,
  42. MLX4_COMMAND_INTERFACE_MAX_REV = 3,
  43. MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
  44. };
  45. extern void __buggy_use_of_MLX4_GET(void);
  46. extern void __buggy_use_of_MLX4_PUT(void);
  47. static bool enable_qos;
  48. module_param(enable_qos, bool, 0444);
  49. MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
  50. #define MLX4_GET(dest, source, offset) \
  51. do { \
  52. void *__p = (char *) (source) + (offset); \
  53. switch (sizeof (dest)) { \
  54. case 1: (dest) = *(u8 *) __p; break; \
  55. case 2: (dest) = be16_to_cpup(__p); break; \
  56. case 4: (dest) = be32_to_cpup(__p); break; \
  57. case 8: (dest) = be64_to_cpup(__p); break; \
  58. default: __buggy_use_of_MLX4_GET(); \
  59. } \
  60. } while (0)
  61. #define MLX4_PUT(dest, source, offset) \
  62. do { \
  63. void *__d = ((char *) (dest) + (offset)); \
  64. switch (sizeof(source)) { \
  65. case 1: *(u8 *) __d = (source); break; \
  66. case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
  67. case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
  68. case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
  69. default: __buggy_use_of_MLX4_PUT(); \
  70. } \
  71. } while (0)
  72. static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
  73. {
  74. static const char *fname[] = {
  75. [ 0] = "RC transport",
  76. [ 1] = "UC transport",
  77. [ 2] = "UD transport",
  78. [ 3] = "XRC transport",
  79. [ 4] = "reliable multicast",
  80. [ 5] = "FCoIB support",
  81. [ 6] = "SRQ support",
  82. [ 7] = "IPoIB checksum offload",
  83. [ 8] = "P_Key violation counter",
  84. [ 9] = "Q_Key violation counter",
  85. [10] = "VMM",
  86. [12] = "DPDP",
  87. [15] = "Big LSO headers",
  88. [16] = "MW support",
  89. [17] = "APM support",
  90. [18] = "Atomic ops support",
  91. [19] = "Raw multicast support",
  92. [20] = "Address vector port checking support",
  93. [21] = "UD multicast support",
  94. [24] = "Demand paging support",
  95. [25] = "Router support",
  96. [30] = "IBoE support",
  97. [32] = "Unicast loopback support",
  98. [34] = "FCS header control",
  99. [38] = "Wake On LAN support",
  100. [40] = "UDP RSS support",
  101. [41] = "Unicast VEP steering support",
  102. [42] = "Multicast VEP steering support",
  103. [48] = "Counters support",
  104. };
  105. int i;
  106. mlx4_dbg(dev, "DEV_CAP flags:\n");
  107. for (i = 0; i < ARRAY_SIZE(fname); ++i)
  108. if (fname[i] && (flags & (1LL << i)))
  109. mlx4_dbg(dev, " %s\n", fname[i]);
  110. }
  111. int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
  112. {
  113. struct mlx4_cmd_mailbox *mailbox;
  114. u32 *inbox;
  115. int err = 0;
  116. #define MOD_STAT_CFG_IN_SIZE 0x100
  117. #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
  118. #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
  119. mailbox = mlx4_alloc_cmd_mailbox(dev);
  120. if (IS_ERR(mailbox))
  121. return PTR_ERR(mailbox);
  122. inbox = mailbox->buf;
  123. memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
  124. MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
  125. MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
  126. err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
  127. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  128. mlx4_free_cmd_mailbox(dev, mailbox);
  129. return err;
  130. }
  131. int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
  132. struct mlx4_vhcr *vhcr,
  133. struct mlx4_cmd_mailbox *inbox,
  134. struct mlx4_cmd_mailbox *outbox,
  135. struct mlx4_cmd_info *cmd)
  136. {
  137. u8 field;
  138. u32 size;
  139. int err = 0;
  140. #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
  141. #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
  142. #define QUERY_FUNC_CAP_FUNCTION_OFFSET 0x3
  143. #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
  144. #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
  145. #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
  146. #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
  147. #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
  148. #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
  149. #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
  150. #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
  151. #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
  152. #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
  153. #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
  154. if (vhcr->op_modifier == 1) {
  155. field = vhcr->in_modifier;
  156. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
  157. field = 0; /* ensure fvl bit is not set */
  158. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
  159. } else if (vhcr->op_modifier == 0) {
  160. field = 1 << 7; /* enable only ethernet interface */
  161. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
  162. field = slave;
  163. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FUNCTION_OFFSET);
  164. field = dev->caps.num_ports;
  165. MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
  166. size = 0; /* no PF behavious is set for now */
  167. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
  168. size = dev->caps.num_qps;
  169. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
  170. size = dev->caps.num_srqs;
  171. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
  172. size = dev->caps.num_cqs;
  173. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
  174. size = dev->caps.num_eqs;
  175. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
  176. size = dev->caps.reserved_eqs;
  177. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
  178. size = dev->caps.num_mpts;
  179. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
  180. size = dev->caps.num_mtts;
  181. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
  182. size = dev->caps.num_mgms + dev->caps.num_amgms;
  183. MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
  184. } else
  185. err = -EINVAL;
  186. return err;
  187. }
  188. int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
  189. {
  190. struct mlx4_cmd_mailbox *mailbox;
  191. u32 *outbox;
  192. u8 field;
  193. u32 size;
  194. int i;
  195. int err = 0;
  196. mailbox = mlx4_alloc_cmd_mailbox(dev);
  197. if (IS_ERR(mailbox))
  198. return PTR_ERR(mailbox);
  199. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
  200. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  201. if (err)
  202. goto out;
  203. outbox = mailbox->buf;
  204. MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
  205. if (!(field & (1 << 7))) {
  206. mlx4_err(dev, "The host doesn't support eth interface\n");
  207. err = -EPROTONOSUPPORT;
  208. goto out;
  209. }
  210. MLX4_GET(field, outbox, QUERY_FUNC_CAP_FUNCTION_OFFSET);
  211. func_cap->function = field;
  212. MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
  213. func_cap->num_ports = field;
  214. MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
  215. func_cap->pf_context_behaviour = size;
  216. MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
  217. func_cap->qp_quota = size & 0xFFFFFF;
  218. MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
  219. func_cap->srq_quota = size & 0xFFFFFF;
  220. MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
  221. func_cap->cq_quota = size & 0xFFFFFF;
  222. MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
  223. func_cap->max_eq = size & 0xFFFFFF;
  224. MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
  225. func_cap->reserved_eq = size & 0xFFFFFF;
  226. MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
  227. func_cap->mpt_quota = size & 0xFFFFFF;
  228. MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
  229. func_cap->mtt_quota = size & 0xFFFFFF;
  230. MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
  231. func_cap->mcg_quota = size & 0xFFFFFF;
  232. for (i = 1; i <= func_cap->num_ports; ++i) {
  233. err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
  234. MLX4_CMD_QUERY_FUNC_CAP,
  235. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  236. if (err)
  237. goto out;
  238. MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
  239. if (field & (1 << 7)) {
  240. mlx4_err(dev, "VLAN is enforced on this port\n");
  241. err = -EPROTONOSUPPORT;
  242. goto out;
  243. }
  244. if (field & (1 << 6)) {
  245. mlx4_err(dev, "Force mac is enabled on this port\n");
  246. err = -EPROTONOSUPPORT;
  247. goto out;
  248. }
  249. MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
  250. func_cap->physical_port[i] = field;
  251. }
  252. /* All other resources are allocated by the master, but we still report
  253. * 'num' and 'reserved' capabilities as follows:
  254. * - num remains the maximum resource index
  255. * - 'num - reserved' is the total available objects of a resource, but
  256. * resource indices may be less than 'reserved'
  257. * TODO: set per-resource quotas */
  258. out:
  259. mlx4_free_cmd_mailbox(dev, mailbox);
  260. return err;
  261. }
  262. int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
  263. {
  264. struct mlx4_cmd_mailbox *mailbox;
  265. u32 *outbox;
  266. u8 field;
  267. u32 field32, flags, ext_flags;
  268. u16 size;
  269. u16 stat_rate;
  270. int err;
  271. int i;
  272. #define QUERY_DEV_CAP_OUT_SIZE 0x100
  273. #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
  274. #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
  275. #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
  276. #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
  277. #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
  278. #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
  279. #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
  280. #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
  281. #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
  282. #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
  283. #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
  284. #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
  285. #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
  286. #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
  287. #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
  288. #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
  289. #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
  290. #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
  291. #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
  292. #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
  293. #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
  294. #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
  295. #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
  296. #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
  297. #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
  298. #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
  299. #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
  300. #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
  301. #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
  302. #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
  303. #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
  304. #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
  305. #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
  306. #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
  307. #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
  308. #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
  309. #define QUERY_DEV_CAP_BF_OFFSET 0x4c
  310. #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
  311. #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
  312. #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
  313. #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
  314. #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
  315. #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
  316. #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
  317. #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
  318. #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
  319. #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
  320. #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
  321. #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
  322. #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
  323. #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
  324. #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
  325. #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
  326. #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
  327. #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
  328. #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
  329. #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
  330. #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
  331. #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
  332. #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
  333. #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
  334. #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
  335. #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
  336. #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
  337. #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
  338. mailbox = mlx4_alloc_cmd_mailbox(dev);
  339. if (IS_ERR(mailbox))
  340. return PTR_ERR(mailbox);
  341. outbox = mailbox->buf;
  342. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
  343. MLX4_CMD_TIME_CLASS_A, !mlx4_is_slave(dev));
  344. if (err)
  345. goto out;
  346. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
  347. dev_cap->reserved_qps = 1 << (field & 0xf);
  348. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
  349. dev_cap->max_qps = 1 << (field & 0x1f);
  350. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
  351. dev_cap->reserved_srqs = 1 << (field >> 4);
  352. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
  353. dev_cap->max_srqs = 1 << (field & 0x1f);
  354. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
  355. dev_cap->max_cq_sz = 1 << field;
  356. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
  357. dev_cap->reserved_cqs = 1 << (field & 0xf);
  358. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
  359. dev_cap->max_cqs = 1 << (field & 0x1f);
  360. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
  361. dev_cap->max_mpts = 1 << (field & 0x3f);
  362. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
  363. dev_cap->reserved_eqs = field & 0xf;
  364. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
  365. dev_cap->max_eqs = 1 << (field & 0xf);
  366. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
  367. dev_cap->reserved_mtts = 1 << (field >> 4);
  368. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
  369. dev_cap->max_mrw_sz = 1 << field;
  370. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
  371. dev_cap->reserved_mrws = 1 << (field & 0xf);
  372. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
  373. dev_cap->max_mtt_seg = 1 << (field & 0x3f);
  374. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
  375. dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
  376. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
  377. dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
  378. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
  379. field &= 0x1f;
  380. if (!field)
  381. dev_cap->max_gso_sz = 0;
  382. else
  383. dev_cap->max_gso_sz = 1 << field;
  384. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
  385. dev_cap->max_rdma_global = 1 << (field & 0x3f);
  386. MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
  387. dev_cap->local_ca_ack_delay = field & 0x1f;
  388. MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
  389. dev_cap->num_ports = field & 0xf;
  390. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
  391. dev_cap->max_msg_sz = 1 << (field & 0x1f);
  392. MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
  393. dev_cap->stat_rate_support = stat_rate;
  394. MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
  395. MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
  396. dev_cap->flags = flags | (u64)ext_flags << 32;
  397. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
  398. dev_cap->reserved_uars = field >> 4;
  399. MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
  400. dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
  401. MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
  402. dev_cap->min_page_sz = 1 << field;
  403. MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
  404. if (field & 0x80) {
  405. MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
  406. dev_cap->bf_reg_size = 1 << (field & 0x1f);
  407. MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
  408. if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
  409. field = 3;
  410. dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
  411. mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
  412. dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
  413. } else {
  414. dev_cap->bf_reg_size = 0;
  415. mlx4_dbg(dev, "BlueFlame not available\n");
  416. }
  417. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
  418. dev_cap->max_sq_sg = field;
  419. MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
  420. dev_cap->max_sq_desc_sz = size;
  421. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
  422. dev_cap->max_qp_per_mcg = 1 << field;
  423. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
  424. dev_cap->reserved_mgms = field & 0xf;
  425. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
  426. dev_cap->max_mcgs = 1 << field;
  427. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
  428. dev_cap->reserved_pds = field >> 4;
  429. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
  430. dev_cap->max_pds = 1 << (field & 0x3f);
  431. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
  432. dev_cap->reserved_xrcds = field >> 4;
  433. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
  434. dev_cap->max_xrcds = 1 << (field & 0x1f);
  435. MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
  436. dev_cap->rdmarc_entry_sz = size;
  437. MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
  438. dev_cap->qpc_entry_sz = size;
  439. MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
  440. dev_cap->aux_entry_sz = size;
  441. MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
  442. dev_cap->altc_entry_sz = size;
  443. MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
  444. dev_cap->eqc_entry_sz = size;
  445. MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
  446. dev_cap->cqc_entry_sz = size;
  447. MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
  448. dev_cap->srq_entry_sz = size;
  449. MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
  450. dev_cap->cmpt_entry_sz = size;
  451. MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
  452. dev_cap->mtt_entry_sz = size;
  453. MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
  454. dev_cap->dmpt_entry_sz = size;
  455. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
  456. dev_cap->max_srq_sz = 1 << field;
  457. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
  458. dev_cap->max_qp_sz = 1 << field;
  459. MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
  460. dev_cap->resize_srq = field & 1;
  461. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
  462. dev_cap->max_rq_sg = field;
  463. MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
  464. dev_cap->max_rq_desc_sz = size;
  465. MLX4_GET(dev_cap->bmme_flags, outbox,
  466. QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
  467. MLX4_GET(dev_cap->reserved_lkey, outbox,
  468. QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
  469. MLX4_GET(dev_cap->max_icm_sz, outbox,
  470. QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
  471. if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
  472. MLX4_GET(dev_cap->max_counters, outbox,
  473. QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
  474. if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  475. for (i = 1; i <= dev_cap->num_ports; ++i) {
  476. MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
  477. dev_cap->max_vl[i] = field >> 4;
  478. MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
  479. dev_cap->ib_mtu[i] = field >> 4;
  480. dev_cap->max_port_width[i] = field & 0xf;
  481. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
  482. dev_cap->max_gids[i] = 1 << (field & 0xf);
  483. MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
  484. dev_cap->max_pkeys[i] = 1 << (field & 0xf);
  485. }
  486. } else {
  487. #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
  488. #define QUERY_PORT_MTU_OFFSET 0x01
  489. #define QUERY_PORT_ETH_MTU_OFFSET 0x02
  490. #define QUERY_PORT_WIDTH_OFFSET 0x06
  491. #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
  492. #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
  493. #define QUERY_PORT_MAX_VL_OFFSET 0x0b
  494. #define QUERY_PORT_MAC_OFFSET 0x10
  495. #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
  496. #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
  497. #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
  498. for (i = 1; i <= dev_cap->num_ports; ++i) {
  499. err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
  500. MLX4_CMD_TIME_CLASS_B,
  501. !mlx4_is_slave(dev));
  502. if (err)
  503. goto out;
  504. MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
  505. dev_cap->supported_port_types[i] = field & 3;
  506. dev_cap->suggested_type[i] = (field >> 3) & 1;
  507. dev_cap->default_sense[i] = (field >> 4) & 1;
  508. MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
  509. dev_cap->ib_mtu[i] = field & 0xf;
  510. MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
  511. dev_cap->max_port_width[i] = field & 0xf;
  512. MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
  513. dev_cap->max_gids[i] = 1 << (field >> 4);
  514. dev_cap->max_pkeys[i] = 1 << (field & 0xf);
  515. MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
  516. dev_cap->max_vl[i] = field & 0xf;
  517. MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
  518. dev_cap->log_max_macs[i] = field & 0xf;
  519. dev_cap->log_max_vlans[i] = field >> 4;
  520. MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
  521. MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
  522. MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
  523. dev_cap->trans_type[i] = field32 >> 24;
  524. dev_cap->vendor_oui[i] = field32 & 0xffffff;
  525. MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
  526. MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
  527. }
  528. }
  529. mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
  530. dev_cap->bmme_flags, dev_cap->reserved_lkey);
  531. /*
  532. * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
  533. * we can't use any EQs whose doorbell falls on that page,
  534. * even if the EQ itself isn't reserved.
  535. */
  536. dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
  537. dev_cap->reserved_eqs);
  538. mlx4_dbg(dev, "Max ICM size %lld MB\n",
  539. (unsigned long long) dev_cap->max_icm_sz >> 20);
  540. mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
  541. dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
  542. mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
  543. dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
  544. mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
  545. dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
  546. mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
  547. dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
  548. mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
  549. dev_cap->reserved_mrws, dev_cap->reserved_mtts);
  550. mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
  551. dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
  552. mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
  553. dev_cap->max_pds, dev_cap->reserved_mgms);
  554. mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
  555. dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
  556. mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
  557. dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
  558. dev_cap->max_port_width[1]);
  559. mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
  560. dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
  561. mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
  562. dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
  563. mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
  564. mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
  565. dump_dev_cap_flags(dev, dev_cap->flags);
  566. out:
  567. mlx4_free_cmd_mailbox(dev, mailbox);
  568. return err;
  569. }
  570. int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
  571. struct mlx4_vhcr *vhcr,
  572. struct mlx4_cmd_mailbox *inbox,
  573. struct mlx4_cmd_mailbox *outbox,
  574. struct mlx4_cmd_info *cmd)
  575. {
  576. u64 def_mac;
  577. u8 port_type;
  578. int err;
  579. #define MLX4_VF_PORT_ETH_ONLY_MASK 0xE6
  580. err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
  581. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  582. MLX4_CMD_NATIVE);
  583. if (!err && dev->caps.function != slave) {
  584. /* set slave default_mac address */
  585. MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
  586. def_mac += slave << 8;
  587. MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
  588. /* get port type - currently only eth is enabled */
  589. MLX4_GET(port_type, outbox->buf,
  590. QUERY_PORT_SUPPORTED_TYPE_OFFSET);
  591. /* Allow only Eth port, no link sensing allowed */
  592. port_type &= MLX4_VF_PORT_ETH_ONLY_MASK;
  593. /* check eth is enabled for this port */
  594. if (!(port_type & 2))
  595. mlx4_dbg(dev, "QUERY PORT: eth not supported by host");
  596. MLX4_PUT(outbox->buf, port_type,
  597. QUERY_PORT_SUPPORTED_TYPE_OFFSET);
  598. }
  599. return err;
  600. }
  601. static int mlx4_QUERY_PORT(struct mlx4_dev *dev, void *ptr, u8 port)
  602. {
  603. struct mlx4_cmd_mailbox *outbox = ptr;
  604. return mlx4_cmd_box(dev, 0, outbox->dma, port, 0,
  605. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  606. MLX4_CMD_WRAPPED);
  607. }
  608. EXPORT_SYMBOL_GPL(mlx4_QUERY_PORT);
  609. int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
  610. {
  611. struct mlx4_cmd_mailbox *mailbox;
  612. struct mlx4_icm_iter iter;
  613. __be64 *pages;
  614. int lg;
  615. int nent = 0;
  616. int i;
  617. int err = 0;
  618. int ts = 0, tc = 0;
  619. mailbox = mlx4_alloc_cmd_mailbox(dev);
  620. if (IS_ERR(mailbox))
  621. return PTR_ERR(mailbox);
  622. memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
  623. pages = mailbox->buf;
  624. for (mlx4_icm_first(icm, &iter);
  625. !mlx4_icm_last(&iter);
  626. mlx4_icm_next(&iter)) {
  627. /*
  628. * We have to pass pages that are aligned to their
  629. * size, so find the least significant 1 in the
  630. * address or size and use that as our log2 size.
  631. */
  632. lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
  633. if (lg < MLX4_ICM_PAGE_SHIFT) {
  634. mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
  635. MLX4_ICM_PAGE_SIZE,
  636. (unsigned long long) mlx4_icm_addr(&iter),
  637. mlx4_icm_size(&iter));
  638. err = -EINVAL;
  639. goto out;
  640. }
  641. for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
  642. if (virt != -1) {
  643. pages[nent * 2] = cpu_to_be64(virt);
  644. virt += 1 << lg;
  645. }
  646. pages[nent * 2 + 1] =
  647. cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
  648. (lg - MLX4_ICM_PAGE_SHIFT));
  649. ts += 1 << (lg - 10);
  650. ++tc;
  651. if (++nent == MLX4_MAILBOX_SIZE / 16) {
  652. err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
  653. MLX4_CMD_TIME_CLASS_B,
  654. MLX4_CMD_NATIVE);
  655. if (err)
  656. goto out;
  657. nent = 0;
  658. }
  659. }
  660. }
  661. if (nent)
  662. err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
  663. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  664. if (err)
  665. goto out;
  666. switch (op) {
  667. case MLX4_CMD_MAP_FA:
  668. mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
  669. break;
  670. case MLX4_CMD_MAP_ICM_AUX:
  671. mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
  672. break;
  673. case MLX4_CMD_MAP_ICM:
  674. mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
  675. tc, ts, (unsigned long long) virt - (ts << 10));
  676. break;
  677. }
  678. out:
  679. mlx4_free_cmd_mailbox(dev, mailbox);
  680. return err;
  681. }
  682. int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
  683. {
  684. return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
  685. }
  686. int mlx4_UNMAP_FA(struct mlx4_dev *dev)
  687. {
  688. return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
  689. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  690. }
  691. int mlx4_RUN_FW(struct mlx4_dev *dev)
  692. {
  693. return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
  694. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  695. }
  696. int mlx4_QUERY_FW(struct mlx4_dev *dev)
  697. {
  698. struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
  699. struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
  700. struct mlx4_cmd_mailbox *mailbox;
  701. u32 *outbox;
  702. int err = 0;
  703. u64 fw_ver;
  704. u16 cmd_if_rev;
  705. u8 lg;
  706. #define QUERY_FW_OUT_SIZE 0x100
  707. #define QUERY_FW_VER_OFFSET 0x00
  708. #define QUERY_FW_PPF_ID 0x09
  709. #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
  710. #define QUERY_FW_MAX_CMD_OFFSET 0x0f
  711. #define QUERY_FW_ERR_START_OFFSET 0x30
  712. #define QUERY_FW_ERR_SIZE_OFFSET 0x38
  713. #define QUERY_FW_ERR_BAR_OFFSET 0x3c
  714. #define QUERY_FW_SIZE_OFFSET 0x00
  715. #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
  716. #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
  717. #define QUERY_FW_COMM_BASE_OFFSET 0x40
  718. #define QUERY_FW_COMM_BAR_OFFSET 0x48
  719. mailbox = mlx4_alloc_cmd_mailbox(dev);
  720. if (IS_ERR(mailbox))
  721. return PTR_ERR(mailbox);
  722. outbox = mailbox->buf;
  723. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
  724. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  725. if (err)
  726. goto out;
  727. MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
  728. /*
  729. * FW subminor version is at more significant bits than minor
  730. * version, so swap here.
  731. */
  732. dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
  733. ((fw_ver & 0xffff0000ull) >> 16) |
  734. ((fw_ver & 0x0000ffffull) << 16);
  735. MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
  736. dev->caps.function = lg;
  737. MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
  738. if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
  739. cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
  740. mlx4_err(dev, "Installed FW has unsupported "
  741. "command interface revision %d.\n",
  742. cmd_if_rev);
  743. mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
  744. (int) (dev->caps.fw_ver >> 32),
  745. (int) (dev->caps.fw_ver >> 16) & 0xffff,
  746. (int) dev->caps.fw_ver & 0xffff);
  747. mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
  748. MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
  749. err = -ENODEV;
  750. goto out;
  751. }
  752. if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
  753. dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
  754. MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
  755. cmd->max_cmds = 1 << lg;
  756. mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
  757. (int) (dev->caps.fw_ver >> 32),
  758. (int) (dev->caps.fw_ver >> 16) & 0xffff,
  759. (int) dev->caps.fw_ver & 0xffff,
  760. cmd_if_rev, cmd->max_cmds);
  761. MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
  762. MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
  763. MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
  764. fw->catas_bar = (fw->catas_bar >> 6) * 2;
  765. mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
  766. (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
  767. MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
  768. MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
  769. MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
  770. fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
  771. MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
  772. MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
  773. fw->comm_bar = (fw->comm_bar >> 6) * 2;
  774. mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
  775. fw->comm_bar, fw->comm_base);
  776. mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
  777. /*
  778. * Round up number of system pages needed in case
  779. * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
  780. */
  781. fw->fw_pages =
  782. ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
  783. (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
  784. mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
  785. (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
  786. out:
  787. mlx4_free_cmd_mailbox(dev, mailbox);
  788. return err;
  789. }
  790. static void get_board_id(void *vsd, char *board_id)
  791. {
  792. int i;
  793. #define VSD_OFFSET_SIG1 0x00
  794. #define VSD_OFFSET_SIG2 0xde
  795. #define VSD_OFFSET_MLX_BOARD_ID 0xd0
  796. #define VSD_OFFSET_TS_BOARD_ID 0x20
  797. #define VSD_SIGNATURE_TOPSPIN 0x5ad
  798. memset(board_id, 0, MLX4_BOARD_ID_LEN);
  799. if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
  800. be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
  801. strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
  802. } else {
  803. /*
  804. * The board ID is a string but the firmware byte
  805. * swaps each 4-byte word before passing it back to
  806. * us. Therefore we need to swab it before printing.
  807. */
  808. for (i = 0; i < 4; ++i)
  809. ((u32 *) board_id)[i] =
  810. swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
  811. }
  812. }
  813. int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
  814. {
  815. struct mlx4_cmd_mailbox *mailbox;
  816. u32 *outbox;
  817. int err;
  818. #define QUERY_ADAPTER_OUT_SIZE 0x100
  819. #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
  820. #define QUERY_ADAPTER_VSD_OFFSET 0x20
  821. mailbox = mlx4_alloc_cmd_mailbox(dev);
  822. if (IS_ERR(mailbox))
  823. return PTR_ERR(mailbox);
  824. outbox = mailbox->buf;
  825. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
  826. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  827. if (err)
  828. goto out;
  829. MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
  830. get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
  831. adapter->board_id);
  832. out:
  833. mlx4_free_cmd_mailbox(dev, mailbox);
  834. return err;
  835. }
  836. int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
  837. {
  838. struct mlx4_cmd_mailbox *mailbox;
  839. __be32 *inbox;
  840. int err;
  841. #define INIT_HCA_IN_SIZE 0x200
  842. #define INIT_HCA_VERSION_OFFSET 0x000
  843. #define INIT_HCA_VERSION 2
  844. #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
  845. #define INIT_HCA_FLAGS_OFFSET 0x014
  846. #define INIT_HCA_QPC_OFFSET 0x020
  847. #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
  848. #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
  849. #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
  850. #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
  851. #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
  852. #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
  853. #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
  854. #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
  855. #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
  856. #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
  857. #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
  858. #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
  859. #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
  860. #define INIT_HCA_MCAST_OFFSET 0x0c0
  861. #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
  862. #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
  863. #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
  864. #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
  865. #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
  866. #define INIT_HCA_TPT_OFFSET 0x0f0
  867. #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
  868. #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
  869. #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
  870. #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
  871. #define INIT_HCA_UAR_OFFSET 0x120
  872. #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
  873. #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
  874. mailbox = mlx4_alloc_cmd_mailbox(dev);
  875. if (IS_ERR(mailbox))
  876. return PTR_ERR(mailbox);
  877. inbox = mailbox->buf;
  878. memset(inbox, 0, INIT_HCA_IN_SIZE);
  879. *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
  880. *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
  881. (ilog2(cache_line_size()) - 4) << 5;
  882. #if defined(__LITTLE_ENDIAN)
  883. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
  884. #elif defined(__BIG_ENDIAN)
  885. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
  886. #else
  887. #error Host endianness not defined
  888. #endif
  889. /* Check port for UD address vector: */
  890. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
  891. /* Enable IPoIB checksumming if we can: */
  892. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
  893. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
  894. /* Enable QoS support if module parameter set */
  895. if (enable_qos)
  896. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
  897. /* enable counters */
  898. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
  899. *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
  900. /* QPC/EEC/CQC/EQC/RDMARC attributes */
  901. MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
  902. MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
  903. MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
  904. MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
  905. MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
  906. MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
  907. MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
  908. MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
  909. MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
  910. MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
  911. MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
  912. MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
  913. /* multicast attributes */
  914. MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
  915. MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
  916. MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
  917. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
  918. MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
  919. MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
  920. /* TPT attributes */
  921. MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
  922. MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
  923. MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
  924. MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
  925. /* UAR attributes */
  926. MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
  927. MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
  928. err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
  929. MLX4_CMD_NATIVE);
  930. if (err)
  931. mlx4_err(dev, "INIT_HCA returns %d\n", err);
  932. mlx4_free_cmd_mailbox(dev, mailbox);
  933. return err;
  934. }
  935. int mlx4_QUERY_HCA(struct mlx4_dev *dev,
  936. struct mlx4_init_hca_param *param)
  937. {
  938. struct mlx4_cmd_mailbox *mailbox;
  939. __be32 *outbox;
  940. int err;
  941. #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
  942. mailbox = mlx4_alloc_cmd_mailbox(dev);
  943. if (IS_ERR(mailbox))
  944. return PTR_ERR(mailbox);
  945. outbox = mailbox->buf;
  946. err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
  947. MLX4_CMD_QUERY_HCA,
  948. MLX4_CMD_TIME_CLASS_B,
  949. !mlx4_is_slave(dev));
  950. if (err)
  951. goto out;
  952. MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
  953. /* QPC/EEC/CQC/EQC/RDMARC attributes */
  954. MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
  955. MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
  956. MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
  957. MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
  958. MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
  959. MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
  960. MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
  961. MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
  962. MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
  963. MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
  964. MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
  965. MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
  966. /* multicast attributes */
  967. MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
  968. MLX4_GET(param->log_mc_entry_sz, outbox,
  969. INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
  970. MLX4_GET(param->log_mc_hash_sz, outbox,
  971. INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
  972. MLX4_GET(param->log_mc_table_sz, outbox,
  973. INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
  974. /* TPT attributes */
  975. MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
  976. MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
  977. MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
  978. MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
  979. /* UAR attributes */
  980. MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
  981. MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
  982. out:
  983. mlx4_free_cmd_mailbox(dev, mailbox);
  984. return err;
  985. }
  986. int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
  987. struct mlx4_vhcr *vhcr,
  988. struct mlx4_cmd_mailbox *inbox,
  989. struct mlx4_cmd_mailbox *outbox,
  990. struct mlx4_cmd_info *cmd)
  991. {
  992. struct mlx4_priv *priv = mlx4_priv(dev);
  993. int port = vhcr->in_modifier;
  994. int err;
  995. if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
  996. return 0;
  997. if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
  998. return -ENODEV;
  999. /* Enable port only if it was previously disabled */
  1000. if (!priv->mfunc.master.init_port_ref[port]) {
  1001. err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
  1002. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  1003. if (err)
  1004. return err;
  1005. priv->mfunc.master.slave_state[slave].init_port_mask |=
  1006. (1 << port);
  1007. }
  1008. ++priv->mfunc.master.init_port_ref[port];
  1009. return 0;
  1010. }
  1011. int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
  1012. {
  1013. struct mlx4_cmd_mailbox *mailbox;
  1014. u32 *inbox;
  1015. int err;
  1016. u32 flags;
  1017. u16 field;
  1018. if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  1019. #define INIT_PORT_IN_SIZE 256
  1020. #define INIT_PORT_FLAGS_OFFSET 0x00
  1021. #define INIT_PORT_FLAG_SIG (1 << 18)
  1022. #define INIT_PORT_FLAG_NG (1 << 17)
  1023. #define INIT_PORT_FLAG_G0 (1 << 16)
  1024. #define INIT_PORT_VL_SHIFT 4
  1025. #define INIT_PORT_PORT_WIDTH_SHIFT 8
  1026. #define INIT_PORT_MTU_OFFSET 0x04
  1027. #define INIT_PORT_MAX_GID_OFFSET 0x06
  1028. #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
  1029. #define INIT_PORT_GUID0_OFFSET 0x10
  1030. #define INIT_PORT_NODE_GUID_OFFSET 0x18
  1031. #define INIT_PORT_SI_GUID_OFFSET 0x20
  1032. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1033. if (IS_ERR(mailbox))
  1034. return PTR_ERR(mailbox);
  1035. inbox = mailbox->buf;
  1036. memset(inbox, 0, INIT_PORT_IN_SIZE);
  1037. flags = 0;
  1038. flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
  1039. flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
  1040. MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
  1041. field = 128 << dev->caps.ib_mtu_cap[port];
  1042. MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
  1043. field = dev->caps.gid_table_len[port];
  1044. MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
  1045. field = dev->caps.pkey_table_len[port];
  1046. MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
  1047. err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
  1048. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  1049. mlx4_free_cmd_mailbox(dev, mailbox);
  1050. } else
  1051. err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
  1052. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  1053. return err;
  1054. }
  1055. EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
  1056. int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
  1057. struct mlx4_vhcr *vhcr,
  1058. struct mlx4_cmd_mailbox *inbox,
  1059. struct mlx4_cmd_mailbox *outbox,
  1060. struct mlx4_cmd_info *cmd)
  1061. {
  1062. struct mlx4_priv *priv = mlx4_priv(dev);
  1063. int port = vhcr->in_modifier;
  1064. int err;
  1065. if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
  1066. (1 << port)))
  1067. return 0;
  1068. if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
  1069. return -ENODEV;
  1070. if (priv->mfunc.master.init_port_ref[port] == 1) {
  1071. err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
  1072. MLX4_CMD_NATIVE);
  1073. if (err)
  1074. return err;
  1075. }
  1076. priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
  1077. --priv->mfunc.master.init_port_ref[port];
  1078. return 0;
  1079. }
  1080. int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
  1081. {
  1082. return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
  1083. MLX4_CMD_WRAPPED);
  1084. }
  1085. EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
  1086. int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
  1087. {
  1088. return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
  1089. MLX4_CMD_NATIVE);
  1090. }
  1091. int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
  1092. {
  1093. int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
  1094. MLX4_CMD_SET_ICM_SIZE,
  1095. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  1096. if (ret)
  1097. return ret;
  1098. /*
  1099. * Round up number of system pages needed in case
  1100. * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
  1101. */
  1102. *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
  1103. (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
  1104. return 0;
  1105. }
  1106. int mlx4_NOP(struct mlx4_dev *dev)
  1107. {
  1108. /* Input modifier of 0x1f means "finish as soon as possible." */
  1109. return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
  1110. }
  1111. #define MLX4_WOL_SETUP_MODE (5 << 28)
  1112. int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
  1113. {
  1114. u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
  1115. return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
  1116. MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
  1117. MLX4_CMD_NATIVE);
  1118. }
  1119. EXPORT_SYMBOL_GPL(mlx4_wol_read);
  1120. int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
  1121. {
  1122. u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
  1123. return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
  1124. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  1125. }
  1126. EXPORT_SYMBOL_GPL(mlx4_wol_write);