i915_drv.h 75 KB

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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #ifndef _I915_DRV_H_
  30. #define _I915_DRV_H_
  31. #include <uapi/drm/i915_drm.h>
  32. #include "i915_reg.h"
  33. #include "intel_bios.h"
  34. #include "intel_ringbuffer.h"
  35. #include <linux/io-mapping.h>
  36. #include <linux/i2c.h>
  37. #include <linux/i2c-algo-bit.h>
  38. #include <drm/intel-gtt.h>
  39. #include <linux/backlight.h>
  40. #include <linux/intel-iommu.h>
  41. #include <linux/kref.h>
  42. #include <linux/pm_qos.h>
  43. /* General customization:
  44. */
  45. #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
  46. #define DRIVER_NAME "i915"
  47. #define DRIVER_DESC "Intel Graphics"
  48. #define DRIVER_DATE "20080730"
  49. enum pipe {
  50. PIPE_A = 0,
  51. PIPE_B,
  52. PIPE_C,
  53. I915_MAX_PIPES
  54. };
  55. #define pipe_name(p) ((p) + 'A')
  56. enum transcoder {
  57. TRANSCODER_A = 0,
  58. TRANSCODER_B,
  59. TRANSCODER_C,
  60. TRANSCODER_EDP = 0xF,
  61. };
  62. #define transcoder_name(t) ((t) + 'A')
  63. enum plane {
  64. PLANE_A = 0,
  65. PLANE_B,
  66. PLANE_C,
  67. };
  68. #define plane_name(p) ((p) + 'A')
  69. #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
  70. enum port {
  71. PORT_A = 0,
  72. PORT_B,
  73. PORT_C,
  74. PORT_D,
  75. PORT_E,
  76. I915_MAX_PORTS
  77. };
  78. #define port_name(p) ((p) + 'A')
  79. enum intel_display_power_domain {
  80. POWER_DOMAIN_PIPE_A,
  81. POWER_DOMAIN_PIPE_B,
  82. POWER_DOMAIN_PIPE_C,
  83. POWER_DOMAIN_PIPE_A_PANEL_FITTER,
  84. POWER_DOMAIN_PIPE_B_PANEL_FITTER,
  85. POWER_DOMAIN_PIPE_C_PANEL_FITTER,
  86. POWER_DOMAIN_TRANSCODER_A,
  87. POWER_DOMAIN_TRANSCODER_B,
  88. POWER_DOMAIN_TRANSCODER_C,
  89. POWER_DOMAIN_TRANSCODER_EDP,
  90. POWER_DOMAIN_VGA,
  91. POWER_DOMAIN_NUM,
  92. };
  93. #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
  94. #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
  95. #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
  96. ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
  97. #define POWER_DOMAIN_TRANSCODER(tran) \
  98. ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
  99. (tran) + POWER_DOMAIN_TRANSCODER_A)
  100. #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
  101. BIT(POWER_DOMAIN_PIPE_A) | \
  102. BIT(POWER_DOMAIN_TRANSCODER_EDP))
  103. enum hpd_pin {
  104. HPD_NONE = 0,
  105. HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
  106. HPD_TV = HPD_NONE, /* TV is known to be unreliable */
  107. HPD_CRT,
  108. HPD_SDVO_B,
  109. HPD_SDVO_C,
  110. HPD_PORT_B,
  111. HPD_PORT_C,
  112. HPD_PORT_D,
  113. HPD_NUM_PINS
  114. };
  115. #define I915_GEM_GPU_DOMAINS \
  116. (I915_GEM_DOMAIN_RENDER | \
  117. I915_GEM_DOMAIN_SAMPLER | \
  118. I915_GEM_DOMAIN_COMMAND | \
  119. I915_GEM_DOMAIN_INSTRUCTION | \
  120. I915_GEM_DOMAIN_VERTEX)
  121. #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
  122. #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  123. list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  124. if ((intel_encoder)->base.crtc == (__crtc))
  125. struct drm_i915_private;
  126. enum intel_dpll_id {
  127. DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
  128. /* real shared dpll ids must be >= 0 */
  129. DPLL_ID_PCH_PLL_A,
  130. DPLL_ID_PCH_PLL_B,
  131. };
  132. #define I915_NUM_PLLS 2
  133. struct intel_dpll_hw_state {
  134. uint32_t dpll;
  135. uint32_t dpll_md;
  136. uint32_t fp0;
  137. uint32_t fp1;
  138. };
  139. struct intel_shared_dpll {
  140. int refcount; /* count of number of CRTCs sharing this PLL */
  141. int active; /* count of number of active CRTCs (i.e. DPMS on) */
  142. bool on; /* is the PLL actually active? Disabled during modeset */
  143. const char *name;
  144. /* should match the index in the dev_priv->shared_dplls array */
  145. enum intel_dpll_id id;
  146. struct intel_dpll_hw_state hw_state;
  147. void (*mode_set)(struct drm_i915_private *dev_priv,
  148. struct intel_shared_dpll *pll);
  149. void (*enable)(struct drm_i915_private *dev_priv,
  150. struct intel_shared_dpll *pll);
  151. void (*disable)(struct drm_i915_private *dev_priv,
  152. struct intel_shared_dpll *pll);
  153. bool (*get_hw_state)(struct drm_i915_private *dev_priv,
  154. struct intel_shared_dpll *pll,
  155. struct intel_dpll_hw_state *hw_state);
  156. };
  157. /* Used by dp and fdi links */
  158. struct intel_link_m_n {
  159. uint32_t tu;
  160. uint32_t gmch_m;
  161. uint32_t gmch_n;
  162. uint32_t link_m;
  163. uint32_t link_n;
  164. };
  165. void intel_link_compute_m_n(int bpp, int nlanes,
  166. int pixel_clock, int link_clock,
  167. struct intel_link_m_n *m_n);
  168. struct intel_ddi_plls {
  169. int spll_refcount;
  170. int wrpll1_refcount;
  171. int wrpll2_refcount;
  172. };
  173. /* Interface history:
  174. *
  175. * 1.1: Original.
  176. * 1.2: Add Power Management
  177. * 1.3: Add vblank support
  178. * 1.4: Fix cmdbuffer path, add heap destroy
  179. * 1.5: Add vblank pipe configuration
  180. * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  181. * - Support vertical blank on secondary display pipe
  182. */
  183. #define DRIVER_MAJOR 1
  184. #define DRIVER_MINOR 6
  185. #define DRIVER_PATCHLEVEL 0
  186. #define WATCH_LISTS 0
  187. #define WATCH_GTT 0
  188. #define I915_GEM_PHYS_CURSOR_0 1
  189. #define I915_GEM_PHYS_CURSOR_1 2
  190. #define I915_GEM_PHYS_OVERLAY_REGS 3
  191. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  192. struct drm_i915_gem_phys_object {
  193. int id;
  194. struct page **page_list;
  195. drm_dma_handle_t *handle;
  196. struct drm_i915_gem_object *cur_obj;
  197. };
  198. struct opregion_header;
  199. struct opregion_acpi;
  200. struct opregion_swsci;
  201. struct opregion_asle;
  202. struct intel_opregion {
  203. struct opregion_header __iomem *header;
  204. struct opregion_acpi __iomem *acpi;
  205. struct opregion_swsci __iomem *swsci;
  206. u32 swsci_gbda_sub_functions;
  207. u32 swsci_sbcb_sub_functions;
  208. struct opregion_asle __iomem *asle;
  209. void __iomem *vbt;
  210. u32 __iomem *lid_state;
  211. };
  212. #define OPREGION_SIZE (8*1024)
  213. struct intel_overlay;
  214. struct intel_overlay_error_state;
  215. struct drm_i915_master_private {
  216. drm_local_map_t *sarea;
  217. struct _drm_i915_sarea *sarea_priv;
  218. };
  219. #define I915_FENCE_REG_NONE -1
  220. #define I915_MAX_NUM_FENCES 32
  221. /* 32 fences + sign bit for FENCE_REG_NONE */
  222. #define I915_MAX_NUM_FENCE_BITS 6
  223. struct drm_i915_fence_reg {
  224. struct list_head lru_list;
  225. struct drm_i915_gem_object *obj;
  226. int pin_count;
  227. };
  228. struct sdvo_device_mapping {
  229. u8 initialized;
  230. u8 dvo_port;
  231. u8 slave_addr;
  232. u8 dvo_wiring;
  233. u8 i2c_pin;
  234. u8 ddc_pin;
  235. };
  236. struct intel_display_error_state;
  237. struct drm_i915_error_state {
  238. struct kref ref;
  239. u32 eir;
  240. u32 pgtbl_er;
  241. u32 ier;
  242. u32 ccid;
  243. u32 derrmr;
  244. u32 forcewake;
  245. bool waiting[I915_NUM_RINGS];
  246. u32 pipestat[I915_MAX_PIPES];
  247. u32 tail[I915_NUM_RINGS];
  248. u32 head[I915_NUM_RINGS];
  249. u32 ctl[I915_NUM_RINGS];
  250. u32 ipeir[I915_NUM_RINGS];
  251. u32 ipehr[I915_NUM_RINGS];
  252. u32 instdone[I915_NUM_RINGS];
  253. u32 acthd[I915_NUM_RINGS];
  254. u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  255. u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  256. u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
  257. /* our own tracking of ring head and tail */
  258. u32 cpu_ring_head[I915_NUM_RINGS];
  259. u32 cpu_ring_tail[I915_NUM_RINGS];
  260. u32 error; /* gen6+ */
  261. u32 err_int; /* gen7 */
  262. u32 instpm[I915_NUM_RINGS];
  263. u32 instps[I915_NUM_RINGS];
  264. u32 extra_instdone[I915_NUM_INSTDONE_REG];
  265. u32 seqno[I915_NUM_RINGS];
  266. u64 bbaddr;
  267. u32 fault_reg[I915_NUM_RINGS];
  268. u32 done_reg;
  269. u32 faddr[I915_NUM_RINGS];
  270. u64 fence[I915_MAX_NUM_FENCES];
  271. struct timeval time;
  272. struct drm_i915_error_ring {
  273. struct drm_i915_error_object {
  274. int page_count;
  275. u32 gtt_offset;
  276. u32 *pages[0];
  277. } *ringbuffer, *batchbuffer, *ctx;
  278. struct drm_i915_error_request {
  279. long jiffies;
  280. u32 seqno;
  281. u32 tail;
  282. } *requests;
  283. int num_requests;
  284. } ring[I915_NUM_RINGS];
  285. struct drm_i915_error_buffer {
  286. u32 size;
  287. u32 name;
  288. u32 rseqno, wseqno;
  289. u32 gtt_offset;
  290. u32 read_domains;
  291. u32 write_domain;
  292. s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  293. s32 pinned:2;
  294. u32 tiling:2;
  295. u32 dirty:1;
  296. u32 purgeable:1;
  297. s32 ring:4;
  298. u32 cache_level:3;
  299. } **active_bo, **pinned_bo;
  300. u32 *active_bo_count, *pinned_bo_count;
  301. struct intel_overlay_error_state *overlay;
  302. struct intel_display_error_state *display;
  303. int hangcheck_score[I915_NUM_RINGS];
  304. enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
  305. };
  306. struct intel_crtc_config;
  307. struct intel_crtc;
  308. struct intel_limit;
  309. struct dpll;
  310. struct drm_i915_display_funcs {
  311. bool (*fbc_enabled)(struct drm_device *dev);
  312. void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  313. void (*disable_fbc)(struct drm_device *dev);
  314. int (*get_display_clock_speed)(struct drm_device *dev);
  315. int (*get_fifo_size)(struct drm_device *dev, int plane);
  316. /**
  317. * find_dpll() - Find the best values for the PLL
  318. * @limit: limits for the PLL
  319. * @crtc: current CRTC
  320. * @target: target frequency in kHz
  321. * @refclk: reference clock frequency in kHz
  322. * @match_clock: if provided, @best_clock P divider must
  323. * match the P divider from @match_clock
  324. * used for LVDS downclocking
  325. * @best_clock: best PLL values found
  326. *
  327. * Returns true on success, false on failure.
  328. */
  329. bool (*find_dpll)(const struct intel_limit *limit,
  330. struct drm_crtc *crtc,
  331. int target, int refclk,
  332. struct dpll *match_clock,
  333. struct dpll *best_clock);
  334. void (*update_wm)(struct drm_crtc *crtc);
  335. void (*update_sprite_wm)(struct drm_plane *plane,
  336. struct drm_crtc *crtc,
  337. uint32_t sprite_width, int pixel_size,
  338. bool enable, bool scaled);
  339. void (*modeset_global_resources)(struct drm_device *dev);
  340. /* Returns the active state of the crtc, and if the crtc is active,
  341. * fills out the pipe-config with the hw state. */
  342. bool (*get_pipe_config)(struct intel_crtc *,
  343. struct intel_crtc_config *);
  344. int (*crtc_mode_set)(struct drm_crtc *crtc,
  345. int x, int y,
  346. struct drm_framebuffer *old_fb);
  347. void (*crtc_enable)(struct drm_crtc *crtc);
  348. void (*crtc_disable)(struct drm_crtc *crtc);
  349. void (*off)(struct drm_crtc *crtc);
  350. void (*write_eld)(struct drm_connector *connector,
  351. struct drm_crtc *crtc,
  352. struct drm_display_mode *mode);
  353. void (*fdi_link_train)(struct drm_crtc *crtc);
  354. void (*init_clock_gating)(struct drm_device *dev);
  355. int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  356. struct drm_framebuffer *fb,
  357. struct drm_i915_gem_object *obj,
  358. uint32_t flags);
  359. int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  360. int x, int y);
  361. void (*hpd_irq_setup)(struct drm_device *dev);
  362. /* clock updates for mode set */
  363. /* cursor updates */
  364. /* render clock increase/decrease */
  365. /* display clock increase/decrease */
  366. /* pll clock increase/decrease */
  367. };
  368. struct intel_uncore_funcs {
  369. void (*force_wake_get)(struct drm_i915_private *dev_priv);
  370. void (*force_wake_put)(struct drm_i915_private *dev_priv);
  371. uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  372. uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  373. uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  374. uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
  375. void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
  376. uint8_t val, bool trace);
  377. void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
  378. uint16_t val, bool trace);
  379. void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
  380. uint32_t val, bool trace);
  381. void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
  382. uint64_t val, bool trace);
  383. };
  384. struct intel_uncore {
  385. spinlock_t lock; /** lock is also taken in irq contexts. */
  386. struct intel_uncore_funcs funcs;
  387. unsigned fifo_count;
  388. unsigned forcewake_count;
  389. struct delayed_work force_wake_work;
  390. };
  391. #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
  392. func(is_mobile) sep \
  393. func(is_i85x) sep \
  394. func(is_i915g) sep \
  395. func(is_i945gm) sep \
  396. func(is_g33) sep \
  397. func(need_gfx_hws) sep \
  398. func(is_g4x) sep \
  399. func(is_pineview) sep \
  400. func(is_broadwater) sep \
  401. func(is_crestline) sep \
  402. func(is_ivybridge) sep \
  403. func(is_valleyview) sep \
  404. func(is_haswell) sep \
  405. func(is_preliminary) sep \
  406. func(has_fbc) sep \
  407. func(has_pipe_cxsr) sep \
  408. func(has_hotplug) sep \
  409. func(cursor_needs_physical) sep \
  410. func(has_overlay) sep \
  411. func(overlay_needs_physical) sep \
  412. func(supports_tv) sep \
  413. func(has_llc) sep \
  414. func(has_ddi) sep \
  415. func(has_fpga_dbg)
  416. #define DEFINE_FLAG(name) u8 name:1
  417. #define SEP_SEMICOLON ;
  418. struct intel_device_info {
  419. u32 display_mmio_offset;
  420. u8 num_pipes:3;
  421. u8 gen;
  422. u8 ring_mask; /* Rings supported by the HW */
  423. DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
  424. };
  425. #undef DEFINE_FLAG
  426. #undef SEP_SEMICOLON
  427. enum i915_cache_level {
  428. I915_CACHE_NONE = 0,
  429. I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
  430. I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
  431. caches, eg sampler/render caches, and the
  432. large Last-Level-Cache. LLC is coherent with
  433. the CPU, but L3 is only visible to the GPU. */
  434. I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
  435. };
  436. typedef uint32_t gen6_gtt_pte_t;
  437. struct i915_address_space {
  438. struct drm_mm mm;
  439. struct drm_device *dev;
  440. struct list_head global_link;
  441. unsigned long start; /* Start offset always 0 for dri2 */
  442. size_t total; /* size addr space maps (ex. 2GB for ggtt) */
  443. struct {
  444. dma_addr_t addr;
  445. struct page *page;
  446. } scratch;
  447. /**
  448. * List of objects currently involved in rendering.
  449. *
  450. * Includes buffers having the contents of their GPU caches
  451. * flushed, not necessarily primitives. last_rendering_seqno
  452. * represents when the rendering involved will be completed.
  453. *
  454. * A reference is held on the buffer while on this list.
  455. */
  456. struct list_head active_list;
  457. /**
  458. * LRU list of objects which are not in the ringbuffer and
  459. * are ready to unbind, but are still in the GTT.
  460. *
  461. * last_rendering_seqno is 0 while an object is in this list.
  462. *
  463. * A reference is not held on the buffer while on this list,
  464. * as merely being GTT-bound shouldn't prevent its being
  465. * freed, and we'll pull it off the list in the free path.
  466. */
  467. struct list_head inactive_list;
  468. /* FIXME: Need a more generic return type */
  469. gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
  470. enum i915_cache_level level);
  471. void (*clear_range)(struct i915_address_space *vm,
  472. unsigned int first_entry,
  473. unsigned int num_entries);
  474. void (*insert_entries)(struct i915_address_space *vm,
  475. struct sg_table *st,
  476. unsigned int first_entry,
  477. enum i915_cache_level cache_level);
  478. void (*cleanup)(struct i915_address_space *vm);
  479. };
  480. /* The Graphics Translation Table is the way in which GEN hardware translates a
  481. * Graphics Virtual Address into a Physical Address. In addition to the normal
  482. * collateral associated with any va->pa translations GEN hardware also has a
  483. * portion of the GTT which can be mapped by the CPU and remain both coherent
  484. * and correct (in cases like swizzling). That region is referred to as GMADR in
  485. * the spec.
  486. */
  487. struct i915_gtt {
  488. struct i915_address_space base;
  489. size_t stolen_size; /* Total size of stolen memory */
  490. unsigned long mappable_end; /* End offset that we can CPU map */
  491. struct io_mapping *mappable; /* Mapping to our CPU mappable region */
  492. phys_addr_t mappable_base; /* PA of our GMADR */
  493. /** "Graphics Stolen Memory" holds the global PTEs */
  494. void __iomem *gsm;
  495. bool do_idle_maps;
  496. int mtrr;
  497. /* global gtt ops */
  498. int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
  499. size_t *stolen, phys_addr_t *mappable_base,
  500. unsigned long *mappable_end);
  501. };
  502. #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
  503. struct i915_hw_ppgtt {
  504. struct i915_address_space base;
  505. unsigned num_pd_entries;
  506. struct page **pt_pages;
  507. uint32_t pd_offset;
  508. dma_addr_t *pt_dma_addr;
  509. int (*enable)(struct drm_device *dev);
  510. };
  511. /**
  512. * A VMA represents a GEM BO that is bound into an address space. Therefore, a
  513. * VMA's presence cannot be guaranteed before binding, or after unbinding the
  514. * object into/from the address space.
  515. *
  516. * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
  517. * will always be <= an objects lifetime. So object refcounting should cover us.
  518. */
  519. struct i915_vma {
  520. struct drm_mm_node node;
  521. struct drm_i915_gem_object *obj;
  522. struct i915_address_space *vm;
  523. /** This object's place on the active/inactive lists */
  524. struct list_head mm_list;
  525. struct list_head vma_link; /* Link in the object's VMA list */
  526. /** This vma's place in the batchbuffer or on the eviction list */
  527. struct list_head exec_list;
  528. /**
  529. * Used for performing relocations during execbuffer insertion.
  530. */
  531. struct hlist_node exec_node;
  532. unsigned long exec_handle;
  533. struct drm_i915_gem_exec_object2 *exec_entry;
  534. };
  535. struct i915_ctx_hang_stats {
  536. /* This context had batch pending when hang was declared */
  537. unsigned batch_pending;
  538. /* This context had batch active when hang was declared */
  539. unsigned batch_active;
  540. /* Time when this context was last blamed for a GPU reset */
  541. unsigned long guilty_ts;
  542. /* This context is banned to submit more work */
  543. bool banned;
  544. };
  545. /* This must match up with the value previously used for execbuf2.rsvd1. */
  546. #define DEFAULT_CONTEXT_ID 0
  547. struct i915_hw_context {
  548. struct kref ref;
  549. int id;
  550. bool is_initialized;
  551. uint8_t remap_slice;
  552. struct drm_i915_file_private *file_priv;
  553. struct intel_ring_buffer *ring;
  554. struct drm_i915_gem_object *obj;
  555. struct i915_ctx_hang_stats hang_stats;
  556. struct list_head link;
  557. };
  558. struct i915_fbc {
  559. unsigned long size;
  560. unsigned int fb_id;
  561. enum plane plane;
  562. int y;
  563. struct drm_mm_node *compressed_fb;
  564. struct drm_mm_node *compressed_llb;
  565. struct intel_fbc_work {
  566. struct delayed_work work;
  567. struct drm_crtc *crtc;
  568. struct drm_framebuffer *fb;
  569. int interval;
  570. } *fbc_work;
  571. enum no_fbc_reason {
  572. FBC_OK, /* FBC is enabled */
  573. FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
  574. FBC_NO_OUTPUT, /* no outputs enabled to compress */
  575. FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
  576. FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  577. FBC_MODE_TOO_LARGE, /* mode too large for compression */
  578. FBC_BAD_PLANE, /* fbc not supported on plane */
  579. FBC_NOT_TILED, /* buffer not tiled */
  580. FBC_MULTIPLE_PIPES, /* more than one pipe active */
  581. FBC_MODULE_PARAM,
  582. FBC_CHIP_DEFAULT, /* disabled by default on this chip */
  583. } no_fbc_reason;
  584. };
  585. struct i915_psr {
  586. bool sink_support;
  587. bool source_ok;
  588. };
  589. enum intel_pch {
  590. PCH_NONE = 0, /* No PCH present */
  591. PCH_IBX, /* Ibexpeak PCH */
  592. PCH_CPT, /* Cougarpoint PCH */
  593. PCH_LPT, /* Lynxpoint PCH */
  594. PCH_NOP,
  595. };
  596. enum intel_sbi_destination {
  597. SBI_ICLK,
  598. SBI_MPHY,
  599. };
  600. #define QUIRK_PIPEA_FORCE (1<<0)
  601. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  602. #define QUIRK_INVERT_BRIGHTNESS (1<<2)
  603. #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
  604. struct intel_fbdev;
  605. struct intel_fbc_work;
  606. struct intel_gmbus {
  607. struct i2c_adapter adapter;
  608. u32 force_bit;
  609. u32 reg0;
  610. u32 gpio_reg;
  611. struct i2c_algo_bit_data bit_algo;
  612. struct drm_i915_private *dev_priv;
  613. };
  614. struct i915_suspend_saved_registers {
  615. u8 saveLBB;
  616. u32 saveDSPACNTR;
  617. u32 saveDSPBCNTR;
  618. u32 saveDSPARB;
  619. u32 savePIPEACONF;
  620. u32 savePIPEBCONF;
  621. u32 savePIPEASRC;
  622. u32 savePIPEBSRC;
  623. u32 saveFPA0;
  624. u32 saveFPA1;
  625. u32 saveDPLL_A;
  626. u32 saveDPLL_A_MD;
  627. u32 saveHTOTAL_A;
  628. u32 saveHBLANK_A;
  629. u32 saveHSYNC_A;
  630. u32 saveVTOTAL_A;
  631. u32 saveVBLANK_A;
  632. u32 saveVSYNC_A;
  633. u32 saveBCLRPAT_A;
  634. u32 saveTRANSACONF;
  635. u32 saveTRANS_HTOTAL_A;
  636. u32 saveTRANS_HBLANK_A;
  637. u32 saveTRANS_HSYNC_A;
  638. u32 saveTRANS_VTOTAL_A;
  639. u32 saveTRANS_VBLANK_A;
  640. u32 saveTRANS_VSYNC_A;
  641. u32 savePIPEASTAT;
  642. u32 saveDSPASTRIDE;
  643. u32 saveDSPASIZE;
  644. u32 saveDSPAPOS;
  645. u32 saveDSPAADDR;
  646. u32 saveDSPASURF;
  647. u32 saveDSPATILEOFF;
  648. u32 savePFIT_PGM_RATIOS;
  649. u32 saveBLC_HIST_CTL;
  650. u32 saveBLC_PWM_CTL;
  651. u32 saveBLC_PWM_CTL2;
  652. u32 saveBLC_CPU_PWM_CTL;
  653. u32 saveBLC_CPU_PWM_CTL2;
  654. u32 saveFPB0;
  655. u32 saveFPB1;
  656. u32 saveDPLL_B;
  657. u32 saveDPLL_B_MD;
  658. u32 saveHTOTAL_B;
  659. u32 saveHBLANK_B;
  660. u32 saveHSYNC_B;
  661. u32 saveVTOTAL_B;
  662. u32 saveVBLANK_B;
  663. u32 saveVSYNC_B;
  664. u32 saveBCLRPAT_B;
  665. u32 saveTRANSBCONF;
  666. u32 saveTRANS_HTOTAL_B;
  667. u32 saveTRANS_HBLANK_B;
  668. u32 saveTRANS_HSYNC_B;
  669. u32 saveTRANS_VTOTAL_B;
  670. u32 saveTRANS_VBLANK_B;
  671. u32 saveTRANS_VSYNC_B;
  672. u32 savePIPEBSTAT;
  673. u32 saveDSPBSTRIDE;
  674. u32 saveDSPBSIZE;
  675. u32 saveDSPBPOS;
  676. u32 saveDSPBADDR;
  677. u32 saveDSPBSURF;
  678. u32 saveDSPBTILEOFF;
  679. u32 saveVGA0;
  680. u32 saveVGA1;
  681. u32 saveVGA_PD;
  682. u32 saveVGACNTRL;
  683. u32 saveADPA;
  684. u32 saveLVDS;
  685. u32 savePP_ON_DELAYS;
  686. u32 savePP_OFF_DELAYS;
  687. u32 saveDVOA;
  688. u32 saveDVOB;
  689. u32 saveDVOC;
  690. u32 savePP_ON;
  691. u32 savePP_OFF;
  692. u32 savePP_CONTROL;
  693. u32 savePP_DIVISOR;
  694. u32 savePFIT_CONTROL;
  695. u32 save_palette_a[256];
  696. u32 save_palette_b[256];
  697. u32 saveDPFC_CB_BASE;
  698. u32 saveFBC_CFB_BASE;
  699. u32 saveFBC_LL_BASE;
  700. u32 saveFBC_CONTROL;
  701. u32 saveFBC_CONTROL2;
  702. u32 saveIER;
  703. u32 saveIIR;
  704. u32 saveIMR;
  705. u32 saveDEIER;
  706. u32 saveDEIMR;
  707. u32 saveGTIER;
  708. u32 saveGTIMR;
  709. u32 saveFDI_RXA_IMR;
  710. u32 saveFDI_RXB_IMR;
  711. u32 saveCACHE_MODE_0;
  712. u32 saveMI_ARB_STATE;
  713. u32 saveSWF0[16];
  714. u32 saveSWF1[16];
  715. u32 saveSWF2[3];
  716. u8 saveMSR;
  717. u8 saveSR[8];
  718. u8 saveGR[25];
  719. u8 saveAR_INDEX;
  720. u8 saveAR[21];
  721. u8 saveDACMASK;
  722. u8 saveCR[37];
  723. uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  724. u32 saveCURACNTR;
  725. u32 saveCURAPOS;
  726. u32 saveCURABASE;
  727. u32 saveCURBCNTR;
  728. u32 saveCURBPOS;
  729. u32 saveCURBBASE;
  730. u32 saveCURSIZE;
  731. u32 saveDP_B;
  732. u32 saveDP_C;
  733. u32 saveDP_D;
  734. u32 savePIPEA_GMCH_DATA_M;
  735. u32 savePIPEB_GMCH_DATA_M;
  736. u32 savePIPEA_GMCH_DATA_N;
  737. u32 savePIPEB_GMCH_DATA_N;
  738. u32 savePIPEA_DP_LINK_M;
  739. u32 savePIPEB_DP_LINK_M;
  740. u32 savePIPEA_DP_LINK_N;
  741. u32 savePIPEB_DP_LINK_N;
  742. u32 saveFDI_RXA_CTL;
  743. u32 saveFDI_TXA_CTL;
  744. u32 saveFDI_RXB_CTL;
  745. u32 saveFDI_TXB_CTL;
  746. u32 savePFA_CTL_1;
  747. u32 savePFB_CTL_1;
  748. u32 savePFA_WIN_SZ;
  749. u32 savePFB_WIN_SZ;
  750. u32 savePFA_WIN_POS;
  751. u32 savePFB_WIN_POS;
  752. u32 savePCH_DREF_CONTROL;
  753. u32 saveDISP_ARB_CTL;
  754. u32 savePIPEA_DATA_M1;
  755. u32 savePIPEA_DATA_N1;
  756. u32 savePIPEA_LINK_M1;
  757. u32 savePIPEA_LINK_N1;
  758. u32 savePIPEB_DATA_M1;
  759. u32 savePIPEB_DATA_N1;
  760. u32 savePIPEB_LINK_M1;
  761. u32 savePIPEB_LINK_N1;
  762. u32 saveMCHBAR_RENDER_STANDBY;
  763. u32 savePCH_PORT_HOTPLUG;
  764. };
  765. struct intel_gen6_power_mgmt {
  766. /* work and pm_iir are protected by dev_priv->irq_lock */
  767. struct work_struct work;
  768. u32 pm_iir;
  769. /* The below variables an all the rps hw state are protected by
  770. * dev->struct mutext. */
  771. u8 cur_delay;
  772. u8 min_delay;
  773. u8 max_delay;
  774. u8 rpe_delay;
  775. u8 rp1_delay;
  776. u8 rp0_delay;
  777. u8 hw_max;
  778. int last_adj;
  779. enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
  780. bool enabled;
  781. struct delayed_work delayed_resume_work;
  782. /*
  783. * Protects RPS/RC6 register access and PCU communication.
  784. * Must be taken after struct_mutex if nested.
  785. */
  786. struct mutex hw_lock;
  787. };
  788. /* defined intel_pm.c */
  789. extern spinlock_t mchdev_lock;
  790. struct intel_ilk_power_mgmt {
  791. u8 cur_delay;
  792. u8 min_delay;
  793. u8 max_delay;
  794. u8 fmax;
  795. u8 fstart;
  796. u64 last_count1;
  797. unsigned long last_time1;
  798. unsigned long chipset_power;
  799. u64 last_count2;
  800. struct timespec last_time2;
  801. unsigned long gfx_power;
  802. u8 corr;
  803. int c_m;
  804. int r_t;
  805. struct drm_i915_gem_object *pwrctx;
  806. struct drm_i915_gem_object *renderctx;
  807. };
  808. /* Power well structure for haswell */
  809. struct i915_power_well {
  810. struct drm_device *device;
  811. struct mutex lock;
  812. /* power well enable/disable usage count */
  813. int count;
  814. int i915_request;
  815. };
  816. struct i915_dri1_state {
  817. unsigned allow_batchbuffer : 1;
  818. u32 __iomem *gfx_hws_cpu_addr;
  819. unsigned int cpp;
  820. int back_offset;
  821. int front_offset;
  822. int current_page;
  823. int page_flipping;
  824. uint32_t counter;
  825. };
  826. struct i915_ums_state {
  827. /**
  828. * Flag if the X Server, and thus DRM, is not currently in
  829. * control of the device.
  830. *
  831. * This is set between LeaveVT and EnterVT. It needs to be
  832. * replaced with a semaphore. It also needs to be
  833. * transitioned away from for kernel modesetting.
  834. */
  835. int mm_suspended;
  836. };
  837. #define MAX_L3_SLICES 2
  838. struct intel_l3_parity {
  839. u32 *remap_info[MAX_L3_SLICES];
  840. struct work_struct error_work;
  841. int which_slice;
  842. };
  843. struct i915_gem_mm {
  844. /** Memory allocator for GTT stolen memory */
  845. struct drm_mm stolen;
  846. /** List of all objects in gtt_space. Used to restore gtt
  847. * mappings on resume */
  848. struct list_head bound_list;
  849. /**
  850. * List of objects which are not bound to the GTT (thus
  851. * are idle and not used by the GPU) but still have
  852. * (presumably uncached) pages still attached.
  853. */
  854. struct list_head unbound_list;
  855. /** Usable portion of the GTT for GEM */
  856. unsigned long stolen_base; /* limited to low memory (32-bit) */
  857. /** PPGTT used for aliasing the PPGTT with the GTT */
  858. struct i915_hw_ppgtt *aliasing_ppgtt;
  859. struct shrinker inactive_shrinker;
  860. bool shrinker_no_lock_stealing;
  861. /** LRU list of objects with fence regs on them. */
  862. struct list_head fence_list;
  863. /**
  864. * We leave the user IRQ off as much as possible,
  865. * but this means that requests will finish and never
  866. * be retired once the system goes idle. Set a timer to
  867. * fire periodically while the ring is running. When it
  868. * fires, go retire requests.
  869. */
  870. struct delayed_work retire_work;
  871. /**
  872. * When we detect an idle GPU, we want to turn on
  873. * powersaving features. So once we see that there
  874. * are no more requests outstanding and no more
  875. * arrive within a small period of time, we fire
  876. * off the idle_work.
  877. */
  878. struct delayed_work idle_work;
  879. /**
  880. * Are we in a non-interruptible section of code like
  881. * modesetting?
  882. */
  883. bool interruptible;
  884. /** Bit 6 swizzling required for X tiling */
  885. uint32_t bit_6_swizzle_x;
  886. /** Bit 6 swizzling required for Y tiling */
  887. uint32_t bit_6_swizzle_y;
  888. /* storage for physical objects */
  889. struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  890. /* accounting, useful for userland debugging */
  891. spinlock_t object_stat_lock;
  892. size_t object_memory;
  893. u32 object_count;
  894. };
  895. struct drm_i915_error_state_buf {
  896. unsigned bytes;
  897. unsigned size;
  898. int err;
  899. u8 *buf;
  900. loff_t start;
  901. loff_t pos;
  902. };
  903. struct i915_error_state_file_priv {
  904. struct drm_device *dev;
  905. struct drm_i915_error_state *error;
  906. };
  907. struct i915_gpu_error {
  908. /* For hangcheck timer */
  909. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  910. #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
  911. /* Hang gpu twice in this window and your context gets banned */
  912. #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
  913. struct timer_list hangcheck_timer;
  914. /* For reset and error_state handling. */
  915. spinlock_t lock;
  916. /* Protected by the above dev->gpu_error.lock. */
  917. struct drm_i915_error_state *first_error;
  918. struct work_struct work;
  919. unsigned long missed_irq_rings;
  920. /**
  921. * State variable and reset counter controlling the reset flow
  922. *
  923. * Upper bits are for the reset counter. This counter is used by the
  924. * wait_seqno code to race-free noticed that a reset event happened and
  925. * that it needs to restart the entire ioctl (since most likely the
  926. * seqno it waited for won't ever signal anytime soon).
  927. *
  928. * This is important for lock-free wait paths, where no contended lock
  929. * naturally enforces the correct ordering between the bail-out of the
  930. * waiter and the gpu reset work code.
  931. *
  932. * Lowest bit controls the reset state machine: Set means a reset is in
  933. * progress. This state will (presuming we don't have any bugs) decay
  934. * into either unset (successful reset) or the special WEDGED value (hw
  935. * terminally sour). All waiters on the reset_queue will be woken when
  936. * that happens.
  937. */
  938. atomic_t reset_counter;
  939. /**
  940. * Special values/flags for reset_counter
  941. *
  942. * Note that the code relies on
  943. * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
  944. * being true.
  945. */
  946. #define I915_RESET_IN_PROGRESS_FLAG 1
  947. #define I915_WEDGED 0xffffffff
  948. /**
  949. * Waitqueue to signal when the reset has completed. Used by clients
  950. * that wait for dev_priv->mm.wedged to settle.
  951. */
  952. wait_queue_head_t reset_queue;
  953. /* For gpu hang simulation. */
  954. unsigned int stop_rings;
  955. /* For missed irq/seqno simulation. */
  956. unsigned int test_irq_rings;
  957. };
  958. enum modeset_restore {
  959. MODESET_ON_LID_OPEN,
  960. MODESET_DONE,
  961. MODESET_SUSPENDED,
  962. };
  963. struct ddi_vbt_port_info {
  964. uint8_t hdmi_level_shift;
  965. uint8_t supports_dvi:1;
  966. uint8_t supports_hdmi:1;
  967. uint8_t supports_dp:1;
  968. };
  969. struct intel_vbt_data {
  970. struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  971. struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  972. /* Feature bits */
  973. unsigned int int_tv_support:1;
  974. unsigned int lvds_dither:1;
  975. unsigned int lvds_vbt:1;
  976. unsigned int int_crt_support:1;
  977. unsigned int lvds_use_ssc:1;
  978. unsigned int display_clock_mode:1;
  979. unsigned int fdi_rx_polarity_inverted:1;
  980. int lvds_ssc_freq;
  981. unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
  982. /* eDP */
  983. int edp_rate;
  984. int edp_lanes;
  985. int edp_preemphasis;
  986. int edp_vswing;
  987. bool edp_initialized;
  988. bool edp_support;
  989. int edp_bpp;
  990. struct edp_power_seq edp_pps;
  991. /* MIPI DSI */
  992. struct {
  993. u16 panel_id;
  994. } dsi;
  995. int crt_ddc_pin;
  996. int child_dev_num;
  997. union child_device_config *child_dev;
  998. struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
  999. };
  1000. enum intel_ddb_partitioning {
  1001. INTEL_DDB_PART_1_2,
  1002. INTEL_DDB_PART_5_6, /* IVB+ */
  1003. };
  1004. struct intel_wm_level {
  1005. bool enable;
  1006. uint32_t pri_val;
  1007. uint32_t spr_val;
  1008. uint32_t cur_val;
  1009. uint32_t fbc_val;
  1010. };
  1011. struct hsw_wm_values {
  1012. uint32_t wm_pipe[3];
  1013. uint32_t wm_lp[3];
  1014. uint32_t wm_lp_spr[3];
  1015. uint32_t wm_linetime[3];
  1016. bool enable_fbc_wm;
  1017. enum intel_ddb_partitioning partitioning;
  1018. };
  1019. /*
  1020. * This struct tracks the state needed for the Package C8+ feature.
  1021. *
  1022. * Package states C8 and deeper are really deep PC states that can only be
  1023. * reached when all the devices on the system allow it, so even if the graphics
  1024. * device allows PC8+, it doesn't mean the system will actually get to these
  1025. * states.
  1026. *
  1027. * Our driver only allows PC8+ when all the outputs are disabled, the power well
  1028. * is disabled and the GPU is idle. When these conditions are met, we manually
  1029. * do the other conditions: disable the interrupts, clocks and switch LCPLL
  1030. * refclk to Fclk.
  1031. *
  1032. * When we really reach PC8 or deeper states (not just when we allow it) we lose
  1033. * the state of some registers, so when we come back from PC8+ we need to
  1034. * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
  1035. * need to take care of the registers kept by RC6.
  1036. *
  1037. * The interrupt disabling is part of the requirements. We can only leave the
  1038. * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
  1039. * can lock the machine.
  1040. *
  1041. * Ideally every piece of our code that needs PC8+ disabled would call
  1042. * hsw_disable_package_c8, which would increment disable_count and prevent the
  1043. * system from reaching PC8+. But we don't have a symmetric way to do this for
  1044. * everything, so we have the requirements_met and gpu_idle variables. When we
  1045. * switch requirements_met or gpu_idle to true we decrease disable_count, and
  1046. * increase it in the opposite case. The requirements_met variable is true when
  1047. * all the CRTCs, encoders and the power well are disabled. The gpu_idle
  1048. * variable is true when the GPU is idle.
  1049. *
  1050. * In addition to everything, we only actually enable PC8+ if disable_count
  1051. * stays at zero for at least some seconds. This is implemented with the
  1052. * enable_work variable. We do this so we don't enable/disable PC8 dozens of
  1053. * consecutive times when all screens are disabled and some background app
  1054. * queries the state of our connectors, or we have some application constantly
  1055. * waking up to use the GPU. Only after the enable_work function actually
  1056. * enables PC8+ the "enable" variable will become true, which means that it can
  1057. * be false even if disable_count is 0.
  1058. *
  1059. * The irqs_disabled variable becomes true exactly after we disable the IRQs and
  1060. * goes back to false exactly before we reenable the IRQs. We use this variable
  1061. * to check if someone is trying to enable/disable IRQs while they're supposed
  1062. * to be disabled. This shouldn't happen and we'll print some error messages in
  1063. * case it happens, but if it actually happens we'll also update the variables
  1064. * inside struct regsave so when we restore the IRQs they will contain the
  1065. * latest expected values.
  1066. *
  1067. * For more, read "Display Sequences for Package C8" on our documentation.
  1068. */
  1069. struct i915_package_c8 {
  1070. bool requirements_met;
  1071. bool gpu_idle;
  1072. bool irqs_disabled;
  1073. /* Only true after the delayed work task actually enables it. */
  1074. bool enabled;
  1075. int disable_count;
  1076. struct mutex lock;
  1077. struct delayed_work enable_work;
  1078. struct {
  1079. uint32_t deimr;
  1080. uint32_t sdeimr;
  1081. uint32_t gtimr;
  1082. uint32_t gtier;
  1083. uint32_t gen6_pmimr;
  1084. } regsave;
  1085. };
  1086. enum intel_pipe_crc_source {
  1087. INTEL_PIPE_CRC_SOURCE_NONE,
  1088. INTEL_PIPE_CRC_SOURCE_PLANE1,
  1089. INTEL_PIPE_CRC_SOURCE_PLANE2,
  1090. INTEL_PIPE_CRC_SOURCE_PF,
  1091. INTEL_PIPE_CRC_SOURCE_PIPE,
  1092. /* TV/DP on pre-gen5/vlv can't use the pipe source. */
  1093. INTEL_PIPE_CRC_SOURCE_TV,
  1094. INTEL_PIPE_CRC_SOURCE_DP_B,
  1095. INTEL_PIPE_CRC_SOURCE_DP_C,
  1096. INTEL_PIPE_CRC_SOURCE_DP_D,
  1097. INTEL_PIPE_CRC_SOURCE_MAX,
  1098. };
  1099. struct intel_pipe_crc_entry {
  1100. uint32_t frame;
  1101. uint32_t crc[5];
  1102. };
  1103. #define INTEL_PIPE_CRC_ENTRIES_NR 128
  1104. struct intel_pipe_crc {
  1105. atomic_t available; /* exclusive access to the device */
  1106. struct intel_pipe_crc_entry *entries;
  1107. enum intel_pipe_crc_source source;
  1108. atomic_t head, tail;
  1109. wait_queue_head_t wq;
  1110. };
  1111. typedef struct drm_i915_private {
  1112. struct drm_device *dev;
  1113. struct kmem_cache *slab;
  1114. const struct intel_device_info *info;
  1115. int relative_constants_mode;
  1116. void __iomem *regs;
  1117. struct intel_uncore uncore;
  1118. struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
  1119. /** gmbus_mutex protects against concurrent usage of the single hw gmbus
  1120. * controller on different i2c buses. */
  1121. struct mutex gmbus_mutex;
  1122. /**
  1123. * Base address of the gmbus and gpio block.
  1124. */
  1125. uint32_t gpio_mmio_base;
  1126. wait_queue_head_t gmbus_wait_queue;
  1127. struct pci_dev *bridge_dev;
  1128. struct intel_ring_buffer ring[I915_NUM_RINGS];
  1129. uint32_t last_seqno, next_seqno;
  1130. drm_dma_handle_t *status_page_dmah;
  1131. struct resource mch_res;
  1132. atomic_t irq_received;
  1133. /* protects the irq masks */
  1134. spinlock_t irq_lock;
  1135. /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
  1136. struct pm_qos_request pm_qos;
  1137. /* DPIO indirect register protection */
  1138. struct mutex dpio_lock;
  1139. /** Cached value of IMR to avoid reads in updating the bitfield */
  1140. u32 irq_mask;
  1141. u32 gt_irq_mask;
  1142. u32 pm_irq_mask;
  1143. struct work_struct hotplug_work;
  1144. bool enable_hotplug_processing;
  1145. struct {
  1146. unsigned long hpd_last_jiffies;
  1147. int hpd_cnt;
  1148. enum {
  1149. HPD_ENABLED = 0,
  1150. HPD_DISABLED = 1,
  1151. HPD_MARK_DISABLED = 2
  1152. } hpd_mark;
  1153. } hpd_stats[HPD_NUM_PINS];
  1154. u32 hpd_event_bits;
  1155. struct timer_list hotplug_reenable_timer;
  1156. int num_plane;
  1157. struct i915_fbc fbc;
  1158. struct intel_opregion opregion;
  1159. struct intel_vbt_data vbt;
  1160. /* overlay */
  1161. struct intel_overlay *overlay;
  1162. unsigned int sprite_scaling_enabled;
  1163. /* backlight */
  1164. struct {
  1165. int level;
  1166. bool enabled;
  1167. spinlock_t lock; /* bl registers and the above bl fields */
  1168. struct backlight_device *device;
  1169. } backlight;
  1170. /* LVDS info */
  1171. bool no_aux_handshake;
  1172. struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  1173. int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  1174. int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  1175. unsigned int fsb_freq, mem_freq, is_ddr3;
  1176. /**
  1177. * wq - Driver workqueue for GEM.
  1178. *
  1179. * NOTE: Work items scheduled here are not allowed to grab any modeset
  1180. * locks, for otherwise the flushing done in the pageflip code will
  1181. * result in deadlocks.
  1182. */
  1183. struct workqueue_struct *wq;
  1184. /* Display functions */
  1185. struct drm_i915_display_funcs display;
  1186. /* PCH chipset type */
  1187. enum intel_pch pch_type;
  1188. unsigned short pch_id;
  1189. unsigned long quirks;
  1190. enum modeset_restore modeset_restore;
  1191. struct mutex modeset_restore_lock;
  1192. struct list_head vm_list; /* Global list of all address spaces */
  1193. struct i915_gtt gtt; /* VMA representing the global address space */
  1194. struct i915_gem_mm mm;
  1195. /* Kernel Modesetting */
  1196. struct sdvo_device_mapping sdvo_mappings[2];
  1197. struct drm_crtc *plane_to_crtc_mapping[3];
  1198. struct drm_crtc *pipe_to_crtc_mapping[3];
  1199. wait_queue_head_t pending_flip_queue;
  1200. int num_shared_dpll;
  1201. struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
  1202. struct intel_ddi_plls ddi_plls;
  1203. /* Reclocking support */
  1204. bool render_reclock_avail;
  1205. bool lvds_downclock_avail;
  1206. /* indicates the reduced downclock for LVDS*/
  1207. int lvds_downclock;
  1208. u16 orig_clock;
  1209. bool mchbar_need_disable;
  1210. struct intel_l3_parity l3_parity;
  1211. /* Cannot be determined by PCIID. You must always read a register. */
  1212. size_t ellc_size;
  1213. /* gen6+ rps state */
  1214. struct intel_gen6_power_mgmt rps;
  1215. /* ilk-only ips/rps state. Everything in here is protected by the global
  1216. * mchdev_lock in intel_pm.c */
  1217. struct intel_ilk_power_mgmt ips;
  1218. /* Haswell power well */
  1219. struct i915_power_well power_well;
  1220. struct i915_psr psr;
  1221. struct i915_gpu_error gpu_error;
  1222. struct drm_i915_gem_object *vlv_pctx;
  1223. #ifdef CONFIG_DRM_I915_FBDEV
  1224. /* list of fbdev register on this device */
  1225. struct intel_fbdev *fbdev;
  1226. #endif
  1227. /*
  1228. * The console may be contended at resume, but we don't
  1229. * want it to block on it.
  1230. */
  1231. struct work_struct console_resume_work;
  1232. struct drm_property *broadcast_rgb_property;
  1233. struct drm_property *force_audio_property;
  1234. bool hw_contexts_disabled;
  1235. uint32_t hw_context_size;
  1236. struct list_head context_list;
  1237. u32 fdi_rx_config;
  1238. struct i915_suspend_saved_registers regfile;
  1239. struct {
  1240. /*
  1241. * Raw watermark latency values:
  1242. * in 0.1us units for WM0,
  1243. * in 0.5us units for WM1+.
  1244. */
  1245. /* primary */
  1246. uint16_t pri_latency[5];
  1247. /* sprite */
  1248. uint16_t spr_latency[5];
  1249. /* cursor */
  1250. uint16_t cur_latency[5];
  1251. /* current hardware state */
  1252. struct hsw_wm_values hw;
  1253. } wm;
  1254. struct i915_package_c8 pc8;
  1255. /* Old dri1 support infrastructure, beware the dragons ya fools entering
  1256. * here! */
  1257. struct i915_dri1_state dri1;
  1258. /* Old ums support infrastructure, same warning applies. */
  1259. struct i915_ums_state ums;
  1260. #ifdef CONFIG_DEBUG_FS
  1261. struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
  1262. #endif
  1263. } drm_i915_private_t;
  1264. static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
  1265. {
  1266. return dev->dev_private;
  1267. }
  1268. /* Iterate over initialised rings */
  1269. #define for_each_ring(ring__, dev_priv__, i__) \
  1270. for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
  1271. if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
  1272. enum hdmi_force_audio {
  1273. HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
  1274. HDMI_AUDIO_OFF, /* force turn off HDMI audio */
  1275. HDMI_AUDIO_AUTO, /* trust EDID */
  1276. HDMI_AUDIO_ON, /* force turn on HDMI audio */
  1277. };
  1278. #define I915_GTT_OFFSET_NONE ((u32)-1)
  1279. struct drm_i915_gem_object_ops {
  1280. /* Interface between the GEM object and its backing storage.
  1281. * get_pages() is called once prior to the use of the associated set
  1282. * of pages before to binding them into the GTT, and put_pages() is
  1283. * called after we no longer need them. As we expect there to be
  1284. * associated cost with migrating pages between the backing storage
  1285. * and making them available for the GPU (e.g. clflush), we may hold
  1286. * onto the pages after they are no longer referenced by the GPU
  1287. * in case they may be used again shortly (for example migrating the
  1288. * pages to a different memory domain within the GTT). put_pages()
  1289. * will therefore most likely be called when the object itself is
  1290. * being released or under memory pressure (where we attempt to
  1291. * reap pages for the shrinker).
  1292. */
  1293. int (*get_pages)(struct drm_i915_gem_object *);
  1294. void (*put_pages)(struct drm_i915_gem_object *);
  1295. };
  1296. struct drm_i915_gem_object {
  1297. struct drm_gem_object base;
  1298. const struct drm_i915_gem_object_ops *ops;
  1299. /** List of VMAs backed by this object */
  1300. struct list_head vma_list;
  1301. /** Stolen memory for this object, instead of being backed by shmem. */
  1302. struct drm_mm_node *stolen;
  1303. struct list_head global_list;
  1304. struct list_head ring_list;
  1305. /** Used in execbuf to temporarily hold a ref */
  1306. struct list_head obj_exec_link;
  1307. /**
  1308. * This is set if the object is on the active lists (has pending
  1309. * rendering and so a non-zero seqno), and is not set if it i s on
  1310. * inactive (ready to be unbound) list.
  1311. */
  1312. unsigned int active:1;
  1313. /**
  1314. * This is set if the object has been written to since last bound
  1315. * to the GTT
  1316. */
  1317. unsigned int dirty:1;
  1318. /**
  1319. * Fence register bits (if any) for this object. Will be set
  1320. * as needed when mapped into the GTT.
  1321. * Protected by dev->struct_mutex.
  1322. */
  1323. signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  1324. /**
  1325. * Advice: are the backing pages purgeable?
  1326. */
  1327. unsigned int madv:2;
  1328. /**
  1329. * Current tiling mode for the object.
  1330. */
  1331. unsigned int tiling_mode:2;
  1332. /**
  1333. * Whether the tiling parameters for the currently associated fence
  1334. * register have changed. Note that for the purposes of tracking
  1335. * tiling changes we also treat the unfenced register, the register
  1336. * slot that the object occupies whilst it executes a fenced
  1337. * command (such as BLT on gen2/3), as a "fence".
  1338. */
  1339. unsigned int fence_dirty:1;
  1340. /** How many users have pinned this object in GTT space. The following
  1341. * users can each hold at most one reference: pwrite/pread, pin_ioctl
  1342. * (via user_pin_count), execbuffer (objects are not allowed multiple
  1343. * times for the same batchbuffer), and the framebuffer code. When
  1344. * switching/pageflipping, the framebuffer code has at most two buffers
  1345. * pinned per crtc.
  1346. *
  1347. * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  1348. * bits with absolutely no headroom. So use 4 bits. */
  1349. unsigned int pin_count:4;
  1350. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  1351. /**
  1352. * Is the object at the current location in the gtt mappable and
  1353. * fenceable? Used to avoid costly recalculations.
  1354. */
  1355. unsigned int map_and_fenceable:1;
  1356. /**
  1357. * Whether the current gtt mapping needs to be mappable (and isn't just
  1358. * mappable by accident). Track pin and fault separate for a more
  1359. * accurate mappable working set.
  1360. */
  1361. unsigned int fault_mappable:1;
  1362. unsigned int pin_mappable:1;
  1363. unsigned int pin_display:1;
  1364. /*
  1365. * Is the GPU currently using a fence to access this buffer,
  1366. */
  1367. unsigned int pending_fenced_gpu_access:1;
  1368. unsigned int fenced_gpu_access:1;
  1369. unsigned int cache_level:3;
  1370. unsigned int has_aliasing_ppgtt_mapping:1;
  1371. unsigned int has_global_gtt_mapping:1;
  1372. unsigned int has_dma_mapping:1;
  1373. struct sg_table *pages;
  1374. int pages_pin_count;
  1375. /* prime dma-buf support */
  1376. void *dma_buf_vmapping;
  1377. int vmapping_count;
  1378. struct intel_ring_buffer *ring;
  1379. /** Breadcrumb of last rendering to the buffer. */
  1380. uint32_t last_read_seqno;
  1381. uint32_t last_write_seqno;
  1382. /** Breadcrumb of last fenced GPU access to the buffer. */
  1383. uint32_t last_fenced_seqno;
  1384. /** Current tiling stride for the object, if it's tiled. */
  1385. uint32_t stride;
  1386. /** References from framebuffers, locks out tiling changes. */
  1387. unsigned long framebuffer_references;
  1388. /** Record of address bit 17 of each page at last unbind. */
  1389. unsigned long *bit_17;
  1390. /** User space pin count and filp owning the pin */
  1391. unsigned long user_pin_count;
  1392. struct drm_file *pin_filp;
  1393. /** for phy allocated objects */
  1394. struct drm_i915_gem_phys_object *phys_obj;
  1395. };
  1396. #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
  1397. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  1398. /**
  1399. * Request queue structure.
  1400. *
  1401. * The request queue allows us to note sequence numbers that have been emitted
  1402. * and may be associated with active buffers to be retired.
  1403. *
  1404. * By keeping this list, we can avoid having to do questionable
  1405. * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  1406. * an emission time with seqnos for tracking how far ahead of the GPU we are.
  1407. */
  1408. struct drm_i915_gem_request {
  1409. /** On Which ring this request was generated */
  1410. struct intel_ring_buffer *ring;
  1411. /** GEM sequence number associated with this request. */
  1412. uint32_t seqno;
  1413. /** Position in the ringbuffer of the start of the request */
  1414. u32 head;
  1415. /** Position in the ringbuffer of the end of the request */
  1416. u32 tail;
  1417. /** Context related to this request */
  1418. struct i915_hw_context *ctx;
  1419. /** Batch buffer related to this request if any */
  1420. struct drm_i915_gem_object *batch_obj;
  1421. /** Time at which this request was emitted, in jiffies. */
  1422. unsigned long emitted_jiffies;
  1423. /** global list entry for this request */
  1424. struct list_head list;
  1425. struct drm_i915_file_private *file_priv;
  1426. /** file_priv list entry for this request */
  1427. struct list_head client_list;
  1428. };
  1429. struct drm_i915_file_private {
  1430. struct drm_i915_private *dev_priv;
  1431. struct {
  1432. spinlock_t lock;
  1433. struct list_head request_list;
  1434. struct delayed_work idle_work;
  1435. } mm;
  1436. struct idr context_idr;
  1437. struct i915_ctx_hang_stats hang_stats;
  1438. atomic_t rps_wait_boost;
  1439. };
  1440. #define INTEL_INFO(dev) (to_i915(dev)->info)
  1441. #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
  1442. #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
  1443. #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
  1444. #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
  1445. #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
  1446. #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
  1447. #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
  1448. #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
  1449. #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
  1450. #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
  1451. #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
  1452. #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
  1453. #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
  1454. #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
  1455. #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
  1456. #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
  1457. #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
  1458. #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
  1459. #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
  1460. (dev)->pdev->device == 0x0152 || \
  1461. (dev)->pdev->device == 0x015a)
  1462. #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
  1463. (dev)->pdev->device == 0x0106 || \
  1464. (dev)->pdev->device == 0x010A)
  1465. #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
  1466. #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
  1467. #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
  1468. #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
  1469. ((dev)->pdev->device & 0xFF00) == 0x0C00)
  1470. #define IS_ULT(dev) (IS_HASWELL(dev) && \
  1471. ((dev)->pdev->device & 0xFF00) == 0x0A00)
  1472. #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
  1473. ((dev)->pdev->device & 0x00F0) == 0x0020)
  1474. #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
  1475. /*
  1476. * The genX designation typically refers to the render engine, so render
  1477. * capability related checks should use IS_GEN, while display and other checks
  1478. * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  1479. * chips, etc.).
  1480. */
  1481. #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
  1482. #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
  1483. #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
  1484. #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
  1485. #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
  1486. #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
  1487. #define RENDER_RING (1<<RCS)
  1488. #define BSD_RING (1<<VCS)
  1489. #define BLT_RING (1<<BCS)
  1490. #define VEBOX_RING (1<<VECS)
  1491. #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
  1492. #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
  1493. #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
  1494. #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
  1495. #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
  1496. #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
  1497. #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
  1498. #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
  1499. #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
  1500. #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
  1501. /* Early gen2 have a totally busted CS tlb and require pinned batches. */
  1502. #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
  1503. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  1504. * rows, which changed the alignment requirements and fence programming.
  1505. */
  1506. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  1507. IS_I915GM(dev)))
  1508. #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  1509. #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
  1510. #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
  1511. #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
  1512. #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
  1513. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  1514. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  1515. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  1516. #define HAS_IPS(dev) (IS_ULT(dev))
  1517. #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
  1518. #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
  1519. #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
  1520. #define HAS_PSR(dev) (IS_HASWELL(dev))
  1521. #define INTEL_PCH_DEVICE_ID_MASK 0xff00
  1522. #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
  1523. #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
  1524. #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
  1525. #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
  1526. #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
  1527. #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
  1528. #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
  1529. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1530. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  1531. #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
  1532. #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
  1533. /* DPF == dynamic parity feature */
  1534. #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  1535. #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
  1536. #define GT_FREQUENCY_MULTIPLIER 50
  1537. #include "i915_trace.h"
  1538. extern const struct drm_ioctl_desc i915_ioctls[];
  1539. extern int i915_max_ioctl;
  1540. extern unsigned int i915_fbpercrtc __always_unused;
  1541. extern int i915_panel_ignore_lid __read_mostly;
  1542. extern unsigned int i915_powersave __read_mostly;
  1543. extern int i915_semaphores __read_mostly;
  1544. extern unsigned int i915_lvds_downclock __read_mostly;
  1545. extern int i915_lvds_channel_mode __read_mostly;
  1546. extern int i915_panel_use_ssc __read_mostly;
  1547. extern int i915_vbt_sdvo_panel_type __read_mostly;
  1548. extern int i915_enable_rc6 __read_mostly;
  1549. extern int i915_enable_fbc __read_mostly;
  1550. extern bool i915_enable_hangcheck __read_mostly;
  1551. extern int i915_enable_ppgtt __read_mostly;
  1552. extern int i915_enable_psr __read_mostly;
  1553. extern unsigned int i915_preliminary_hw_support __read_mostly;
  1554. extern int i915_disable_power_well __read_mostly;
  1555. extern int i915_enable_ips __read_mostly;
  1556. extern bool i915_fastboot __read_mostly;
  1557. extern int i915_enable_pc8 __read_mostly;
  1558. extern int i915_pc8_timeout __read_mostly;
  1559. extern bool i915_prefault_disable __read_mostly;
  1560. extern int i915_suspend(struct drm_device *dev, pm_message_t state);
  1561. extern int i915_resume(struct drm_device *dev);
  1562. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  1563. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  1564. /* i915_dma.c */
  1565. void i915_update_dri1_breadcrumb(struct drm_device *dev);
  1566. extern void i915_kernel_lost_context(struct drm_device * dev);
  1567. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  1568. extern int i915_driver_unload(struct drm_device *);
  1569. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  1570. extern void i915_driver_lastclose(struct drm_device * dev);
  1571. extern void i915_driver_preclose(struct drm_device *dev,
  1572. struct drm_file *file_priv);
  1573. extern void i915_driver_postclose(struct drm_device *dev,
  1574. struct drm_file *file_priv);
  1575. extern int i915_driver_device_is_agp(struct drm_device * dev);
  1576. #ifdef CONFIG_COMPAT
  1577. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  1578. unsigned long arg);
  1579. #endif
  1580. extern int i915_emit_box(struct drm_device *dev,
  1581. struct drm_clip_rect *box,
  1582. int DR1, int DR4);
  1583. extern int intel_gpu_reset(struct drm_device *dev);
  1584. extern int i915_reset(struct drm_device *dev);
  1585. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  1586. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  1587. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  1588. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  1589. extern void intel_console_resume(struct work_struct *work);
  1590. /* i915_irq.c */
  1591. void i915_queue_hangcheck(struct drm_device *dev);
  1592. void i915_handle_error(struct drm_device *dev, bool wedged);
  1593. extern void intel_irq_init(struct drm_device *dev);
  1594. extern void intel_pm_init(struct drm_device *dev);
  1595. extern void intel_hpd_init(struct drm_device *dev);
  1596. extern void intel_pm_init(struct drm_device *dev);
  1597. extern void intel_uncore_sanitize(struct drm_device *dev);
  1598. extern void intel_uncore_early_sanitize(struct drm_device *dev);
  1599. extern void intel_uncore_init(struct drm_device *dev);
  1600. extern void intel_uncore_clear_errors(struct drm_device *dev);
  1601. extern void intel_uncore_check_errors(struct drm_device *dev);
  1602. extern void intel_uncore_fini(struct drm_device *dev);
  1603. void
  1604. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1605. void
  1606. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1607. /* i915_gem.c */
  1608. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  1609. struct drm_file *file_priv);
  1610. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  1611. struct drm_file *file_priv);
  1612. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  1613. struct drm_file *file_priv);
  1614. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  1615. struct drm_file *file_priv);
  1616. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1617. struct drm_file *file_priv);
  1618. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1619. struct drm_file *file_priv);
  1620. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1621. struct drm_file *file_priv);
  1622. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1623. struct drm_file *file_priv);
  1624. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  1625. struct drm_file *file_priv);
  1626. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1627. struct drm_file *file_priv);
  1628. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  1629. struct drm_file *file_priv);
  1630. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  1631. struct drm_file *file_priv);
  1632. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  1633. struct drm_file *file_priv);
  1634. int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
  1635. struct drm_file *file);
  1636. int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  1637. struct drm_file *file);
  1638. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  1639. struct drm_file *file_priv);
  1640. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  1641. struct drm_file *file_priv);
  1642. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  1643. struct drm_file *file_priv);
  1644. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  1645. struct drm_file *file_priv);
  1646. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  1647. struct drm_file *file_priv);
  1648. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  1649. struct drm_file *file_priv);
  1650. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  1651. struct drm_file *file_priv);
  1652. int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
  1653. struct drm_file *file_priv);
  1654. void i915_gem_load(struct drm_device *dev);
  1655. void *i915_gem_object_alloc(struct drm_device *dev);
  1656. void i915_gem_object_free(struct drm_i915_gem_object *obj);
  1657. void i915_gem_object_init(struct drm_i915_gem_object *obj,
  1658. const struct drm_i915_gem_object_ops *ops);
  1659. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  1660. size_t size);
  1661. void i915_gem_free_object(struct drm_gem_object *obj);
  1662. void i915_gem_vma_destroy(struct i915_vma *vma);
  1663. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  1664. struct i915_address_space *vm,
  1665. uint32_t alignment,
  1666. bool map_and_fenceable,
  1667. bool nonblocking);
  1668. void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
  1669. int __must_check i915_vma_unbind(struct i915_vma *vma);
  1670. int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
  1671. int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
  1672. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  1673. void i915_gem_lastclose(struct drm_device *dev);
  1674. int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
  1675. static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
  1676. {
  1677. struct sg_page_iter sg_iter;
  1678. for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
  1679. return sg_page_iter_page(&sg_iter);
  1680. return NULL;
  1681. }
  1682. static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
  1683. {
  1684. BUG_ON(obj->pages == NULL);
  1685. obj->pages_pin_count++;
  1686. }
  1687. static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
  1688. {
  1689. BUG_ON(obj->pages_pin_count == 0);
  1690. obj->pages_pin_count--;
  1691. }
  1692. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  1693. int i915_gem_object_sync(struct drm_i915_gem_object *obj,
  1694. struct intel_ring_buffer *to);
  1695. void i915_vma_move_to_active(struct i915_vma *vma,
  1696. struct intel_ring_buffer *ring);
  1697. int i915_gem_dumb_create(struct drm_file *file_priv,
  1698. struct drm_device *dev,
  1699. struct drm_mode_create_dumb *args);
  1700. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  1701. uint32_t handle, uint64_t *offset);
  1702. /**
  1703. * Returns true if seq1 is later than seq2.
  1704. */
  1705. static inline bool
  1706. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  1707. {
  1708. return (int32_t)(seq1 - seq2) >= 0;
  1709. }
  1710. int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
  1711. int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
  1712. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
  1713. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  1714. static inline bool
  1715. i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
  1716. {
  1717. if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1718. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1719. dev_priv->fence_regs[obj->fence_reg].pin_count++;
  1720. return true;
  1721. } else
  1722. return false;
  1723. }
  1724. static inline void
  1725. i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
  1726. {
  1727. if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1728. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1729. WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
  1730. dev_priv->fence_regs[obj->fence_reg].pin_count--;
  1731. }
  1732. }
  1733. bool i915_gem_retire_requests(struct drm_device *dev);
  1734. void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
  1735. int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
  1736. bool interruptible);
  1737. static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
  1738. {
  1739. return unlikely(atomic_read(&error->reset_counter)
  1740. & I915_RESET_IN_PROGRESS_FLAG);
  1741. }
  1742. static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
  1743. {
  1744. return atomic_read(&error->reset_counter) == I915_WEDGED;
  1745. }
  1746. void i915_gem_reset(struct drm_device *dev);
  1747. bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
  1748. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  1749. int __must_check i915_gem_init(struct drm_device *dev);
  1750. int __must_check i915_gem_init_hw(struct drm_device *dev);
  1751. int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
  1752. void i915_gem_init_swizzling(struct drm_device *dev);
  1753. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  1754. int __must_check i915_gpu_idle(struct drm_device *dev);
  1755. int __must_check i915_gem_suspend(struct drm_device *dev);
  1756. int __i915_add_request(struct intel_ring_buffer *ring,
  1757. struct drm_file *file,
  1758. struct drm_i915_gem_object *batch_obj,
  1759. u32 *seqno);
  1760. #define i915_add_request(ring, seqno) \
  1761. __i915_add_request(ring, NULL, NULL, seqno)
  1762. int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
  1763. uint32_t seqno);
  1764. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  1765. int __must_check
  1766. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  1767. bool write);
  1768. int __must_check
  1769. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
  1770. int __must_check
  1771. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  1772. u32 alignment,
  1773. struct intel_ring_buffer *pipelined);
  1774. void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
  1775. int i915_gem_attach_phys_object(struct drm_device *dev,
  1776. struct drm_i915_gem_object *obj,
  1777. int id,
  1778. int align);
  1779. void i915_gem_detach_phys_object(struct drm_device *dev,
  1780. struct drm_i915_gem_object *obj);
  1781. void i915_gem_free_all_phys_object(struct drm_device *dev);
  1782. int i915_gem_open(struct drm_device *dev, struct drm_file *file);
  1783. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  1784. uint32_t
  1785. i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
  1786. uint32_t
  1787. i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
  1788. int tiling_mode, bool fenced);
  1789. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  1790. enum i915_cache_level cache_level);
  1791. struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
  1792. struct dma_buf *dma_buf);
  1793. struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
  1794. struct drm_gem_object *gem_obj, int flags);
  1795. void i915_gem_restore_fences(struct drm_device *dev);
  1796. unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
  1797. struct i915_address_space *vm);
  1798. bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
  1799. bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
  1800. struct i915_address_space *vm);
  1801. unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
  1802. struct i915_address_space *vm);
  1803. struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
  1804. struct i915_address_space *vm);
  1805. struct i915_vma *
  1806. i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
  1807. struct i915_address_space *vm);
  1808. struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
  1809. /* Some GGTT VM helpers */
  1810. #define obj_to_ggtt(obj) \
  1811. (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
  1812. static inline bool i915_is_ggtt(struct i915_address_space *vm)
  1813. {
  1814. struct i915_address_space *ggtt =
  1815. &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
  1816. return vm == ggtt;
  1817. }
  1818. static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
  1819. {
  1820. return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
  1821. }
  1822. static inline unsigned long
  1823. i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
  1824. {
  1825. return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
  1826. }
  1827. static inline unsigned long
  1828. i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
  1829. {
  1830. return i915_gem_obj_size(obj, obj_to_ggtt(obj));
  1831. }
  1832. static inline int __must_check
  1833. i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
  1834. uint32_t alignment,
  1835. bool map_and_fenceable,
  1836. bool nonblocking)
  1837. {
  1838. return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment,
  1839. map_and_fenceable, nonblocking);
  1840. }
  1841. /* i915_gem_context.c */
  1842. void i915_gem_context_init(struct drm_device *dev);
  1843. void i915_gem_context_fini(struct drm_device *dev);
  1844. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
  1845. int i915_switch_context(struct intel_ring_buffer *ring,
  1846. struct drm_file *file, int to_id);
  1847. void i915_gem_context_free(struct kref *ctx_ref);
  1848. static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
  1849. {
  1850. kref_get(&ctx->ref);
  1851. }
  1852. static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
  1853. {
  1854. kref_put(&ctx->ref, i915_gem_context_free);
  1855. }
  1856. struct i915_ctx_hang_stats * __must_check
  1857. i915_gem_context_get_hang_stats(struct drm_device *dev,
  1858. struct drm_file *file,
  1859. u32 id);
  1860. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  1861. struct drm_file *file);
  1862. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  1863. struct drm_file *file);
  1864. /* i915_gem_gtt.c */
  1865. void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
  1866. void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
  1867. struct drm_i915_gem_object *obj,
  1868. enum i915_cache_level cache_level);
  1869. void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
  1870. struct drm_i915_gem_object *obj);
  1871. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  1872. int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
  1873. void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
  1874. enum i915_cache_level cache_level);
  1875. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  1876. void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
  1877. void i915_gem_init_global_gtt(struct drm_device *dev);
  1878. void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
  1879. unsigned long mappable_end, unsigned long end);
  1880. int i915_gem_gtt_init(struct drm_device *dev);
  1881. static inline void i915_gem_chipset_flush(struct drm_device *dev)
  1882. {
  1883. if (INTEL_INFO(dev)->gen < 6)
  1884. intel_gtt_chipset_flush();
  1885. }
  1886. /* i915_gem_evict.c */
  1887. int __must_check i915_gem_evict_something(struct drm_device *dev,
  1888. struct i915_address_space *vm,
  1889. int min_size,
  1890. unsigned alignment,
  1891. unsigned cache_level,
  1892. bool mappable,
  1893. bool nonblock);
  1894. int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
  1895. int i915_gem_evict_everything(struct drm_device *dev);
  1896. /* i915_gem_stolen.c */
  1897. int i915_gem_init_stolen(struct drm_device *dev);
  1898. int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
  1899. void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
  1900. void i915_gem_cleanup_stolen(struct drm_device *dev);
  1901. struct drm_i915_gem_object *
  1902. i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
  1903. struct drm_i915_gem_object *
  1904. i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
  1905. u32 stolen_offset,
  1906. u32 gtt_offset,
  1907. u32 size);
  1908. void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
  1909. /* i915_gem_tiling.c */
  1910. static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
  1911. {
  1912. drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
  1913. return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
  1914. obj->tiling_mode != I915_TILING_NONE;
  1915. }
  1916. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  1917. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1918. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1919. /* i915_gem_debug.c */
  1920. #if WATCH_LISTS
  1921. int i915_verify_lists(struct drm_device *dev);
  1922. #else
  1923. #define i915_verify_lists(dev) 0
  1924. #endif
  1925. /* i915_debugfs.c */
  1926. int i915_debugfs_init(struct drm_minor *minor);
  1927. void i915_debugfs_cleanup(struct drm_minor *minor);
  1928. #ifdef CONFIG_DEBUG_FS
  1929. void intel_display_crc_init(struct drm_device *dev);
  1930. #else
  1931. static inline void intel_display_crc_init(struct drm_device *dev) {}
  1932. #endif
  1933. /* i915_gpu_error.c */
  1934. __printf(2, 3)
  1935. void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
  1936. int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
  1937. const struct i915_error_state_file_priv *error);
  1938. int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
  1939. size_t count, loff_t pos);
  1940. static inline void i915_error_state_buf_release(
  1941. struct drm_i915_error_state_buf *eb)
  1942. {
  1943. kfree(eb->buf);
  1944. }
  1945. void i915_capture_error_state(struct drm_device *dev);
  1946. void i915_error_state_get(struct drm_device *dev,
  1947. struct i915_error_state_file_priv *error_priv);
  1948. void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
  1949. void i915_destroy_error_state(struct drm_device *dev);
  1950. void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
  1951. const char *i915_cache_level_str(int type);
  1952. /* i915_suspend.c */
  1953. extern int i915_save_state(struct drm_device *dev);
  1954. extern int i915_restore_state(struct drm_device *dev);
  1955. /* i915_ums.c */
  1956. void i915_save_display_reg(struct drm_device *dev);
  1957. void i915_restore_display_reg(struct drm_device *dev);
  1958. /* i915_sysfs.c */
  1959. void i915_setup_sysfs(struct drm_device *dev_priv);
  1960. void i915_teardown_sysfs(struct drm_device *dev_priv);
  1961. /* intel_i2c.c */
  1962. extern int intel_setup_gmbus(struct drm_device *dev);
  1963. extern void intel_teardown_gmbus(struct drm_device *dev);
  1964. static inline bool intel_gmbus_is_port_valid(unsigned port)
  1965. {
  1966. return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
  1967. }
  1968. extern struct i2c_adapter *intel_gmbus_get_adapter(
  1969. struct drm_i915_private *dev_priv, unsigned port);
  1970. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  1971. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  1972. static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  1973. {
  1974. return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  1975. }
  1976. extern void intel_i2c_reset(struct drm_device *dev);
  1977. /* intel_opregion.c */
  1978. struct intel_encoder;
  1979. extern int intel_opregion_setup(struct drm_device *dev);
  1980. #ifdef CONFIG_ACPI
  1981. extern void intel_opregion_init(struct drm_device *dev);
  1982. extern void intel_opregion_fini(struct drm_device *dev);
  1983. extern void intel_opregion_asle_intr(struct drm_device *dev);
  1984. extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
  1985. bool enable);
  1986. extern int intel_opregion_notify_adapter(struct drm_device *dev,
  1987. pci_power_t state);
  1988. #else
  1989. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  1990. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  1991. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  1992. static inline int
  1993. intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
  1994. {
  1995. return 0;
  1996. }
  1997. static inline int
  1998. intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
  1999. {
  2000. return 0;
  2001. }
  2002. #endif
  2003. /* intel_acpi.c */
  2004. #ifdef CONFIG_ACPI
  2005. extern void intel_register_dsm_handler(void);
  2006. extern void intel_unregister_dsm_handler(void);
  2007. #else
  2008. static inline void intel_register_dsm_handler(void) { return; }
  2009. static inline void intel_unregister_dsm_handler(void) { return; }
  2010. #endif /* CONFIG_ACPI */
  2011. /* modesetting */
  2012. extern void intel_modeset_init_hw(struct drm_device *dev);
  2013. extern void intel_modeset_suspend_hw(struct drm_device *dev);
  2014. extern void intel_modeset_init(struct drm_device *dev);
  2015. extern void intel_modeset_gem_init(struct drm_device *dev);
  2016. extern void intel_modeset_cleanup(struct drm_device *dev);
  2017. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  2018. extern void intel_modeset_setup_hw_state(struct drm_device *dev,
  2019. bool force_restore);
  2020. extern void i915_redisable_vga(struct drm_device *dev);
  2021. extern bool intel_fbc_enabled(struct drm_device *dev);
  2022. extern void intel_disable_fbc(struct drm_device *dev);
  2023. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  2024. extern void intel_init_pch_refclk(struct drm_device *dev);
  2025. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  2026. extern void valleyview_set_rps(struct drm_device *dev, u8 val);
  2027. extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
  2028. extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
  2029. extern void intel_detect_pch(struct drm_device *dev);
  2030. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  2031. extern int intel_enable_rc6(const struct drm_device *dev);
  2032. extern bool i915_semaphore_is_enabled(struct drm_device *dev);
  2033. int i915_reg_read_ioctl(struct drm_device *dev, void *data,
  2034. struct drm_file *file);
  2035. /* overlay */
  2036. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  2037. extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
  2038. struct intel_overlay_error_state *error);
  2039. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  2040. extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
  2041. struct drm_device *dev,
  2042. struct intel_display_error_state *error);
  2043. /* On SNB platform, before reading ring registers forcewake bit
  2044. * must be set to prevent GT core from power down and stale values being
  2045. * returned.
  2046. */
  2047. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  2048. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  2049. int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
  2050. int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
  2051. /* intel_sideband.c */
  2052. u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
  2053. void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
  2054. u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
  2055. u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
  2056. void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2057. u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
  2058. void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2059. u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
  2060. void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2061. u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
  2062. void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
  2063. u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
  2064. void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
  2065. u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
  2066. enum intel_sbi_destination destination);
  2067. void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
  2068. enum intel_sbi_destination destination);
  2069. int vlv_gpu_freq(int ddr_freq, int val);
  2070. int vlv_freq_opcode(int ddr_freq, int val);
  2071. #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
  2072. #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
  2073. #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
  2074. #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
  2075. #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
  2076. #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
  2077. #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
  2078. #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
  2079. #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
  2080. #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
  2081. #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
  2082. #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
  2083. #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
  2084. #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
  2085. /* "Broadcast RGB" property */
  2086. #define INTEL_BROADCAST_RGB_AUTO 0
  2087. #define INTEL_BROADCAST_RGB_FULL 1
  2088. #define INTEL_BROADCAST_RGB_LIMITED 2
  2089. static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
  2090. {
  2091. if (HAS_PCH_SPLIT(dev))
  2092. return CPU_VGACNTRL;
  2093. else if (IS_VALLEYVIEW(dev))
  2094. return VLV_VGACNTRL;
  2095. else
  2096. return VGACNTRL;
  2097. }
  2098. static inline void __user *to_user_ptr(u64 address)
  2099. {
  2100. return (void __user *)(uintptr_t)address;
  2101. }
  2102. static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
  2103. {
  2104. unsigned long j = msecs_to_jiffies(m);
  2105. return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
  2106. }
  2107. static inline unsigned long
  2108. timespec_to_jiffies_timeout(const struct timespec *value)
  2109. {
  2110. unsigned long j = timespec_to_jiffies(value);
  2111. return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
  2112. }
  2113. #endif