dove.dtsi 6.6 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "marvell,dove";
  4. model = "Marvell Armada 88AP510 SoC";
  5. aliases {
  6. gpio0 = &gpio0;
  7. gpio1 = &gpio1;
  8. gpio2 = &gpio2;
  9. };
  10. soc@f1000000 {
  11. compatible = "simple-bus";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. interrupt-parent = <&intc>;
  15. ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
  16. 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
  17. 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
  18. 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
  19. 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
  20. 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
  21. 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
  22. 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
  23. l2: l2-cache {
  24. compatible = "marvell,tauros2-cache";
  25. marvell,tauros2-cache-features = <0>;
  26. };
  27. timer: timer@20300 {
  28. compatible = "marvell,orion-timer";
  29. reg = <0x20300 0x20>;
  30. interrupt-parent = <&bridge_intc>;
  31. interrupts = <1>, <2>;
  32. clocks = <&core_clk 0>;
  33. };
  34. intc: main-interrupt-ctrl@20200 {
  35. compatible = "marvell,orion-intc";
  36. interrupt-controller;
  37. #interrupt-cells = <1>;
  38. reg = <0x20200 0x10>, <0x20210 0x10>;
  39. };
  40. bridge_intc: bridge-interrupt-ctrl@20110 {
  41. compatible = "marvell,orion-bridge-intc";
  42. interrupt-controller;
  43. #interrupt-cells = <1>;
  44. reg = <0x20110 0x8>;
  45. interrupts = <0>;
  46. marvell,#interrupts = <5>;
  47. };
  48. core_clk: core-clocks@d0214 {
  49. compatible = "marvell,dove-core-clock";
  50. reg = <0xd0214 0x4>;
  51. #clock-cells = <1>;
  52. };
  53. gate_clk: clock-gating-control@d0038 {
  54. compatible = "marvell,dove-gating-clock";
  55. reg = <0xd0038 0x4>;
  56. clocks = <&core_clk 0>;
  57. #clock-cells = <1>;
  58. };
  59. thermal: thermal@d001c {
  60. compatible = "marvell,dove-thermal";
  61. reg = <0xd001c 0x0c>, <0xd005c 0x08>;
  62. };
  63. uart0: serial@12000 {
  64. compatible = "ns16550a";
  65. reg = <0x12000 0x100>;
  66. reg-shift = <2>;
  67. interrupts = <7>;
  68. clocks = <&core_clk 0>;
  69. status = "disabled";
  70. };
  71. uart1: serial@12100 {
  72. compatible = "ns16550a";
  73. reg = <0x12100 0x100>;
  74. reg-shift = <2>;
  75. interrupts = <8>;
  76. clocks = <&core_clk 0>;
  77. status = "disabled";
  78. };
  79. uart2: serial@12200 {
  80. compatible = "ns16550a";
  81. reg = <0x12000 0x100>;
  82. reg-shift = <2>;
  83. interrupts = <9>;
  84. clocks = <&core_clk 0>;
  85. status = "disabled";
  86. };
  87. uart3: serial@12300 {
  88. compatible = "ns16550a";
  89. reg = <0x12100 0x100>;
  90. reg-shift = <2>;
  91. interrupts = <10>;
  92. clocks = <&core_clk 0>;
  93. status = "disabled";
  94. };
  95. gpio0: gpio@d0400 {
  96. compatible = "marvell,orion-gpio";
  97. #gpio-cells = <2>;
  98. gpio-controller;
  99. reg = <0xd0400 0x20>;
  100. ngpios = <32>;
  101. interrupt-controller;
  102. #interrupt-cells = <2>;
  103. interrupts = <12>, <13>, <14>, <60>;
  104. };
  105. gpio1: gpio@d0420 {
  106. compatible = "marvell,orion-gpio";
  107. #gpio-cells = <2>;
  108. gpio-controller;
  109. reg = <0xd0420 0x20>;
  110. ngpios = <32>;
  111. interrupt-controller;
  112. #interrupt-cells = <2>;
  113. interrupts = <61>;
  114. };
  115. gpio2: gpio@e8400 {
  116. compatible = "marvell,orion-gpio";
  117. #gpio-cells = <2>;
  118. gpio-controller;
  119. reg = <0xe8400 0x0c>;
  120. ngpios = <8>;
  121. };
  122. pinctrl: pinctrl@d0200 {
  123. compatible = "marvell,dove-pinctrl";
  124. reg = <0xd0200 0x10>;
  125. clocks = <&gate_clk 22>;
  126. };
  127. spi0: spi@10600 {
  128. compatible = "marvell,orion-spi";
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. cell-index = <0>;
  132. interrupts = <6>;
  133. reg = <0x10600 0x28>;
  134. clocks = <&core_clk 0>;
  135. status = "disabled";
  136. };
  137. spi1: spi@14600 {
  138. compatible = "marvell,orion-spi";
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. cell-index = <1>;
  142. interrupts = <5>;
  143. reg = <0x14600 0x28>;
  144. clocks = <&core_clk 0>;
  145. status = "disabled";
  146. };
  147. i2c0: i2c@11000 {
  148. compatible = "marvell,mv64xxx-i2c";
  149. reg = <0x11000 0x20>;
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. interrupts = <11>;
  153. clock-frequency = <400000>;
  154. timeout-ms = <1000>;
  155. clocks = <&core_clk 0>;
  156. status = "disabled";
  157. };
  158. ehci0: usb-host@50000 {
  159. compatible = "marvell,orion-ehci";
  160. reg = <0x50000 0x1000>;
  161. interrupts = <24>;
  162. clocks = <&gate_clk 0>;
  163. status = "okay";
  164. };
  165. ehci1: usb-host@51000 {
  166. compatible = "marvell,orion-ehci";
  167. reg = <0x51000 0x1000>;
  168. interrupts = <25>;
  169. clocks = <&gate_clk 1>;
  170. status = "okay";
  171. };
  172. sdio0: sdio@92000 {
  173. compatible = "marvell,dove-sdhci";
  174. reg = <0x92000 0x100>;
  175. interrupts = <35>, <37>;
  176. clocks = <&gate_clk 8>;
  177. status = "disabled";
  178. };
  179. sdio1: sdio@90000 {
  180. compatible = "marvell,dove-sdhci";
  181. reg = <0x90000 0x100>;
  182. interrupts = <36>, <38>;
  183. clocks = <&gate_clk 9>;
  184. status = "disabled";
  185. };
  186. sata0: sata@a0000 {
  187. compatible = "marvell,orion-sata";
  188. reg = <0xa0000 0x2400>;
  189. interrupts = <62>;
  190. clocks = <&gate_clk 3>;
  191. nr-ports = <1>;
  192. status = "disabled";
  193. };
  194. rtc@d8500 {
  195. compatible = "marvell,orion-rtc";
  196. reg = <0xd8500 0x20>;
  197. };
  198. crypto: crypto@30000 {
  199. compatible = "marvell,orion-crypto";
  200. reg = <0x30000 0x10000>,
  201. <0xc8000000 0x800>;
  202. reg-names = "regs", "sram";
  203. interrupts = <31>;
  204. clocks = <&gate_clk 15>;
  205. status = "okay";
  206. };
  207. xor0: dma-engine@60800 {
  208. compatible = "marvell,orion-xor";
  209. reg = <0x60800 0x100
  210. 0x60a00 0x100>;
  211. clocks = <&gate_clk 23>;
  212. status = "okay";
  213. channel0 {
  214. interrupts = <39>;
  215. dmacap,memcpy;
  216. dmacap,xor;
  217. };
  218. channel1 {
  219. interrupts = <40>;
  220. dmacap,memset;
  221. dmacap,memcpy;
  222. dmacap,xor;
  223. };
  224. };
  225. xor1: dma-engine@60900 {
  226. compatible = "marvell,orion-xor";
  227. reg = <0x60900 0x100
  228. 0x60b00 0x100>;
  229. clocks = <&gate_clk 24>;
  230. status = "okay";
  231. channel0 {
  232. interrupts = <42>;
  233. dmacap,memcpy;
  234. dmacap,xor;
  235. };
  236. channel1 {
  237. interrupts = <43>;
  238. dmacap,memset;
  239. dmacap,memcpy;
  240. dmacap,xor;
  241. };
  242. };
  243. mdio: mdio-bus@72004 {
  244. compatible = "marvell,orion-mdio";
  245. #address-cells = <1>;
  246. #size-cells = <0>;
  247. reg = <0x72004 0x84>;
  248. interrupts = <30>;
  249. clocks = <&gate_clk 2>;
  250. status = "disabled";
  251. ethphy: ethernet-phy {
  252. device-type = "ethernet-phy";
  253. /* set phy address in board file */
  254. };
  255. };
  256. eth: ethernet-controller@72000 {
  257. compatible = "marvell,orion-eth";
  258. #address-cells = <1>;
  259. #size-cells = <0>;
  260. reg = <0x72000 0x4000>;
  261. clocks = <&gate_clk 2>;
  262. marvell,tx-checksum-limit = <1600>;
  263. status = "disabled";
  264. ethernet-port@0 {
  265. device_type = "network";
  266. compatible = "marvell,orion-eth-port";
  267. reg = <0>;
  268. interrupts = <29>;
  269. /* overwrite MAC address in bootloader */
  270. local-mac-address = [00 00 00 00 00 00];
  271. phy-handle = <&ethphy>;
  272. };
  273. };
  274. };
  275. };