intel_display.c 157 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/module.h>
  27. #include <linux/input.h>
  28. #include <linux/i2c.h>
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include "drmP.h"
  32. #include "intel_drv.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. #include "drm_dp_helper.h"
  36. #include "drm_crtc_helper.h"
  37. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  38. bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  39. static void intel_update_watermarks(struct drm_device *dev);
  40. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  41. typedef struct {
  42. /* given values */
  43. int n;
  44. int m1, m2;
  45. int p1, p2;
  46. /* derived values */
  47. int dot;
  48. int vco;
  49. int m;
  50. int p;
  51. } intel_clock_t;
  52. typedef struct {
  53. int min, max;
  54. } intel_range_t;
  55. typedef struct {
  56. int dot_limit;
  57. int p2_slow, p2_fast;
  58. } intel_p2_t;
  59. #define INTEL_P2_NUM 2
  60. typedef struct intel_limit intel_limit_t;
  61. struct intel_limit {
  62. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  63. intel_p2_t p2;
  64. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  65. int, int, intel_clock_t *);
  66. };
  67. #define I8XX_DOT_MIN 25000
  68. #define I8XX_DOT_MAX 350000
  69. #define I8XX_VCO_MIN 930000
  70. #define I8XX_VCO_MAX 1400000
  71. #define I8XX_N_MIN 3
  72. #define I8XX_N_MAX 16
  73. #define I8XX_M_MIN 96
  74. #define I8XX_M_MAX 140
  75. #define I8XX_M1_MIN 18
  76. #define I8XX_M1_MAX 26
  77. #define I8XX_M2_MIN 6
  78. #define I8XX_M2_MAX 16
  79. #define I8XX_P_MIN 4
  80. #define I8XX_P_MAX 128
  81. #define I8XX_P1_MIN 2
  82. #define I8XX_P1_MAX 33
  83. #define I8XX_P1_LVDS_MIN 1
  84. #define I8XX_P1_LVDS_MAX 6
  85. #define I8XX_P2_SLOW 4
  86. #define I8XX_P2_FAST 2
  87. #define I8XX_P2_LVDS_SLOW 14
  88. #define I8XX_P2_LVDS_FAST 7
  89. #define I8XX_P2_SLOW_LIMIT 165000
  90. #define I9XX_DOT_MIN 20000
  91. #define I9XX_DOT_MAX 400000
  92. #define I9XX_VCO_MIN 1400000
  93. #define I9XX_VCO_MAX 2800000
  94. #define PINEVIEW_VCO_MIN 1700000
  95. #define PINEVIEW_VCO_MAX 3500000
  96. #define I9XX_N_MIN 1
  97. #define I9XX_N_MAX 6
  98. /* Pineview's Ncounter is a ring counter */
  99. #define PINEVIEW_N_MIN 3
  100. #define PINEVIEW_N_MAX 6
  101. #define I9XX_M_MIN 70
  102. #define I9XX_M_MAX 120
  103. #define PINEVIEW_M_MIN 2
  104. #define PINEVIEW_M_MAX 256
  105. #define I9XX_M1_MIN 10
  106. #define I9XX_M1_MAX 22
  107. #define I9XX_M2_MIN 5
  108. #define I9XX_M2_MAX 9
  109. /* Pineview M1 is reserved, and must be 0 */
  110. #define PINEVIEW_M1_MIN 0
  111. #define PINEVIEW_M1_MAX 0
  112. #define PINEVIEW_M2_MIN 0
  113. #define PINEVIEW_M2_MAX 254
  114. #define I9XX_P_SDVO_DAC_MIN 5
  115. #define I9XX_P_SDVO_DAC_MAX 80
  116. #define I9XX_P_LVDS_MIN 7
  117. #define I9XX_P_LVDS_MAX 98
  118. #define PINEVIEW_P_LVDS_MIN 7
  119. #define PINEVIEW_P_LVDS_MAX 112
  120. #define I9XX_P1_MIN 1
  121. #define I9XX_P1_MAX 8
  122. #define I9XX_P2_SDVO_DAC_SLOW 10
  123. #define I9XX_P2_SDVO_DAC_FAST 5
  124. #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
  125. #define I9XX_P2_LVDS_SLOW 14
  126. #define I9XX_P2_LVDS_FAST 7
  127. #define I9XX_P2_LVDS_SLOW_LIMIT 112000
  128. /*The parameter is for SDVO on G4x platform*/
  129. #define G4X_DOT_SDVO_MIN 25000
  130. #define G4X_DOT_SDVO_MAX 270000
  131. #define G4X_VCO_MIN 1750000
  132. #define G4X_VCO_MAX 3500000
  133. #define G4X_N_SDVO_MIN 1
  134. #define G4X_N_SDVO_MAX 4
  135. #define G4X_M_SDVO_MIN 104
  136. #define G4X_M_SDVO_MAX 138
  137. #define G4X_M1_SDVO_MIN 17
  138. #define G4X_M1_SDVO_MAX 23
  139. #define G4X_M2_SDVO_MIN 5
  140. #define G4X_M2_SDVO_MAX 11
  141. #define G4X_P_SDVO_MIN 10
  142. #define G4X_P_SDVO_MAX 30
  143. #define G4X_P1_SDVO_MIN 1
  144. #define G4X_P1_SDVO_MAX 3
  145. #define G4X_P2_SDVO_SLOW 10
  146. #define G4X_P2_SDVO_FAST 10
  147. #define G4X_P2_SDVO_LIMIT 270000
  148. /*The parameter is for HDMI_DAC on G4x platform*/
  149. #define G4X_DOT_HDMI_DAC_MIN 22000
  150. #define G4X_DOT_HDMI_DAC_MAX 400000
  151. #define G4X_N_HDMI_DAC_MIN 1
  152. #define G4X_N_HDMI_DAC_MAX 4
  153. #define G4X_M_HDMI_DAC_MIN 104
  154. #define G4X_M_HDMI_DAC_MAX 138
  155. #define G4X_M1_HDMI_DAC_MIN 16
  156. #define G4X_M1_HDMI_DAC_MAX 23
  157. #define G4X_M2_HDMI_DAC_MIN 5
  158. #define G4X_M2_HDMI_DAC_MAX 11
  159. #define G4X_P_HDMI_DAC_MIN 5
  160. #define G4X_P_HDMI_DAC_MAX 80
  161. #define G4X_P1_HDMI_DAC_MIN 1
  162. #define G4X_P1_HDMI_DAC_MAX 8
  163. #define G4X_P2_HDMI_DAC_SLOW 10
  164. #define G4X_P2_HDMI_DAC_FAST 5
  165. #define G4X_P2_HDMI_DAC_LIMIT 165000
  166. /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
  167. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
  168. #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
  169. #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
  170. #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
  171. #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
  172. #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
  173. #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
  174. #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
  175. #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
  176. #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
  177. #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
  178. #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
  179. #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
  180. #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
  181. #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
  182. #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
  183. #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
  184. /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
  185. #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
  186. #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
  187. #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
  188. #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
  189. #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
  190. #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
  191. #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
  192. #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
  193. #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
  194. #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
  195. #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
  196. #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
  197. #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
  198. #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
  199. #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
  200. #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
  201. #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
  202. /*The parameter is for DISPLAY PORT on G4x platform*/
  203. #define G4X_DOT_DISPLAY_PORT_MIN 161670
  204. #define G4X_DOT_DISPLAY_PORT_MAX 227000
  205. #define G4X_N_DISPLAY_PORT_MIN 1
  206. #define G4X_N_DISPLAY_PORT_MAX 2
  207. #define G4X_M_DISPLAY_PORT_MIN 97
  208. #define G4X_M_DISPLAY_PORT_MAX 108
  209. #define G4X_M1_DISPLAY_PORT_MIN 0x10
  210. #define G4X_M1_DISPLAY_PORT_MAX 0x12
  211. #define G4X_M2_DISPLAY_PORT_MIN 0x05
  212. #define G4X_M2_DISPLAY_PORT_MAX 0x06
  213. #define G4X_P_DISPLAY_PORT_MIN 10
  214. #define G4X_P_DISPLAY_PORT_MAX 20
  215. #define G4X_P1_DISPLAY_PORT_MIN 1
  216. #define G4X_P1_DISPLAY_PORT_MAX 2
  217. #define G4X_P2_DISPLAY_PORT_SLOW 10
  218. #define G4X_P2_DISPLAY_PORT_FAST 10
  219. #define G4X_P2_DISPLAY_PORT_LIMIT 0
  220. /* Ironlake / Sandybridge */
  221. /* as we calculate clock using (register_value + 2) for
  222. N/M1/M2, so here the range value for them is (actual_value-2).
  223. */
  224. #define IRONLAKE_DOT_MIN 25000
  225. #define IRONLAKE_DOT_MAX 350000
  226. #define IRONLAKE_VCO_MIN 1760000
  227. #define IRONLAKE_VCO_MAX 3510000
  228. #define IRONLAKE_M1_MIN 12
  229. #define IRONLAKE_M1_MAX 22
  230. #define IRONLAKE_M2_MIN 5
  231. #define IRONLAKE_M2_MAX 9
  232. #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
  233. /* We have parameter ranges for different type of outputs. */
  234. /* DAC & HDMI Refclk 120Mhz */
  235. #define IRONLAKE_DAC_N_MIN 1
  236. #define IRONLAKE_DAC_N_MAX 5
  237. #define IRONLAKE_DAC_M_MIN 79
  238. #define IRONLAKE_DAC_M_MAX 127
  239. #define IRONLAKE_DAC_P_MIN 5
  240. #define IRONLAKE_DAC_P_MAX 80
  241. #define IRONLAKE_DAC_P1_MIN 1
  242. #define IRONLAKE_DAC_P1_MAX 8
  243. #define IRONLAKE_DAC_P2_SLOW 10
  244. #define IRONLAKE_DAC_P2_FAST 5
  245. /* LVDS single-channel 120Mhz refclk */
  246. #define IRONLAKE_LVDS_S_N_MIN 1
  247. #define IRONLAKE_LVDS_S_N_MAX 3
  248. #define IRONLAKE_LVDS_S_M_MIN 79
  249. #define IRONLAKE_LVDS_S_M_MAX 118
  250. #define IRONLAKE_LVDS_S_P_MIN 28
  251. #define IRONLAKE_LVDS_S_P_MAX 112
  252. #define IRONLAKE_LVDS_S_P1_MIN 2
  253. #define IRONLAKE_LVDS_S_P1_MAX 8
  254. #define IRONLAKE_LVDS_S_P2_SLOW 14
  255. #define IRONLAKE_LVDS_S_P2_FAST 14
  256. /* LVDS dual-channel 120Mhz refclk */
  257. #define IRONLAKE_LVDS_D_N_MIN 1
  258. #define IRONLAKE_LVDS_D_N_MAX 3
  259. #define IRONLAKE_LVDS_D_M_MIN 79
  260. #define IRONLAKE_LVDS_D_M_MAX 127
  261. #define IRONLAKE_LVDS_D_P_MIN 14
  262. #define IRONLAKE_LVDS_D_P_MAX 56
  263. #define IRONLAKE_LVDS_D_P1_MIN 2
  264. #define IRONLAKE_LVDS_D_P1_MAX 8
  265. #define IRONLAKE_LVDS_D_P2_SLOW 7
  266. #define IRONLAKE_LVDS_D_P2_FAST 7
  267. /* LVDS single-channel 100Mhz refclk */
  268. #define IRONLAKE_LVDS_S_SSC_N_MIN 1
  269. #define IRONLAKE_LVDS_S_SSC_N_MAX 2
  270. #define IRONLAKE_LVDS_S_SSC_M_MIN 79
  271. #define IRONLAKE_LVDS_S_SSC_M_MAX 126
  272. #define IRONLAKE_LVDS_S_SSC_P_MIN 28
  273. #define IRONLAKE_LVDS_S_SSC_P_MAX 112
  274. #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
  275. #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
  276. #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
  277. #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
  278. /* LVDS dual-channel 100Mhz refclk */
  279. #define IRONLAKE_LVDS_D_SSC_N_MIN 1
  280. #define IRONLAKE_LVDS_D_SSC_N_MAX 3
  281. #define IRONLAKE_LVDS_D_SSC_M_MIN 79
  282. #define IRONLAKE_LVDS_D_SSC_M_MAX 126
  283. #define IRONLAKE_LVDS_D_SSC_P_MIN 14
  284. #define IRONLAKE_LVDS_D_SSC_P_MAX 42
  285. #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
  286. #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
  287. #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
  288. #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
  289. /* DisplayPort */
  290. #define IRONLAKE_DP_N_MIN 1
  291. #define IRONLAKE_DP_N_MAX 2
  292. #define IRONLAKE_DP_M_MIN 81
  293. #define IRONLAKE_DP_M_MAX 90
  294. #define IRONLAKE_DP_P_MIN 10
  295. #define IRONLAKE_DP_P_MAX 20
  296. #define IRONLAKE_DP_P2_FAST 10
  297. #define IRONLAKE_DP_P2_SLOW 10
  298. #define IRONLAKE_DP_P2_LIMIT 0
  299. #define IRONLAKE_DP_P1_MIN 1
  300. #define IRONLAKE_DP_P1_MAX 2
  301. static bool
  302. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  303. int target, int refclk, intel_clock_t *best_clock);
  304. static bool
  305. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  306. int target, int refclk, intel_clock_t *best_clock);
  307. static bool
  308. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  309. int target, int refclk, intel_clock_t *best_clock);
  310. static bool
  311. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  312. int target, int refclk, intel_clock_t *best_clock);
  313. static const intel_limit_t intel_limits_i8xx_dvo = {
  314. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  315. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  316. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  317. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  318. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  319. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  320. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  321. .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
  322. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  323. .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
  324. .find_pll = intel_find_best_PLL,
  325. };
  326. static const intel_limit_t intel_limits_i8xx_lvds = {
  327. .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
  328. .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
  329. .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
  330. .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
  331. .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
  332. .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
  333. .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
  334. .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
  335. .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
  336. .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
  337. .find_pll = intel_find_best_PLL,
  338. };
  339. static const intel_limit_t intel_limits_i9xx_sdvo = {
  340. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  341. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  342. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  343. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  344. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  345. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  346. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  347. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  348. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  349. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  350. .find_pll = intel_find_best_PLL,
  351. };
  352. static const intel_limit_t intel_limits_i9xx_lvds = {
  353. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  354. .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
  355. .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
  356. .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
  357. .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
  358. .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
  359. .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
  360. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  361. /* The single-channel range is 25-112Mhz, and dual-channel
  362. * is 80-224Mhz. Prefer single channel as much as possible.
  363. */
  364. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  365. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
  366. .find_pll = intel_find_best_PLL,
  367. };
  368. /* below parameter and function is for G4X Chipset Family*/
  369. static const intel_limit_t intel_limits_g4x_sdvo = {
  370. .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
  371. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  372. .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
  373. .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
  374. .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
  375. .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
  376. .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
  377. .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
  378. .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
  379. .p2_slow = G4X_P2_SDVO_SLOW,
  380. .p2_fast = G4X_P2_SDVO_FAST
  381. },
  382. .find_pll = intel_g4x_find_best_PLL,
  383. };
  384. static const intel_limit_t intel_limits_g4x_hdmi = {
  385. .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
  386. .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
  387. .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
  388. .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
  389. .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
  390. .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
  391. .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
  392. .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
  393. .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
  394. .p2_slow = G4X_P2_HDMI_DAC_SLOW,
  395. .p2_fast = G4X_P2_HDMI_DAC_FAST
  396. },
  397. .find_pll = intel_g4x_find_best_PLL,
  398. };
  399. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  400. .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
  401. .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
  402. .vco = { .min = G4X_VCO_MIN,
  403. .max = G4X_VCO_MAX },
  404. .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
  405. .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
  406. .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
  407. .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
  408. .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
  409. .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
  410. .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
  411. .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
  412. .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
  413. .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
  414. .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
  415. .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
  416. .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
  417. .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
  418. .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
  419. },
  420. .find_pll = intel_g4x_find_best_PLL,
  421. };
  422. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  423. .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
  424. .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
  425. .vco = { .min = G4X_VCO_MIN,
  426. .max = G4X_VCO_MAX },
  427. .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
  428. .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
  429. .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
  430. .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
  431. .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
  432. .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
  433. .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
  434. .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
  435. .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
  436. .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
  437. .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
  438. .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
  439. .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
  440. .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
  441. .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
  442. },
  443. .find_pll = intel_g4x_find_best_PLL,
  444. };
  445. static const intel_limit_t intel_limits_g4x_display_port = {
  446. .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
  447. .max = G4X_DOT_DISPLAY_PORT_MAX },
  448. .vco = { .min = G4X_VCO_MIN,
  449. .max = G4X_VCO_MAX},
  450. .n = { .min = G4X_N_DISPLAY_PORT_MIN,
  451. .max = G4X_N_DISPLAY_PORT_MAX },
  452. .m = { .min = G4X_M_DISPLAY_PORT_MIN,
  453. .max = G4X_M_DISPLAY_PORT_MAX },
  454. .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
  455. .max = G4X_M1_DISPLAY_PORT_MAX },
  456. .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
  457. .max = G4X_M2_DISPLAY_PORT_MAX },
  458. .p = { .min = G4X_P_DISPLAY_PORT_MIN,
  459. .max = G4X_P_DISPLAY_PORT_MAX },
  460. .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
  461. .max = G4X_P1_DISPLAY_PORT_MAX},
  462. .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
  463. .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
  464. .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
  465. .find_pll = intel_find_pll_g4x_dp,
  466. };
  467. static const intel_limit_t intel_limits_pineview_sdvo = {
  468. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
  469. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  470. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  471. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  472. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  473. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  474. .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
  475. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  476. .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
  477. .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
  478. .find_pll = intel_find_best_PLL,
  479. };
  480. static const intel_limit_t intel_limits_pineview_lvds = {
  481. .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
  482. .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
  483. .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
  484. .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
  485. .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
  486. .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
  487. .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
  488. .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
  489. /* Pineview only supports single-channel mode. */
  490. .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
  491. .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
  492. .find_pll = intel_find_best_PLL,
  493. };
  494. static const intel_limit_t intel_limits_ironlake_dac = {
  495. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  496. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  497. .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
  498. .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
  499. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  500. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  501. .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
  502. .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
  503. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  504. .p2_slow = IRONLAKE_DAC_P2_SLOW,
  505. .p2_fast = IRONLAKE_DAC_P2_FAST },
  506. .find_pll = intel_g4x_find_best_PLL,
  507. };
  508. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  509. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  510. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  511. .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
  512. .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
  513. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  514. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  515. .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
  516. .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
  517. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  518. .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
  519. .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
  520. .find_pll = intel_g4x_find_best_PLL,
  521. };
  522. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  523. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  524. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  525. .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
  526. .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
  527. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  528. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  529. .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
  530. .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
  531. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  532. .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
  533. .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
  534. .find_pll = intel_g4x_find_best_PLL,
  535. };
  536. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  537. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  538. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  539. .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
  540. .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
  541. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  542. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  543. .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
  544. .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
  545. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  546. .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
  547. .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
  548. .find_pll = intel_g4x_find_best_PLL,
  549. };
  550. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  551. .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
  552. .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
  553. .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
  554. .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
  555. .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
  556. .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
  557. .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
  558. .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
  559. .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
  560. .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
  561. .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
  562. .find_pll = intel_g4x_find_best_PLL,
  563. };
  564. static const intel_limit_t intel_limits_ironlake_display_port = {
  565. .dot = { .min = IRONLAKE_DOT_MIN,
  566. .max = IRONLAKE_DOT_MAX },
  567. .vco = { .min = IRONLAKE_VCO_MIN,
  568. .max = IRONLAKE_VCO_MAX},
  569. .n = { .min = IRONLAKE_DP_N_MIN,
  570. .max = IRONLAKE_DP_N_MAX },
  571. .m = { .min = IRONLAKE_DP_M_MIN,
  572. .max = IRONLAKE_DP_M_MAX },
  573. .m1 = { .min = IRONLAKE_M1_MIN,
  574. .max = IRONLAKE_M1_MAX },
  575. .m2 = { .min = IRONLAKE_M2_MIN,
  576. .max = IRONLAKE_M2_MAX },
  577. .p = { .min = IRONLAKE_DP_P_MIN,
  578. .max = IRONLAKE_DP_P_MAX },
  579. .p1 = { .min = IRONLAKE_DP_P1_MIN,
  580. .max = IRONLAKE_DP_P1_MAX},
  581. .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
  582. .p2_slow = IRONLAKE_DP_P2_SLOW,
  583. .p2_fast = IRONLAKE_DP_P2_FAST },
  584. .find_pll = intel_find_pll_ironlake_dp,
  585. };
  586. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
  587. {
  588. struct drm_device *dev = crtc->dev;
  589. struct drm_i915_private *dev_priv = dev->dev_private;
  590. const intel_limit_t *limit;
  591. int refclk = 120;
  592. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  593. if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
  594. refclk = 100;
  595. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  596. LVDS_CLKB_POWER_UP) {
  597. /* LVDS dual channel */
  598. if (refclk == 100)
  599. limit = &intel_limits_ironlake_dual_lvds_100m;
  600. else
  601. limit = &intel_limits_ironlake_dual_lvds;
  602. } else {
  603. if (refclk == 100)
  604. limit = &intel_limits_ironlake_single_lvds_100m;
  605. else
  606. limit = &intel_limits_ironlake_single_lvds;
  607. }
  608. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  609. HAS_eDP)
  610. limit = &intel_limits_ironlake_display_port;
  611. else
  612. limit = &intel_limits_ironlake_dac;
  613. return limit;
  614. }
  615. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  616. {
  617. struct drm_device *dev = crtc->dev;
  618. struct drm_i915_private *dev_priv = dev->dev_private;
  619. const intel_limit_t *limit;
  620. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  621. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  622. LVDS_CLKB_POWER_UP)
  623. /* LVDS with dual channel */
  624. limit = &intel_limits_g4x_dual_channel_lvds;
  625. else
  626. /* LVDS with dual channel */
  627. limit = &intel_limits_g4x_single_channel_lvds;
  628. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  629. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  630. limit = &intel_limits_g4x_hdmi;
  631. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  632. limit = &intel_limits_g4x_sdvo;
  633. } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  634. limit = &intel_limits_g4x_display_port;
  635. } else /* The option is for other outputs */
  636. limit = &intel_limits_i9xx_sdvo;
  637. return limit;
  638. }
  639. static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
  640. {
  641. struct drm_device *dev = crtc->dev;
  642. const intel_limit_t *limit;
  643. if (HAS_PCH_SPLIT(dev))
  644. limit = intel_ironlake_limit(crtc);
  645. else if (IS_G4X(dev)) {
  646. limit = intel_g4x_limit(crtc);
  647. } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
  648. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  649. limit = &intel_limits_i9xx_lvds;
  650. else
  651. limit = &intel_limits_i9xx_sdvo;
  652. } else if (IS_PINEVIEW(dev)) {
  653. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  654. limit = &intel_limits_pineview_lvds;
  655. else
  656. limit = &intel_limits_pineview_sdvo;
  657. } else {
  658. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  659. limit = &intel_limits_i8xx_lvds;
  660. else
  661. limit = &intel_limits_i8xx_dvo;
  662. }
  663. return limit;
  664. }
  665. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  666. static void pineview_clock(int refclk, intel_clock_t *clock)
  667. {
  668. clock->m = clock->m2 + 2;
  669. clock->p = clock->p1 * clock->p2;
  670. clock->vco = refclk * clock->m / clock->n;
  671. clock->dot = clock->vco / clock->p;
  672. }
  673. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  674. {
  675. if (IS_PINEVIEW(dev)) {
  676. pineview_clock(refclk, clock);
  677. return;
  678. }
  679. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  680. clock->p = clock->p1 * clock->p2;
  681. clock->vco = refclk * clock->m / (clock->n + 2);
  682. clock->dot = clock->vco / clock->p;
  683. }
  684. /**
  685. * Returns whether any output on the specified pipe is of the specified type
  686. */
  687. bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
  688. {
  689. struct drm_device *dev = crtc->dev;
  690. struct drm_mode_config *mode_config = &dev->mode_config;
  691. struct drm_encoder *l_entry;
  692. list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
  693. if (l_entry && l_entry->crtc == crtc) {
  694. struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
  695. if (intel_encoder->type == type)
  696. return true;
  697. }
  698. }
  699. return false;
  700. }
  701. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  702. /**
  703. * Returns whether the given set of divisors are valid for a given refclk with
  704. * the given connectors.
  705. */
  706. static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
  707. {
  708. const intel_limit_t *limit = intel_limit (crtc);
  709. struct drm_device *dev = crtc->dev;
  710. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  711. INTELPllInvalid ("p1 out of range\n");
  712. if (clock->p < limit->p.min || limit->p.max < clock->p)
  713. INTELPllInvalid ("p out of range\n");
  714. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  715. INTELPllInvalid ("m2 out of range\n");
  716. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  717. INTELPllInvalid ("m1 out of range\n");
  718. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  719. INTELPllInvalid ("m1 <= m2\n");
  720. if (clock->m < limit->m.min || limit->m.max < clock->m)
  721. INTELPllInvalid ("m out of range\n");
  722. if (clock->n < limit->n.min || limit->n.max < clock->n)
  723. INTELPllInvalid ("n out of range\n");
  724. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  725. INTELPllInvalid ("vco out of range\n");
  726. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  727. * connector, etc., rather than just a single range.
  728. */
  729. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  730. INTELPllInvalid ("dot out of range\n");
  731. return true;
  732. }
  733. static bool
  734. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  735. int target, int refclk, intel_clock_t *best_clock)
  736. {
  737. struct drm_device *dev = crtc->dev;
  738. struct drm_i915_private *dev_priv = dev->dev_private;
  739. intel_clock_t clock;
  740. int err = target;
  741. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  742. (I915_READ(LVDS)) != 0) {
  743. /*
  744. * For LVDS, if the panel is on, just rely on its current
  745. * settings for dual-channel. We haven't figured out how to
  746. * reliably set up different single/dual channel state, if we
  747. * even can.
  748. */
  749. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  750. LVDS_CLKB_POWER_UP)
  751. clock.p2 = limit->p2.p2_fast;
  752. else
  753. clock.p2 = limit->p2.p2_slow;
  754. } else {
  755. if (target < limit->p2.dot_limit)
  756. clock.p2 = limit->p2.p2_slow;
  757. else
  758. clock.p2 = limit->p2.p2_fast;
  759. }
  760. memset (best_clock, 0, sizeof (*best_clock));
  761. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  762. clock.m1++) {
  763. for (clock.m2 = limit->m2.min;
  764. clock.m2 <= limit->m2.max; clock.m2++) {
  765. /* m1 is always 0 in Pineview */
  766. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  767. break;
  768. for (clock.n = limit->n.min;
  769. clock.n <= limit->n.max; clock.n++) {
  770. for (clock.p1 = limit->p1.min;
  771. clock.p1 <= limit->p1.max; clock.p1++) {
  772. int this_err;
  773. intel_clock(dev, refclk, &clock);
  774. if (!intel_PLL_is_valid(crtc, &clock))
  775. continue;
  776. this_err = abs(clock.dot - target);
  777. if (this_err < err) {
  778. *best_clock = clock;
  779. err = this_err;
  780. }
  781. }
  782. }
  783. }
  784. }
  785. return (err != target);
  786. }
  787. static bool
  788. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  789. int target, int refclk, intel_clock_t *best_clock)
  790. {
  791. struct drm_device *dev = crtc->dev;
  792. struct drm_i915_private *dev_priv = dev->dev_private;
  793. intel_clock_t clock;
  794. int max_n;
  795. bool found;
  796. /* approximately equals target * 0.00488 */
  797. int err_most = (target >> 8) + (target >> 10);
  798. found = false;
  799. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  800. int lvds_reg;
  801. if (HAS_PCH_SPLIT(dev))
  802. lvds_reg = PCH_LVDS;
  803. else
  804. lvds_reg = LVDS;
  805. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  806. LVDS_CLKB_POWER_UP)
  807. clock.p2 = limit->p2.p2_fast;
  808. else
  809. clock.p2 = limit->p2.p2_slow;
  810. } else {
  811. if (target < limit->p2.dot_limit)
  812. clock.p2 = limit->p2.p2_slow;
  813. else
  814. clock.p2 = limit->p2.p2_fast;
  815. }
  816. memset(best_clock, 0, sizeof(*best_clock));
  817. max_n = limit->n.max;
  818. /* based on hardware requirement, prefer smaller n to precision */
  819. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  820. /* based on hardware requirement, prefere larger m1,m2 */
  821. for (clock.m1 = limit->m1.max;
  822. clock.m1 >= limit->m1.min; clock.m1--) {
  823. for (clock.m2 = limit->m2.max;
  824. clock.m2 >= limit->m2.min; clock.m2--) {
  825. for (clock.p1 = limit->p1.max;
  826. clock.p1 >= limit->p1.min; clock.p1--) {
  827. int this_err;
  828. intel_clock(dev, refclk, &clock);
  829. if (!intel_PLL_is_valid(crtc, &clock))
  830. continue;
  831. this_err = abs(clock.dot - target) ;
  832. if (this_err < err_most) {
  833. *best_clock = clock;
  834. err_most = this_err;
  835. max_n = clock.n;
  836. found = true;
  837. }
  838. }
  839. }
  840. }
  841. }
  842. return found;
  843. }
  844. static bool
  845. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  846. int target, int refclk, intel_clock_t *best_clock)
  847. {
  848. struct drm_device *dev = crtc->dev;
  849. intel_clock_t clock;
  850. /* return directly when it is eDP */
  851. if (HAS_eDP)
  852. return true;
  853. if (target < 200000) {
  854. clock.n = 1;
  855. clock.p1 = 2;
  856. clock.p2 = 10;
  857. clock.m1 = 12;
  858. clock.m2 = 9;
  859. } else {
  860. clock.n = 2;
  861. clock.p1 = 1;
  862. clock.p2 = 10;
  863. clock.m1 = 14;
  864. clock.m2 = 8;
  865. }
  866. intel_clock(dev, refclk, &clock);
  867. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  868. return true;
  869. }
  870. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  871. static bool
  872. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  873. int target, int refclk, intel_clock_t *best_clock)
  874. {
  875. intel_clock_t clock;
  876. if (target < 200000) {
  877. clock.p1 = 2;
  878. clock.p2 = 10;
  879. clock.n = 2;
  880. clock.m1 = 23;
  881. clock.m2 = 8;
  882. } else {
  883. clock.p1 = 1;
  884. clock.p2 = 10;
  885. clock.n = 1;
  886. clock.m1 = 14;
  887. clock.m2 = 2;
  888. }
  889. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  890. clock.p = (clock.p1 * clock.p2);
  891. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  892. clock.vco = 0;
  893. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  894. return true;
  895. }
  896. void
  897. intel_wait_for_vblank(struct drm_device *dev)
  898. {
  899. /* Wait for 20ms, i.e. one cycle at 50hz. */
  900. msleep(20);
  901. }
  902. /* Parameters have changed, update FBC info */
  903. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  904. {
  905. struct drm_device *dev = crtc->dev;
  906. struct drm_i915_private *dev_priv = dev->dev_private;
  907. struct drm_framebuffer *fb = crtc->fb;
  908. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  909. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  910. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  911. int plane, i;
  912. u32 fbc_ctl, fbc_ctl2;
  913. dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  914. if (fb->pitch < dev_priv->cfb_pitch)
  915. dev_priv->cfb_pitch = fb->pitch;
  916. /* FBC_CTL wants 64B units */
  917. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  918. dev_priv->cfb_fence = obj_priv->fence_reg;
  919. dev_priv->cfb_plane = intel_crtc->plane;
  920. plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  921. /* Clear old tags */
  922. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  923. I915_WRITE(FBC_TAG + (i * 4), 0);
  924. /* Set it up... */
  925. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
  926. if (obj_priv->tiling_mode != I915_TILING_NONE)
  927. fbc_ctl2 |= FBC_CTL_CPU_FENCE;
  928. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  929. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  930. /* enable it... */
  931. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  932. if (IS_I945GM(dev))
  933. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  934. fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  935. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  936. if (obj_priv->tiling_mode != I915_TILING_NONE)
  937. fbc_ctl |= dev_priv->cfb_fence;
  938. I915_WRITE(FBC_CONTROL, fbc_ctl);
  939. DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
  940. dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
  941. }
  942. void i8xx_disable_fbc(struct drm_device *dev)
  943. {
  944. struct drm_i915_private *dev_priv = dev->dev_private;
  945. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  946. u32 fbc_ctl;
  947. if (!I915_HAS_FBC(dev))
  948. return;
  949. if (!(I915_READ(FBC_CONTROL) & FBC_CTL_EN))
  950. return; /* Already off, just return */
  951. /* Disable compression */
  952. fbc_ctl = I915_READ(FBC_CONTROL);
  953. fbc_ctl &= ~FBC_CTL_EN;
  954. I915_WRITE(FBC_CONTROL, fbc_ctl);
  955. /* Wait for compressing bit to clear */
  956. while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) {
  957. if (time_after(jiffies, timeout)) {
  958. DRM_DEBUG_DRIVER("FBC idle timed out\n");
  959. break;
  960. }
  961. ; /* do nothing */
  962. }
  963. intel_wait_for_vblank(dev);
  964. DRM_DEBUG_KMS("disabled FBC\n");
  965. }
  966. static bool i8xx_fbc_enabled(struct drm_device *dev)
  967. {
  968. struct drm_i915_private *dev_priv = dev->dev_private;
  969. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  970. }
  971. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  972. {
  973. struct drm_device *dev = crtc->dev;
  974. struct drm_i915_private *dev_priv = dev->dev_private;
  975. struct drm_framebuffer *fb = crtc->fb;
  976. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  977. struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
  978. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  979. int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
  980. DPFC_CTL_PLANEB);
  981. unsigned long stall_watermark = 200;
  982. u32 dpfc_ctl;
  983. dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
  984. dev_priv->cfb_fence = obj_priv->fence_reg;
  985. dev_priv->cfb_plane = intel_crtc->plane;
  986. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  987. if (obj_priv->tiling_mode != I915_TILING_NONE) {
  988. dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
  989. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  990. } else {
  991. I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
  992. }
  993. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  994. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  995. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  996. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  997. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  998. /* enable it... */
  999. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  1000. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1001. }
  1002. void g4x_disable_fbc(struct drm_device *dev)
  1003. {
  1004. struct drm_i915_private *dev_priv = dev->dev_private;
  1005. u32 dpfc_ctl;
  1006. /* Disable compression */
  1007. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1008. dpfc_ctl &= ~DPFC_CTL_EN;
  1009. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1010. intel_wait_for_vblank(dev);
  1011. DRM_DEBUG_KMS("disabled FBC\n");
  1012. }
  1013. static bool g4x_fbc_enabled(struct drm_device *dev)
  1014. {
  1015. struct drm_i915_private *dev_priv = dev->dev_private;
  1016. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  1017. }
  1018. bool intel_fbc_enabled(struct drm_device *dev)
  1019. {
  1020. struct drm_i915_private *dev_priv = dev->dev_private;
  1021. if (!dev_priv->display.fbc_enabled)
  1022. return false;
  1023. return dev_priv->display.fbc_enabled(dev);
  1024. }
  1025. void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1026. {
  1027. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  1028. if (!dev_priv->display.enable_fbc)
  1029. return;
  1030. dev_priv->display.enable_fbc(crtc, interval);
  1031. }
  1032. void intel_disable_fbc(struct drm_device *dev)
  1033. {
  1034. struct drm_i915_private *dev_priv = dev->dev_private;
  1035. if (!dev_priv->display.disable_fbc)
  1036. return;
  1037. dev_priv->display.disable_fbc(dev);
  1038. }
  1039. /**
  1040. * intel_update_fbc - enable/disable FBC as needed
  1041. * @crtc: CRTC to point the compressor at
  1042. * @mode: mode in use
  1043. *
  1044. * Set up the framebuffer compression hardware at mode set time. We
  1045. * enable it if possible:
  1046. * - plane A only (on pre-965)
  1047. * - no pixel mulitply/line duplication
  1048. * - no alpha buffer discard
  1049. * - no dual wide
  1050. * - framebuffer <= 2048 in width, 1536 in height
  1051. *
  1052. * We can't assume that any compression will take place (worst case),
  1053. * so the compressed buffer has to be the same size as the uncompressed
  1054. * one. It also must reside (along with the line length buffer) in
  1055. * stolen memory.
  1056. *
  1057. * We need to enable/disable FBC on a global basis.
  1058. */
  1059. static void intel_update_fbc(struct drm_crtc *crtc,
  1060. struct drm_display_mode *mode)
  1061. {
  1062. struct drm_device *dev = crtc->dev;
  1063. struct drm_i915_private *dev_priv = dev->dev_private;
  1064. struct drm_framebuffer *fb = crtc->fb;
  1065. struct intel_framebuffer *intel_fb;
  1066. struct drm_i915_gem_object *obj_priv;
  1067. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1068. int plane = intel_crtc->plane;
  1069. if (!i915_powersave)
  1070. return;
  1071. if (!I915_HAS_FBC(dev))
  1072. return;
  1073. if (!crtc->fb)
  1074. return;
  1075. intel_fb = to_intel_framebuffer(fb);
  1076. obj_priv = to_intel_bo(intel_fb->obj);
  1077. /*
  1078. * If FBC is already on, we just have to verify that we can
  1079. * keep it that way...
  1080. * Need to disable if:
  1081. * - changing FBC params (stride, fence, mode)
  1082. * - new fb is too large to fit in compressed buffer
  1083. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1084. */
  1085. if (intel_fb->obj->size > dev_priv->cfb_size) {
  1086. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1087. "compression\n");
  1088. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1089. goto out_disable;
  1090. }
  1091. if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
  1092. (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
  1093. DRM_DEBUG_KMS("mode incompatible with compression, "
  1094. "disabling\n");
  1095. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  1096. goto out_disable;
  1097. }
  1098. if ((mode->hdisplay > 2048) ||
  1099. (mode->vdisplay > 1536)) {
  1100. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1101. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  1102. goto out_disable;
  1103. }
  1104. if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
  1105. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1106. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  1107. goto out_disable;
  1108. }
  1109. if (obj_priv->tiling_mode != I915_TILING_X) {
  1110. DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
  1111. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  1112. goto out_disable;
  1113. }
  1114. if (intel_fbc_enabled(dev)) {
  1115. /* We can re-enable it in this case, but need to update pitch */
  1116. if ((fb->pitch > dev_priv->cfb_pitch) ||
  1117. (obj_priv->fence_reg != dev_priv->cfb_fence) ||
  1118. (plane != dev_priv->cfb_plane))
  1119. intel_disable_fbc(dev);
  1120. }
  1121. /* Now try to turn it back on if possible */
  1122. if (!intel_fbc_enabled(dev))
  1123. intel_enable_fbc(crtc, 500);
  1124. return;
  1125. out_disable:
  1126. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1127. /* Multiple disables should be harmless */
  1128. if (intel_fbc_enabled(dev))
  1129. intel_disable_fbc(dev);
  1130. }
  1131. static int
  1132. intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
  1133. {
  1134. struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
  1135. u32 alignment;
  1136. int ret;
  1137. switch (obj_priv->tiling_mode) {
  1138. case I915_TILING_NONE:
  1139. alignment = 64 * 1024;
  1140. break;
  1141. case I915_TILING_X:
  1142. /* pin() will align the object as required by fence */
  1143. alignment = 0;
  1144. break;
  1145. case I915_TILING_Y:
  1146. /* FIXME: Is this true? */
  1147. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1148. return -EINVAL;
  1149. default:
  1150. BUG();
  1151. }
  1152. ret = i915_gem_object_pin(obj, alignment);
  1153. if (ret != 0)
  1154. return ret;
  1155. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1156. * fence, whereas 965+ only requires a fence if using
  1157. * framebuffer compression. For simplicity, we always install
  1158. * a fence as the cost is not that onerous.
  1159. */
  1160. if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
  1161. obj_priv->tiling_mode != I915_TILING_NONE) {
  1162. ret = i915_gem_object_get_fence_reg(obj);
  1163. if (ret != 0) {
  1164. i915_gem_object_unpin(obj);
  1165. return ret;
  1166. }
  1167. }
  1168. return 0;
  1169. }
  1170. static int
  1171. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1172. struct drm_framebuffer *old_fb)
  1173. {
  1174. struct drm_device *dev = crtc->dev;
  1175. struct drm_i915_private *dev_priv = dev->dev_private;
  1176. struct drm_i915_master_private *master_priv;
  1177. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1178. struct intel_framebuffer *intel_fb;
  1179. struct drm_i915_gem_object *obj_priv;
  1180. struct drm_gem_object *obj;
  1181. int pipe = intel_crtc->pipe;
  1182. int plane = intel_crtc->plane;
  1183. unsigned long Start, Offset;
  1184. int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
  1185. int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
  1186. int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
  1187. int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
  1188. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1189. u32 dspcntr;
  1190. int ret;
  1191. /* no fb bound */
  1192. if (!crtc->fb) {
  1193. DRM_DEBUG_KMS("No FB bound\n");
  1194. return 0;
  1195. }
  1196. switch (plane) {
  1197. case 0:
  1198. case 1:
  1199. break;
  1200. default:
  1201. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1202. return -EINVAL;
  1203. }
  1204. intel_fb = to_intel_framebuffer(crtc->fb);
  1205. obj = intel_fb->obj;
  1206. obj_priv = to_intel_bo(obj);
  1207. mutex_lock(&dev->struct_mutex);
  1208. ret = intel_pin_and_fence_fb_obj(dev, obj);
  1209. if (ret != 0) {
  1210. mutex_unlock(&dev->struct_mutex);
  1211. return ret;
  1212. }
  1213. ret = i915_gem_object_set_to_display_plane(obj);
  1214. if (ret != 0) {
  1215. i915_gem_object_unpin(obj);
  1216. mutex_unlock(&dev->struct_mutex);
  1217. return ret;
  1218. }
  1219. dspcntr = I915_READ(dspcntr_reg);
  1220. /* Mask out pixel format bits in case we change it */
  1221. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1222. switch (crtc->fb->bits_per_pixel) {
  1223. case 8:
  1224. dspcntr |= DISPPLANE_8BPP;
  1225. break;
  1226. case 16:
  1227. if (crtc->fb->depth == 15)
  1228. dspcntr |= DISPPLANE_15_16BPP;
  1229. else
  1230. dspcntr |= DISPPLANE_16BPP;
  1231. break;
  1232. case 24:
  1233. case 32:
  1234. if (crtc->fb->depth == 30)
  1235. dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
  1236. else
  1237. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1238. break;
  1239. default:
  1240. DRM_ERROR("Unknown color depth\n");
  1241. i915_gem_object_unpin(obj);
  1242. mutex_unlock(&dev->struct_mutex);
  1243. return -EINVAL;
  1244. }
  1245. if (IS_I965G(dev)) {
  1246. if (obj_priv->tiling_mode != I915_TILING_NONE)
  1247. dspcntr |= DISPPLANE_TILED;
  1248. else
  1249. dspcntr &= ~DISPPLANE_TILED;
  1250. }
  1251. if (HAS_PCH_SPLIT(dev))
  1252. /* must disable */
  1253. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1254. I915_WRITE(dspcntr_reg, dspcntr);
  1255. Start = obj_priv->gtt_offset;
  1256. Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
  1257. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
  1258. I915_WRITE(dspstride, crtc->fb->pitch);
  1259. if (IS_I965G(dev)) {
  1260. I915_WRITE(dspbase, Offset);
  1261. I915_READ(dspbase);
  1262. I915_WRITE(dspsurf, Start);
  1263. I915_READ(dspsurf);
  1264. I915_WRITE(dsptileoff, (y << 16) | x);
  1265. } else {
  1266. I915_WRITE(dspbase, Start + Offset);
  1267. I915_READ(dspbase);
  1268. }
  1269. if ((IS_I965G(dev) || plane == 0))
  1270. intel_update_fbc(crtc, &crtc->mode);
  1271. intel_wait_for_vblank(dev);
  1272. if (old_fb) {
  1273. intel_fb = to_intel_framebuffer(old_fb);
  1274. obj_priv = to_intel_bo(intel_fb->obj);
  1275. i915_gem_object_unpin(intel_fb->obj);
  1276. }
  1277. intel_increase_pllclock(crtc, true);
  1278. mutex_unlock(&dev->struct_mutex);
  1279. if (!dev->primary->master)
  1280. return 0;
  1281. master_priv = dev->primary->master->driver_priv;
  1282. if (!master_priv->sarea_priv)
  1283. return 0;
  1284. if (pipe) {
  1285. master_priv->sarea_priv->pipeB_x = x;
  1286. master_priv->sarea_priv->pipeB_y = y;
  1287. } else {
  1288. master_priv->sarea_priv->pipeA_x = x;
  1289. master_priv->sarea_priv->pipeA_y = y;
  1290. }
  1291. return 0;
  1292. }
  1293. /* Disable the VGA plane that we never use */
  1294. static void i915_disable_vga (struct drm_device *dev)
  1295. {
  1296. struct drm_i915_private *dev_priv = dev->dev_private;
  1297. u8 sr1;
  1298. u32 vga_reg;
  1299. if (HAS_PCH_SPLIT(dev))
  1300. vga_reg = CPU_VGACNTRL;
  1301. else
  1302. vga_reg = VGACNTRL;
  1303. if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
  1304. return;
  1305. I915_WRITE8(VGA_SR_INDEX, 1);
  1306. sr1 = I915_READ8(VGA_SR_DATA);
  1307. I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
  1308. udelay(100);
  1309. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  1310. }
  1311. static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
  1312. {
  1313. struct drm_device *dev = crtc->dev;
  1314. struct drm_i915_private *dev_priv = dev->dev_private;
  1315. u32 dpa_ctl;
  1316. DRM_DEBUG_KMS("\n");
  1317. dpa_ctl = I915_READ(DP_A);
  1318. dpa_ctl &= ~DP_PLL_ENABLE;
  1319. I915_WRITE(DP_A, dpa_ctl);
  1320. }
  1321. static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
  1322. {
  1323. struct drm_device *dev = crtc->dev;
  1324. struct drm_i915_private *dev_priv = dev->dev_private;
  1325. u32 dpa_ctl;
  1326. dpa_ctl = I915_READ(DP_A);
  1327. dpa_ctl |= DP_PLL_ENABLE;
  1328. I915_WRITE(DP_A, dpa_ctl);
  1329. udelay(200);
  1330. }
  1331. static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
  1332. {
  1333. struct drm_device *dev = crtc->dev;
  1334. struct drm_i915_private *dev_priv = dev->dev_private;
  1335. u32 dpa_ctl;
  1336. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  1337. dpa_ctl = I915_READ(DP_A);
  1338. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  1339. if (clock < 200000) {
  1340. u32 temp;
  1341. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  1342. /* workaround for 160Mhz:
  1343. 1) program 0x4600c bits 15:0 = 0x8124
  1344. 2) program 0x46010 bit 0 = 1
  1345. 3) program 0x46034 bit 24 = 1
  1346. 4) program 0x64000 bit 14 = 1
  1347. */
  1348. temp = I915_READ(0x4600c);
  1349. temp &= 0xffff0000;
  1350. I915_WRITE(0x4600c, temp | 0x8124);
  1351. temp = I915_READ(0x46010);
  1352. I915_WRITE(0x46010, temp | 1);
  1353. temp = I915_READ(0x46034);
  1354. I915_WRITE(0x46034, temp | (1 << 24));
  1355. } else {
  1356. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  1357. }
  1358. I915_WRITE(DP_A, dpa_ctl);
  1359. udelay(500);
  1360. }
  1361. /* The FDI link training functions for ILK/Ibexpeak. */
  1362. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  1363. {
  1364. struct drm_device *dev = crtc->dev;
  1365. struct drm_i915_private *dev_priv = dev->dev_private;
  1366. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1367. int pipe = intel_crtc->pipe;
  1368. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1369. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1370. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1371. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1372. u32 temp, tries = 0;
  1373. /* enable CPU FDI TX and PCH FDI RX */
  1374. temp = I915_READ(fdi_tx_reg);
  1375. temp |= FDI_TX_ENABLE;
  1376. temp &= ~(7 << 19);
  1377. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1378. temp &= ~FDI_LINK_TRAIN_NONE;
  1379. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1380. I915_WRITE(fdi_tx_reg, temp);
  1381. I915_READ(fdi_tx_reg);
  1382. temp = I915_READ(fdi_rx_reg);
  1383. temp &= ~FDI_LINK_TRAIN_NONE;
  1384. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1385. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1386. I915_READ(fdi_rx_reg);
  1387. udelay(150);
  1388. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1389. for train result */
  1390. temp = I915_READ(fdi_rx_imr_reg);
  1391. temp &= ~FDI_RX_SYMBOL_LOCK;
  1392. temp &= ~FDI_RX_BIT_LOCK;
  1393. I915_WRITE(fdi_rx_imr_reg, temp);
  1394. I915_READ(fdi_rx_imr_reg);
  1395. udelay(150);
  1396. for (;;) {
  1397. temp = I915_READ(fdi_rx_iir_reg);
  1398. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1399. if ((temp & FDI_RX_BIT_LOCK)) {
  1400. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1401. I915_WRITE(fdi_rx_iir_reg,
  1402. temp | FDI_RX_BIT_LOCK);
  1403. break;
  1404. }
  1405. tries++;
  1406. if (tries > 5) {
  1407. DRM_DEBUG_KMS("FDI train 1 fail!\n");
  1408. break;
  1409. }
  1410. }
  1411. /* Train 2 */
  1412. temp = I915_READ(fdi_tx_reg);
  1413. temp &= ~FDI_LINK_TRAIN_NONE;
  1414. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1415. I915_WRITE(fdi_tx_reg, temp);
  1416. temp = I915_READ(fdi_rx_reg);
  1417. temp &= ~FDI_LINK_TRAIN_NONE;
  1418. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1419. I915_WRITE(fdi_rx_reg, temp);
  1420. udelay(150);
  1421. tries = 0;
  1422. for (;;) {
  1423. temp = I915_READ(fdi_rx_iir_reg);
  1424. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1425. if (temp & FDI_RX_SYMBOL_LOCK) {
  1426. I915_WRITE(fdi_rx_iir_reg,
  1427. temp | FDI_RX_SYMBOL_LOCK);
  1428. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1429. break;
  1430. }
  1431. tries++;
  1432. if (tries > 5) {
  1433. DRM_DEBUG_KMS("FDI train 2 fail!\n");
  1434. break;
  1435. }
  1436. }
  1437. DRM_DEBUG_KMS("FDI train done\n");
  1438. }
  1439. static int snb_b_fdi_train_param [] = {
  1440. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  1441. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  1442. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  1443. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  1444. };
  1445. /* The FDI link training functions for SNB/Cougarpoint. */
  1446. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  1447. {
  1448. struct drm_device *dev = crtc->dev;
  1449. struct drm_i915_private *dev_priv = dev->dev_private;
  1450. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1451. int pipe = intel_crtc->pipe;
  1452. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1453. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1454. int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
  1455. int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
  1456. u32 temp, i;
  1457. /* enable CPU FDI TX and PCH FDI RX */
  1458. temp = I915_READ(fdi_tx_reg);
  1459. temp |= FDI_TX_ENABLE;
  1460. temp &= ~(7 << 19);
  1461. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1462. temp &= ~FDI_LINK_TRAIN_NONE;
  1463. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1464. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1465. /* SNB-B */
  1466. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1467. I915_WRITE(fdi_tx_reg, temp);
  1468. I915_READ(fdi_tx_reg);
  1469. temp = I915_READ(fdi_rx_reg);
  1470. if (HAS_PCH_CPT(dev)) {
  1471. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1472. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1473. } else {
  1474. temp &= ~FDI_LINK_TRAIN_NONE;
  1475. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1476. }
  1477. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
  1478. I915_READ(fdi_rx_reg);
  1479. udelay(150);
  1480. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  1481. for train result */
  1482. temp = I915_READ(fdi_rx_imr_reg);
  1483. temp &= ~FDI_RX_SYMBOL_LOCK;
  1484. temp &= ~FDI_RX_BIT_LOCK;
  1485. I915_WRITE(fdi_rx_imr_reg, temp);
  1486. I915_READ(fdi_rx_imr_reg);
  1487. udelay(150);
  1488. for (i = 0; i < 4; i++ ) {
  1489. temp = I915_READ(fdi_tx_reg);
  1490. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1491. temp |= snb_b_fdi_train_param[i];
  1492. I915_WRITE(fdi_tx_reg, temp);
  1493. udelay(500);
  1494. temp = I915_READ(fdi_rx_iir_reg);
  1495. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1496. if (temp & FDI_RX_BIT_LOCK) {
  1497. I915_WRITE(fdi_rx_iir_reg,
  1498. temp | FDI_RX_BIT_LOCK);
  1499. DRM_DEBUG_KMS("FDI train 1 done.\n");
  1500. break;
  1501. }
  1502. }
  1503. if (i == 4)
  1504. DRM_DEBUG_KMS("FDI train 1 fail!\n");
  1505. /* Train 2 */
  1506. temp = I915_READ(fdi_tx_reg);
  1507. temp &= ~FDI_LINK_TRAIN_NONE;
  1508. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1509. if (IS_GEN6(dev)) {
  1510. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1511. /* SNB-B */
  1512. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  1513. }
  1514. I915_WRITE(fdi_tx_reg, temp);
  1515. temp = I915_READ(fdi_rx_reg);
  1516. if (HAS_PCH_CPT(dev)) {
  1517. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1518. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  1519. } else {
  1520. temp &= ~FDI_LINK_TRAIN_NONE;
  1521. temp |= FDI_LINK_TRAIN_PATTERN_2;
  1522. }
  1523. I915_WRITE(fdi_rx_reg, temp);
  1524. udelay(150);
  1525. for (i = 0; i < 4; i++ ) {
  1526. temp = I915_READ(fdi_tx_reg);
  1527. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  1528. temp |= snb_b_fdi_train_param[i];
  1529. I915_WRITE(fdi_tx_reg, temp);
  1530. udelay(500);
  1531. temp = I915_READ(fdi_rx_iir_reg);
  1532. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  1533. if (temp & FDI_RX_SYMBOL_LOCK) {
  1534. I915_WRITE(fdi_rx_iir_reg,
  1535. temp | FDI_RX_SYMBOL_LOCK);
  1536. DRM_DEBUG_KMS("FDI train 2 done.\n");
  1537. break;
  1538. }
  1539. }
  1540. if (i == 4)
  1541. DRM_DEBUG_KMS("FDI train 2 fail!\n");
  1542. DRM_DEBUG_KMS("FDI train done.\n");
  1543. }
  1544. static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
  1545. {
  1546. struct drm_device *dev = crtc->dev;
  1547. struct drm_i915_private *dev_priv = dev->dev_private;
  1548. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1549. int pipe = intel_crtc->pipe;
  1550. int plane = intel_crtc->plane;
  1551. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  1552. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1553. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1554. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1555. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  1556. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  1557. int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
  1558. int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
  1559. int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
  1560. int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
  1561. int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  1562. int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  1563. int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  1564. int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  1565. int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  1566. int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  1567. int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
  1568. int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
  1569. int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
  1570. int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
  1571. int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
  1572. int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  1573. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  1574. u32 temp;
  1575. int n;
  1576. u32 pipe_bpc;
  1577. temp = I915_READ(pipeconf_reg);
  1578. pipe_bpc = temp & PIPE_BPC_MASK;
  1579. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1580. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1581. */
  1582. switch (mode) {
  1583. case DRM_MODE_DPMS_ON:
  1584. case DRM_MODE_DPMS_STANDBY:
  1585. case DRM_MODE_DPMS_SUSPEND:
  1586. DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
  1587. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1588. temp = I915_READ(PCH_LVDS);
  1589. if ((temp & LVDS_PORT_EN) == 0) {
  1590. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  1591. POSTING_READ(PCH_LVDS);
  1592. }
  1593. }
  1594. if (HAS_eDP) {
  1595. /* enable eDP PLL */
  1596. ironlake_enable_pll_edp(crtc);
  1597. } else {
  1598. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  1599. temp = I915_READ(fdi_rx_reg);
  1600. /*
  1601. * make the BPC in FDI Rx be consistent with that in
  1602. * pipeconf reg.
  1603. */
  1604. temp &= ~(0x7 << 16);
  1605. temp |= (pipe_bpc << 11);
  1606. temp &= ~(7 << 19);
  1607. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  1608. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  1609. I915_READ(fdi_rx_reg);
  1610. udelay(200);
  1611. /* Switch from Rawclk to PCDclk */
  1612. temp = I915_READ(fdi_rx_reg);
  1613. I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
  1614. I915_READ(fdi_rx_reg);
  1615. udelay(200);
  1616. /* Enable CPU FDI TX PLL, always on for Ironlake */
  1617. temp = I915_READ(fdi_tx_reg);
  1618. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  1619. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  1620. I915_READ(fdi_tx_reg);
  1621. udelay(100);
  1622. }
  1623. }
  1624. /* Enable panel fitting for LVDS */
  1625. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1626. temp = I915_READ(pf_ctl_reg);
  1627. I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
  1628. /* currently full aspect */
  1629. I915_WRITE(pf_win_pos, 0);
  1630. I915_WRITE(pf_win_size,
  1631. (dev_priv->panel_fixed_mode->hdisplay << 16) |
  1632. (dev_priv->panel_fixed_mode->vdisplay));
  1633. }
  1634. /* Enable CPU pipe */
  1635. temp = I915_READ(pipeconf_reg);
  1636. if ((temp & PIPEACONF_ENABLE) == 0) {
  1637. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1638. I915_READ(pipeconf_reg);
  1639. udelay(100);
  1640. }
  1641. /* configure and enable CPU plane */
  1642. temp = I915_READ(dspcntr_reg);
  1643. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1644. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1645. /* Flush the plane changes */
  1646. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1647. }
  1648. if (!HAS_eDP) {
  1649. /* For PCH output, training FDI link */
  1650. if (IS_GEN6(dev))
  1651. gen6_fdi_link_train(crtc);
  1652. else
  1653. ironlake_fdi_link_train(crtc);
  1654. /* enable PCH DPLL */
  1655. temp = I915_READ(pch_dpll_reg);
  1656. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1657. I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
  1658. I915_READ(pch_dpll_reg);
  1659. }
  1660. udelay(200);
  1661. if (HAS_PCH_CPT(dev)) {
  1662. /* Be sure PCH DPLL SEL is set */
  1663. temp = I915_READ(PCH_DPLL_SEL);
  1664. if (trans_dpll_sel == 0 &&
  1665. (temp & TRANSA_DPLL_ENABLE) == 0)
  1666. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  1667. else if (trans_dpll_sel == 1 &&
  1668. (temp & TRANSB_DPLL_ENABLE) == 0)
  1669. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1670. I915_WRITE(PCH_DPLL_SEL, temp);
  1671. I915_READ(PCH_DPLL_SEL);
  1672. }
  1673. /* set transcoder timing */
  1674. I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
  1675. I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
  1676. I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
  1677. I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
  1678. I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
  1679. I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
  1680. /* enable normal train */
  1681. temp = I915_READ(fdi_tx_reg);
  1682. temp &= ~FDI_LINK_TRAIN_NONE;
  1683. I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
  1684. FDI_TX_ENHANCE_FRAME_ENABLE);
  1685. I915_READ(fdi_tx_reg);
  1686. temp = I915_READ(fdi_rx_reg);
  1687. if (HAS_PCH_CPT(dev)) {
  1688. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1689. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  1690. } else {
  1691. temp &= ~FDI_LINK_TRAIN_NONE;
  1692. temp |= FDI_LINK_TRAIN_NONE;
  1693. }
  1694. I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  1695. I915_READ(fdi_rx_reg);
  1696. /* wait one idle pattern time */
  1697. udelay(100);
  1698. /* For PCH DP, enable TRANS_DP_CTL */
  1699. if (HAS_PCH_CPT(dev) &&
  1700. intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  1701. int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
  1702. int reg;
  1703. reg = I915_READ(trans_dp_ctl);
  1704. reg &= ~TRANS_DP_PORT_SEL_MASK;
  1705. reg = TRANS_DP_OUTPUT_ENABLE |
  1706. TRANS_DP_ENH_FRAMING |
  1707. TRANS_DP_VSYNC_ACTIVE_HIGH |
  1708. TRANS_DP_HSYNC_ACTIVE_HIGH;
  1709. switch (intel_trans_dp_port_sel(crtc)) {
  1710. case PCH_DP_B:
  1711. reg |= TRANS_DP_PORT_SEL_B;
  1712. break;
  1713. case PCH_DP_C:
  1714. reg |= TRANS_DP_PORT_SEL_C;
  1715. break;
  1716. case PCH_DP_D:
  1717. reg |= TRANS_DP_PORT_SEL_D;
  1718. break;
  1719. default:
  1720. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  1721. reg |= TRANS_DP_PORT_SEL_B;
  1722. break;
  1723. }
  1724. I915_WRITE(trans_dp_ctl, reg);
  1725. POSTING_READ(trans_dp_ctl);
  1726. }
  1727. /* enable PCH transcoder */
  1728. temp = I915_READ(transconf_reg);
  1729. /*
  1730. * make the BPC in transcoder be consistent with
  1731. * that in pipeconf reg.
  1732. */
  1733. temp &= ~PIPE_BPC_MASK;
  1734. temp |= pipe_bpc;
  1735. I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  1736. I915_READ(transconf_reg);
  1737. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
  1738. ;
  1739. }
  1740. intel_crtc_load_lut(crtc);
  1741. break;
  1742. case DRM_MODE_DPMS_OFF:
  1743. DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
  1744. drm_vblank_off(dev, pipe);
  1745. /* Disable display plane */
  1746. temp = I915_READ(dspcntr_reg);
  1747. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1748. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1749. /* Flush the plane changes */
  1750. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1751. I915_READ(dspbase_reg);
  1752. }
  1753. i915_disable_vga(dev);
  1754. /* disable cpu pipe, disable after all planes disabled */
  1755. temp = I915_READ(pipeconf_reg);
  1756. if ((temp & PIPEACONF_ENABLE) != 0) {
  1757. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1758. I915_READ(pipeconf_reg);
  1759. n = 0;
  1760. /* wait for cpu pipe off, pipe state */
  1761. while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
  1762. n++;
  1763. if (n < 60) {
  1764. udelay(500);
  1765. continue;
  1766. } else {
  1767. DRM_DEBUG_KMS("pipe %d off delay\n",
  1768. pipe);
  1769. break;
  1770. }
  1771. }
  1772. } else
  1773. DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
  1774. udelay(100);
  1775. /* Disable PF */
  1776. temp = I915_READ(pf_ctl_reg);
  1777. if ((temp & PF_ENABLE) != 0) {
  1778. I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
  1779. I915_READ(pf_ctl_reg);
  1780. }
  1781. I915_WRITE(pf_win_size, 0);
  1782. POSTING_READ(pf_win_size);
  1783. /* disable CPU FDI tx and PCH FDI rx */
  1784. temp = I915_READ(fdi_tx_reg);
  1785. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
  1786. I915_READ(fdi_tx_reg);
  1787. temp = I915_READ(fdi_rx_reg);
  1788. /* BPC in FDI rx is consistent with that in pipeconf */
  1789. temp &= ~(0x07 << 16);
  1790. temp |= (pipe_bpc << 11);
  1791. I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  1792. I915_READ(fdi_rx_reg);
  1793. udelay(100);
  1794. /* still set train pattern 1 */
  1795. temp = I915_READ(fdi_tx_reg);
  1796. temp &= ~FDI_LINK_TRAIN_NONE;
  1797. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1798. I915_WRITE(fdi_tx_reg, temp);
  1799. POSTING_READ(fdi_tx_reg);
  1800. temp = I915_READ(fdi_rx_reg);
  1801. if (HAS_PCH_CPT(dev)) {
  1802. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  1803. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  1804. } else {
  1805. temp &= ~FDI_LINK_TRAIN_NONE;
  1806. temp |= FDI_LINK_TRAIN_PATTERN_1;
  1807. }
  1808. I915_WRITE(fdi_rx_reg, temp);
  1809. POSTING_READ(fdi_rx_reg);
  1810. udelay(100);
  1811. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  1812. temp = I915_READ(PCH_LVDS);
  1813. I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
  1814. I915_READ(PCH_LVDS);
  1815. udelay(100);
  1816. }
  1817. /* disable PCH transcoder */
  1818. temp = I915_READ(transconf_reg);
  1819. if ((temp & TRANS_ENABLE) != 0) {
  1820. I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
  1821. I915_READ(transconf_reg);
  1822. n = 0;
  1823. /* wait for PCH transcoder off, transcoder state */
  1824. while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
  1825. n++;
  1826. if (n < 60) {
  1827. udelay(500);
  1828. continue;
  1829. } else {
  1830. DRM_DEBUG_KMS("transcoder %d off "
  1831. "delay\n", pipe);
  1832. break;
  1833. }
  1834. }
  1835. }
  1836. temp = I915_READ(transconf_reg);
  1837. /* BPC in transcoder is consistent with that in pipeconf */
  1838. temp &= ~PIPE_BPC_MASK;
  1839. temp |= pipe_bpc;
  1840. I915_WRITE(transconf_reg, temp);
  1841. I915_READ(transconf_reg);
  1842. udelay(100);
  1843. if (HAS_PCH_CPT(dev)) {
  1844. /* disable TRANS_DP_CTL */
  1845. int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
  1846. int reg;
  1847. reg = I915_READ(trans_dp_ctl);
  1848. reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  1849. I915_WRITE(trans_dp_ctl, reg);
  1850. POSTING_READ(trans_dp_ctl);
  1851. /* disable DPLL_SEL */
  1852. temp = I915_READ(PCH_DPLL_SEL);
  1853. if (trans_dpll_sel == 0)
  1854. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  1855. else
  1856. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  1857. I915_WRITE(PCH_DPLL_SEL, temp);
  1858. I915_READ(PCH_DPLL_SEL);
  1859. }
  1860. /* disable PCH DPLL */
  1861. temp = I915_READ(pch_dpll_reg);
  1862. I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1863. I915_READ(pch_dpll_reg);
  1864. if (HAS_eDP) {
  1865. ironlake_disable_pll_edp(crtc);
  1866. }
  1867. /* Switch from PCDclk to Rawclk */
  1868. temp = I915_READ(fdi_rx_reg);
  1869. temp &= ~FDI_SEL_PCDCLK;
  1870. I915_WRITE(fdi_rx_reg, temp);
  1871. I915_READ(fdi_rx_reg);
  1872. /* Disable CPU FDI TX PLL */
  1873. temp = I915_READ(fdi_tx_reg);
  1874. I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
  1875. I915_READ(fdi_tx_reg);
  1876. udelay(100);
  1877. temp = I915_READ(fdi_rx_reg);
  1878. temp &= ~FDI_RX_PLL_ENABLE;
  1879. I915_WRITE(fdi_rx_reg, temp);
  1880. I915_READ(fdi_rx_reg);
  1881. /* Wait for the clocks to turn off. */
  1882. udelay(100);
  1883. break;
  1884. }
  1885. }
  1886. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  1887. {
  1888. struct intel_overlay *overlay;
  1889. int ret;
  1890. if (!enable && intel_crtc->overlay) {
  1891. overlay = intel_crtc->overlay;
  1892. mutex_lock(&overlay->dev->struct_mutex);
  1893. for (;;) {
  1894. ret = intel_overlay_switch_off(overlay);
  1895. if (ret == 0)
  1896. break;
  1897. ret = intel_overlay_recover_from_interrupt(overlay, 0);
  1898. if (ret != 0) {
  1899. /* overlay doesn't react anymore. Usually
  1900. * results in a black screen and an unkillable
  1901. * X server. */
  1902. BUG();
  1903. overlay->hw_wedged = HW_WEDGED;
  1904. break;
  1905. }
  1906. }
  1907. mutex_unlock(&overlay->dev->struct_mutex);
  1908. }
  1909. /* Let userspace switch the overlay on again. In most cases userspace
  1910. * has to recompute where to put it anyway. */
  1911. return;
  1912. }
  1913. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  1914. {
  1915. struct drm_device *dev = crtc->dev;
  1916. struct drm_i915_private *dev_priv = dev->dev_private;
  1917. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1918. int pipe = intel_crtc->pipe;
  1919. int plane = intel_crtc->plane;
  1920. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  1921. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  1922. int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
  1923. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  1924. u32 temp;
  1925. /* XXX: When our outputs are all unaware of DPMS modes other than off
  1926. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  1927. */
  1928. switch (mode) {
  1929. case DRM_MODE_DPMS_ON:
  1930. case DRM_MODE_DPMS_STANDBY:
  1931. case DRM_MODE_DPMS_SUSPEND:
  1932. intel_update_watermarks(dev);
  1933. /* Enable the DPLL */
  1934. temp = I915_READ(dpll_reg);
  1935. if ((temp & DPLL_VCO_ENABLE) == 0) {
  1936. I915_WRITE(dpll_reg, temp);
  1937. I915_READ(dpll_reg);
  1938. /* Wait for the clocks to stabilize. */
  1939. udelay(150);
  1940. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1941. I915_READ(dpll_reg);
  1942. /* Wait for the clocks to stabilize. */
  1943. udelay(150);
  1944. I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
  1945. I915_READ(dpll_reg);
  1946. /* Wait for the clocks to stabilize. */
  1947. udelay(150);
  1948. }
  1949. /* Enable the pipe */
  1950. temp = I915_READ(pipeconf_reg);
  1951. if ((temp & PIPEACONF_ENABLE) == 0)
  1952. I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
  1953. /* Enable the plane */
  1954. temp = I915_READ(dspcntr_reg);
  1955. if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
  1956. I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
  1957. /* Flush the plane changes */
  1958. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1959. }
  1960. intel_crtc_load_lut(crtc);
  1961. if ((IS_I965G(dev) || plane == 0))
  1962. intel_update_fbc(crtc, &crtc->mode);
  1963. /* Give the overlay scaler a chance to enable if it's on this pipe */
  1964. intel_crtc_dpms_overlay(intel_crtc, true);
  1965. break;
  1966. case DRM_MODE_DPMS_OFF:
  1967. intel_update_watermarks(dev);
  1968. /* Give the overlay scaler a chance to disable if it's on this pipe */
  1969. intel_crtc_dpms_overlay(intel_crtc, false);
  1970. drm_vblank_off(dev, pipe);
  1971. if (dev_priv->cfb_plane == plane &&
  1972. dev_priv->display.disable_fbc)
  1973. dev_priv->display.disable_fbc(dev);
  1974. /* Disable the VGA plane that we never use */
  1975. i915_disable_vga(dev);
  1976. /* Disable display plane */
  1977. temp = I915_READ(dspcntr_reg);
  1978. if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
  1979. I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
  1980. /* Flush the plane changes */
  1981. I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
  1982. I915_READ(dspbase_reg);
  1983. }
  1984. if (!IS_I9XX(dev)) {
  1985. /* Wait for vblank for the disable to take effect */
  1986. intel_wait_for_vblank(dev);
  1987. }
  1988. /* Next, disable display pipes */
  1989. temp = I915_READ(pipeconf_reg);
  1990. if ((temp & PIPEACONF_ENABLE) != 0) {
  1991. I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
  1992. I915_READ(pipeconf_reg);
  1993. }
  1994. /* Wait for vblank for the disable to take effect. */
  1995. intel_wait_for_vblank(dev);
  1996. temp = I915_READ(dpll_reg);
  1997. if ((temp & DPLL_VCO_ENABLE) != 0) {
  1998. I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
  1999. I915_READ(dpll_reg);
  2000. }
  2001. /* Wait for the clocks to turn off. */
  2002. udelay(150);
  2003. break;
  2004. }
  2005. }
  2006. /**
  2007. * Sets the power management mode of the pipe and plane.
  2008. *
  2009. * This code should probably grow support for turning the cursor off and back
  2010. * on appropriately at the same time as we're turning the pipe off/on.
  2011. */
  2012. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  2013. {
  2014. struct drm_device *dev = crtc->dev;
  2015. struct drm_i915_private *dev_priv = dev->dev_private;
  2016. struct drm_i915_master_private *master_priv;
  2017. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2018. int pipe = intel_crtc->pipe;
  2019. bool enabled;
  2020. dev_priv->display.dpms(crtc, mode);
  2021. intel_crtc->dpms_mode = mode;
  2022. if (!dev->primary->master)
  2023. return;
  2024. master_priv = dev->primary->master->driver_priv;
  2025. if (!master_priv->sarea_priv)
  2026. return;
  2027. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  2028. switch (pipe) {
  2029. case 0:
  2030. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2031. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2032. break;
  2033. case 1:
  2034. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2035. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2036. break;
  2037. default:
  2038. DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
  2039. break;
  2040. }
  2041. }
  2042. static void intel_crtc_prepare (struct drm_crtc *crtc)
  2043. {
  2044. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2045. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  2046. }
  2047. static void intel_crtc_commit (struct drm_crtc *crtc)
  2048. {
  2049. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2050. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  2051. }
  2052. void intel_encoder_prepare (struct drm_encoder *encoder)
  2053. {
  2054. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2055. /* lvds has its own version of prepare see intel_lvds_prepare */
  2056. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  2057. }
  2058. void intel_encoder_commit (struct drm_encoder *encoder)
  2059. {
  2060. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2061. /* lvds has its own version of commit see intel_lvds_commit */
  2062. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2063. }
  2064. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  2065. struct drm_display_mode *mode,
  2066. struct drm_display_mode *adjusted_mode)
  2067. {
  2068. struct drm_device *dev = crtc->dev;
  2069. if (HAS_PCH_SPLIT(dev)) {
  2070. /* FDI link clock is fixed at 2.7G */
  2071. if (mode->clock * 3 > 27000 * 4)
  2072. return MODE_CLOCK_HIGH;
  2073. }
  2074. return true;
  2075. }
  2076. static int i945_get_display_clock_speed(struct drm_device *dev)
  2077. {
  2078. return 400000;
  2079. }
  2080. static int i915_get_display_clock_speed(struct drm_device *dev)
  2081. {
  2082. return 333000;
  2083. }
  2084. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  2085. {
  2086. return 200000;
  2087. }
  2088. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  2089. {
  2090. u16 gcfgc = 0;
  2091. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  2092. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  2093. return 133000;
  2094. else {
  2095. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  2096. case GC_DISPLAY_CLOCK_333_MHZ:
  2097. return 333000;
  2098. default:
  2099. case GC_DISPLAY_CLOCK_190_200_MHZ:
  2100. return 190000;
  2101. }
  2102. }
  2103. }
  2104. static int i865_get_display_clock_speed(struct drm_device *dev)
  2105. {
  2106. return 266000;
  2107. }
  2108. static int i855_get_display_clock_speed(struct drm_device *dev)
  2109. {
  2110. u16 hpllcc = 0;
  2111. /* Assume that the hardware is in the high speed state. This
  2112. * should be the default.
  2113. */
  2114. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  2115. case GC_CLOCK_133_200:
  2116. case GC_CLOCK_100_200:
  2117. return 200000;
  2118. case GC_CLOCK_166_250:
  2119. return 250000;
  2120. case GC_CLOCK_100_133:
  2121. return 133000;
  2122. }
  2123. /* Shouldn't happen */
  2124. return 0;
  2125. }
  2126. static int i830_get_display_clock_speed(struct drm_device *dev)
  2127. {
  2128. return 133000;
  2129. }
  2130. /**
  2131. * Return the pipe currently connected to the panel fitter,
  2132. * or -1 if the panel fitter is not present or not in use
  2133. */
  2134. int intel_panel_fitter_pipe (struct drm_device *dev)
  2135. {
  2136. struct drm_i915_private *dev_priv = dev->dev_private;
  2137. u32 pfit_control;
  2138. /* i830 doesn't have a panel fitter */
  2139. if (IS_I830(dev))
  2140. return -1;
  2141. pfit_control = I915_READ(PFIT_CONTROL);
  2142. /* See if the panel fitter is in use */
  2143. if ((pfit_control & PFIT_ENABLE) == 0)
  2144. return -1;
  2145. /* 965 can place panel fitter on either pipe */
  2146. if (IS_I965G(dev))
  2147. return (pfit_control >> 29) & 0x3;
  2148. /* older chips can only use pipe 1 */
  2149. return 1;
  2150. }
  2151. struct fdi_m_n {
  2152. u32 tu;
  2153. u32 gmch_m;
  2154. u32 gmch_n;
  2155. u32 link_m;
  2156. u32 link_n;
  2157. };
  2158. static void
  2159. fdi_reduce_ratio(u32 *num, u32 *den)
  2160. {
  2161. while (*num > 0xffffff || *den > 0xffffff) {
  2162. *num >>= 1;
  2163. *den >>= 1;
  2164. }
  2165. }
  2166. #define DATA_N 0x800000
  2167. #define LINK_N 0x80000
  2168. static void
  2169. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  2170. int link_clock, struct fdi_m_n *m_n)
  2171. {
  2172. u64 temp;
  2173. m_n->tu = 64; /* default size */
  2174. temp = (u64) DATA_N * pixel_clock;
  2175. temp = div_u64(temp, link_clock);
  2176. m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
  2177. m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
  2178. m_n->gmch_n = DATA_N;
  2179. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  2180. temp = (u64) LINK_N * pixel_clock;
  2181. m_n->link_m = div_u64(temp, link_clock);
  2182. m_n->link_n = LINK_N;
  2183. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  2184. }
  2185. struct intel_watermark_params {
  2186. unsigned long fifo_size;
  2187. unsigned long max_wm;
  2188. unsigned long default_wm;
  2189. unsigned long guard_size;
  2190. unsigned long cacheline_size;
  2191. };
  2192. /* Pineview has different values for various configs */
  2193. static struct intel_watermark_params pineview_display_wm = {
  2194. PINEVIEW_DISPLAY_FIFO,
  2195. PINEVIEW_MAX_WM,
  2196. PINEVIEW_DFT_WM,
  2197. PINEVIEW_GUARD_WM,
  2198. PINEVIEW_FIFO_LINE_SIZE
  2199. };
  2200. static struct intel_watermark_params pineview_display_hplloff_wm = {
  2201. PINEVIEW_DISPLAY_FIFO,
  2202. PINEVIEW_MAX_WM,
  2203. PINEVIEW_DFT_HPLLOFF_WM,
  2204. PINEVIEW_GUARD_WM,
  2205. PINEVIEW_FIFO_LINE_SIZE
  2206. };
  2207. static struct intel_watermark_params pineview_cursor_wm = {
  2208. PINEVIEW_CURSOR_FIFO,
  2209. PINEVIEW_CURSOR_MAX_WM,
  2210. PINEVIEW_CURSOR_DFT_WM,
  2211. PINEVIEW_CURSOR_GUARD_WM,
  2212. PINEVIEW_FIFO_LINE_SIZE,
  2213. };
  2214. static struct intel_watermark_params pineview_cursor_hplloff_wm = {
  2215. PINEVIEW_CURSOR_FIFO,
  2216. PINEVIEW_CURSOR_MAX_WM,
  2217. PINEVIEW_CURSOR_DFT_WM,
  2218. PINEVIEW_CURSOR_GUARD_WM,
  2219. PINEVIEW_FIFO_LINE_SIZE
  2220. };
  2221. static struct intel_watermark_params g4x_wm_info = {
  2222. G4X_FIFO_SIZE,
  2223. G4X_MAX_WM,
  2224. G4X_MAX_WM,
  2225. 2,
  2226. G4X_FIFO_LINE_SIZE,
  2227. };
  2228. static struct intel_watermark_params i945_wm_info = {
  2229. I945_FIFO_SIZE,
  2230. I915_MAX_WM,
  2231. 1,
  2232. 2,
  2233. I915_FIFO_LINE_SIZE
  2234. };
  2235. static struct intel_watermark_params i915_wm_info = {
  2236. I915_FIFO_SIZE,
  2237. I915_MAX_WM,
  2238. 1,
  2239. 2,
  2240. I915_FIFO_LINE_SIZE
  2241. };
  2242. static struct intel_watermark_params i855_wm_info = {
  2243. I855GM_FIFO_SIZE,
  2244. I915_MAX_WM,
  2245. 1,
  2246. 2,
  2247. I830_FIFO_LINE_SIZE
  2248. };
  2249. static struct intel_watermark_params i830_wm_info = {
  2250. I830_FIFO_SIZE,
  2251. I915_MAX_WM,
  2252. 1,
  2253. 2,
  2254. I830_FIFO_LINE_SIZE
  2255. };
  2256. static struct intel_watermark_params ironlake_display_wm_info = {
  2257. ILK_DISPLAY_FIFO,
  2258. ILK_DISPLAY_MAXWM,
  2259. ILK_DISPLAY_DFTWM,
  2260. 2,
  2261. ILK_FIFO_LINE_SIZE
  2262. };
  2263. static struct intel_watermark_params ironlake_display_srwm_info = {
  2264. ILK_DISPLAY_SR_FIFO,
  2265. ILK_DISPLAY_MAX_SRWM,
  2266. ILK_DISPLAY_DFT_SRWM,
  2267. 2,
  2268. ILK_FIFO_LINE_SIZE
  2269. };
  2270. static struct intel_watermark_params ironlake_cursor_srwm_info = {
  2271. ILK_CURSOR_SR_FIFO,
  2272. ILK_CURSOR_MAX_SRWM,
  2273. ILK_CURSOR_DFT_SRWM,
  2274. 2,
  2275. ILK_FIFO_LINE_SIZE
  2276. };
  2277. /**
  2278. * intel_calculate_wm - calculate watermark level
  2279. * @clock_in_khz: pixel clock
  2280. * @wm: chip FIFO params
  2281. * @pixel_size: display pixel size
  2282. * @latency_ns: memory latency for the platform
  2283. *
  2284. * Calculate the watermark level (the level at which the display plane will
  2285. * start fetching from memory again). Each chip has a different display
  2286. * FIFO size and allocation, so the caller needs to figure that out and pass
  2287. * in the correct intel_watermark_params structure.
  2288. *
  2289. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  2290. * on the pixel size. When it reaches the watermark level, it'll start
  2291. * fetching FIFO line sized based chunks from memory until the FIFO fills
  2292. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  2293. * will occur, and a display engine hang could result.
  2294. */
  2295. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  2296. struct intel_watermark_params *wm,
  2297. int pixel_size,
  2298. unsigned long latency_ns)
  2299. {
  2300. long entries_required, wm_size;
  2301. /*
  2302. * Note: we need to make sure we don't overflow for various clock &
  2303. * latency values.
  2304. * clocks go from a few thousand to several hundred thousand.
  2305. * latency is usually a few thousand
  2306. */
  2307. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  2308. 1000;
  2309. entries_required /= wm->cacheline_size;
  2310. DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
  2311. wm_size = wm->fifo_size - (entries_required + wm->guard_size);
  2312. DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
  2313. /* Don't promote wm_size to unsigned... */
  2314. if (wm_size > (long)wm->max_wm)
  2315. wm_size = wm->max_wm;
  2316. if (wm_size <= 0)
  2317. wm_size = wm->default_wm;
  2318. return wm_size;
  2319. }
  2320. struct cxsr_latency {
  2321. int is_desktop;
  2322. unsigned long fsb_freq;
  2323. unsigned long mem_freq;
  2324. unsigned long display_sr;
  2325. unsigned long display_hpll_disable;
  2326. unsigned long cursor_sr;
  2327. unsigned long cursor_hpll_disable;
  2328. };
  2329. static struct cxsr_latency cxsr_latency_table[] = {
  2330. {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  2331. {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  2332. {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  2333. {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  2334. {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  2335. {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  2336. {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  2337. {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  2338. {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  2339. {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  2340. {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  2341. {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  2342. {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  2343. {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  2344. {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  2345. {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  2346. {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  2347. {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  2348. };
  2349. static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
  2350. int mem)
  2351. {
  2352. int i;
  2353. struct cxsr_latency *latency;
  2354. if (fsb == 0 || mem == 0)
  2355. return NULL;
  2356. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  2357. latency = &cxsr_latency_table[i];
  2358. if (is_desktop == latency->is_desktop &&
  2359. fsb == latency->fsb_freq && mem == latency->mem_freq)
  2360. return latency;
  2361. }
  2362. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2363. return NULL;
  2364. }
  2365. static void pineview_disable_cxsr(struct drm_device *dev)
  2366. {
  2367. struct drm_i915_private *dev_priv = dev->dev_private;
  2368. u32 reg;
  2369. /* deactivate cxsr */
  2370. reg = I915_READ(DSPFW3);
  2371. reg &= ~(PINEVIEW_SELF_REFRESH_EN);
  2372. I915_WRITE(DSPFW3, reg);
  2373. DRM_INFO("Big FIFO is disabled\n");
  2374. }
  2375. /*
  2376. * Latency for FIFO fetches is dependent on several factors:
  2377. * - memory configuration (speed, channels)
  2378. * - chipset
  2379. * - current MCH state
  2380. * It can be fairly high in some situations, so here we assume a fairly
  2381. * pessimal value. It's a tradeoff between extra memory fetches (if we
  2382. * set this value too high, the FIFO will fetch frequently to stay full)
  2383. * and power consumption (set it too low to save power and we might see
  2384. * FIFO underruns and display "flicker").
  2385. *
  2386. * A value of 5us seems to be a good balance; safe for very low end
  2387. * platforms but not overly aggressive on lower latency configs.
  2388. */
  2389. static const int latency_ns = 5000;
  2390. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  2391. {
  2392. struct drm_i915_private *dev_priv = dev->dev_private;
  2393. uint32_t dsparb = I915_READ(DSPARB);
  2394. int size;
  2395. if (plane == 0)
  2396. size = dsparb & 0x7f;
  2397. else
  2398. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
  2399. (dsparb & 0x7f);
  2400. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2401. plane ? "B" : "A", size);
  2402. return size;
  2403. }
  2404. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  2405. {
  2406. struct drm_i915_private *dev_priv = dev->dev_private;
  2407. uint32_t dsparb = I915_READ(DSPARB);
  2408. int size;
  2409. if (plane == 0)
  2410. size = dsparb & 0x1ff;
  2411. else
  2412. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
  2413. (dsparb & 0x1ff);
  2414. size >>= 1; /* Convert to cachelines */
  2415. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2416. plane ? "B" : "A", size);
  2417. return size;
  2418. }
  2419. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  2420. {
  2421. struct drm_i915_private *dev_priv = dev->dev_private;
  2422. uint32_t dsparb = I915_READ(DSPARB);
  2423. int size;
  2424. size = dsparb & 0x7f;
  2425. size >>= 2; /* Convert to cachelines */
  2426. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2427. plane ? "B" : "A",
  2428. size);
  2429. return size;
  2430. }
  2431. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  2432. {
  2433. struct drm_i915_private *dev_priv = dev->dev_private;
  2434. uint32_t dsparb = I915_READ(DSPARB);
  2435. int size;
  2436. size = dsparb & 0x7f;
  2437. size >>= 1; /* Convert to cachelines */
  2438. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  2439. plane ? "B" : "A", size);
  2440. return size;
  2441. }
  2442. static void pineview_update_wm(struct drm_device *dev, int planea_clock,
  2443. int planeb_clock, int sr_hdisplay, int pixel_size)
  2444. {
  2445. struct drm_i915_private *dev_priv = dev->dev_private;
  2446. u32 reg;
  2447. unsigned long wm;
  2448. struct cxsr_latency *latency;
  2449. int sr_clock;
  2450. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
  2451. dev_priv->mem_freq);
  2452. if (!latency) {
  2453. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  2454. pineview_disable_cxsr(dev);
  2455. return;
  2456. }
  2457. if (!planea_clock || !planeb_clock) {
  2458. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2459. /* Display SR */
  2460. wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
  2461. pixel_size, latency->display_sr);
  2462. reg = I915_READ(DSPFW1);
  2463. reg &= ~DSPFW_SR_MASK;
  2464. reg |= wm << DSPFW_SR_SHIFT;
  2465. I915_WRITE(DSPFW1, reg);
  2466. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  2467. /* cursor SR */
  2468. wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
  2469. pixel_size, latency->cursor_sr);
  2470. reg = I915_READ(DSPFW3);
  2471. reg &= ~DSPFW_CURSOR_SR_MASK;
  2472. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  2473. I915_WRITE(DSPFW3, reg);
  2474. /* Display HPLL off SR */
  2475. wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
  2476. pixel_size, latency->display_hpll_disable);
  2477. reg = I915_READ(DSPFW3);
  2478. reg &= ~DSPFW_HPLL_SR_MASK;
  2479. reg |= wm & DSPFW_HPLL_SR_MASK;
  2480. I915_WRITE(DSPFW3, reg);
  2481. /* cursor HPLL off SR */
  2482. wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
  2483. pixel_size, latency->cursor_hpll_disable);
  2484. reg = I915_READ(DSPFW3);
  2485. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  2486. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  2487. I915_WRITE(DSPFW3, reg);
  2488. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  2489. /* activate cxsr */
  2490. reg = I915_READ(DSPFW3);
  2491. reg |= PINEVIEW_SELF_REFRESH_EN;
  2492. I915_WRITE(DSPFW3, reg);
  2493. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  2494. } else {
  2495. pineview_disable_cxsr(dev);
  2496. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  2497. }
  2498. }
  2499. static void g4x_update_wm(struct drm_device *dev, int planea_clock,
  2500. int planeb_clock, int sr_hdisplay, int pixel_size)
  2501. {
  2502. struct drm_i915_private *dev_priv = dev->dev_private;
  2503. int total_size, cacheline_size;
  2504. int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
  2505. struct intel_watermark_params planea_params, planeb_params;
  2506. unsigned long line_time_us;
  2507. int sr_clock, sr_entries = 0, entries_required;
  2508. /* Create copies of the base settings for each pipe */
  2509. planea_params = planeb_params = g4x_wm_info;
  2510. /* Grab a couple of global values before we overwrite them */
  2511. total_size = planea_params.fifo_size;
  2512. cacheline_size = planea_params.cacheline_size;
  2513. /*
  2514. * Note: we need to make sure we don't overflow for various clock &
  2515. * latency values.
  2516. * clocks go from a few thousand to several hundred thousand.
  2517. * latency is usually a few thousand
  2518. */
  2519. entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
  2520. 1000;
  2521. entries_required /= G4X_FIFO_LINE_SIZE;
  2522. planea_wm = entries_required + planea_params.guard_size;
  2523. entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
  2524. 1000;
  2525. entries_required /= G4X_FIFO_LINE_SIZE;
  2526. planeb_wm = entries_required + planeb_params.guard_size;
  2527. cursora_wm = cursorb_wm = 16;
  2528. cursor_sr = 32;
  2529. DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2530. /* Calc sr entries for one plane configs */
  2531. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2532. /* self-refresh has much higher latency */
  2533. static const int sr_latency_ns = 12000;
  2534. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2535. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2536. /* Use ns/us then divide to preserve precision */
  2537. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2538. pixel_size * sr_hdisplay) / 1000;
  2539. sr_entries = roundup(sr_entries / cacheline_size, 1);
  2540. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2541. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2542. } else {
  2543. /* Turn off self refresh if both pipes are enabled */
  2544. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2545. & ~FW_BLC_SELF_EN);
  2546. }
  2547. DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
  2548. planea_wm, planeb_wm, sr_entries);
  2549. planea_wm &= 0x3f;
  2550. planeb_wm &= 0x3f;
  2551. I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
  2552. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  2553. (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
  2554. I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  2555. (cursora_wm << DSPFW_CURSORA_SHIFT));
  2556. /* HPLL off in SR has some issues on G4x... disable it */
  2557. I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  2558. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  2559. }
  2560. static void i965_update_wm(struct drm_device *dev, int planea_clock,
  2561. int planeb_clock, int sr_hdisplay, int pixel_size)
  2562. {
  2563. struct drm_i915_private *dev_priv = dev->dev_private;
  2564. unsigned long line_time_us;
  2565. int sr_clock, sr_entries, srwm = 1;
  2566. /* Calc sr entries for one plane configs */
  2567. if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
  2568. /* self-refresh has much higher latency */
  2569. static const int sr_latency_ns = 12000;
  2570. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2571. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2572. /* Use ns/us then divide to preserve precision */
  2573. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2574. pixel_size * sr_hdisplay) / 1000;
  2575. sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
  2576. DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
  2577. srwm = I945_FIFO_SIZE - sr_entries;
  2578. if (srwm < 0)
  2579. srwm = 1;
  2580. srwm &= 0x3f;
  2581. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  2582. } else {
  2583. /* Turn off self refresh if both pipes are enabled */
  2584. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2585. & ~FW_BLC_SELF_EN);
  2586. }
  2587. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  2588. srwm);
  2589. /* 965 has limitations... */
  2590. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
  2591. (8 << 0));
  2592. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  2593. }
  2594. static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
  2595. int planeb_clock, int sr_hdisplay, int pixel_size)
  2596. {
  2597. struct drm_i915_private *dev_priv = dev->dev_private;
  2598. uint32_t fwater_lo;
  2599. uint32_t fwater_hi;
  2600. int total_size, cacheline_size, cwm, srwm = 1;
  2601. int planea_wm, planeb_wm;
  2602. struct intel_watermark_params planea_params, planeb_params;
  2603. unsigned long line_time_us;
  2604. int sr_clock, sr_entries = 0;
  2605. /* Create copies of the base settings for each pipe */
  2606. if (IS_I965GM(dev) || IS_I945GM(dev))
  2607. planea_params = planeb_params = i945_wm_info;
  2608. else if (IS_I9XX(dev))
  2609. planea_params = planeb_params = i915_wm_info;
  2610. else
  2611. planea_params = planeb_params = i855_wm_info;
  2612. /* Grab a couple of global values before we overwrite them */
  2613. total_size = planea_params.fifo_size;
  2614. cacheline_size = planea_params.cacheline_size;
  2615. /* Update per-plane FIFO sizes */
  2616. planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2617. planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  2618. planea_wm = intel_calculate_wm(planea_clock, &planea_params,
  2619. pixel_size, latency_ns);
  2620. planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
  2621. pixel_size, latency_ns);
  2622. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  2623. /*
  2624. * Overlay gets an aggressive default since video jitter is bad.
  2625. */
  2626. cwm = 2;
  2627. /* Calc sr entries for one plane configs */
  2628. if (HAS_FW_BLC(dev) && sr_hdisplay &&
  2629. (!planea_clock || !planeb_clock)) {
  2630. /* self-refresh has much higher latency */
  2631. static const int sr_latency_ns = 6000;
  2632. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2633. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2634. /* Use ns/us then divide to preserve precision */
  2635. sr_entries = (((sr_latency_ns / line_time_us) + 1) *
  2636. pixel_size * sr_hdisplay) / 1000;
  2637. sr_entries = roundup(sr_entries / cacheline_size, 1);
  2638. DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
  2639. srwm = total_size - sr_entries;
  2640. if (srwm < 0)
  2641. srwm = 1;
  2642. if (IS_I945G(dev) || IS_I945GM(dev))
  2643. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  2644. else if (IS_I915GM(dev)) {
  2645. /* 915M has a smaller SRWM field */
  2646. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  2647. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  2648. }
  2649. } else {
  2650. /* Turn off self refresh if both pipes are enabled */
  2651. if (IS_I945G(dev) || IS_I945GM(dev)) {
  2652. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  2653. & ~FW_BLC_SELF_EN);
  2654. } else if (IS_I915GM(dev)) {
  2655. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  2656. }
  2657. }
  2658. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  2659. planea_wm, planeb_wm, cwm, srwm);
  2660. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  2661. fwater_hi = (cwm & 0x1f);
  2662. /* Set request length to 8 cachelines per fetch */
  2663. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  2664. fwater_hi = fwater_hi | (1 << 8);
  2665. I915_WRITE(FW_BLC, fwater_lo);
  2666. I915_WRITE(FW_BLC2, fwater_hi);
  2667. }
  2668. static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
  2669. int unused2, int pixel_size)
  2670. {
  2671. struct drm_i915_private *dev_priv = dev->dev_private;
  2672. uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  2673. int planea_wm;
  2674. i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  2675. planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
  2676. pixel_size, latency_ns);
  2677. fwater_lo |= (3<<8) | planea_wm;
  2678. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  2679. I915_WRITE(FW_BLC, fwater_lo);
  2680. }
  2681. #define ILK_LP0_PLANE_LATENCY 700
  2682. static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
  2683. int planeb_clock, int sr_hdisplay, int pixel_size)
  2684. {
  2685. struct drm_i915_private *dev_priv = dev->dev_private;
  2686. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  2687. int sr_wm, cursor_wm;
  2688. unsigned long line_time_us;
  2689. int sr_clock, entries_required;
  2690. u32 reg_value;
  2691. /* Calculate and update the watermark for plane A */
  2692. if (planea_clock) {
  2693. entries_required = ((planea_clock / 1000) * pixel_size *
  2694. ILK_LP0_PLANE_LATENCY) / 1000;
  2695. entries_required = DIV_ROUND_UP(entries_required,
  2696. ironlake_display_wm_info.cacheline_size);
  2697. planea_wm = entries_required +
  2698. ironlake_display_wm_info.guard_size;
  2699. if (planea_wm > (int)ironlake_display_wm_info.max_wm)
  2700. planea_wm = ironlake_display_wm_info.max_wm;
  2701. cursora_wm = 16;
  2702. reg_value = I915_READ(WM0_PIPEA_ILK);
  2703. reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  2704. reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
  2705. (cursora_wm & WM0_PIPE_CURSOR_MASK);
  2706. I915_WRITE(WM0_PIPEA_ILK, reg_value);
  2707. DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
  2708. "cursor: %d\n", planea_wm, cursora_wm);
  2709. }
  2710. /* Calculate and update the watermark for plane B */
  2711. if (planeb_clock) {
  2712. entries_required = ((planeb_clock / 1000) * pixel_size *
  2713. ILK_LP0_PLANE_LATENCY) / 1000;
  2714. entries_required = DIV_ROUND_UP(entries_required,
  2715. ironlake_display_wm_info.cacheline_size);
  2716. planeb_wm = entries_required +
  2717. ironlake_display_wm_info.guard_size;
  2718. if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
  2719. planeb_wm = ironlake_display_wm_info.max_wm;
  2720. cursorb_wm = 16;
  2721. reg_value = I915_READ(WM0_PIPEB_ILK);
  2722. reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  2723. reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
  2724. (cursorb_wm & WM0_PIPE_CURSOR_MASK);
  2725. I915_WRITE(WM0_PIPEB_ILK, reg_value);
  2726. DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
  2727. "cursor: %d\n", planeb_wm, cursorb_wm);
  2728. }
  2729. /*
  2730. * Calculate and update the self-refresh watermark only when one
  2731. * display plane is used.
  2732. */
  2733. if (!planea_clock || !planeb_clock) {
  2734. int line_count;
  2735. /* Read the self-refresh latency. The unit is 0.5us */
  2736. int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
  2737. sr_clock = planea_clock ? planea_clock : planeb_clock;
  2738. line_time_us = ((sr_hdisplay * 1000) / sr_clock);
  2739. /* Use ns/us then divide to preserve precision */
  2740. line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
  2741. / 1000;
  2742. /* calculate the self-refresh watermark for display plane */
  2743. entries_required = line_count * sr_hdisplay * pixel_size;
  2744. entries_required = DIV_ROUND_UP(entries_required,
  2745. ironlake_display_srwm_info.cacheline_size);
  2746. sr_wm = entries_required +
  2747. ironlake_display_srwm_info.guard_size;
  2748. /* calculate the self-refresh watermark for display cursor */
  2749. entries_required = line_count * pixel_size * 64;
  2750. entries_required = DIV_ROUND_UP(entries_required,
  2751. ironlake_cursor_srwm_info.cacheline_size);
  2752. cursor_wm = entries_required +
  2753. ironlake_cursor_srwm_info.guard_size;
  2754. /* configure watermark and enable self-refresh */
  2755. reg_value = I915_READ(WM1_LP_ILK);
  2756. reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
  2757. WM1_LP_CURSOR_MASK);
  2758. reg_value |= WM1_LP_SR_EN |
  2759. (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
  2760. (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
  2761. I915_WRITE(WM1_LP_ILK, reg_value);
  2762. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  2763. "cursor %d\n", sr_wm, cursor_wm);
  2764. } else {
  2765. /* Turn off self refresh if both pipes are enabled */
  2766. I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
  2767. }
  2768. }
  2769. /**
  2770. * intel_update_watermarks - update FIFO watermark values based on current modes
  2771. *
  2772. * Calculate watermark values for the various WM regs based on current mode
  2773. * and plane configuration.
  2774. *
  2775. * There are several cases to deal with here:
  2776. * - normal (i.e. non-self-refresh)
  2777. * - self-refresh (SR) mode
  2778. * - lines are large relative to FIFO size (buffer can hold up to 2)
  2779. * - lines are small relative to FIFO size (buffer can hold more than 2
  2780. * lines), so need to account for TLB latency
  2781. *
  2782. * The normal calculation is:
  2783. * watermark = dotclock * bytes per pixel * latency
  2784. * where latency is platform & configuration dependent (we assume pessimal
  2785. * values here).
  2786. *
  2787. * The SR calculation is:
  2788. * watermark = (trunc(latency/line time)+1) * surface width *
  2789. * bytes per pixel
  2790. * where
  2791. * line time = htotal / dotclock
  2792. * and latency is assumed to be high, as above.
  2793. *
  2794. * The final value programmed to the register should always be rounded up,
  2795. * and include an extra 2 entries to account for clock crossings.
  2796. *
  2797. * We don't use the sprite, so we can ignore that. And on Crestline we have
  2798. * to set the non-SR watermarks to 8.
  2799. */
  2800. static void intel_update_watermarks(struct drm_device *dev)
  2801. {
  2802. struct drm_i915_private *dev_priv = dev->dev_private;
  2803. struct drm_crtc *crtc;
  2804. struct intel_crtc *intel_crtc;
  2805. int sr_hdisplay = 0;
  2806. unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
  2807. int enabled = 0, pixel_size = 0;
  2808. if (!dev_priv->display.update_wm)
  2809. return;
  2810. /* Get the clock config from both planes */
  2811. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2812. intel_crtc = to_intel_crtc(crtc);
  2813. if (crtc->enabled) {
  2814. enabled++;
  2815. if (intel_crtc->plane == 0) {
  2816. DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
  2817. intel_crtc->pipe, crtc->mode.clock);
  2818. planea_clock = crtc->mode.clock;
  2819. } else {
  2820. DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
  2821. intel_crtc->pipe, crtc->mode.clock);
  2822. planeb_clock = crtc->mode.clock;
  2823. }
  2824. sr_hdisplay = crtc->mode.hdisplay;
  2825. sr_clock = crtc->mode.clock;
  2826. if (crtc->fb)
  2827. pixel_size = crtc->fb->bits_per_pixel / 8;
  2828. else
  2829. pixel_size = 4; /* by default */
  2830. }
  2831. }
  2832. if (enabled <= 0)
  2833. return;
  2834. dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
  2835. sr_hdisplay, pixel_size);
  2836. }
  2837. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  2838. struct drm_display_mode *mode,
  2839. struct drm_display_mode *adjusted_mode,
  2840. int x, int y,
  2841. struct drm_framebuffer *old_fb)
  2842. {
  2843. struct drm_device *dev = crtc->dev;
  2844. struct drm_i915_private *dev_priv = dev->dev_private;
  2845. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2846. int pipe = intel_crtc->pipe;
  2847. int plane = intel_crtc->plane;
  2848. int fp_reg = (pipe == 0) ? FPA0 : FPB0;
  2849. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  2850. int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
  2851. int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
  2852. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  2853. int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
  2854. int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
  2855. int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
  2856. int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
  2857. int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
  2858. int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
  2859. int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
  2860. int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
  2861. int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
  2862. int refclk, num_connectors = 0;
  2863. intel_clock_t clock, reduced_clock;
  2864. u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
  2865. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  2866. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  2867. bool is_edp = false;
  2868. struct drm_mode_config *mode_config = &dev->mode_config;
  2869. struct drm_encoder *encoder;
  2870. struct intel_encoder *intel_encoder = NULL;
  2871. const intel_limit_t *limit;
  2872. int ret;
  2873. struct fdi_m_n m_n = {0};
  2874. int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
  2875. int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
  2876. int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
  2877. int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
  2878. int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
  2879. int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
  2880. int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
  2881. int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
  2882. int trans_dpll_sel = (pipe == 0) ? 0 : 1;
  2883. int lvds_reg = LVDS;
  2884. u32 temp;
  2885. int sdvo_pixel_multiply;
  2886. int target_clock;
  2887. drm_vblank_pre_modeset(dev, pipe);
  2888. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  2889. if (!encoder || encoder->crtc != crtc)
  2890. continue;
  2891. intel_encoder = enc_to_intel_encoder(encoder);
  2892. switch (intel_encoder->type) {
  2893. case INTEL_OUTPUT_LVDS:
  2894. is_lvds = true;
  2895. break;
  2896. case INTEL_OUTPUT_SDVO:
  2897. case INTEL_OUTPUT_HDMI:
  2898. is_sdvo = true;
  2899. if (intel_encoder->needs_tv_clock)
  2900. is_tv = true;
  2901. break;
  2902. case INTEL_OUTPUT_DVO:
  2903. is_dvo = true;
  2904. break;
  2905. case INTEL_OUTPUT_TVOUT:
  2906. is_tv = true;
  2907. break;
  2908. case INTEL_OUTPUT_ANALOG:
  2909. is_crt = true;
  2910. break;
  2911. case INTEL_OUTPUT_DISPLAYPORT:
  2912. is_dp = true;
  2913. break;
  2914. case INTEL_OUTPUT_EDP:
  2915. is_edp = true;
  2916. break;
  2917. }
  2918. num_connectors++;
  2919. }
  2920. if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
  2921. refclk = dev_priv->lvds_ssc_freq * 1000;
  2922. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  2923. refclk / 1000);
  2924. } else if (IS_I9XX(dev)) {
  2925. refclk = 96000;
  2926. if (HAS_PCH_SPLIT(dev))
  2927. refclk = 120000; /* 120Mhz refclk */
  2928. } else {
  2929. refclk = 48000;
  2930. }
  2931. /*
  2932. * Returns a set of divisors for the desired target clock with the given
  2933. * refclk, or FALSE. The returned values represent the clock equation:
  2934. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  2935. */
  2936. limit = intel_limit(crtc);
  2937. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
  2938. if (!ok) {
  2939. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  2940. drm_vblank_post_modeset(dev, pipe);
  2941. return -EINVAL;
  2942. }
  2943. if (is_lvds && dev_priv->lvds_downclock_avail) {
  2944. has_reduced_clock = limit->find_pll(limit, crtc,
  2945. dev_priv->lvds_downclock,
  2946. refclk,
  2947. &reduced_clock);
  2948. if (has_reduced_clock && (clock.p != reduced_clock.p)) {
  2949. /*
  2950. * If the different P is found, it means that we can't
  2951. * switch the display clock by using the FP0/FP1.
  2952. * In such case we will disable the LVDS downclock
  2953. * feature.
  2954. */
  2955. DRM_DEBUG_KMS("Different P is found for "
  2956. "LVDS clock/downclock\n");
  2957. has_reduced_clock = 0;
  2958. }
  2959. }
  2960. /* SDVO TV has fixed PLL values depend on its clock range,
  2961. this mirrors vbios setting. */
  2962. if (is_sdvo && is_tv) {
  2963. if (adjusted_mode->clock >= 100000
  2964. && adjusted_mode->clock < 140500) {
  2965. clock.p1 = 2;
  2966. clock.p2 = 10;
  2967. clock.n = 3;
  2968. clock.m1 = 16;
  2969. clock.m2 = 8;
  2970. } else if (adjusted_mode->clock >= 140500
  2971. && adjusted_mode->clock <= 200000) {
  2972. clock.p1 = 1;
  2973. clock.p2 = 10;
  2974. clock.n = 6;
  2975. clock.m1 = 12;
  2976. clock.m2 = 8;
  2977. }
  2978. }
  2979. /* FDI link */
  2980. if (HAS_PCH_SPLIT(dev)) {
  2981. int lane = 0, link_bw, bpp;
  2982. /* eDP doesn't require FDI link, so just set DP M/N
  2983. according to current link config */
  2984. if (is_edp) {
  2985. target_clock = mode->clock;
  2986. intel_edp_link_config(intel_encoder,
  2987. &lane, &link_bw);
  2988. } else {
  2989. /* DP over FDI requires target mode clock
  2990. instead of link clock */
  2991. if (is_dp)
  2992. target_clock = mode->clock;
  2993. else
  2994. target_clock = adjusted_mode->clock;
  2995. link_bw = 270000;
  2996. }
  2997. /* determine panel color depth */
  2998. temp = I915_READ(pipeconf_reg);
  2999. temp &= ~PIPE_BPC_MASK;
  3000. if (is_lvds) {
  3001. int lvds_reg = I915_READ(PCH_LVDS);
  3002. /* the BPC will be 6 if it is 18-bit LVDS panel */
  3003. if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
  3004. temp |= PIPE_8BPC;
  3005. else
  3006. temp |= PIPE_6BPC;
  3007. } else if (is_edp) {
  3008. switch (dev_priv->edp_bpp/3) {
  3009. case 8:
  3010. temp |= PIPE_8BPC;
  3011. break;
  3012. case 10:
  3013. temp |= PIPE_10BPC;
  3014. break;
  3015. case 6:
  3016. temp |= PIPE_6BPC;
  3017. break;
  3018. case 12:
  3019. temp |= PIPE_12BPC;
  3020. break;
  3021. }
  3022. } else
  3023. temp |= PIPE_8BPC;
  3024. I915_WRITE(pipeconf_reg, temp);
  3025. I915_READ(pipeconf_reg);
  3026. switch (temp & PIPE_BPC_MASK) {
  3027. case PIPE_8BPC:
  3028. bpp = 24;
  3029. break;
  3030. case PIPE_10BPC:
  3031. bpp = 30;
  3032. break;
  3033. case PIPE_6BPC:
  3034. bpp = 18;
  3035. break;
  3036. case PIPE_12BPC:
  3037. bpp = 36;
  3038. break;
  3039. default:
  3040. DRM_ERROR("unknown pipe bpc value\n");
  3041. bpp = 24;
  3042. }
  3043. if (!lane) {
  3044. /*
  3045. * Account for spread spectrum to avoid
  3046. * oversubscribing the link. Max center spread
  3047. * is 2.5%; use 5% for safety's sake.
  3048. */
  3049. u32 bps = target_clock * bpp * 21 / 20;
  3050. lane = bps / (link_bw * 8) + 1;
  3051. }
  3052. intel_crtc->fdi_lanes = lane;
  3053. ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
  3054. }
  3055. /* Ironlake: try to setup display ref clock before DPLL
  3056. * enabling. This is only under driver's control after
  3057. * PCH B stepping, previous chipset stepping should be
  3058. * ignoring this setting.
  3059. */
  3060. if (HAS_PCH_SPLIT(dev)) {
  3061. temp = I915_READ(PCH_DREF_CONTROL);
  3062. /* Always enable nonspread source */
  3063. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  3064. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  3065. I915_WRITE(PCH_DREF_CONTROL, temp);
  3066. POSTING_READ(PCH_DREF_CONTROL);
  3067. temp &= ~DREF_SSC_SOURCE_MASK;
  3068. temp |= DREF_SSC_SOURCE_ENABLE;
  3069. I915_WRITE(PCH_DREF_CONTROL, temp);
  3070. POSTING_READ(PCH_DREF_CONTROL);
  3071. udelay(200);
  3072. if (is_edp) {
  3073. if (dev_priv->lvds_use_ssc) {
  3074. temp |= DREF_SSC1_ENABLE;
  3075. I915_WRITE(PCH_DREF_CONTROL, temp);
  3076. POSTING_READ(PCH_DREF_CONTROL);
  3077. udelay(200);
  3078. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  3079. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  3080. I915_WRITE(PCH_DREF_CONTROL, temp);
  3081. POSTING_READ(PCH_DREF_CONTROL);
  3082. } else {
  3083. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  3084. I915_WRITE(PCH_DREF_CONTROL, temp);
  3085. POSTING_READ(PCH_DREF_CONTROL);
  3086. }
  3087. }
  3088. }
  3089. if (IS_PINEVIEW(dev)) {
  3090. fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
  3091. if (has_reduced_clock)
  3092. fp2 = (1 << reduced_clock.n) << 16 |
  3093. reduced_clock.m1 << 8 | reduced_clock.m2;
  3094. } else {
  3095. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  3096. if (has_reduced_clock)
  3097. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  3098. reduced_clock.m2;
  3099. }
  3100. if (!HAS_PCH_SPLIT(dev))
  3101. dpll = DPLL_VGA_MODE_DIS;
  3102. if (IS_I9XX(dev)) {
  3103. if (is_lvds)
  3104. dpll |= DPLLB_MODE_LVDS;
  3105. else
  3106. dpll |= DPLLB_MODE_DAC_SERIAL;
  3107. if (is_sdvo) {
  3108. dpll |= DPLL_DVO_HIGH_SPEED;
  3109. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  3110. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3111. dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3112. else if (HAS_PCH_SPLIT(dev))
  3113. dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  3114. }
  3115. if (is_dp)
  3116. dpll |= DPLL_DVO_HIGH_SPEED;
  3117. /* compute bitmask from p1 value */
  3118. if (IS_PINEVIEW(dev))
  3119. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3120. else {
  3121. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3122. /* also FPA1 */
  3123. if (HAS_PCH_SPLIT(dev))
  3124. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3125. if (IS_G4X(dev) && has_reduced_clock)
  3126. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3127. }
  3128. switch (clock.p2) {
  3129. case 5:
  3130. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3131. break;
  3132. case 7:
  3133. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3134. break;
  3135. case 10:
  3136. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3137. break;
  3138. case 14:
  3139. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3140. break;
  3141. }
  3142. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
  3143. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3144. } else {
  3145. if (is_lvds) {
  3146. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3147. } else {
  3148. if (clock.p1 == 2)
  3149. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3150. else
  3151. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3152. if (clock.p2 == 4)
  3153. dpll |= PLL_P2_DIVIDE_BY_4;
  3154. }
  3155. }
  3156. if (is_sdvo && is_tv)
  3157. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3158. else if (is_tv)
  3159. /* XXX: just matching BIOS for now */
  3160. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3161. dpll |= 3;
  3162. else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
  3163. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3164. else
  3165. dpll |= PLL_REF_INPUT_DREFCLK;
  3166. /* setup pipeconf */
  3167. pipeconf = I915_READ(pipeconf_reg);
  3168. /* Set up the display plane register */
  3169. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3170. /* Ironlake's plane is forced to pipe, bit 24 is to
  3171. enable color space conversion */
  3172. if (!HAS_PCH_SPLIT(dev)) {
  3173. if (pipe == 0)
  3174. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3175. else
  3176. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3177. }
  3178. if (pipe == 0 && !IS_I965G(dev)) {
  3179. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3180. * core speed.
  3181. *
  3182. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3183. * pipe == 0 check?
  3184. */
  3185. if (mode->clock >
  3186. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3187. pipeconf |= PIPEACONF_DOUBLE_WIDE;
  3188. else
  3189. pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
  3190. }
  3191. /* Disable the panel fitter if it was on our pipe */
  3192. if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
  3193. I915_WRITE(PFIT_CONTROL, 0);
  3194. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  3195. drm_mode_debug_printmodeline(mode);
  3196. /* assign to Ironlake registers */
  3197. if (HAS_PCH_SPLIT(dev)) {
  3198. fp_reg = pch_fp_reg;
  3199. dpll_reg = pch_dpll_reg;
  3200. }
  3201. if (is_edp) {
  3202. ironlake_disable_pll_edp(crtc);
  3203. } else if ((dpll & DPLL_VCO_ENABLE)) {
  3204. I915_WRITE(fp_reg, fp);
  3205. I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
  3206. I915_READ(dpll_reg);
  3207. udelay(150);
  3208. }
  3209. /* enable transcoder DPLL */
  3210. if (HAS_PCH_CPT(dev)) {
  3211. temp = I915_READ(PCH_DPLL_SEL);
  3212. if (trans_dpll_sel == 0)
  3213. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  3214. else
  3215. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  3216. I915_WRITE(PCH_DPLL_SEL, temp);
  3217. I915_READ(PCH_DPLL_SEL);
  3218. udelay(150);
  3219. }
  3220. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  3221. * This is an exception to the general rule that mode_set doesn't turn
  3222. * things on.
  3223. */
  3224. if (is_lvds) {
  3225. u32 lvds;
  3226. if (HAS_PCH_SPLIT(dev))
  3227. lvds_reg = PCH_LVDS;
  3228. lvds = I915_READ(lvds_reg);
  3229. lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  3230. if (pipe == 1) {
  3231. if (HAS_PCH_CPT(dev))
  3232. lvds |= PORT_TRANS_B_SEL_CPT;
  3233. else
  3234. lvds |= LVDS_PIPEB_SELECT;
  3235. } else {
  3236. if (HAS_PCH_CPT(dev))
  3237. lvds &= ~PORT_TRANS_SEL_MASK;
  3238. else
  3239. lvds &= ~LVDS_PIPEB_SELECT;
  3240. }
  3241. /* set the corresponsding LVDS_BORDER bit */
  3242. lvds |= dev_priv->lvds_border_bits;
  3243. /* Set the B0-B3 data pairs corresponding to whether we're going to
  3244. * set the DPLLs for dual-channel mode or not.
  3245. */
  3246. if (clock.p2 == 7)
  3247. lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  3248. else
  3249. lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  3250. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  3251. * appropriately here, but we need to look more thoroughly into how
  3252. * panels behave in the two modes.
  3253. */
  3254. /* set the dithering flag */
  3255. if (IS_I965G(dev)) {
  3256. if (dev_priv->lvds_dither) {
  3257. if (HAS_PCH_SPLIT(dev)) {
  3258. pipeconf |= PIPE_ENABLE_DITHER;
  3259. pipeconf |= PIPE_DITHER_TYPE_ST01;
  3260. } else
  3261. lvds |= LVDS_ENABLE_DITHER;
  3262. } else {
  3263. if (HAS_PCH_SPLIT(dev)) {
  3264. pipeconf &= ~PIPE_ENABLE_DITHER;
  3265. pipeconf &= ~PIPE_DITHER_TYPE_MASK;
  3266. } else
  3267. lvds &= ~LVDS_ENABLE_DITHER;
  3268. }
  3269. }
  3270. I915_WRITE(lvds_reg, lvds);
  3271. I915_READ(lvds_reg);
  3272. }
  3273. if (is_dp)
  3274. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3275. else if (HAS_PCH_SPLIT(dev)) {
  3276. /* For non-DP output, clear any trans DP clock recovery setting.*/
  3277. if (pipe == 0) {
  3278. I915_WRITE(TRANSA_DATA_M1, 0);
  3279. I915_WRITE(TRANSA_DATA_N1, 0);
  3280. I915_WRITE(TRANSA_DP_LINK_M1, 0);
  3281. I915_WRITE(TRANSA_DP_LINK_N1, 0);
  3282. } else {
  3283. I915_WRITE(TRANSB_DATA_M1, 0);
  3284. I915_WRITE(TRANSB_DATA_N1, 0);
  3285. I915_WRITE(TRANSB_DP_LINK_M1, 0);
  3286. I915_WRITE(TRANSB_DP_LINK_N1, 0);
  3287. }
  3288. }
  3289. if (!is_edp) {
  3290. I915_WRITE(fp_reg, fp);
  3291. I915_WRITE(dpll_reg, dpll);
  3292. I915_READ(dpll_reg);
  3293. /* Wait for the clocks to stabilize. */
  3294. udelay(150);
  3295. if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
  3296. if (is_sdvo) {
  3297. sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
  3298. I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
  3299. ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
  3300. } else
  3301. I915_WRITE(dpll_md_reg, 0);
  3302. } else {
  3303. /* write it again -- the BIOS does, after all */
  3304. I915_WRITE(dpll_reg, dpll);
  3305. }
  3306. I915_READ(dpll_reg);
  3307. /* Wait for the clocks to stabilize. */
  3308. udelay(150);
  3309. }
  3310. if (is_lvds && has_reduced_clock && i915_powersave) {
  3311. I915_WRITE(fp_reg + 4, fp2);
  3312. intel_crtc->lowfreq_avail = true;
  3313. if (HAS_PIPE_CXSR(dev)) {
  3314. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  3315. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  3316. }
  3317. } else {
  3318. I915_WRITE(fp_reg + 4, fp);
  3319. intel_crtc->lowfreq_avail = false;
  3320. if (HAS_PIPE_CXSR(dev)) {
  3321. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  3322. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  3323. }
  3324. }
  3325. I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
  3326. ((adjusted_mode->crtc_htotal - 1) << 16));
  3327. I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
  3328. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3329. I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
  3330. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3331. I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
  3332. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3333. I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
  3334. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3335. I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
  3336. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3337. /* pipesrc and dspsize control the size that is scaled from, which should
  3338. * always be the user's requested size.
  3339. */
  3340. if (!HAS_PCH_SPLIT(dev)) {
  3341. I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
  3342. (mode->hdisplay - 1));
  3343. I915_WRITE(dsppos_reg, 0);
  3344. }
  3345. I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3346. if (HAS_PCH_SPLIT(dev)) {
  3347. I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
  3348. I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
  3349. I915_WRITE(link_m1_reg, m_n.link_m);
  3350. I915_WRITE(link_n1_reg, m_n.link_n);
  3351. if (is_edp) {
  3352. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  3353. } else {
  3354. /* enable FDI RX PLL too */
  3355. temp = I915_READ(fdi_rx_reg);
  3356. I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
  3357. I915_READ(fdi_rx_reg);
  3358. udelay(200);
  3359. /* enable FDI TX PLL too */
  3360. temp = I915_READ(fdi_tx_reg);
  3361. I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
  3362. I915_READ(fdi_tx_reg);
  3363. /* enable FDI RX PCDCLK */
  3364. temp = I915_READ(fdi_rx_reg);
  3365. I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
  3366. I915_READ(fdi_rx_reg);
  3367. udelay(200);
  3368. }
  3369. }
  3370. I915_WRITE(pipeconf_reg, pipeconf);
  3371. I915_READ(pipeconf_reg);
  3372. intel_wait_for_vblank(dev);
  3373. if (IS_IRONLAKE(dev)) {
  3374. /* enable address swizzle for tiling buffer */
  3375. temp = I915_READ(DISP_ARB_CTL);
  3376. I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
  3377. }
  3378. I915_WRITE(dspcntr_reg, dspcntr);
  3379. /* Flush the plane changes */
  3380. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  3381. if ((IS_I965G(dev) || plane == 0))
  3382. intel_update_fbc(crtc, &crtc->mode);
  3383. intel_update_watermarks(dev);
  3384. drm_vblank_post_modeset(dev, pipe);
  3385. return ret;
  3386. }
  3387. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  3388. void intel_crtc_load_lut(struct drm_crtc *crtc)
  3389. {
  3390. struct drm_device *dev = crtc->dev;
  3391. struct drm_i915_private *dev_priv = dev->dev_private;
  3392. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3393. int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
  3394. int i;
  3395. /* The clocks have to be on to load the palette. */
  3396. if (!crtc->enabled)
  3397. return;
  3398. /* use legacy palette for Ironlake */
  3399. if (HAS_PCH_SPLIT(dev))
  3400. palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
  3401. LGC_PALETTE_B;
  3402. for (i = 0; i < 256; i++) {
  3403. I915_WRITE(palreg + 4 * i,
  3404. (intel_crtc->lut_r[i] << 16) |
  3405. (intel_crtc->lut_g[i] << 8) |
  3406. intel_crtc->lut_b[i]);
  3407. }
  3408. }
  3409. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  3410. struct drm_file *file_priv,
  3411. uint32_t handle,
  3412. uint32_t width, uint32_t height)
  3413. {
  3414. struct drm_device *dev = crtc->dev;
  3415. struct drm_i915_private *dev_priv = dev->dev_private;
  3416. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3417. struct drm_gem_object *bo;
  3418. struct drm_i915_gem_object *obj_priv;
  3419. int pipe = intel_crtc->pipe;
  3420. uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
  3421. uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
  3422. uint32_t temp = I915_READ(control);
  3423. size_t addr;
  3424. int ret;
  3425. DRM_DEBUG_KMS("\n");
  3426. /* if we want to turn off the cursor ignore width and height */
  3427. if (!handle) {
  3428. DRM_DEBUG_KMS("cursor off\n");
  3429. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  3430. temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  3431. temp |= CURSOR_MODE_DISABLE;
  3432. } else {
  3433. temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  3434. }
  3435. addr = 0;
  3436. bo = NULL;
  3437. mutex_lock(&dev->struct_mutex);
  3438. goto finish;
  3439. }
  3440. /* Currently we only support 64x64 cursors */
  3441. if (width != 64 || height != 64) {
  3442. DRM_ERROR("we currently only support 64x64 cursors\n");
  3443. return -EINVAL;
  3444. }
  3445. bo = drm_gem_object_lookup(dev, file_priv, handle);
  3446. if (!bo)
  3447. return -ENOENT;
  3448. obj_priv = to_intel_bo(bo);
  3449. if (bo->size < width * height * 4) {
  3450. DRM_ERROR("buffer is to small\n");
  3451. ret = -ENOMEM;
  3452. goto fail;
  3453. }
  3454. /* we only need to pin inside GTT if cursor is non-phy */
  3455. mutex_lock(&dev->struct_mutex);
  3456. if (!dev_priv->info->cursor_needs_physical) {
  3457. ret = i915_gem_object_pin(bo, PAGE_SIZE);
  3458. if (ret) {
  3459. DRM_ERROR("failed to pin cursor bo\n");
  3460. goto fail_locked;
  3461. }
  3462. addr = obj_priv->gtt_offset;
  3463. } else {
  3464. ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
  3465. if (ret) {
  3466. DRM_ERROR("failed to attach phys object\n");
  3467. goto fail_locked;
  3468. }
  3469. addr = obj_priv->phys_obj->handle->busaddr;
  3470. }
  3471. if (!IS_I9XX(dev))
  3472. I915_WRITE(CURSIZE, (height << 12) | width);
  3473. /* Hooray for CUR*CNTR differences */
  3474. if (IS_MOBILE(dev) || IS_I9XX(dev)) {
  3475. temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  3476. temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  3477. temp |= (pipe << 28); /* Connect to correct pipe */
  3478. } else {
  3479. temp &= ~(CURSOR_FORMAT_MASK);
  3480. temp |= CURSOR_ENABLE;
  3481. temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
  3482. }
  3483. finish:
  3484. I915_WRITE(control, temp);
  3485. I915_WRITE(base, addr);
  3486. if (intel_crtc->cursor_bo) {
  3487. if (dev_priv->info->cursor_needs_physical) {
  3488. if (intel_crtc->cursor_bo != bo)
  3489. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  3490. } else
  3491. i915_gem_object_unpin(intel_crtc->cursor_bo);
  3492. drm_gem_object_unreference(intel_crtc->cursor_bo);
  3493. }
  3494. mutex_unlock(&dev->struct_mutex);
  3495. intel_crtc->cursor_addr = addr;
  3496. intel_crtc->cursor_bo = bo;
  3497. return 0;
  3498. fail_locked:
  3499. mutex_unlock(&dev->struct_mutex);
  3500. fail:
  3501. drm_gem_object_unreference_unlocked(bo);
  3502. return ret;
  3503. }
  3504. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  3505. {
  3506. struct drm_device *dev = crtc->dev;
  3507. struct drm_i915_private *dev_priv = dev->dev_private;
  3508. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3509. struct intel_framebuffer *intel_fb;
  3510. int pipe = intel_crtc->pipe;
  3511. uint32_t temp = 0;
  3512. uint32_t adder;
  3513. if (crtc->fb) {
  3514. intel_fb = to_intel_framebuffer(crtc->fb);
  3515. intel_mark_busy(dev, intel_fb->obj);
  3516. }
  3517. if (x < 0) {
  3518. temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  3519. x = -x;
  3520. }
  3521. if (y < 0) {
  3522. temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  3523. y = -y;
  3524. }
  3525. temp |= x << CURSOR_X_SHIFT;
  3526. temp |= y << CURSOR_Y_SHIFT;
  3527. adder = intel_crtc->cursor_addr;
  3528. I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
  3529. I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
  3530. return 0;
  3531. }
  3532. /** Sets the color ramps on behalf of RandR */
  3533. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  3534. u16 blue, int regno)
  3535. {
  3536. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3537. intel_crtc->lut_r[regno] = red >> 8;
  3538. intel_crtc->lut_g[regno] = green >> 8;
  3539. intel_crtc->lut_b[regno] = blue >> 8;
  3540. }
  3541. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  3542. u16 *blue, int regno)
  3543. {
  3544. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3545. *red = intel_crtc->lut_r[regno] << 8;
  3546. *green = intel_crtc->lut_g[regno] << 8;
  3547. *blue = intel_crtc->lut_b[regno] << 8;
  3548. }
  3549. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  3550. u16 *blue, uint32_t size)
  3551. {
  3552. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3553. int i;
  3554. if (size != 256)
  3555. return;
  3556. for (i = 0; i < 256; i++) {
  3557. intel_crtc->lut_r[i] = red[i] >> 8;
  3558. intel_crtc->lut_g[i] = green[i] >> 8;
  3559. intel_crtc->lut_b[i] = blue[i] >> 8;
  3560. }
  3561. intel_crtc_load_lut(crtc);
  3562. }
  3563. /**
  3564. * Get a pipe with a simple mode set on it for doing load-based monitor
  3565. * detection.
  3566. *
  3567. * It will be up to the load-detect code to adjust the pipe as appropriate for
  3568. * its requirements. The pipe will be connected to no other encoders.
  3569. *
  3570. * Currently this code will only succeed if there is a pipe with no encoders
  3571. * configured for it. In the future, it could choose to temporarily disable
  3572. * some outputs to free up a pipe for its use.
  3573. *
  3574. * \return crtc, or NULL if no pipes are available.
  3575. */
  3576. /* VESA 640x480x72Hz mode to set on the pipe */
  3577. static struct drm_display_mode load_detect_mode = {
  3578. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  3579. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  3580. };
  3581. struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
  3582. struct drm_connector *connector,
  3583. struct drm_display_mode *mode,
  3584. int *dpms_mode)
  3585. {
  3586. struct intel_crtc *intel_crtc;
  3587. struct drm_crtc *possible_crtc;
  3588. struct drm_crtc *supported_crtc =NULL;
  3589. struct drm_encoder *encoder = &intel_encoder->enc;
  3590. struct drm_crtc *crtc = NULL;
  3591. struct drm_device *dev = encoder->dev;
  3592. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3593. struct drm_crtc_helper_funcs *crtc_funcs;
  3594. int i = -1;
  3595. /*
  3596. * Algorithm gets a little messy:
  3597. * - if the connector already has an assigned crtc, use it (but make
  3598. * sure it's on first)
  3599. * - try to find the first unused crtc that can drive this connector,
  3600. * and use that if we find one
  3601. * - if there are no unused crtcs available, try to use the first
  3602. * one we found that supports the connector
  3603. */
  3604. /* See if we already have a CRTC for this connector */
  3605. if (encoder->crtc) {
  3606. crtc = encoder->crtc;
  3607. /* Make sure the crtc and connector are running */
  3608. intel_crtc = to_intel_crtc(crtc);
  3609. *dpms_mode = intel_crtc->dpms_mode;
  3610. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3611. crtc_funcs = crtc->helper_private;
  3612. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3613. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  3614. }
  3615. return crtc;
  3616. }
  3617. /* Find an unused one (if possible) */
  3618. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  3619. i++;
  3620. if (!(encoder->possible_crtcs & (1 << i)))
  3621. continue;
  3622. if (!possible_crtc->enabled) {
  3623. crtc = possible_crtc;
  3624. break;
  3625. }
  3626. if (!supported_crtc)
  3627. supported_crtc = possible_crtc;
  3628. }
  3629. /*
  3630. * If we didn't find an unused CRTC, don't use any.
  3631. */
  3632. if (!crtc) {
  3633. return NULL;
  3634. }
  3635. encoder->crtc = crtc;
  3636. connector->encoder = encoder;
  3637. intel_encoder->load_detect_temp = true;
  3638. intel_crtc = to_intel_crtc(crtc);
  3639. *dpms_mode = intel_crtc->dpms_mode;
  3640. if (!crtc->enabled) {
  3641. if (!mode)
  3642. mode = &load_detect_mode;
  3643. drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
  3644. } else {
  3645. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  3646. crtc_funcs = crtc->helper_private;
  3647. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  3648. }
  3649. /* Add this connector to the crtc */
  3650. encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
  3651. encoder_funcs->commit(encoder);
  3652. }
  3653. /* let the connector get through one full cycle before testing */
  3654. intel_wait_for_vblank(dev);
  3655. return crtc;
  3656. }
  3657. void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
  3658. struct drm_connector *connector, int dpms_mode)
  3659. {
  3660. struct drm_encoder *encoder = &intel_encoder->enc;
  3661. struct drm_device *dev = encoder->dev;
  3662. struct drm_crtc *crtc = encoder->crtc;
  3663. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  3664. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  3665. if (intel_encoder->load_detect_temp) {
  3666. encoder->crtc = NULL;
  3667. connector->encoder = NULL;
  3668. intel_encoder->load_detect_temp = false;
  3669. crtc->enabled = drm_helper_crtc_in_use(crtc);
  3670. drm_helper_disable_unused_functions(dev);
  3671. }
  3672. /* Switch crtc and encoder back off if necessary */
  3673. if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
  3674. if (encoder->crtc == crtc)
  3675. encoder_funcs->dpms(encoder, dpms_mode);
  3676. crtc_funcs->dpms(crtc, dpms_mode);
  3677. }
  3678. }
  3679. /* Returns the clock of the currently programmed mode of the given pipe. */
  3680. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  3681. {
  3682. struct drm_i915_private *dev_priv = dev->dev_private;
  3683. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3684. int pipe = intel_crtc->pipe;
  3685. u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
  3686. u32 fp;
  3687. intel_clock_t clock;
  3688. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  3689. fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
  3690. else
  3691. fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
  3692. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  3693. if (IS_PINEVIEW(dev)) {
  3694. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  3695. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  3696. } else {
  3697. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  3698. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  3699. }
  3700. if (IS_I9XX(dev)) {
  3701. if (IS_PINEVIEW(dev))
  3702. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  3703. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  3704. else
  3705. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  3706. DPLL_FPA01_P1_POST_DIV_SHIFT);
  3707. switch (dpll & DPLL_MODE_MASK) {
  3708. case DPLLB_MODE_DAC_SERIAL:
  3709. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  3710. 5 : 10;
  3711. break;
  3712. case DPLLB_MODE_LVDS:
  3713. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  3714. 7 : 14;
  3715. break;
  3716. default:
  3717. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  3718. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  3719. return 0;
  3720. }
  3721. /* XXX: Handle the 100Mhz refclk */
  3722. intel_clock(dev, 96000, &clock);
  3723. } else {
  3724. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  3725. if (is_lvds) {
  3726. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  3727. DPLL_FPA01_P1_POST_DIV_SHIFT);
  3728. clock.p2 = 14;
  3729. if ((dpll & PLL_REF_INPUT_MASK) ==
  3730. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  3731. /* XXX: might not be 66MHz */
  3732. intel_clock(dev, 66000, &clock);
  3733. } else
  3734. intel_clock(dev, 48000, &clock);
  3735. } else {
  3736. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  3737. clock.p1 = 2;
  3738. else {
  3739. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  3740. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  3741. }
  3742. if (dpll & PLL_P2_DIVIDE_BY_4)
  3743. clock.p2 = 4;
  3744. else
  3745. clock.p2 = 2;
  3746. intel_clock(dev, 48000, &clock);
  3747. }
  3748. }
  3749. /* XXX: It would be nice to validate the clocks, but we can't reuse
  3750. * i830PllIsValid() because it relies on the xf86_config connector
  3751. * configuration being accurate, which it isn't necessarily.
  3752. */
  3753. return clock.dot;
  3754. }
  3755. /** Returns the currently programmed mode of the given pipe. */
  3756. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  3757. struct drm_crtc *crtc)
  3758. {
  3759. struct drm_i915_private *dev_priv = dev->dev_private;
  3760. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3761. int pipe = intel_crtc->pipe;
  3762. struct drm_display_mode *mode;
  3763. int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
  3764. int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
  3765. int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
  3766. int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
  3767. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  3768. if (!mode)
  3769. return NULL;
  3770. mode->clock = intel_crtc_clock_get(dev, crtc);
  3771. mode->hdisplay = (htot & 0xffff) + 1;
  3772. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  3773. mode->hsync_start = (hsync & 0xffff) + 1;
  3774. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  3775. mode->vdisplay = (vtot & 0xffff) + 1;
  3776. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  3777. mode->vsync_start = (vsync & 0xffff) + 1;
  3778. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  3779. drm_mode_set_name(mode);
  3780. drm_mode_set_crtcinfo(mode, 0);
  3781. return mode;
  3782. }
  3783. #define GPU_IDLE_TIMEOUT 500 /* ms */
  3784. /* When this timer fires, we've been idle for awhile */
  3785. static void intel_gpu_idle_timer(unsigned long arg)
  3786. {
  3787. struct drm_device *dev = (struct drm_device *)arg;
  3788. drm_i915_private_t *dev_priv = dev->dev_private;
  3789. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  3790. dev_priv->busy = false;
  3791. queue_work(dev_priv->wq, &dev_priv->idle_work);
  3792. }
  3793. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  3794. static void intel_crtc_idle_timer(unsigned long arg)
  3795. {
  3796. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  3797. struct drm_crtc *crtc = &intel_crtc->base;
  3798. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  3799. DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
  3800. intel_crtc->busy = false;
  3801. queue_work(dev_priv->wq, &dev_priv->idle_work);
  3802. }
  3803. static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
  3804. {
  3805. struct drm_device *dev = crtc->dev;
  3806. drm_i915_private_t *dev_priv = dev->dev_private;
  3807. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3808. int pipe = intel_crtc->pipe;
  3809. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3810. int dpll = I915_READ(dpll_reg);
  3811. if (HAS_PCH_SPLIT(dev))
  3812. return;
  3813. if (!dev_priv->lvds_downclock_avail)
  3814. return;
  3815. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  3816. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  3817. /* Unlock panel regs */
  3818. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
  3819. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  3820. I915_WRITE(dpll_reg, dpll);
  3821. dpll = I915_READ(dpll_reg);
  3822. intel_wait_for_vblank(dev);
  3823. dpll = I915_READ(dpll_reg);
  3824. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  3825. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  3826. /* ...and lock them again */
  3827. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  3828. }
  3829. /* Schedule downclock */
  3830. if (schedule)
  3831. mod_timer(&intel_crtc->idle_timer, jiffies +
  3832. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  3833. }
  3834. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  3835. {
  3836. struct drm_device *dev = crtc->dev;
  3837. drm_i915_private_t *dev_priv = dev->dev_private;
  3838. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3839. int pipe = intel_crtc->pipe;
  3840. int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
  3841. int dpll = I915_READ(dpll_reg);
  3842. if (HAS_PCH_SPLIT(dev))
  3843. return;
  3844. if (!dev_priv->lvds_downclock_avail)
  3845. return;
  3846. /*
  3847. * Since this is called by a timer, we should never get here in
  3848. * the manual case.
  3849. */
  3850. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  3851. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  3852. /* Unlock panel regs */
  3853. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
  3854. dpll |= DISPLAY_RATE_SELECT_FPA1;
  3855. I915_WRITE(dpll_reg, dpll);
  3856. dpll = I915_READ(dpll_reg);
  3857. intel_wait_for_vblank(dev);
  3858. dpll = I915_READ(dpll_reg);
  3859. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  3860. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  3861. /* ...and lock them again */
  3862. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  3863. }
  3864. }
  3865. /**
  3866. * intel_idle_update - adjust clocks for idleness
  3867. * @work: work struct
  3868. *
  3869. * Either the GPU or display (or both) went idle. Check the busy status
  3870. * here and adjust the CRTC and GPU clocks as necessary.
  3871. */
  3872. static void intel_idle_update(struct work_struct *work)
  3873. {
  3874. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  3875. idle_work);
  3876. struct drm_device *dev = dev_priv->dev;
  3877. struct drm_crtc *crtc;
  3878. struct intel_crtc *intel_crtc;
  3879. if (!i915_powersave)
  3880. return;
  3881. mutex_lock(&dev->struct_mutex);
  3882. if (IS_I945G(dev) || IS_I945GM(dev)) {
  3883. DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
  3884. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  3885. }
  3886. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3887. /* Skip inactive CRTCs */
  3888. if (!crtc->fb)
  3889. continue;
  3890. intel_crtc = to_intel_crtc(crtc);
  3891. if (!intel_crtc->busy)
  3892. intel_decrease_pllclock(crtc);
  3893. }
  3894. mutex_unlock(&dev->struct_mutex);
  3895. }
  3896. /**
  3897. * intel_mark_busy - mark the GPU and possibly the display busy
  3898. * @dev: drm device
  3899. * @obj: object we're operating on
  3900. *
  3901. * Callers can use this function to indicate that the GPU is busy processing
  3902. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  3903. * buffer), we'll also mark the display as busy, so we know to increase its
  3904. * clock frequency.
  3905. */
  3906. void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
  3907. {
  3908. drm_i915_private_t *dev_priv = dev->dev_private;
  3909. struct drm_crtc *crtc = NULL;
  3910. struct intel_framebuffer *intel_fb;
  3911. struct intel_crtc *intel_crtc;
  3912. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  3913. return;
  3914. if (!dev_priv->busy) {
  3915. if (IS_I945G(dev) || IS_I945GM(dev)) {
  3916. u32 fw_blc_self;
  3917. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  3918. fw_blc_self = I915_READ(FW_BLC_SELF);
  3919. fw_blc_self &= ~FW_BLC_SELF_EN;
  3920. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  3921. }
  3922. dev_priv->busy = true;
  3923. } else
  3924. mod_timer(&dev_priv->idle_timer, jiffies +
  3925. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  3926. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3927. if (!crtc->fb)
  3928. continue;
  3929. intel_crtc = to_intel_crtc(crtc);
  3930. intel_fb = to_intel_framebuffer(crtc->fb);
  3931. if (intel_fb->obj == obj) {
  3932. if (!intel_crtc->busy) {
  3933. if (IS_I945G(dev) || IS_I945GM(dev)) {
  3934. u32 fw_blc_self;
  3935. DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
  3936. fw_blc_self = I915_READ(FW_BLC_SELF);
  3937. fw_blc_self &= ~FW_BLC_SELF_EN;
  3938. I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
  3939. }
  3940. /* Non-busy -> busy, upclock */
  3941. intel_increase_pllclock(crtc, true);
  3942. intel_crtc->busy = true;
  3943. } else {
  3944. /* Busy -> busy, put off timer */
  3945. mod_timer(&intel_crtc->idle_timer, jiffies +
  3946. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  3947. }
  3948. }
  3949. }
  3950. }
  3951. static void intel_crtc_destroy(struct drm_crtc *crtc)
  3952. {
  3953. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3954. drm_crtc_cleanup(crtc);
  3955. kfree(intel_crtc);
  3956. }
  3957. struct intel_unpin_work {
  3958. struct work_struct work;
  3959. struct drm_device *dev;
  3960. struct drm_gem_object *old_fb_obj;
  3961. struct drm_gem_object *pending_flip_obj;
  3962. struct drm_pending_vblank_event *event;
  3963. int pending;
  3964. };
  3965. static void intel_unpin_work_fn(struct work_struct *__work)
  3966. {
  3967. struct intel_unpin_work *work =
  3968. container_of(__work, struct intel_unpin_work, work);
  3969. mutex_lock(&work->dev->struct_mutex);
  3970. i915_gem_object_unpin(work->old_fb_obj);
  3971. drm_gem_object_unreference(work->pending_flip_obj);
  3972. drm_gem_object_unreference(work->old_fb_obj);
  3973. mutex_unlock(&work->dev->struct_mutex);
  3974. kfree(work);
  3975. }
  3976. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  3977. {
  3978. drm_i915_private_t *dev_priv = dev->dev_private;
  3979. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  3980. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3981. struct intel_unpin_work *work;
  3982. struct drm_i915_gem_object *obj_priv;
  3983. struct drm_pending_vblank_event *e;
  3984. struct timeval now;
  3985. unsigned long flags;
  3986. /* Ignore early vblank irqs */
  3987. if (intel_crtc == NULL)
  3988. return;
  3989. spin_lock_irqsave(&dev->event_lock, flags);
  3990. work = intel_crtc->unpin_work;
  3991. if (work == NULL || !work->pending) {
  3992. if (work && !work->pending) {
  3993. obj_priv = to_intel_bo(work->pending_flip_obj);
  3994. DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
  3995. obj_priv,
  3996. atomic_read(&obj_priv->pending_flip));
  3997. }
  3998. spin_unlock_irqrestore(&dev->event_lock, flags);
  3999. return;
  4000. }
  4001. intel_crtc->unpin_work = NULL;
  4002. drm_vblank_put(dev, intel_crtc->pipe);
  4003. if (work->event) {
  4004. e = work->event;
  4005. do_gettimeofday(&now);
  4006. e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
  4007. e->event.tv_sec = now.tv_sec;
  4008. e->event.tv_usec = now.tv_usec;
  4009. list_add_tail(&e->base.link,
  4010. &e->base.file_priv->event_list);
  4011. wake_up_interruptible(&e->base.file_priv->event_wait);
  4012. }
  4013. spin_unlock_irqrestore(&dev->event_lock, flags);
  4014. obj_priv = to_intel_bo(work->pending_flip_obj);
  4015. /* Initial scanout buffer will have a 0 pending flip count */
  4016. if ((atomic_read(&obj_priv->pending_flip) == 0) ||
  4017. atomic_dec_and_test(&obj_priv->pending_flip))
  4018. DRM_WAKEUP(&dev_priv->pending_flip_queue);
  4019. schedule_work(&work->work);
  4020. }
  4021. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  4022. {
  4023. drm_i915_private_t *dev_priv = dev->dev_private;
  4024. struct intel_crtc *intel_crtc =
  4025. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  4026. unsigned long flags;
  4027. spin_lock_irqsave(&dev->event_lock, flags);
  4028. if (intel_crtc->unpin_work) {
  4029. intel_crtc->unpin_work->pending = 1;
  4030. } else {
  4031. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  4032. }
  4033. spin_unlock_irqrestore(&dev->event_lock, flags);
  4034. }
  4035. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  4036. struct drm_framebuffer *fb,
  4037. struct drm_pending_vblank_event *event)
  4038. {
  4039. struct drm_device *dev = crtc->dev;
  4040. struct drm_i915_private *dev_priv = dev->dev_private;
  4041. struct intel_framebuffer *intel_fb;
  4042. struct drm_i915_gem_object *obj_priv;
  4043. struct drm_gem_object *obj;
  4044. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4045. struct intel_unpin_work *work;
  4046. unsigned long flags;
  4047. int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
  4048. int ret, pipesrc;
  4049. work = kzalloc(sizeof *work, GFP_KERNEL);
  4050. if (work == NULL)
  4051. return -ENOMEM;
  4052. mutex_lock(&dev->struct_mutex);
  4053. work->event = event;
  4054. work->dev = crtc->dev;
  4055. intel_fb = to_intel_framebuffer(crtc->fb);
  4056. work->old_fb_obj = intel_fb->obj;
  4057. INIT_WORK(&work->work, intel_unpin_work_fn);
  4058. /* We borrow the event spin lock for protecting unpin_work */
  4059. spin_lock_irqsave(&dev->event_lock, flags);
  4060. if (intel_crtc->unpin_work) {
  4061. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  4062. spin_unlock_irqrestore(&dev->event_lock, flags);
  4063. kfree(work);
  4064. mutex_unlock(&dev->struct_mutex);
  4065. return -EBUSY;
  4066. }
  4067. intel_crtc->unpin_work = work;
  4068. spin_unlock_irqrestore(&dev->event_lock, flags);
  4069. intel_fb = to_intel_framebuffer(fb);
  4070. obj = intel_fb->obj;
  4071. ret = intel_pin_and_fence_fb_obj(dev, obj);
  4072. if (ret != 0) {
  4073. DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
  4074. to_intel_bo(obj));
  4075. kfree(work);
  4076. intel_crtc->unpin_work = NULL;
  4077. mutex_unlock(&dev->struct_mutex);
  4078. return ret;
  4079. }
  4080. /* Reference the objects for the scheduled work. */
  4081. drm_gem_object_reference(work->old_fb_obj);
  4082. drm_gem_object_reference(obj);
  4083. crtc->fb = fb;
  4084. i915_gem_object_flush_write_domain(obj);
  4085. drm_vblank_get(dev, intel_crtc->pipe);
  4086. obj_priv = to_intel_bo(obj);
  4087. atomic_inc(&obj_priv->pending_flip);
  4088. work->pending_flip_obj = obj;
  4089. BEGIN_LP_RING(4);
  4090. OUT_RING(MI_DISPLAY_FLIP |
  4091. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  4092. OUT_RING(fb->pitch);
  4093. if (IS_I965G(dev)) {
  4094. OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
  4095. pipesrc = I915_READ(pipesrc_reg);
  4096. OUT_RING(pipesrc & 0x0fff0fff);
  4097. } else {
  4098. OUT_RING(obj_priv->gtt_offset);
  4099. OUT_RING(MI_NOOP);
  4100. }
  4101. ADVANCE_LP_RING();
  4102. mutex_unlock(&dev->struct_mutex);
  4103. return 0;
  4104. }
  4105. static const struct drm_crtc_helper_funcs intel_helper_funcs = {
  4106. .dpms = intel_crtc_dpms,
  4107. .mode_fixup = intel_crtc_mode_fixup,
  4108. .mode_set = intel_crtc_mode_set,
  4109. .mode_set_base = intel_pipe_set_base,
  4110. .prepare = intel_crtc_prepare,
  4111. .commit = intel_crtc_commit,
  4112. .load_lut = intel_crtc_load_lut,
  4113. };
  4114. static const struct drm_crtc_funcs intel_crtc_funcs = {
  4115. .cursor_set = intel_crtc_cursor_set,
  4116. .cursor_move = intel_crtc_cursor_move,
  4117. .gamma_set = intel_crtc_gamma_set,
  4118. .set_config = drm_crtc_helper_set_config,
  4119. .destroy = intel_crtc_destroy,
  4120. .page_flip = intel_crtc_page_flip,
  4121. };
  4122. static void intel_crtc_init(struct drm_device *dev, int pipe)
  4123. {
  4124. drm_i915_private_t *dev_priv = dev->dev_private;
  4125. struct intel_crtc *intel_crtc;
  4126. int i;
  4127. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  4128. if (intel_crtc == NULL)
  4129. return;
  4130. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  4131. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  4132. intel_crtc->pipe = pipe;
  4133. intel_crtc->plane = pipe;
  4134. for (i = 0; i < 256; i++) {
  4135. intel_crtc->lut_r[i] = i;
  4136. intel_crtc->lut_g[i] = i;
  4137. intel_crtc->lut_b[i] = i;
  4138. }
  4139. /* Swap pipes & planes for FBC on pre-965 */
  4140. intel_crtc->pipe = pipe;
  4141. intel_crtc->plane = pipe;
  4142. if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
  4143. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  4144. intel_crtc->plane = ((pipe == 0) ? 1 : 0);
  4145. }
  4146. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  4147. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  4148. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  4149. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  4150. intel_crtc->cursor_addr = 0;
  4151. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  4152. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  4153. intel_crtc->busy = false;
  4154. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  4155. (unsigned long)intel_crtc);
  4156. }
  4157. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  4158. struct drm_file *file_priv)
  4159. {
  4160. drm_i915_private_t *dev_priv = dev->dev_private;
  4161. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  4162. struct drm_mode_object *drmmode_obj;
  4163. struct intel_crtc *crtc;
  4164. if (!dev_priv) {
  4165. DRM_ERROR("called with no initialization\n");
  4166. return -EINVAL;
  4167. }
  4168. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  4169. DRM_MODE_OBJECT_CRTC);
  4170. if (!drmmode_obj) {
  4171. DRM_ERROR("no such CRTC id\n");
  4172. return -EINVAL;
  4173. }
  4174. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  4175. pipe_from_crtc_id->pipe = crtc->pipe;
  4176. return 0;
  4177. }
  4178. struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
  4179. {
  4180. struct drm_crtc *crtc = NULL;
  4181. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4182. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4183. if (intel_crtc->pipe == pipe)
  4184. break;
  4185. }
  4186. return crtc;
  4187. }
  4188. static int intel_encoder_clones(struct drm_device *dev, int type_mask)
  4189. {
  4190. int index_mask = 0;
  4191. struct drm_encoder *encoder;
  4192. int entry = 0;
  4193. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  4194. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  4195. if (type_mask & intel_encoder->clone_mask)
  4196. index_mask |= (1 << entry);
  4197. entry++;
  4198. }
  4199. return index_mask;
  4200. }
  4201. static void intel_setup_outputs(struct drm_device *dev)
  4202. {
  4203. struct drm_i915_private *dev_priv = dev->dev_private;
  4204. struct drm_encoder *encoder;
  4205. intel_crt_init(dev);
  4206. /* Set up integrated LVDS */
  4207. if (IS_MOBILE(dev) && !IS_I830(dev))
  4208. intel_lvds_init(dev);
  4209. if (HAS_PCH_SPLIT(dev)) {
  4210. int found;
  4211. if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
  4212. intel_dp_init(dev, DP_A);
  4213. if (I915_READ(HDMIB) & PORT_DETECTED) {
  4214. /* PCH SDVOB multiplex with HDMIB */
  4215. found = intel_sdvo_init(dev, PCH_SDVOB);
  4216. if (!found)
  4217. intel_hdmi_init(dev, HDMIB);
  4218. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  4219. intel_dp_init(dev, PCH_DP_B);
  4220. }
  4221. if (I915_READ(HDMIC) & PORT_DETECTED)
  4222. intel_hdmi_init(dev, HDMIC);
  4223. if (I915_READ(HDMID) & PORT_DETECTED)
  4224. intel_hdmi_init(dev, HDMID);
  4225. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  4226. intel_dp_init(dev, PCH_DP_C);
  4227. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  4228. intel_dp_init(dev, PCH_DP_D);
  4229. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  4230. bool found = false;
  4231. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4232. DRM_DEBUG_KMS("probing SDVOB\n");
  4233. found = intel_sdvo_init(dev, SDVOB);
  4234. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  4235. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  4236. intel_hdmi_init(dev, SDVOB);
  4237. }
  4238. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  4239. DRM_DEBUG_KMS("probing DP_B\n");
  4240. intel_dp_init(dev, DP_B);
  4241. }
  4242. }
  4243. /* Before G4X SDVOC doesn't have its own detect register */
  4244. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  4245. DRM_DEBUG_KMS("probing SDVOC\n");
  4246. found = intel_sdvo_init(dev, SDVOC);
  4247. }
  4248. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  4249. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  4250. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  4251. intel_hdmi_init(dev, SDVOC);
  4252. }
  4253. if (SUPPORTS_INTEGRATED_DP(dev)) {
  4254. DRM_DEBUG_KMS("probing DP_C\n");
  4255. intel_dp_init(dev, DP_C);
  4256. }
  4257. }
  4258. if (SUPPORTS_INTEGRATED_DP(dev) &&
  4259. (I915_READ(DP_D) & DP_DETECTED)) {
  4260. DRM_DEBUG_KMS("probing DP_D\n");
  4261. intel_dp_init(dev, DP_D);
  4262. }
  4263. } else if (IS_GEN2(dev))
  4264. intel_dvo_init(dev);
  4265. if (SUPPORTS_TV(dev))
  4266. intel_tv_init(dev);
  4267. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  4268. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  4269. encoder->possible_crtcs = intel_encoder->crtc_mask;
  4270. encoder->possible_clones = intel_encoder_clones(dev,
  4271. intel_encoder->clone_mask);
  4272. }
  4273. }
  4274. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  4275. {
  4276. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4277. drm_framebuffer_cleanup(fb);
  4278. drm_gem_object_unreference_unlocked(intel_fb->obj);
  4279. kfree(intel_fb);
  4280. }
  4281. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  4282. struct drm_file *file_priv,
  4283. unsigned int *handle)
  4284. {
  4285. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  4286. struct drm_gem_object *object = intel_fb->obj;
  4287. return drm_gem_handle_create(file_priv, object, handle);
  4288. }
  4289. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  4290. .destroy = intel_user_framebuffer_destroy,
  4291. .create_handle = intel_user_framebuffer_create_handle,
  4292. };
  4293. int intel_framebuffer_init(struct drm_device *dev,
  4294. struct intel_framebuffer *intel_fb,
  4295. struct drm_mode_fb_cmd *mode_cmd,
  4296. struct drm_gem_object *obj)
  4297. {
  4298. int ret;
  4299. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  4300. if (ret) {
  4301. DRM_ERROR("framebuffer init failed %d\n", ret);
  4302. return ret;
  4303. }
  4304. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  4305. intel_fb->obj = obj;
  4306. return 0;
  4307. }
  4308. static struct drm_framebuffer *
  4309. intel_user_framebuffer_create(struct drm_device *dev,
  4310. struct drm_file *filp,
  4311. struct drm_mode_fb_cmd *mode_cmd)
  4312. {
  4313. struct drm_gem_object *obj;
  4314. struct intel_framebuffer *intel_fb;
  4315. int ret;
  4316. obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
  4317. if (!obj)
  4318. return NULL;
  4319. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  4320. if (!intel_fb)
  4321. return NULL;
  4322. ret = intel_framebuffer_init(dev, intel_fb,
  4323. mode_cmd, obj);
  4324. if (ret) {
  4325. drm_gem_object_unreference_unlocked(obj);
  4326. kfree(intel_fb);
  4327. return NULL;
  4328. }
  4329. return &intel_fb->base;
  4330. }
  4331. static const struct drm_mode_config_funcs intel_mode_funcs = {
  4332. .fb_create = intel_user_framebuffer_create,
  4333. .output_poll_changed = intel_fb_output_poll_changed,
  4334. };
  4335. static struct drm_gem_object *
  4336. intel_alloc_power_context(struct drm_device *dev)
  4337. {
  4338. struct drm_gem_object *pwrctx;
  4339. int ret;
  4340. pwrctx = i915_gem_alloc_object(dev, 4096);
  4341. if (!pwrctx) {
  4342. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  4343. return NULL;
  4344. }
  4345. mutex_lock(&dev->struct_mutex);
  4346. ret = i915_gem_object_pin(pwrctx, 4096);
  4347. if (ret) {
  4348. DRM_ERROR("failed to pin power context: %d\n", ret);
  4349. goto err_unref;
  4350. }
  4351. ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
  4352. if (ret) {
  4353. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  4354. goto err_unpin;
  4355. }
  4356. mutex_unlock(&dev->struct_mutex);
  4357. return pwrctx;
  4358. err_unpin:
  4359. i915_gem_object_unpin(pwrctx);
  4360. err_unref:
  4361. drm_gem_object_unreference(pwrctx);
  4362. mutex_unlock(&dev->struct_mutex);
  4363. return NULL;
  4364. }
  4365. void ironlake_enable_drps(struct drm_device *dev)
  4366. {
  4367. struct drm_i915_private *dev_priv = dev->dev_private;
  4368. u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
  4369. u8 fmax, fmin, fstart, vstart;
  4370. int i = 0;
  4371. /* 100ms RC evaluation intervals */
  4372. I915_WRITE(RCUPEI, 100000);
  4373. I915_WRITE(RCDNEI, 100000);
  4374. /* Set max/min thresholds to 90ms and 80ms respectively */
  4375. I915_WRITE(RCBMAXAVG, 90000);
  4376. I915_WRITE(RCBMINAVG, 80000);
  4377. I915_WRITE(MEMIHYST, 1);
  4378. /* Set up min, max, and cur for interrupt handling */
  4379. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  4380. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  4381. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  4382. MEMMODE_FSTART_SHIFT;
  4383. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  4384. PXVFREQ_PX_SHIFT;
  4385. dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
  4386. dev_priv->min_delay = fmin;
  4387. dev_priv->cur_delay = fstart;
  4388. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  4389. /*
  4390. * Interrupts will be enabled in ironlake_irq_postinstall
  4391. */
  4392. I915_WRITE(VIDSTART, vstart);
  4393. POSTING_READ(VIDSTART);
  4394. rgvmodectl |= MEMMODE_SWMODE_EN;
  4395. I915_WRITE(MEMMODECTL, rgvmodectl);
  4396. while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
  4397. if (i++ > 100) {
  4398. DRM_ERROR("stuck trying to change perf mode\n");
  4399. break;
  4400. }
  4401. msleep(1);
  4402. }
  4403. msleep(1);
  4404. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  4405. (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  4406. I915_WRITE(MEMSWCTL, rgvswctl);
  4407. POSTING_READ(MEMSWCTL);
  4408. rgvswctl |= MEMCTL_CMD_STS;
  4409. I915_WRITE(MEMSWCTL, rgvswctl);
  4410. }
  4411. void ironlake_disable_drps(struct drm_device *dev)
  4412. {
  4413. struct drm_i915_private *dev_priv = dev->dev_private;
  4414. u32 rgvswctl;
  4415. u8 fstart;
  4416. /* Ack interrupts, disable EFC interrupt */
  4417. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  4418. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  4419. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  4420. I915_WRITE(DEIIR, DE_PCU_EVENT);
  4421. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  4422. /* Go back to the starting frequency */
  4423. fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
  4424. MEMMODE_FSTART_SHIFT;
  4425. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  4426. (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  4427. I915_WRITE(MEMSWCTL, rgvswctl);
  4428. msleep(1);
  4429. rgvswctl |= MEMCTL_CMD_STS;
  4430. I915_WRITE(MEMSWCTL, rgvswctl);
  4431. msleep(1);
  4432. }
  4433. void intel_init_clock_gating(struct drm_device *dev)
  4434. {
  4435. struct drm_i915_private *dev_priv = dev->dev_private;
  4436. /*
  4437. * Disable clock gating reported to work incorrectly according to the
  4438. * specs, but enable as much else as we can.
  4439. */
  4440. if (HAS_PCH_SPLIT(dev)) {
  4441. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  4442. if (IS_IRONLAKE(dev)) {
  4443. /* Required for FBC */
  4444. dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
  4445. /* Required for CxSR */
  4446. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  4447. I915_WRITE(PCH_3DCGDIS0,
  4448. MARIUNIT_CLOCK_GATE_DISABLE |
  4449. SVSMUNIT_CLOCK_GATE_DISABLE);
  4450. }
  4451. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  4452. /*
  4453. * According to the spec the following bits should be set in
  4454. * order to enable memory self-refresh
  4455. * The bit 22/21 of 0x42004
  4456. * The bit 5 of 0x42020
  4457. * The bit 15 of 0x45000
  4458. */
  4459. if (IS_IRONLAKE(dev)) {
  4460. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  4461. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  4462. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  4463. I915_WRITE(ILK_DSPCLK_GATE,
  4464. (I915_READ(ILK_DSPCLK_GATE) |
  4465. ILK_DPARB_CLK_GATE));
  4466. I915_WRITE(DISP_ARB_CTL,
  4467. (I915_READ(DISP_ARB_CTL) |
  4468. DISP_FBC_WM_DIS));
  4469. }
  4470. return;
  4471. } else if (IS_G4X(dev)) {
  4472. uint32_t dspclk_gate;
  4473. I915_WRITE(RENCLK_GATE_D1, 0);
  4474. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  4475. GS_UNIT_CLOCK_GATE_DISABLE |
  4476. CL_UNIT_CLOCK_GATE_DISABLE);
  4477. I915_WRITE(RAMCLK_GATE_D, 0);
  4478. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  4479. OVRUNIT_CLOCK_GATE_DISABLE |
  4480. OVCUNIT_CLOCK_GATE_DISABLE;
  4481. if (IS_GM45(dev))
  4482. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  4483. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  4484. } else if (IS_I965GM(dev)) {
  4485. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  4486. I915_WRITE(RENCLK_GATE_D2, 0);
  4487. I915_WRITE(DSPCLK_GATE_D, 0);
  4488. I915_WRITE(RAMCLK_GATE_D, 0);
  4489. I915_WRITE16(DEUC, 0);
  4490. } else if (IS_I965G(dev)) {
  4491. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  4492. I965_RCC_CLOCK_GATE_DISABLE |
  4493. I965_RCPB_CLOCK_GATE_DISABLE |
  4494. I965_ISC_CLOCK_GATE_DISABLE |
  4495. I965_FBC_CLOCK_GATE_DISABLE);
  4496. I915_WRITE(RENCLK_GATE_D2, 0);
  4497. } else if (IS_I9XX(dev)) {
  4498. u32 dstate = I915_READ(D_STATE);
  4499. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  4500. DSTATE_DOT_CLOCK_GATING;
  4501. I915_WRITE(D_STATE, dstate);
  4502. } else if (IS_I85X(dev) || IS_I865G(dev)) {
  4503. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  4504. } else if (IS_I830(dev)) {
  4505. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  4506. }
  4507. /*
  4508. * GPU can automatically power down the render unit if given a page
  4509. * to save state.
  4510. */
  4511. if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
  4512. struct drm_i915_gem_object *obj_priv = NULL;
  4513. if (dev_priv->pwrctx) {
  4514. obj_priv = to_intel_bo(dev_priv->pwrctx);
  4515. } else {
  4516. struct drm_gem_object *pwrctx;
  4517. pwrctx = intel_alloc_power_context(dev);
  4518. if (pwrctx) {
  4519. dev_priv->pwrctx = pwrctx;
  4520. obj_priv = to_intel_bo(pwrctx);
  4521. }
  4522. }
  4523. if (obj_priv) {
  4524. I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
  4525. I915_WRITE(MCHBAR_RENDER_STANDBY,
  4526. I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
  4527. }
  4528. }
  4529. }
  4530. /* Set up chip specific display functions */
  4531. static void intel_init_display(struct drm_device *dev)
  4532. {
  4533. struct drm_i915_private *dev_priv = dev->dev_private;
  4534. /* We always want a DPMS function */
  4535. if (HAS_PCH_SPLIT(dev))
  4536. dev_priv->display.dpms = ironlake_crtc_dpms;
  4537. else
  4538. dev_priv->display.dpms = i9xx_crtc_dpms;
  4539. if (I915_HAS_FBC(dev)) {
  4540. if (IS_GM45(dev)) {
  4541. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  4542. dev_priv->display.enable_fbc = g4x_enable_fbc;
  4543. dev_priv->display.disable_fbc = g4x_disable_fbc;
  4544. } else if (IS_I965GM(dev)) {
  4545. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  4546. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  4547. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  4548. }
  4549. /* 855GM needs testing */
  4550. }
  4551. /* Returns the core display clock speed */
  4552. if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
  4553. dev_priv->display.get_display_clock_speed =
  4554. i945_get_display_clock_speed;
  4555. else if (IS_I915G(dev))
  4556. dev_priv->display.get_display_clock_speed =
  4557. i915_get_display_clock_speed;
  4558. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  4559. dev_priv->display.get_display_clock_speed =
  4560. i9xx_misc_get_display_clock_speed;
  4561. else if (IS_I915GM(dev))
  4562. dev_priv->display.get_display_clock_speed =
  4563. i915gm_get_display_clock_speed;
  4564. else if (IS_I865G(dev))
  4565. dev_priv->display.get_display_clock_speed =
  4566. i865_get_display_clock_speed;
  4567. else if (IS_I85X(dev))
  4568. dev_priv->display.get_display_clock_speed =
  4569. i855_get_display_clock_speed;
  4570. else /* 852, 830 */
  4571. dev_priv->display.get_display_clock_speed =
  4572. i830_get_display_clock_speed;
  4573. /* For FIFO watermark updates */
  4574. if (HAS_PCH_SPLIT(dev)) {
  4575. if (IS_IRONLAKE(dev)) {
  4576. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  4577. dev_priv->display.update_wm = ironlake_update_wm;
  4578. else {
  4579. DRM_DEBUG_KMS("Failed to get proper latency. "
  4580. "Disable CxSR\n");
  4581. dev_priv->display.update_wm = NULL;
  4582. }
  4583. } else
  4584. dev_priv->display.update_wm = NULL;
  4585. } else if (IS_PINEVIEW(dev)) {
  4586. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  4587. dev_priv->fsb_freq,
  4588. dev_priv->mem_freq)) {
  4589. DRM_INFO("failed to find known CxSR latency "
  4590. "(found fsb freq %d, mem freq %d), "
  4591. "disabling CxSR\n",
  4592. dev_priv->fsb_freq, dev_priv->mem_freq);
  4593. /* Disable CxSR and never update its watermark again */
  4594. pineview_disable_cxsr(dev);
  4595. dev_priv->display.update_wm = NULL;
  4596. } else
  4597. dev_priv->display.update_wm = pineview_update_wm;
  4598. } else if (IS_G4X(dev))
  4599. dev_priv->display.update_wm = g4x_update_wm;
  4600. else if (IS_I965G(dev))
  4601. dev_priv->display.update_wm = i965_update_wm;
  4602. else if (IS_I9XX(dev)) {
  4603. dev_priv->display.update_wm = i9xx_update_wm;
  4604. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  4605. } else if (IS_I85X(dev)) {
  4606. dev_priv->display.update_wm = i9xx_update_wm;
  4607. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  4608. } else {
  4609. dev_priv->display.update_wm = i830_update_wm;
  4610. if (IS_845G(dev))
  4611. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  4612. else
  4613. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  4614. }
  4615. }
  4616. void intel_modeset_init(struct drm_device *dev)
  4617. {
  4618. struct drm_i915_private *dev_priv = dev->dev_private;
  4619. int num_pipe;
  4620. int i;
  4621. drm_mode_config_init(dev);
  4622. dev->mode_config.min_width = 0;
  4623. dev->mode_config.min_height = 0;
  4624. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  4625. intel_init_display(dev);
  4626. if (IS_I965G(dev)) {
  4627. dev->mode_config.max_width = 8192;
  4628. dev->mode_config.max_height = 8192;
  4629. } else if (IS_I9XX(dev)) {
  4630. dev->mode_config.max_width = 4096;
  4631. dev->mode_config.max_height = 4096;
  4632. } else {
  4633. dev->mode_config.max_width = 2048;
  4634. dev->mode_config.max_height = 2048;
  4635. }
  4636. /* set memory base */
  4637. if (IS_I9XX(dev))
  4638. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
  4639. else
  4640. dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
  4641. if (IS_MOBILE(dev) || IS_I9XX(dev))
  4642. num_pipe = 2;
  4643. else
  4644. num_pipe = 1;
  4645. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  4646. num_pipe, num_pipe > 1 ? "s" : "");
  4647. for (i = 0; i < num_pipe; i++) {
  4648. intel_crtc_init(dev, i);
  4649. }
  4650. intel_setup_outputs(dev);
  4651. intel_init_clock_gating(dev);
  4652. if (IS_IRONLAKE_M(dev))
  4653. ironlake_enable_drps(dev);
  4654. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  4655. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  4656. (unsigned long)dev);
  4657. intel_setup_overlay(dev);
  4658. }
  4659. void intel_modeset_cleanup(struct drm_device *dev)
  4660. {
  4661. struct drm_i915_private *dev_priv = dev->dev_private;
  4662. struct drm_crtc *crtc;
  4663. struct intel_crtc *intel_crtc;
  4664. mutex_lock(&dev->struct_mutex);
  4665. drm_kms_helper_poll_fini(dev);
  4666. intel_fbdev_fini(dev);
  4667. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  4668. /* Skip inactive CRTCs */
  4669. if (!crtc->fb)
  4670. continue;
  4671. intel_crtc = to_intel_crtc(crtc);
  4672. intel_increase_pllclock(crtc, false);
  4673. del_timer_sync(&intel_crtc->idle_timer);
  4674. }
  4675. del_timer_sync(&dev_priv->idle_timer);
  4676. if (dev_priv->display.disable_fbc)
  4677. dev_priv->display.disable_fbc(dev);
  4678. if (dev_priv->pwrctx) {
  4679. struct drm_i915_gem_object *obj_priv;
  4680. obj_priv = to_intel_bo(dev_priv->pwrctx);
  4681. I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
  4682. I915_READ(PWRCTXA);
  4683. i915_gem_object_unpin(dev_priv->pwrctx);
  4684. drm_gem_object_unreference(dev_priv->pwrctx);
  4685. }
  4686. if (IS_IRONLAKE_M(dev))
  4687. ironlake_disable_drps(dev);
  4688. mutex_unlock(&dev->struct_mutex);
  4689. drm_mode_config_cleanup(dev);
  4690. }
  4691. /*
  4692. * Return which encoder is currently attached for connector.
  4693. */
  4694. struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
  4695. {
  4696. struct drm_mode_object *obj;
  4697. struct drm_encoder *encoder;
  4698. int i;
  4699. for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
  4700. if (connector->encoder_ids[i] == 0)
  4701. break;
  4702. obj = drm_mode_object_find(connector->dev,
  4703. connector->encoder_ids[i],
  4704. DRM_MODE_OBJECT_ENCODER);
  4705. if (!obj)
  4706. continue;
  4707. encoder = obj_to_encoder(obj);
  4708. return encoder;
  4709. }
  4710. return NULL;
  4711. }
  4712. /*
  4713. * set vga decode state - true == enable VGA decode
  4714. */
  4715. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  4716. {
  4717. struct drm_i915_private *dev_priv = dev->dev_private;
  4718. u16 gmch_ctrl;
  4719. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  4720. if (state)
  4721. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  4722. else
  4723. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  4724. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  4725. return 0;
  4726. }