cx88-dvb.c 26 KB

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  1. /*
  2. *
  3. * device driver for Conexant 2388x based TV cards
  4. * MPEG Transport Stream (DVB) routines
  5. *
  6. * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
  7. * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/device.h>
  26. #include <linux/fs.h>
  27. #include <linux/kthread.h>
  28. #include <linux/file.h>
  29. #include <linux/suspend.h>
  30. #include "cx88.h"
  31. #include "dvb-pll.h"
  32. #include <media/v4l2-common.h>
  33. #include "mt352.h"
  34. #include "mt352_priv.h"
  35. #include "cx88-vp3054-i2c.h"
  36. #include "zl10353.h"
  37. #include "cx22702.h"
  38. #include "or51132.h"
  39. #include "lgdt330x.h"
  40. #include "s5h1409.h"
  41. #include "xc5000.h"
  42. #include "nxt200x.h"
  43. #include "cx24123.h"
  44. #include "isl6421.h"
  45. #include "tuner-xc2028.h"
  46. #include "tuner-xc2028-types.h"
  47. MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
  48. MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  49. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  50. MODULE_LICENSE("GPL");
  51. static unsigned int debug;
  52. module_param(debug, int, 0644);
  53. MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
  54. #define dprintk(level,fmt, arg...) if (debug >= level) \
  55. printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
  56. /* ------------------------------------------------------------------ */
  57. static int dvb_buf_setup(struct videobuf_queue *q,
  58. unsigned int *count, unsigned int *size)
  59. {
  60. struct cx8802_dev *dev = q->priv_data;
  61. dev->ts_packet_size = 188 * 4;
  62. dev->ts_packet_count = 32;
  63. *size = dev->ts_packet_size * dev->ts_packet_count;
  64. *count = 32;
  65. return 0;
  66. }
  67. static int dvb_buf_prepare(struct videobuf_queue *q,
  68. struct videobuf_buffer *vb, enum v4l2_field field)
  69. {
  70. struct cx8802_dev *dev = q->priv_data;
  71. return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
  72. }
  73. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  74. {
  75. struct cx8802_dev *dev = q->priv_data;
  76. cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
  77. }
  78. static void dvb_buf_release(struct videobuf_queue *q,
  79. struct videobuf_buffer *vb)
  80. {
  81. cx88_free_buffer(q, (struct cx88_buffer*)vb);
  82. }
  83. static struct videobuf_queue_ops dvb_qops = {
  84. .buf_setup = dvb_buf_setup,
  85. .buf_prepare = dvb_buf_prepare,
  86. .buf_queue = dvb_buf_queue,
  87. .buf_release = dvb_buf_release,
  88. };
  89. /* ------------------------------------------------------------------ */
  90. static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
  91. {
  92. struct cx8802_dev *dev= fe->dvb->priv;
  93. struct cx8802_driver *drv = NULL;
  94. int ret = 0;
  95. drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
  96. if (drv) {
  97. if (acquire)
  98. ret = drv->request_acquire(drv);
  99. else
  100. ret = drv->request_release(drv);
  101. }
  102. return ret;
  103. }
  104. /* ------------------------------------------------------------------ */
  105. static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
  106. {
  107. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
  108. static u8 reset [] = { RESET, 0x80 };
  109. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  110. static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
  111. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  112. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  113. mt352_write(fe, clock_config, sizeof(clock_config));
  114. udelay(200);
  115. mt352_write(fe, reset, sizeof(reset));
  116. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  117. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  118. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  119. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  120. return 0;
  121. }
  122. static int dvico_dual_demod_init(struct dvb_frontend *fe)
  123. {
  124. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
  125. static u8 reset [] = { RESET, 0x80 };
  126. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  127. static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
  128. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  129. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  130. mt352_write(fe, clock_config, sizeof(clock_config));
  131. udelay(200);
  132. mt352_write(fe, reset, sizeof(reset));
  133. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  134. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  135. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  136. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  137. return 0;
  138. }
  139. static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
  140. {
  141. static u8 clock_config [] = { 0x89, 0x38, 0x39 };
  142. static u8 reset [] = { 0x50, 0x80 };
  143. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  144. static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
  145. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  146. static u8 dntv_extra[] = { 0xB5, 0x7A };
  147. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  148. mt352_write(fe, clock_config, sizeof(clock_config));
  149. udelay(2000);
  150. mt352_write(fe, reset, sizeof(reset));
  151. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  152. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  153. udelay(2000);
  154. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  155. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  156. return 0;
  157. }
  158. static struct mt352_config dvico_fusionhdtv = {
  159. .demod_address = 0x0f,
  160. .demod_init = dvico_fusionhdtv_demod_init,
  161. };
  162. static struct mt352_config dntv_live_dvbt_config = {
  163. .demod_address = 0x0f,
  164. .demod_init = dntv_live_dvbt_demod_init,
  165. };
  166. static struct mt352_config dvico_fusionhdtv_dual = {
  167. .demod_address = 0x0f,
  168. .demod_init = dvico_dual_demod_init,
  169. };
  170. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  171. static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
  172. {
  173. static u8 clock_config [] = { 0x89, 0x38, 0x38 };
  174. static u8 reset [] = { 0x50, 0x80 };
  175. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  176. static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
  177. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  178. static u8 dntv_extra[] = { 0xB5, 0x7A };
  179. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  180. mt352_write(fe, clock_config, sizeof(clock_config));
  181. udelay(2000);
  182. mt352_write(fe, reset, sizeof(reset));
  183. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  184. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  185. udelay(2000);
  186. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  187. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  188. return 0;
  189. }
  190. static struct mt352_config dntv_live_dvbt_pro_config = {
  191. .demod_address = 0x0f,
  192. .no_tuner = 1,
  193. .demod_init = dntv_live_dvbt_pro_demod_init,
  194. };
  195. #endif
  196. static struct zl10353_config dvico_fusionhdtv_hybrid = {
  197. .demod_address = 0x0f,
  198. .no_tuner = 1,
  199. };
  200. static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
  201. .demod_address = 0x0f,
  202. };
  203. static struct cx22702_config connexant_refboard_config = {
  204. .demod_address = 0x43,
  205. .output_mode = CX22702_SERIAL_OUTPUT,
  206. };
  207. static struct cx22702_config hauppauge_hvr_config = {
  208. .demod_address = 0x63,
  209. .output_mode = CX22702_SERIAL_OUTPUT,
  210. };
  211. static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  212. {
  213. struct cx8802_dev *dev= fe->dvb->priv;
  214. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  215. return 0;
  216. }
  217. static struct or51132_config pchdtv_hd3000 = {
  218. .demod_address = 0x15,
  219. .set_ts_params = or51132_set_ts_param,
  220. };
  221. static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
  222. {
  223. struct cx8802_dev *dev= fe->dvb->priv;
  224. struct cx88_core *core = dev->core;
  225. dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
  226. if (index == 0)
  227. cx_clear(MO_GP0_IO, 8);
  228. else
  229. cx_set(MO_GP0_IO, 8);
  230. return 0;
  231. }
  232. static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  233. {
  234. struct cx8802_dev *dev= fe->dvb->priv;
  235. if (is_punctured)
  236. dev->ts_gen_cntrl |= 0x04;
  237. else
  238. dev->ts_gen_cntrl &= ~0x04;
  239. return 0;
  240. }
  241. static struct lgdt330x_config fusionhdtv_3_gold = {
  242. .demod_address = 0x0e,
  243. .demod_chip = LGDT3302,
  244. .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
  245. .set_ts_params = lgdt330x_set_ts_param,
  246. };
  247. static struct lgdt330x_config fusionhdtv_5_gold = {
  248. .demod_address = 0x0e,
  249. .demod_chip = LGDT3303,
  250. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  251. .set_ts_params = lgdt330x_set_ts_param,
  252. };
  253. static struct lgdt330x_config pchdtv_hd5500 = {
  254. .demod_address = 0x59,
  255. .demod_chip = LGDT3303,
  256. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  257. .set_ts_params = lgdt330x_set_ts_param,
  258. };
  259. static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  260. {
  261. struct cx8802_dev *dev= fe->dvb->priv;
  262. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  263. return 0;
  264. }
  265. static struct nxt200x_config ati_hdtvwonder = {
  266. .demod_address = 0x0a,
  267. .set_ts_params = nxt200x_set_ts_param,
  268. };
  269. static int cx24123_set_ts_param(struct dvb_frontend* fe,
  270. int is_punctured)
  271. {
  272. struct cx8802_dev *dev= fe->dvb->priv;
  273. dev->ts_gen_cntrl = 0x02;
  274. return 0;
  275. }
  276. static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
  277. fe_sec_voltage_t voltage)
  278. {
  279. struct cx8802_dev *dev= fe->dvb->priv;
  280. struct cx88_core *core = dev->core;
  281. if (voltage == SEC_VOLTAGE_OFF)
  282. cx_write(MO_GP0_IO, 0x000006fb);
  283. else
  284. cx_write(MO_GP0_IO, 0x000006f9);
  285. if (core->prev_set_voltage)
  286. return core->prev_set_voltage(fe, voltage);
  287. return 0;
  288. }
  289. static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
  290. fe_sec_voltage_t voltage)
  291. {
  292. struct cx8802_dev *dev= fe->dvb->priv;
  293. struct cx88_core *core = dev->core;
  294. if (voltage == SEC_VOLTAGE_OFF) {
  295. dprintk(1,"LNB Voltage OFF\n");
  296. cx_write(MO_GP0_IO, 0x0000efff);
  297. }
  298. if (core->prev_set_voltage)
  299. return core->prev_set_voltage(fe, voltage);
  300. return 0;
  301. }
  302. static int cx88_xc3028_callback(void *ptr, int command, int arg)
  303. {
  304. struct cx88_core *core = ptr;
  305. switch (command) {
  306. case XC2028_TUNER_RESET:
  307. /* Send the tuner in then out of reset */
  308. dprintk(1, "%s: XC2028_TUNER_RESET %d\n", __FUNCTION__, arg);
  309. switch (core->boardnr) {
  310. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  311. /* GPIO-4 xc3028 tuner */
  312. cx_set(MO_GP0_IO, 0x00001000);
  313. cx_clear(MO_GP0_IO, 0x00000010);
  314. msleep(100);
  315. cx_set(MO_GP0_IO, 0x00000010);
  316. msleep(100);
  317. break;
  318. }
  319. break;
  320. case XC2028_RESET_CLK:
  321. dprintk(1, "%s: XC2028_RESET_CLK %d\n", __FUNCTION__, arg);
  322. break;
  323. default:
  324. dprintk(1, "%s: unknown command %d, arg %d\n", __FUNCTION__,
  325. command, arg);
  326. return -EINVAL;
  327. }
  328. return 0;
  329. }
  330. static struct cx24123_config geniatech_dvbs_config = {
  331. .demod_address = 0x55,
  332. .set_ts_params = cx24123_set_ts_param,
  333. };
  334. static struct cx24123_config hauppauge_novas_config = {
  335. .demod_address = 0x55,
  336. .set_ts_params = cx24123_set_ts_param,
  337. };
  338. static struct cx24123_config kworld_dvbs_100_config = {
  339. .demod_address = 0x15,
  340. .set_ts_params = cx24123_set_ts_param,
  341. .lnb_polarity = 1,
  342. };
  343. static struct s5h1409_config pinnacle_pctv_hd_800i_config = {
  344. .demod_address = 0x32 >> 1,
  345. .output_mode = S5H1409_PARALLEL_OUTPUT,
  346. .gpio = S5H1409_GPIO_ON,
  347. .qam_if = 44000,
  348. .inversion = S5H1409_INVERSION_OFF,
  349. .status_mode = S5H1409_DEMODLOCKING,
  350. .mpeg_timing = S5H1409_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK,
  351. };
  352. static struct s5h1409_config dvico_hdtv5_pci_nano_config = {
  353. .demod_address = 0x32 >> 1,
  354. .output_mode = S5H1409_SERIAL_OUTPUT,
  355. .gpio = S5H1409_GPIO_OFF,
  356. .inversion = S5H1409_INVERSION_OFF,
  357. .status_mode = S5H1409_DEMODLOCKING,
  358. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  359. };
  360. static struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
  361. .i2c_address = 0x64,
  362. .if_khz = 5380,
  363. .tuner_callback = cx88_tuner_callback,
  364. };
  365. static struct zl10353_config cx88_geniatech_x8000_mt = {
  366. .demod_address = (0x1e >> 1),
  367. .no_tuner = 1,
  368. };
  369. static int dvb_register(struct cx8802_dev *dev)
  370. {
  371. int attach_xc3028 = 0;
  372. /* init struct videobuf_dvb */
  373. dev->dvb.name = dev->core->name;
  374. dev->ts_gen_cntrl = 0x0c;
  375. /* init frontend */
  376. switch (dev->core->boardnr) {
  377. case CX88_BOARD_HAUPPAUGE_DVB_T1:
  378. dev->dvb.frontend = dvb_attach(cx22702_attach,
  379. &connexant_refboard_config,
  380. &dev->core->i2c_adap);
  381. if (dev->dvb.frontend != NULL) {
  382. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  383. &dev->core->i2c_adap,
  384. DVB_PLL_THOMSON_DTT759X);
  385. }
  386. break;
  387. case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
  388. case CX88_BOARD_CONEXANT_DVB_T1:
  389. case CX88_BOARD_KWORLD_DVB_T_CX22702:
  390. case CX88_BOARD_WINFAST_DTV1000:
  391. dev->dvb.frontend = dvb_attach(cx22702_attach,
  392. &connexant_refboard_config,
  393. &dev->core->i2c_adap);
  394. if (dev->dvb.frontend != NULL) {
  395. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  396. &dev->core->i2c_adap,
  397. DVB_PLL_THOMSON_DTT7579);
  398. }
  399. break;
  400. case CX88_BOARD_WINFAST_DTV2000H:
  401. case CX88_BOARD_HAUPPAUGE_HVR1100:
  402. case CX88_BOARD_HAUPPAUGE_HVR1100LP:
  403. case CX88_BOARD_HAUPPAUGE_HVR1300:
  404. case CX88_BOARD_HAUPPAUGE_HVR3000:
  405. dev->dvb.frontend = dvb_attach(cx22702_attach,
  406. &hauppauge_hvr_config,
  407. &dev->core->i2c_adap);
  408. if (dev->dvb.frontend != NULL) {
  409. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  410. &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
  411. }
  412. break;
  413. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
  414. dev->dvb.frontend = dvb_attach(mt352_attach,
  415. &dvico_fusionhdtv,
  416. &dev->core->i2c_adap);
  417. if (dev->dvb.frontend != NULL) {
  418. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  419. NULL, DVB_PLL_THOMSON_DTT7579);
  420. break;
  421. }
  422. /* ZL10353 replaces MT352 on later cards */
  423. dev->dvb.frontend = dvb_attach(zl10353_attach,
  424. &dvico_fusionhdtv_plus_v1_1,
  425. &dev->core->i2c_adap);
  426. if (dev->dvb.frontend != NULL) {
  427. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  428. NULL, DVB_PLL_THOMSON_DTT7579);
  429. }
  430. break;
  431. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
  432. /* The tin box says DEE1601, but it seems to be DTT7579
  433. * compatible, with a slightly different MT352 AGC gain. */
  434. dev->dvb.frontend = dvb_attach(mt352_attach,
  435. &dvico_fusionhdtv_dual,
  436. &dev->core->i2c_adap);
  437. if (dev->dvb.frontend != NULL) {
  438. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  439. NULL, DVB_PLL_THOMSON_DTT7579);
  440. break;
  441. }
  442. /* ZL10353 replaces MT352 on later cards */
  443. dev->dvb.frontend = dvb_attach(zl10353_attach,
  444. &dvico_fusionhdtv_plus_v1_1,
  445. &dev->core->i2c_adap);
  446. if (dev->dvb.frontend != NULL) {
  447. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  448. NULL, DVB_PLL_THOMSON_DTT7579);
  449. }
  450. break;
  451. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
  452. dev->dvb.frontend = dvb_attach(mt352_attach,
  453. &dvico_fusionhdtv,
  454. &dev->core->i2c_adap);
  455. if (dev->dvb.frontend != NULL) {
  456. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  457. NULL, DVB_PLL_LG_Z201);
  458. }
  459. break;
  460. case CX88_BOARD_KWORLD_DVB_T:
  461. case CX88_BOARD_DNTV_LIVE_DVB_T:
  462. case CX88_BOARD_ADSTECH_DVB_T_PCI:
  463. dev->dvb.frontend = dvb_attach(mt352_attach,
  464. &dntv_live_dvbt_config,
  465. &dev->core->i2c_adap);
  466. if (dev->dvb.frontend != NULL) {
  467. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  468. NULL, DVB_PLL_UNKNOWN_1);
  469. }
  470. break;
  471. case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
  472. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  473. /* MT352 is on a secondary I2C bus made from some GPIO lines */
  474. dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
  475. &dev->vp3054->adap);
  476. if (dev->dvb.frontend != NULL) {
  477. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  478. &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
  479. }
  480. #else
  481. printk(KERN_ERR "%s/2: built without vp3054 support\n", dev->core->name);
  482. #endif
  483. break;
  484. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
  485. dev->dvb.frontend = dvb_attach(zl10353_attach,
  486. &dvico_fusionhdtv_hybrid,
  487. &dev->core->i2c_adap);
  488. if (dev->dvb.frontend != NULL) {
  489. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  490. &dev->core->i2c_adap,
  491. DVB_PLL_THOMSON_FE6600);
  492. }
  493. break;
  494. case CX88_BOARD_PCHDTV_HD3000:
  495. dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
  496. &dev->core->i2c_adap);
  497. if (dev->dvb.frontend != NULL) {
  498. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  499. &dev->core->i2c_adap,
  500. DVB_PLL_THOMSON_DTT761X);
  501. }
  502. break;
  503. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  504. dev->ts_gen_cntrl = 0x08;
  505. {
  506. /* Do a hardware reset of chip before using it. */
  507. struct cx88_core *core = dev->core;
  508. cx_clear(MO_GP0_IO, 1);
  509. mdelay(100);
  510. cx_set(MO_GP0_IO, 1);
  511. mdelay(200);
  512. /* Select RF connector callback */
  513. fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
  514. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  515. &fusionhdtv_3_gold,
  516. &dev->core->i2c_adap);
  517. if (dev->dvb.frontend != NULL) {
  518. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  519. &dev->core->i2c_adap,
  520. DVB_PLL_MICROTUNE_4042);
  521. }
  522. }
  523. break;
  524. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  525. dev->ts_gen_cntrl = 0x08;
  526. {
  527. /* Do a hardware reset of chip before using it. */
  528. struct cx88_core *core = dev->core;
  529. cx_clear(MO_GP0_IO, 1);
  530. mdelay(100);
  531. cx_set(MO_GP0_IO, 9);
  532. mdelay(200);
  533. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  534. &fusionhdtv_3_gold,
  535. &dev->core->i2c_adap);
  536. if (dev->dvb.frontend != NULL) {
  537. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  538. &dev->core->i2c_adap,
  539. DVB_PLL_THOMSON_DTT761X);
  540. }
  541. }
  542. break;
  543. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  544. dev->ts_gen_cntrl = 0x08;
  545. {
  546. /* Do a hardware reset of chip before using it. */
  547. struct cx88_core *core = dev->core;
  548. cx_clear(MO_GP0_IO, 1);
  549. mdelay(100);
  550. cx_set(MO_GP0_IO, 1);
  551. mdelay(200);
  552. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  553. &fusionhdtv_5_gold,
  554. &dev->core->i2c_adap);
  555. if (dev->dvb.frontend != NULL) {
  556. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  557. &dev->core->i2c_adap,
  558. DVB_PLL_LG_TDVS_H06XF);
  559. }
  560. }
  561. break;
  562. case CX88_BOARD_PCHDTV_HD5500:
  563. dev->ts_gen_cntrl = 0x08;
  564. {
  565. /* Do a hardware reset of chip before using it. */
  566. struct cx88_core *core = dev->core;
  567. cx_clear(MO_GP0_IO, 1);
  568. mdelay(100);
  569. cx_set(MO_GP0_IO, 1);
  570. mdelay(200);
  571. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  572. &pchdtv_hd5500,
  573. &dev->core->i2c_adap);
  574. if (dev->dvb.frontend != NULL) {
  575. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  576. &dev->core->i2c_adap,
  577. DVB_PLL_LG_TDVS_H06XF);
  578. }
  579. }
  580. break;
  581. case CX88_BOARD_ATI_HDTVWONDER:
  582. dev->dvb.frontend = dvb_attach(nxt200x_attach,
  583. &ati_hdtvwonder,
  584. &dev->core->i2c_adap);
  585. if (dev->dvb.frontend != NULL) {
  586. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  587. NULL, DVB_PLL_TUV1236D);
  588. }
  589. break;
  590. case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
  591. case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
  592. dev->dvb.frontend = dvb_attach(cx24123_attach,
  593. &hauppauge_novas_config,
  594. &dev->core->i2c_adap);
  595. if (dev->dvb.frontend) {
  596. dvb_attach(isl6421_attach, dev->dvb.frontend,
  597. &dev->core->i2c_adap, 0x08, 0x00, 0x00);
  598. }
  599. break;
  600. case CX88_BOARD_KWORLD_DVBS_100:
  601. dev->dvb.frontend = dvb_attach(cx24123_attach,
  602. &kworld_dvbs_100_config,
  603. &dev->core->i2c_adap);
  604. if (dev->dvb.frontend) {
  605. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  606. dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
  607. }
  608. break;
  609. case CX88_BOARD_GENIATECH_DVBS:
  610. dev->dvb.frontend = dvb_attach(cx24123_attach,
  611. &geniatech_dvbs_config,
  612. &dev->core->i2c_adap);
  613. if (dev->dvb.frontend) {
  614. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  615. dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
  616. }
  617. break;
  618. case CX88_BOARD_PINNACLE_PCTV_HD_800i:
  619. dev->dvb.frontend = dvb_attach(s5h1409_attach,
  620. &pinnacle_pctv_hd_800i_config,
  621. &dev->core->i2c_adap);
  622. if (dev->dvb.frontend != NULL) {
  623. /* tuner_config.video_dev must point to
  624. * i2c_adap.algo_data
  625. */
  626. pinnacle_pctv_hd_800i_tuner_config.priv =
  627. dev->core->i2c_adap.algo_data;
  628. dvb_attach(xc5000_attach, dev->dvb.frontend,
  629. &dev->core->i2c_adap,
  630. &pinnacle_pctv_hd_800i_tuner_config);
  631. }
  632. break;
  633. case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
  634. dev->dvb.frontend = dvb_attach(s5h1409_attach,
  635. &dvico_hdtv5_pci_nano_config,
  636. &dev->core->i2c_adap);
  637. if (dev->dvb.frontend != NULL) {
  638. struct dvb_frontend *fe;
  639. struct xc2028_config cfg = {
  640. .i2c_adap = &dev->core->i2c_adap,
  641. .i2c_addr = 0x61,
  642. .video_dev = dev->core,
  643. .callback = cx88_xc3028_callback,
  644. };
  645. static struct xc2028_ctrl ctl = {
  646. .fname = "xc3028-v27.fw",
  647. .max_len = 64,
  648. .scode_table = OREN538,
  649. };
  650. fe = dvb_attach(xc2028_attach,
  651. dev->dvb.frontend, &cfg);
  652. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  653. fe->ops.tuner_ops.set_config(fe, &ctl);
  654. }
  655. break;
  656. case CX88_BOARD_PINNACLE_HYBRID_PCTV:
  657. dev->dvb.frontend = dvb_attach(zl10353_attach,
  658. &cx88_geniatech_x8000_mt,
  659. &dev->core->i2c_adap);
  660. attach_xc3028 = 1;
  661. break;
  662. case CX88_BOARD_GENIATECH_X8000_MT:
  663. dev->ts_gen_cntrl = 0x00;
  664. dev->dvb.frontend = dvb_attach(zl10353_attach,
  665. &cx88_geniatech_x8000_mt,
  666. &dev->core->i2c_adap);
  667. attach_xc3028 = 1;
  668. break;
  669. default:
  670. printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
  671. dev->core->name);
  672. break;
  673. }
  674. if (NULL == dev->dvb.frontend) {
  675. printk(KERN_ERR
  676. "%s/2: frontend initialization failed\n",
  677. dev->core->name);
  678. return -1;
  679. }
  680. if (attach_xc3028) {
  681. struct dvb_frontend *fe;
  682. struct xc2028_config cfg = {
  683. .i2c_adap = &dev->core->i2c_adap,
  684. .i2c_addr = 0x61,
  685. .video_dev = dev->core,
  686. };
  687. fe = dvb_attach(xc2028_attach, dev->dvb.frontend, &cfg);
  688. if (!fe) {
  689. printk(KERN_ERR "%s/2: xc3028 attach failed\n",
  690. dev->core->name);
  691. dvb_frontend_detach(dev->dvb.frontend);
  692. dvb_unregister_frontend(dev->dvb.frontend);
  693. dev->dvb.frontend = NULL;
  694. return -1;
  695. }
  696. }
  697. /* Ensure all frontends negotiate bus access */
  698. dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  699. /* Put the analog decoder in standby to keep it quiet */
  700. cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
  701. /* register everything */
  702. return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
  703. }
  704. /* ----------------------------------------------------------- */
  705. /* CX8802 MPEG -> mini driver - We have been given the hardware */
  706. static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
  707. {
  708. struct cx88_core *core = drv->core;
  709. int err = 0;
  710. dprintk( 1, "%s\n", __FUNCTION__);
  711. switch (core->boardnr) {
  712. case CX88_BOARD_HAUPPAUGE_HVR1300:
  713. /* We arrive here with either the cx23416 or the cx22702
  714. * on the bus. Take the bus from the cx23416 and enable the
  715. * cx22702 demod
  716. */
  717. cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */
  718. cx_clear(MO_GP0_IO, 0x00000004);
  719. udelay(1000);
  720. break;
  721. default:
  722. err = -ENODEV;
  723. }
  724. return err;
  725. }
  726. /* CX8802 MPEG -> mini driver - We no longer have the hardware */
  727. static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
  728. {
  729. struct cx88_core *core = drv->core;
  730. int err = 0;
  731. dprintk( 1, "%s\n", __FUNCTION__);
  732. switch (core->boardnr) {
  733. case CX88_BOARD_HAUPPAUGE_HVR1300:
  734. /* Do Nothing, leave the cx22702 on the bus. */
  735. break;
  736. default:
  737. err = -ENODEV;
  738. }
  739. return err;
  740. }
  741. static int cx8802_dvb_probe(struct cx8802_driver *drv)
  742. {
  743. struct cx88_core *core = drv->core;
  744. struct cx8802_dev *dev = drv->core->dvbdev;
  745. int err;
  746. dprintk( 1, "%s\n", __FUNCTION__);
  747. dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
  748. core->boardnr,
  749. core->name,
  750. core->pci_bus,
  751. core->pci_slot);
  752. err = -ENODEV;
  753. if (!(core->board.mpeg & CX88_MPEG_DVB))
  754. goto fail_core;
  755. /* If vp3054 isn't enabled, a stub will just return 0 */
  756. err = vp3054_i2c_probe(dev);
  757. if (0 != err)
  758. goto fail_core;
  759. /* dvb stuff */
  760. printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name);
  761. videobuf_queue_sg_init(&dev->dvb.dvbq, &dvb_qops,
  762. &dev->pci->dev, &dev->slock,
  763. V4L2_BUF_TYPE_VIDEO_CAPTURE,
  764. V4L2_FIELD_TOP,
  765. sizeof(struct cx88_buffer),
  766. dev);
  767. err = dvb_register(dev);
  768. if (err != 0)
  769. printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n",
  770. core->name, err);
  771. fail_core:
  772. return err;
  773. }
  774. static int cx8802_dvb_remove(struct cx8802_driver *drv)
  775. {
  776. struct cx8802_dev *dev = drv->core->dvbdev;
  777. /* dvb */
  778. videobuf_dvb_unregister(&dev->dvb);
  779. vp3054_i2c_remove(dev);
  780. return 0;
  781. }
  782. static struct cx8802_driver cx8802_dvb_driver = {
  783. .type_id = CX88_MPEG_DVB,
  784. .hw_access = CX8802_DRVCTL_SHARED,
  785. .probe = cx8802_dvb_probe,
  786. .remove = cx8802_dvb_remove,
  787. .advise_acquire = cx8802_dvb_advise_acquire,
  788. .advise_release = cx8802_dvb_advise_release,
  789. };
  790. static int dvb_init(void)
  791. {
  792. printk(KERN_INFO "cx88/2: cx2388x dvb driver version %d.%d.%d loaded\n",
  793. (CX88_VERSION_CODE >> 16) & 0xff,
  794. (CX88_VERSION_CODE >> 8) & 0xff,
  795. CX88_VERSION_CODE & 0xff);
  796. #ifdef SNAPSHOT
  797. printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
  798. SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
  799. #endif
  800. return cx8802_register_driver(&cx8802_dvb_driver);
  801. }
  802. static void dvb_fini(void)
  803. {
  804. cx8802_unregister_driver(&cx8802_dvb_driver);
  805. }
  806. module_init(dvb_init);
  807. module_exit(dvb_fini);
  808. /*
  809. * Local variables:
  810. * c-basic-offset: 8
  811. * compile-command: "make DVB=1"
  812. * End:
  813. */