stex.c 34 KB

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  1. /*
  2. * SuperTrak EX Series Storage Controller driver for Linux
  3. *
  4. * Copyright (C) 2005, 2006 Promise Technology Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Written By:
  12. * Ed Lin <promise_linux@promise.com>
  13. *
  14. * Version: 3.0.0.1
  15. *
  16. */
  17. #include <linux/init.h>
  18. #include <linux/errno.h>
  19. #include <linux/kernel.h>
  20. #include <linux/delay.h>
  21. #include <linux/sched.h>
  22. #include <linux/time.h>
  23. #include <linux/pci.h>
  24. #include <linux/blkdev.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/types.h>
  27. #include <linux/module.h>
  28. #include <linux/spinlock.h>
  29. #include <asm/io.h>
  30. #include <asm/irq.h>
  31. #include <asm/byteorder.h>
  32. #include <scsi/scsi.h>
  33. #include <scsi/scsi_device.h>
  34. #include <scsi/scsi_cmnd.h>
  35. #include <scsi/scsi_host.h>
  36. #include <scsi/scsi_tcq.h>
  37. #define DRV_NAME "stex"
  38. #define ST_DRIVER_VERSION "3.0.0.1"
  39. #define ST_VER_MAJOR 3
  40. #define ST_VER_MINOR 0
  41. #define ST_OEM 0
  42. #define ST_BUILD_VER 1
  43. enum {
  44. /* MU register offset */
  45. IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  46. IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  47. OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  48. OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  49. IDBL = 0x20, /* MU_INBOUND_DOORBELL */
  50. IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  51. IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  52. ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
  53. OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  54. OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  55. /* MU register value */
  56. MU_INBOUND_DOORBELL_HANDSHAKE = 1,
  57. MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
  58. MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
  59. MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
  60. MU_INBOUND_DOORBELL_RESET = 16,
  61. MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
  62. MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
  63. MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
  64. MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
  65. MU_OUTBOUND_DOORBELL_HASEVENT = 16,
  66. /* MU status code */
  67. MU_STATE_STARTING = 1,
  68. MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
  69. MU_STATE_SEND_HANDSHAKE_FRAME = 3,
  70. MU_STATE_STARTED = 4,
  71. MU_STATE_RESETTING = 5,
  72. MU_MAX_DELAY_TIME = 240000,
  73. MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
  74. MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
  75. HMU_PARTNER_TYPE = 2,
  76. /* firmware returned values */
  77. SRB_STATUS_SUCCESS = 0x01,
  78. SRB_STATUS_ERROR = 0x04,
  79. SRB_STATUS_BUSY = 0x05,
  80. SRB_STATUS_INVALID_REQUEST = 0x06,
  81. SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
  82. SRB_SEE_SENSE = 0x80,
  83. /* task attribute */
  84. TASK_ATTRIBUTE_SIMPLE = 0x0,
  85. TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
  86. TASK_ATTRIBUTE_ORDERED = 0x2,
  87. TASK_ATTRIBUTE_ACA = 0x4,
  88. /* request count, etc. */
  89. MU_MAX_REQUEST = 32,
  90. /* one message wasted, use MU_MAX_REQUEST+1
  91. to handle MU_MAX_REQUEST messages */
  92. MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
  93. MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
  94. STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
  95. REQ_VARIABLE_LEN = 1024,
  96. STATUS_VAR_LEN = 128,
  97. ST_CAN_QUEUE = MU_MAX_REQUEST,
  98. ST_CMD_PER_LUN = MU_MAX_REQUEST,
  99. ST_MAX_SG = 32,
  100. /* sg flags */
  101. SG_CF_EOT = 0x80, /* end of table */
  102. SG_CF_64B = 0x40, /* 64 bit item */
  103. SG_CF_HOST = 0x20, /* sg in host memory */
  104. ST_MAX_ARRAY_SUPPORTED = 16,
  105. ST_MAX_TARGET_NUM = (ST_MAX_ARRAY_SUPPORTED+1),
  106. ST_MAX_LUN_PER_TARGET = 16,
  107. st_shasta = 0,
  108. st_vsc = 1,
  109. st_vsc1 = 2,
  110. st_yosemite = 3,
  111. PASSTHRU_REQ_TYPE = 0x00000001,
  112. PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
  113. ST_INTERNAL_TIMEOUT = 30,
  114. ST_TO_CMD = 0,
  115. ST_FROM_CMD = 1,
  116. /* vendor specific commands of Promise */
  117. MGT_CMD = 0xd8,
  118. SINBAND_MGT_CMD = 0xd9,
  119. ARRAY_CMD = 0xe0,
  120. CONTROLLER_CMD = 0xe1,
  121. DEBUGGING_CMD = 0xe2,
  122. PASSTHRU_CMD = 0xe3,
  123. PASSTHRU_GET_ADAPTER = 0x05,
  124. PASSTHRU_GET_DRVVER = 0x10,
  125. CTLR_CONFIG_CMD = 0x03,
  126. CTLR_SHUTDOWN = 0x0d,
  127. CTLR_POWER_STATE_CHANGE = 0x0e,
  128. CTLR_POWER_SAVING = 0x01,
  129. PASSTHRU_SIGNATURE = 0x4e415041,
  130. MGT_CMD_SIGNATURE = 0xba,
  131. INQUIRY_EVPD = 0x01,
  132. ST_ADDITIONAL_MEM = 0x200000,
  133. };
  134. /* SCSI inquiry data */
  135. typedef struct st_inq {
  136. u8 DeviceType :5;
  137. u8 DeviceTypeQualifier :3;
  138. u8 DeviceTypeModifier :7;
  139. u8 RemovableMedia :1;
  140. u8 Versions;
  141. u8 ResponseDataFormat :4;
  142. u8 HiSupport :1;
  143. u8 NormACA :1;
  144. u8 ReservedBit :1;
  145. u8 AERC :1;
  146. u8 AdditionalLength;
  147. u8 Reserved[2];
  148. u8 SoftReset :1;
  149. u8 CommandQueue :1;
  150. u8 Reserved2 :1;
  151. u8 LinkedCommands :1;
  152. u8 Synchronous :1;
  153. u8 Wide16Bit :1;
  154. u8 Wide32Bit :1;
  155. u8 RelativeAddressing :1;
  156. u8 VendorId[8];
  157. u8 ProductId[16];
  158. u8 ProductRevisionLevel[4];
  159. u8 VendorSpecific[20];
  160. u8 Reserved3[40];
  161. } ST_INQ;
  162. struct st_sgitem {
  163. u8 ctrl; /* SG_CF_xxx */
  164. u8 reserved[3];
  165. __le32 count;
  166. __le32 addr;
  167. __le32 addr_hi;
  168. };
  169. struct st_sgtable {
  170. __le16 sg_count;
  171. __le16 max_sg_count;
  172. __le32 sz_in_byte;
  173. struct st_sgitem table[ST_MAX_SG];
  174. };
  175. struct handshake_frame {
  176. __le32 rb_phy; /* request payload queue physical address */
  177. __le32 rb_phy_hi;
  178. __le16 req_sz; /* size of each request payload */
  179. __le16 req_cnt; /* count of reqs the buffer can hold */
  180. __le16 status_sz; /* size of each status payload */
  181. __le16 status_cnt; /* count of status the buffer can hold */
  182. __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
  183. __le32 hosttime_hi;
  184. u8 partner_type; /* who sends this frame */
  185. u8 reserved0[7];
  186. __le32 partner_ver_major;
  187. __le32 partner_ver_minor;
  188. __le32 partner_ver_oem;
  189. __le32 partner_ver_build;
  190. __le32 extra_offset; /* NEW */
  191. __le32 extra_size; /* NEW */
  192. u32 reserved1[2];
  193. };
  194. struct req_msg {
  195. __le16 tag;
  196. u8 lun;
  197. u8 target;
  198. u8 task_attr;
  199. u8 task_manage;
  200. u8 prd_entry;
  201. u8 payload_sz; /* payload size in 4-byte, not used */
  202. u8 cdb[STEX_CDB_LENGTH];
  203. u8 variable[REQ_VARIABLE_LEN];
  204. };
  205. struct status_msg {
  206. __le16 tag;
  207. u8 lun;
  208. u8 target;
  209. u8 srb_status;
  210. u8 scsi_status;
  211. u8 reserved;
  212. u8 payload_sz; /* payload size in 4-byte */
  213. u8 variable[STATUS_VAR_LEN];
  214. };
  215. struct ver_info {
  216. u32 major;
  217. u32 minor;
  218. u32 oem;
  219. u32 build;
  220. u32 reserved[2];
  221. };
  222. struct st_frame {
  223. u32 base[6];
  224. u32 rom_addr;
  225. struct ver_info drv_ver;
  226. struct ver_info bios_ver;
  227. u32 bus;
  228. u32 slot;
  229. u32 irq_level;
  230. u32 irq_vec;
  231. u32 id;
  232. u32 subid;
  233. u32 dimm_size;
  234. u8 dimm_type;
  235. u8 reserved[3];
  236. u32 channel;
  237. u32 reserved1;
  238. };
  239. struct st_drvver {
  240. u32 major;
  241. u32 minor;
  242. u32 oem;
  243. u32 build;
  244. u32 signature[2];
  245. u8 console_id;
  246. u8 host_no;
  247. u8 reserved0[2];
  248. u32 reserved[3];
  249. };
  250. #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
  251. #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
  252. #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
  253. #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
  254. #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
  255. struct st_ccb {
  256. struct req_msg *req;
  257. struct scsi_cmnd *cmd;
  258. void *sense_buffer;
  259. unsigned int sense_bufflen;
  260. int sg_count;
  261. u32 req_type;
  262. u8 srb_status;
  263. u8 scsi_status;
  264. };
  265. struct st_hba {
  266. void __iomem *mmio_base; /* iomapped PCI memory space */
  267. void *dma_mem;
  268. dma_addr_t dma_handle;
  269. size_t dma_size;
  270. struct Scsi_Host *host;
  271. struct pci_dev *pdev;
  272. u32 req_head;
  273. u32 req_tail;
  274. u32 status_head;
  275. u32 status_tail;
  276. struct status_msg *status_buffer;
  277. void *copy_buffer; /* temp buffer for driver-handled commands */
  278. struct st_ccb ccb[MU_MAX_REQUEST];
  279. struct st_ccb *wait_ccb;
  280. wait_queue_head_t waitq;
  281. unsigned int mu_status;
  282. int out_req_cnt;
  283. unsigned int cardtype;
  284. };
  285. static const char console_inq_page[] =
  286. {
  287. 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
  288. 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
  289. 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
  290. 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
  291. 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
  292. 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
  293. 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
  294. 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
  295. };
  296. MODULE_AUTHOR("Ed Lin");
  297. MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
  298. MODULE_LICENSE("GPL");
  299. MODULE_VERSION(ST_DRIVER_VERSION);
  300. static void stex_gettime(__le32 *time)
  301. {
  302. struct timeval tv;
  303. do_gettimeofday(&tv);
  304. *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
  305. *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
  306. }
  307. static struct status_msg *stex_get_status(struct st_hba *hba)
  308. {
  309. struct status_msg *status =
  310. hba->status_buffer + hba->status_tail;
  311. ++hba->status_tail;
  312. hba->status_tail %= MU_STATUS_COUNT;
  313. return status;
  314. }
  315. static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
  316. {
  317. cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
  318. cmd->sense_buffer[0] = 0x70; /* fixed format, current */
  319. cmd->sense_buffer[2] = sk;
  320. cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
  321. cmd->sense_buffer[12] = asc;
  322. cmd->sense_buffer[13] = ascq;
  323. }
  324. static void stex_invalid_field(struct scsi_cmnd *cmd,
  325. void (*done)(struct scsi_cmnd *))
  326. {
  327. /* "Invalid field in cbd" */
  328. stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
  329. done(cmd);
  330. }
  331. static struct req_msg *stex_alloc_req(struct st_hba *hba)
  332. {
  333. struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
  334. hba->req_head;
  335. ++hba->req_head;
  336. hba->req_head %= MU_REQ_COUNT;
  337. return req;
  338. }
  339. static int stex_map_sg(struct st_hba *hba,
  340. struct req_msg *req, struct st_ccb *ccb)
  341. {
  342. struct pci_dev *pdev = hba->pdev;
  343. struct scsi_cmnd *cmd;
  344. dma_addr_t dma_handle;
  345. struct scatterlist *src;
  346. struct st_sgtable *dst;
  347. int i;
  348. cmd = ccb->cmd;
  349. dst = (struct st_sgtable *)req->variable;
  350. dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
  351. dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
  352. if (cmd->use_sg) {
  353. int n_elem;
  354. src = (struct scatterlist *) cmd->request_buffer;
  355. n_elem = pci_map_sg(pdev, src,
  356. cmd->use_sg, cmd->sc_data_direction);
  357. if (n_elem <= 0)
  358. return -EIO;
  359. ccb->sg_count = n_elem;
  360. dst->sg_count = cpu_to_le16((u16)n_elem);
  361. for (i = 0; i < n_elem; i++, src++) {
  362. dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
  363. dst->table[i].addr =
  364. cpu_to_le32(sg_dma_address(src) & 0xffffffff);
  365. dst->table[i].addr_hi =
  366. cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
  367. dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
  368. }
  369. dst->table[--i].ctrl |= SG_CF_EOT;
  370. return 0;
  371. }
  372. dma_handle = pci_map_single(pdev, cmd->request_buffer,
  373. cmd->request_bufflen, cmd->sc_data_direction);
  374. cmd->SCp.dma_handle = dma_handle;
  375. ccb->sg_count = 1;
  376. dst->sg_count = cpu_to_le16(1);
  377. dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
  378. dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
  379. dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
  380. dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
  381. return 0;
  382. }
  383. static void stex_internal_copy(struct scsi_cmnd *cmd,
  384. const void *src, size_t *count, int sg_count, int direction)
  385. {
  386. size_t lcount;
  387. size_t len;
  388. void *s, *d, *base = NULL;
  389. if (*count > cmd->request_bufflen)
  390. *count = cmd->request_bufflen;
  391. lcount = *count;
  392. while (lcount) {
  393. len = lcount;
  394. s = (void *)src;
  395. if (cmd->use_sg) {
  396. size_t offset = *count - lcount;
  397. s += offset;
  398. base = scsi_kmap_atomic_sg(cmd->request_buffer,
  399. sg_count, &offset, &len);
  400. if (base == NULL) {
  401. *count -= lcount;
  402. return;
  403. }
  404. d = base + offset;
  405. } else
  406. d = cmd->request_buffer;
  407. if (direction == ST_TO_CMD)
  408. memcpy(d, s, len);
  409. else
  410. memcpy(s, d, len);
  411. lcount -= len;
  412. if (cmd->use_sg)
  413. scsi_kunmap_atomic_sg(base);
  414. }
  415. }
  416. static int stex_direct_copy(struct scsi_cmnd *cmd,
  417. const void *src, size_t count)
  418. {
  419. struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  420. size_t cp_len = count;
  421. int n_elem = 0;
  422. if (cmd->use_sg) {
  423. n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
  424. cmd->use_sg, cmd->sc_data_direction);
  425. if (n_elem <= 0)
  426. return 0;
  427. }
  428. stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
  429. if (cmd->use_sg)
  430. pci_unmap_sg(hba->pdev, cmd->request_buffer,
  431. cmd->use_sg, cmd->sc_data_direction);
  432. return cp_len == count;
  433. }
  434. static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
  435. {
  436. struct st_frame *p;
  437. size_t count = sizeof(struct st_frame);
  438. p = hba->copy_buffer;
  439. stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
  440. memset(p->base, 0, sizeof(u32)*6);
  441. *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
  442. p->rom_addr = 0;
  443. p->drv_ver.major = ST_VER_MAJOR;
  444. p->drv_ver.minor = ST_VER_MINOR;
  445. p->drv_ver.oem = ST_OEM;
  446. p->drv_ver.build = ST_BUILD_VER;
  447. p->bus = hba->pdev->bus->number;
  448. p->slot = hba->pdev->devfn;
  449. p->irq_level = 0;
  450. p->irq_vec = hba->pdev->irq;
  451. p->id = hba->pdev->vendor << 16 | hba->pdev->device;
  452. p->subid =
  453. hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
  454. stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
  455. }
  456. static void
  457. stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
  458. {
  459. req->tag = cpu_to_le16(tag);
  460. req->task_attr = TASK_ATTRIBUTE_SIMPLE;
  461. req->task_manage = 0; /* not supported yet */
  462. hba->ccb[tag].req = req;
  463. hba->out_req_cnt++;
  464. writel(hba->req_head, hba->mmio_base + IMR0);
  465. writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
  466. readl(hba->mmio_base + IDBL); /* flush */
  467. }
  468. static int
  469. stex_slave_alloc(struct scsi_device *sdev)
  470. {
  471. /* Cheat: usually extracted from Inquiry data */
  472. sdev->tagged_supported = 1;
  473. scsi_activate_tcq(sdev, sdev->host->can_queue);
  474. return 0;
  475. }
  476. static int
  477. stex_slave_config(struct scsi_device *sdev)
  478. {
  479. sdev->use_10_for_rw = 1;
  480. sdev->use_10_for_ms = 1;
  481. sdev->timeout = 60 * HZ;
  482. sdev->tagged_supported = 1;
  483. return 0;
  484. }
  485. static void
  486. stex_slave_destroy(struct scsi_device *sdev)
  487. {
  488. scsi_deactivate_tcq(sdev, 1);
  489. }
  490. static int
  491. stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
  492. {
  493. struct st_hba *hba;
  494. struct Scsi_Host *host;
  495. unsigned int id,lun;
  496. struct req_msg *req;
  497. u16 tag;
  498. host = cmd->device->host;
  499. id = cmd->device->id;
  500. lun = cmd->device->channel; /* firmware lun issue work around */
  501. hba = (struct st_hba *) &host->hostdata[0];
  502. switch (cmd->cmnd[0]) {
  503. case MODE_SENSE_10:
  504. {
  505. static char ms10_caching_page[12] =
  506. { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
  507. unsigned char page;
  508. page = cmd->cmnd[2] & 0x3f;
  509. if (page == 0x8 || page == 0x3f) {
  510. stex_direct_copy(cmd, ms10_caching_page,
  511. sizeof(ms10_caching_page));
  512. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  513. done(cmd);
  514. } else
  515. stex_invalid_field(cmd, done);
  516. return 0;
  517. }
  518. case INQUIRY:
  519. if (id != ST_MAX_ARRAY_SUPPORTED)
  520. break;
  521. if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
  522. stex_direct_copy(cmd, console_inq_page,
  523. sizeof(console_inq_page));
  524. cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
  525. done(cmd);
  526. } else
  527. stex_invalid_field(cmd, done);
  528. return 0;
  529. case PASSTHRU_CMD:
  530. if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
  531. struct st_drvver ver;
  532. ver.major = ST_VER_MAJOR;
  533. ver.minor = ST_VER_MINOR;
  534. ver.oem = ST_OEM;
  535. ver.build = ST_BUILD_VER;
  536. ver.signature[0] = PASSTHRU_SIGNATURE;
  537. ver.console_id = ST_MAX_ARRAY_SUPPORTED;
  538. ver.host_no = hba->host->host_no;
  539. cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
  540. DID_OK << 16 | COMMAND_COMPLETE << 8 :
  541. DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  542. done(cmd);
  543. return 0;
  544. }
  545. default:
  546. break;
  547. }
  548. cmd->scsi_done = done;
  549. tag = cmd->request->tag;
  550. if (unlikely(tag >= host->can_queue))
  551. return SCSI_MLQUEUE_HOST_BUSY;
  552. req = stex_alloc_req(hba);
  553. if (hba->cardtype == st_yosemite) {
  554. req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id;
  555. req->target = 0;
  556. } else {
  557. req->lun = lun;
  558. req->target = id;
  559. }
  560. /* cdb */
  561. memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
  562. hba->ccb[tag].cmd = cmd;
  563. hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  564. hba->ccb[tag].sense_buffer = cmd->sense_buffer;
  565. hba->ccb[tag].req_type = 0;
  566. if (cmd->sc_data_direction != DMA_NONE)
  567. stex_map_sg(hba, req, &hba->ccb[tag]);
  568. stex_send_cmd(hba, req, tag);
  569. return 0;
  570. }
  571. static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
  572. {
  573. if (cmd->sc_data_direction != DMA_NONE) {
  574. if (cmd->use_sg)
  575. pci_unmap_sg(hba->pdev, cmd->request_buffer,
  576. cmd->use_sg, cmd->sc_data_direction);
  577. else
  578. pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
  579. cmd->request_bufflen, cmd->sc_data_direction);
  580. }
  581. }
  582. static void stex_scsi_done(struct st_ccb *ccb)
  583. {
  584. struct scsi_cmnd *cmd = ccb->cmd;
  585. int result;
  586. if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
  587. result = ccb->scsi_status;
  588. switch (ccb->scsi_status) {
  589. case SAM_STAT_GOOD:
  590. result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
  591. break;
  592. case SAM_STAT_CHECK_CONDITION:
  593. result |= DRIVER_SENSE << 24;
  594. break;
  595. case SAM_STAT_BUSY:
  596. result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  597. break;
  598. default:
  599. result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  600. break;
  601. }
  602. }
  603. else if (ccb->srb_status & SRB_SEE_SENSE)
  604. result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
  605. else switch (ccb->srb_status) {
  606. case SRB_STATUS_SELECTION_TIMEOUT:
  607. result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
  608. break;
  609. case SRB_STATUS_BUSY:
  610. result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
  611. break;
  612. case SRB_STATUS_INVALID_REQUEST:
  613. case SRB_STATUS_ERROR:
  614. default:
  615. result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
  616. break;
  617. }
  618. cmd->result = result;
  619. cmd->scsi_done(cmd);
  620. }
  621. static void stex_copy_data(struct st_ccb *ccb,
  622. struct status_msg *resp, unsigned int variable)
  623. {
  624. size_t count = variable;
  625. if (resp->scsi_status != SAM_STAT_GOOD) {
  626. if (ccb->sense_buffer != NULL)
  627. memcpy(ccb->sense_buffer, resp->variable,
  628. min(variable, ccb->sense_bufflen));
  629. return;
  630. }
  631. if (ccb->cmd == NULL)
  632. return;
  633. stex_internal_copy(ccb->cmd,
  634. resp->variable, &count, ccb->sg_count, ST_TO_CMD);
  635. }
  636. static void stex_ys_commands(struct st_hba *hba,
  637. struct st_ccb *ccb, struct status_msg *resp)
  638. {
  639. size_t count;
  640. if (ccb->cmd->cmnd[0] == MGT_CMD &&
  641. resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
  642. ccb->cmd->request_bufflen =
  643. le32_to_cpu(*(__le32 *)&resp->variable[0]);
  644. return;
  645. }
  646. if (resp->srb_status != 0)
  647. return;
  648. /* determine inquiry command status by DeviceTypeQualifier */
  649. if (ccb->cmd->cmnd[0] == INQUIRY &&
  650. resp->scsi_status == SAM_STAT_GOOD) {
  651. ST_INQ *inq_data;
  652. count = STEX_EXTRA_SIZE;
  653. stex_internal_copy(ccb->cmd, hba->copy_buffer,
  654. &count, ccb->sg_count, ST_FROM_CMD);
  655. inq_data = (ST_INQ *)hba->copy_buffer;
  656. if (inq_data->DeviceTypeQualifier != 0)
  657. ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
  658. else
  659. ccb->srb_status = SRB_STATUS_SUCCESS;
  660. } else if (ccb->cmd->cmnd[0] == REPORT_LUNS) {
  661. u8 *report_lun_data = (u8 *)hba->copy_buffer;
  662. count = STEX_EXTRA_SIZE;
  663. stex_internal_copy(ccb->cmd, report_lun_data,
  664. &count, ccb->sg_count, ST_FROM_CMD);
  665. if (report_lun_data[2] || report_lun_data[3]) {
  666. report_lun_data[2] = 0x00;
  667. report_lun_data[3] = 0x08;
  668. stex_internal_copy(ccb->cmd, report_lun_data,
  669. &count, ccb->sg_count, ST_TO_CMD);
  670. }
  671. }
  672. }
  673. static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
  674. {
  675. void __iomem *base = hba->mmio_base;
  676. struct status_msg *resp;
  677. struct st_ccb *ccb;
  678. unsigned int size;
  679. u16 tag;
  680. if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
  681. return;
  682. /* status payloads */
  683. hba->status_head = readl(base + OMR1);
  684. if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
  685. printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
  686. pci_name(hba->pdev));
  687. return;
  688. }
  689. /*
  690. * it's not a valid status payload if:
  691. * 1. there are no pending requests(e.g. during init stage)
  692. * 2. there are some pending requests, but the controller is in
  693. * reset status, and its type is not st_yosemite
  694. * firmware of st_yosemite in reset status will return pending requests
  695. * to driver, so we allow it to pass
  696. */
  697. if (unlikely(hba->out_req_cnt <= 0 ||
  698. (hba->mu_status == MU_STATE_RESETTING &&
  699. hba->cardtype != st_yosemite))) {
  700. hba->status_tail = hba->status_head;
  701. goto update_status;
  702. }
  703. while (hba->status_tail != hba->status_head) {
  704. resp = stex_get_status(hba);
  705. tag = le16_to_cpu(resp->tag);
  706. if (unlikely(tag >= hba->host->can_queue)) {
  707. printk(KERN_WARNING DRV_NAME
  708. "(%s): invalid tag\n", pci_name(hba->pdev));
  709. continue;
  710. }
  711. ccb = &hba->ccb[tag];
  712. if (hba->wait_ccb == ccb)
  713. hba->wait_ccb = NULL;
  714. if (unlikely(ccb->req == NULL)) {
  715. printk(KERN_WARNING DRV_NAME
  716. "(%s): lagging req\n", pci_name(hba->pdev));
  717. hba->out_req_cnt--;
  718. continue;
  719. }
  720. size = resp->payload_sz * sizeof(u32); /* payload size */
  721. if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
  722. size > sizeof(*resp))) {
  723. printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
  724. pci_name(hba->pdev));
  725. } else {
  726. size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
  727. if (size)
  728. stex_copy_data(ccb, resp, size);
  729. }
  730. ccb->srb_status = resp->srb_status;
  731. ccb->scsi_status = resp->scsi_status;
  732. if (likely(ccb->cmd != NULL)) {
  733. if (hba->cardtype == st_yosemite)
  734. stex_ys_commands(hba, ccb, resp);
  735. if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
  736. ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
  737. stex_controller_info(hba, ccb);
  738. stex_unmap_sg(hba, ccb->cmd);
  739. stex_scsi_done(ccb);
  740. hba->out_req_cnt--;
  741. } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
  742. hba->out_req_cnt--;
  743. if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
  744. ccb->req_type = 0;
  745. continue;
  746. }
  747. ccb->req_type = 0;
  748. if (waitqueue_active(&hba->waitq))
  749. wake_up(&hba->waitq);
  750. }
  751. }
  752. update_status:
  753. writel(hba->status_head, base + IMR1);
  754. readl(base + IMR1); /* flush */
  755. }
  756. static irqreturn_t stex_intr(int irq, void *__hba)
  757. {
  758. struct st_hba *hba = __hba;
  759. void __iomem *base = hba->mmio_base;
  760. u32 data;
  761. unsigned long flags;
  762. int handled = 0;
  763. spin_lock_irqsave(hba->host->host_lock, flags);
  764. data = readl(base + ODBL);
  765. if (data && data != 0xffffffff) {
  766. /* clear the interrupt */
  767. writel(data, base + ODBL);
  768. readl(base + ODBL); /* flush */
  769. stex_mu_intr(hba, data);
  770. handled = 1;
  771. }
  772. spin_unlock_irqrestore(hba->host->host_lock, flags);
  773. return IRQ_RETVAL(handled);
  774. }
  775. static int stex_handshake(struct st_hba *hba)
  776. {
  777. void __iomem *base = hba->mmio_base;
  778. struct handshake_frame *h;
  779. dma_addr_t status_phys;
  780. u32 data;
  781. int i;
  782. if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
  783. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  784. readl(base + IDBL);
  785. for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
  786. && i < MU_MAX_DELAY_TIME; i++) {
  787. rmb();
  788. msleep(1);
  789. }
  790. if (i == MU_MAX_DELAY_TIME) {
  791. printk(KERN_ERR DRV_NAME
  792. "(%s): no handshake signature\n",
  793. pci_name(hba->pdev));
  794. return -1;
  795. }
  796. }
  797. udelay(10);
  798. data = readl(base + OMR1);
  799. if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
  800. data &= 0x0000ffff;
  801. if (hba->host->can_queue > data)
  802. hba->host->can_queue = data;
  803. }
  804. h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  805. h->rb_phy = cpu_to_le32(hba->dma_handle);
  806. h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
  807. h->req_sz = cpu_to_le16(sizeof(struct req_msg));
  808. h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
  809. h->status_sz = cpu_to_le16(sizeof(struct status_msg));
  810. h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
  811. stex_gettime(&h->hosttime);
  812. h->partner_type = HMU_PARTNER_TYPE;
  813. if (hba->dma_size > STEX_BUFFER_SIZE) {
  814. h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
  815. h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
  816. } else
  817. h->extra_offset = h->extra_size = 0;
  818. status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
  819. writel(status_phys, base + IMR0);
  820. readl(base + IMR0);
  821. writel((status_phys >> 16) >> 16, base + IMR1);
  822. readl(base + IMR1);
  823. writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
  824. readl(base + OMR0);
  825. writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
  826. readl(base + IDBL); /* flush */
  827. udelay(10);
  828. for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
  829. && i < MU_MAX_DELAY_TIME; i++) {
  830. rmb();
  831. msleep(1);
  832. }
  833. if (i == MU_MAX_DELAY_TIME) {
  834. printk(KERN_ERR DRV_NAME
  835. "(%s): no signature after handshake frame\n",
  836. pci_name(hba->pdev));
  837. return -1;
  838. }
  839. writel(0, base + IMR0);
  840. readl(base + IMR0);
  841. writel(0, base + OMR0);
  842. readl(base + OMR0);
  843. writel(0, base + IMR1);
  844. readl(base + IMR1);
  845. writel(0, base + OMR1);
  846. readl(base + OMR1); /* flush */
  847. hba->mu_status = MU_STATE_STARTED;
  848. return 0;
  849. }
  850. static int stex_abort(struct scsi_cmnd *cmd)
  851. {
  852. struct Scsi_Host *host = cmd->device->host;
  853. struct st_hba *hba = (struct st_hba *)host->hostdata;
  854. u16 tag = cmd->request->tag;
  855. void __iomem *base;
  856. u32 data;
  857. int result = SUCCESS;
  858. unsigned long flags;
  859. base = hba->mmio_base;
  860. spin_lock_irqsave(host->host_lock, flags);
  861. if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
  862. hba->wait_ccb = &hba->ccb[tag];
  863. else {
  864. for (tag = 0; tag < host->can_queue; tag++)
  865. if (hba->ccb[tag].cmd == cmd) {
  866. hba->wait_ccb = &hba->ccb[tag];
  867. break;
  868. }
  869. if (tag >= host->can_queue)
  870. goto out;
  871. }
  872. data = readl(base + ODBL);
  873. if (data == 0 || data == 0xffffffff)
  874. goto fail_out;
  875. writel(data, base + ODBL);
  876. readl(base + ODBL); /* flush */
  877. stex_mu_intr(hba, data);
  878. if (hba->wait_ccb == NULL) {
  879. printk(KERN_WARNING DRV_NAME
  880. "(%s): lost interrupt\n", pci_name(hba->pdev));
  881. goto out;
  882. }
  883. fail_out:
  884. stex_unmap_sg(hba, cmd);
  885. hba->wait_ccb->req = NULL; /* nullify the req's future return */
  886. hba->wait_ccb = NULL;
  887. result = FAILED;
  888. out:
  889. spin_unlock_irqrestore(host->host_lock, flags);
  890. return result;
  891. }
  892. static void stex_hard_reset(struct st_hba *hba)
  893. {
  894. struct pci_bus *bus;
  895. int i;
  896. u16 pci_cmd;
  897. u8 pci_bctl;
  898. for (i = 0; i < 16; i++)
  899. pci_read_config_dword(hba->pdev, i * 4,
  900. &hba->pdev->saved_config_space[i]);
  901. /* Reset secondary bus. Our controller(MU/ATU) is the only device on
  902. secondary bus. Consult Intel 80331/3 developer's manual for detail */
  903. bus = hba->pdev->bus;
  904. pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
  905. pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
  906. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  907. msleep(1);
  908. pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
  909. pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
  910. for (i = 0; i < MU_MAX_DELAY_TIME; i++) {
  911. pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
  912. if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
  913. break;
  914. msleep(1);
  915. }
  916. ssleep(5);
  917. for (i = 0; i < 16; i++)
  918. pci_write_config_dword(hba->pdev, i * 4,
  919. hba->pdev->saved_config_space[i]);
  920. }
  921. static int stex_reset(struct scsi_cmnd *cmd)
  922. {
  923. struct st_hba *hba;
  924. unsigned long flags;
  925. unsigned long before;
  926. hba = (struct st_hba *) &cmd->device->host->hostdata[0];
  927. hba->mu_status = MU_STATE_RESETTING;
  928. if (hba->cardtype == st_shasta)
  929. stex_hard_reset(hba);
  930. if (hba->cardtype != st_yosemite) {
  931. if (stex_handshake(hba)) {
  932. printk(KERN_WARNING DRV_NAME
  933. "(%s): resetting: handshake failed\n",
  934. pci_name(hba->pdev));
  935. return FAILED;
  936. }
  937. spin_lock_irqsave(hba->host->host_lock, flags);
  938. hba->req_head = 0;
  939. hba->req_tail = 0;
  940. hba->status_head = 0;
  941. hba->status_tail = 0;
  942. hba->out_req_cnt = 0;
  943. spin_unlock_irqrestore(hba->host->host_lock, flags);
  944. return SUCCESS;
  945. }
  946. /* st_yosemite */
  947. writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
  948. readl(hba->mmio_base + IDBL); /* flush */
  949. before = jiffies;
  950. while (hba->out_req_cnt > 0) {
  951. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
  952. printk(KERN_WARNING DRV_NAME
  953. "(%s): reset timeout\n", pci_name(hba->pdev));
  954. return FAILED;
  955. }
  956. msleep(1);
  957. }
  958. hba->mu_status = MU_STATE_STARTED;
  959. return SUCCESS;
  960. }
  961. static int stex_biosparam(struct scsi_device *sdev,
  962. struct block_device *bdev, sector_t capacity, int geom[])
  963. {
  964. int heads = 255, sectors = 63;
  965. if (capacity < 0x200000) {
  966. heads = 64;
  967. sectors = 32;
  968. }
  969. sector_div(capacity, heads * sectors);
  970. geom[0] = heads;
  971. geom[1] = sectors;
  972. geom[2] = capacity;
  973. return 0;
  974. }
  975. static struct scsi_host_template driver_template = {
  976. .module = THIS_MODULE,
  977. .name = DRV_NAME,
  978. .proc_name = DRV_NAME,
  979. .bios_param = stex_biosparam,
  980. .queuecommand = stex_queuecommand,
  981. .slave_alloc = stex_slave_alloc,
  982. .slave_configure = stex_slave_config,
  983. .slave_destroy = stex_slave_destroy,
  984. .eh_abort_handler = stex_abort,
  985. .eh_host_reset_handler = stex_reset,
  986. .can_queue = ST_CAN_QUEUE,
  987. .this_id = -1,
  988. .sg_tablesize = ST_MAX_SG,
  989. .cmd_per_lun = ST_CMD_PER_LUN,
  990. };
  991. static int stex_set_dma_mask(struct pci_dev * pdev)
  992. {
  993. int ret;
  994. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
  995. && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
  996. return 0;
  997. ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  998. if (!ret)
  999. ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  1000. return ret;
  1001. }
  1002. static int __devinit
  1003. stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1004. {
  1005. struct st_hba *hba;
  1006. struct Scsi_Host *host;
  1007. int err;
  1008. err = pci_enable_device(pdev);
  1009. if (err)
  1010. return err;
  1011. pci_set_master(pdev);
  1012. host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
  1013. if (!host) {
  1014. printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
  1015. pci_name(pdev));
  1016. err = -ENOMEM;
  1017. goto out_disable;
  1018. }
  1019. hba = (struct st_hba *)host->hostdata;
  1020. memset(hba, 0, sizeof(struct st_hba));
  1021. err = pci_request_regions(pdev, DRV_NAME);
  1022. if (err < 0) {
  1023. printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
  1024. pci_name(pdev));
  1025. goto out_scsi_host_put;
  1026. }
  1027. hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
  1028. pci_resource_len(pdev, 0));
  1029. if ( !hba->mmio_base) {
  1030. printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
  1031. pci_name(pdev));
  1032. err = -ENOMEM;
  1033. goto out_release_regions;
  1034. }
  1035. err = stex_set_dma_mask(pdev);
  1036. if (err) {
  1037. printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
  1038. pci_name(pdev));
  1039. goto out_iounmap;
  1040. }
  1041. hba->cardtype = (unsigned int) id->driver_data;
  1042. if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
  1043. hba->cardtype = st_vsc1;
  1044. hba->dma_size = (hba->cardtype == st_vsc1) ?
  1045. (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
  1046. hba->dma_mem = dma_alloc_coherent(&pdev->dev,
  1047. hba->dma_size, &hba->dma_handle, GFP_KERNEL);
  1048. if (!hba->dma_mem) {
  1049. err = -ENOMEM;
  1050. printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
  1051. pci_name(pdev));
  1052. goto out_iounmap;
  1053. }
  1054. hba->status_buffer =
  1055. (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
  1056. hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
  1057. hba->mu_status = MU_STATE_STARTING;
  1058. /* firmware uses id/lun pair for a logical drive, but lun would be
  1059. always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
  1060. channel to map lun here */
  1061. host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
  1062. host->max_id = ST_MAX_TARGET_NUM;
  1063. host->max_lun = 1;
  1064. host->unique_id = host->host_no;
  1065. host->max_cmd_len = STEX_CDB_LENGTH;
  1066. hba->host = host;
  1067. hba->pdev = pdev;
  1068. init_waitqueue_head(&hba->waitq);
  1069. err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
  1070. if (err) {
  1071. printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
  1072. pci_name(pdev));
  1073. goto out_pci_free;
  1074. }
  1075. err = stex_handshake(hba);
  1076. if (err)
  1077. goto out_free_irq;
  1078. err = scsi_init_shared_tag_map(host, host->can_queue);
  1079. if (err) {
  1080. printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
  1081. pci_name(pdev));
  1082. goto out_free_irq;
  1083. }
  1084. pci_set_drvdata(pdev, hba);
  1085. err = scsi_add_host(host, &pdev->dev);
  1086. if (err) {
  1087. printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
  1088. pci_name(pdev));
  1089. goto out_free_irq;
  1090. }
  1091. scsi_scan_host(host);
  1092. return 0;
  1093. out_free_irq:
  1094. free_irq(pdev->irq, hba);
  1095. out_pci_free:
  1096. dma_free_coherent(&pdev->dev, hba->dma_size,
  1097. hba->dma_mem, hba->dma_handle);
  1098. out_iounmap:
  1099. iounmap(hba->mmio_base);
  1100. out_release_regions:
  1101. pci_release_regions(pdev);
  1102. out_scsi_host_put:
  1103. scsi_host_put(host);
  1104. out_disable:
  1105. pci_disable_device(pdev);
  1106. return err;
  1107. }
  1108. static void stex_hba_stop(struct st_hba *hba)
  1109. {
  1110. struct req_msg *req;
  1111. unsigned long flags;
  1112. unsigned long before;
  1113. u16 tag = 0;
  1114. spin_lock_irqsave(hba->host->host_lock, flags);
  1115. req = stex_alloc_req(hba);
  1116. memset(req->cdb, 0, STEX_CDB_LENGTH);
  1117. if (hba->cardtype == st_yosemite) {
  1118. req->cdb[0] = MGT_CMD;
  1119. req->cdb[1] = MGT_CMD_SIGNATURE;
  1120. req->cdb[2] = CTLR_CONFIG_CMD;
  1121. req->cdb[3] = CTLR_SHUTDOWN;
  1122. } else {
  1123. req->cdb[0] = CONTROLLER_CMD;
  1124. req->cdb[1] = CTLR_POWER_STATE_CHANGE;
  1125. req->cdb[2] = CTLR_POWER_SAVING;
  1126. }
  1127. hba->ccb[tag].cmd = NULL;
  1128. hba->ccb[tag].sg_count = 0;
  1129. hba->ccb[tag].sense_bufflen = 0;
  1130. hba->ccb[tag].sense_buffer = NULL;
  1131. hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
  1132. stex_send_cmd(hba, req, tag);
  1133. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1134. before = jiffies;
  1135. while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
  1136. if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
  1137. return;
  1138. msleep(10);
  1139. }
  1140. }
  1141. static void stex_hba_free(struct st_hba *hba)
  1142. {
  1143. free_irq(hba->pdev->irq, hba);
  1144. iounmap(hba->mmio_base);
  1145. pci_release_regions(hba->pdev);
  1146. dma_free_coherent(&hba->pdev->dev, hba->dma_size,
  1147. hba->dma_mem, hba->dma_handle);
  1148. }
  1149. static void stex_remove(struct pci_dev *pdev)
  1150. {
  1151. struct st_hba *hba = pci_get_drvdata(pdev);
  1152. scsi_remove_host(hba->host);
  1153. pci_set_drvdata(pdev, NULL);
  1154. stex_hba_stop(hba);
  1155. stex_hba_free(hba);
  1156. scsi_host_put(hba->host);
  1157. pci_disable_device(pdev);
  1158. }
  1159. static void stex_shutdown(struct pci_dev *pdev)
  1160. {
  1161. struct st_hba *hba = pci_get_drvdata(pdev);
  1162. stex_hba_stop(hba);
  1163. }
  1164. static struct pci_device_id stex_pci_tbl[] = {
  1165. /* st_shasta */
  1166. { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1167. st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
  1168. { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1169. st_shasta }, /* SuperTrak EX12350 */
  1170. { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1171. st_shasta }, /* SuperTrak EX4350 */
  1172. { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1173. st_shasta }, /* SuperTrak EX24350 */
  1174. /* st_vsc */
  1175. { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
  1176. /* st_yosemite */
  1177. { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
  1178. st_yosemite }, /* SuperTrak EX4650 */
  1179. { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
  1180. st_yosemite }, /* SuperTrak EX4650o */
  1181. { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
  1182. st_yosemite }, /* SuperTrak EX8650EL */
  1183. { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
  1184. st_yosemite }, /* SuperTrak EX8650 */
  1185. { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
  1186. st_yosemite }, /* SuperTrak EX8654 */
  1187. { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  1188. st_yosemite }, /* generic st_yosemite */
  1189. { } /* terminate list */
  1190. };
  1191. MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
  1192. static struct pci_driver stex_pci_driver = {
  1193. .name = DRV_NAME,
  1194. .id_table = stex_pci_tbl,
  1195. .probe = stex_probe,
  1196. .remove = __devexit_p(stex_remove),
  1197. .shutdown = stex_shutdown,
  1198. };
  1199. static int __init stex_init(void)
  1200. {
  1201. printk(KERN_INFO DRV_NAME
  1202. ": Promise SuperTrak EX Driver version: %s\n",
  1203. ST_DRIVER_VERSION);
  1204. return pci_register_driver(&stex_pci_driver);
  1205. }
  1206. static void __exit stex_exit(void)
  1207. {
  1208. pci_unregister_driver(&stex_pci_driver);
  1209. }
  1210. module_init(stex_init);
  1211. module_exit(stex_exit);