i915_irq.c 31 KB

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  1. /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #include <linux/sysrq.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "i915_drm.h"
  32. #include "i915_drv.h"
  33. #include "i915_trace.h"
  34. #include "intel_drv.h"
  35. #define MAX_NOPID ((u32)~0)
  36. /**
  37. * Interrupts that are always left unmasked.
  38. *
  39. * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  40. * we leave them always unmasked in IMR and then control enabling them through
  41. * PIPESTAT alone.
  42. */
  43. #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
  44. I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  45. I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
  46. I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  47. /** Interrupts that we mask and unmask at runtime. */
  48. #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  49. #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  50. PIPE_VBLANK_INTERRUPT_STATUS)
  51. #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  52. PIPE_VBLANK_INTERRUPT_ENABLE)
  53. #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
  54. DRM_I915_VBLANK_PIPE_B)
  55. void
  56. igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  57. {
  58. if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  59. dev_priv->gt_irq_mask_reg &= ~mask;
  60. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  61. (void) I915_READ(GTIMR);
  62. }
  63. }
  64. static inline void
  65. igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  66. {
  67. if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  68. dev_priv->gt_irq_mask_reg |= mask;
  69. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  70. (void) I915_READ(GTIMR);
  71. }
  72. }
  73. /* For display hotplug interrupt */
  74. void
  75. igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  76. {
  77. if ((dev_priv->irq_mask_reg & mask) != 0) {
  78. dev_priv->irq_mask_reg &= ~mask;
  79. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  80. (void) I915_READ(DEIMR);
  81. }
  82. }
  83. static inline void
  84. igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  85. {
  86. if ((dev_priv->irq_mask_reg & mask) != mask) {
  87. dev_priv->irq_mask_reg |= mask;
  88. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  89. (void) I915_READ(DEIMR);
  90. }
  91. }
  92. void
  93. i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  94. {
  95. if ((dev_priv->irq_mask_reg & mask) != 0) {
  96. dev_priv->irq_mask_reg &= ~mask;
  97. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  98. (void) I915_READ(IMR);
  99. }
  100. }
  101. static inline void
  102. i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  103. {
  104. if ((dev_priv->irq_mask_reg & mask) != mask) {
  105. dev_priv->irq_mask_reg |= mask;
  106. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  107. (void) I915_READ(IMR);
  108. }
  109. }
  110. static inline u32
  111. i915_pipestat(int pipe)
  112. {
  113. if (pipe == 0)
  114. return PIPEASTAT;
  115. if (pipe == 1)
  116. return PIPEBSTAT;
  117. BUG();
  118. }
  119. void
  120. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  121. {
  122. if ((dev_priv->pipestat[pipe] & mask) != mask) {
  123. u32 reg = i915_pipestat(pipe);
  124. dev_priv->pipestat[pipe] |= mask;
  125. /* Enable the interrupt, clear any pending status */
  126. I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  127. (void) I915_READ(reg);
  128. }
  129. }
  130. void
  131. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  132. {
  133. if ((dev_priv->pipestat[pipe] & mask) != 0) {
  134. u32 reg = i915_pipestat(pipe);
  135. dev_priv->pipestat[pipe] &= ~mask;
  136. I915_WRITE(reg, dev_priv->pipestat[pipe]);
  137. (void) I915_READ(reg);
  138. }
  139. }
  140. /**
  141. * i915_pipe_enabled - check if a pipe is enabled
  142. * @dev: DRM device
  143. * @pipe: pipe to check
  144. *
  145. * Reading certain registers when the pipe is disabled can hang the chip.
  146. * Use this routine to make sure the PLL is running and the pipe is active
  147. * before reading such registers if unsure.
  148. */
  149. static int
  150. i915_pipe_enabled(struct drm_device *dev, int pipe)
  151. {
  152. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  153. unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
  154. if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
  155. return 1;
  156. return 0;
  157. }
  158. /* Called from drm generic code, passed a 'crtc', which
  159. * we use as a pipe index
  160. */
  161. u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
  162. {
  163. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  164. unsigned long high_frame;
  165. unsigned long low_frame;
  166. u32 high1, high2, low, count;
  167. high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
  168. low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
  169. if (!i915_pipe_enabled(dev, pipe)) {
  170. DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
  171. return 0;
  172. }
  173. /*
  174. * High & low register fields aren't synchronized, so make sure
  175. * we get a low value that's stable across two reads of the high
  176. * register.
  177. */
  178. do {
  179. high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
  180. PIPE_FRAME_HIGH_SHIFT);
  181. low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
  182. PIPE_FRAME_LOW_SHIFT);
  183. high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
  184. PIPE_FRAME_HIGH_SHIFT);
  185. } while (high1 != high2);
  186. count = (high1 << 8) | low;
  187. return count;
  188. }
  189. u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
  190. {
  191. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  192. int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
  193. if (!i915_pipe_enabled(dev, pipe)) {
  194. DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
  195. return 0;
  196. }
  197. return I915_READ(reg);
  198. }
  199. /*
  200. * Handle hotplug events outside the interrupt handler proper.
  201. */
  202. static void i915_hotplug_work_func(struct work_struct *work)
  203. {
  204. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  205. hotplug_work);
  206. struct drm_device *dev = dev_priv->dev;
  207. struct drm_mode_config *mode_config = &dev->mode_config;
  208. struct drm_connector *connector;
  209. if (mode_config->num_connector) {
  210. list_for_each_entry(connector, &mode_config->connector_list, head) {
  211. struct intel_output *intel_output = to_intel_output(connector);
  212. if (intel_output->hot_plug)
  213. (*intel_output->hot_plug) (intel_output);
  214. }
  215. }
  216. /* Just fire off a uevent and let userspace tell us what to do */
  217. drm_sysfs_hotplug_event(dev);
  218. }
  219. irqreturn_t igdng_irq_handler(struct drm_device *dev)
  220. {
  221. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  222. int ret = IRQ_NONE;
  223. u32 de_iir, gt_iir;
  224. u32 new_de_iir, new_gt_iir;
  225. struct drm_i915_master_private *master_priv;
  226. de_iir = I915_READ(DEIIR);
  227. gt_iir = I915_READ(GTIIR);
  228. for (;;) {
  229. if (de_iir == 0 && gt_iir == 0)
  230. break;
  231. ret = IRQ_HANDLED;
  232. I915_WRITE(DEIIR, de_iir);
  233. new_de_iir = I915_READ(DEIIR);
  234. I915_WRITE(GTIIR, gt_iir);
  235. new_gt_iir = I915_READ(GTIIR);
  236. if (dev->primary->master) {
  237. master_priv = dev->primary->master->driver_priv;
  238. if (master_priv->sarea_priv)
  239. master_priv->sarea_priv->last_dispatch =
  240. READ_BREADCRUMB(dev_priv);
  241. }
  242. if (gt_iir & GT_USER_INTERRUPT) {
  243. u32 seqno = i915_get_gem_seqno(dev);
  244. dev_priv->mm.irq_gem_seqno = seqno;
  245. trace_i915_gem_request_complete(dev, seqno);
  246. DRM_WAKEUP(&dev_priv->irq_queue);
  247. }
  248. de_iir = new_de_iir;
  249. gt_iir = new_gt_iir;
  250. }
  251. return ret;
  252. }
  253. /**
  254. * i915_error_work_func - do process context error handling work
  255. * @work: work struct
  256. *
  257. * Fire an error uevent so userspace can see that a hang or error
  258. * was detected.
  259. */
  260. static void i915_error_work_func(struct work_struct *work)
  261. {
  262. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  263. error_work);
  264. struct drm_device *dev = dev_priv->dev;
  265. char *error_event[] = { "ERROR=1", NULL };
  266. char *reset_event[] = { "RESET=1", NULL };
  267. char *reset_done_event[] = { "ERROR=0", NULL };
  268. DRM_DEBUG("generating error event\n");
  269. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
  270. if (atomic_read(&dev_priv->mm.wedged)) {
  271. if (IS_I965G(dev)) {
  272. DRM_DEBUG("resetting chip\n");
  273. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
  274. if (!i965_reset(dev, GDRST_RENDER)) {
  275. atomic_set(&dev_priv->mm.wedged, 0);
  276. kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
  277. }
  278. } else {
  279. printk("reboot required\n");
  280. }
  281. }
  282. }
  283. /**
  284. * i915_capture_error_state - capture an error record for later analysis
  285. * @dev: drm device
  286. *
  287. * Should be called when an error is detected (either a hang or an error
  288. * interrupt) to capture error state from the time of the error. Fills
  289. * out a structure which becomes available in debugfs for user level tools
  290. * to pick up.
  291. */
  292. static void i915_capture_error_state(struct drm_device *dev)
  293. {
  294. struct drm_i915_private *dev_priv = dev->dev_private;
  295. struct drm_i915_error_state *error;
  296. unsigned long flags;
  297. spin_lock_irqsave(&dev_priv->error_lock, flags);
  298. if (dev_priv->first_error)
  299. goto out;
  300. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  301. if (!error) {
  302. DRM_DEBUG("out ot memory, not capturing error state\n");
  303. goto out;
  304. }
  305. error->eir = I915_READ(EIR);
  306. error->pgtbl_er = I915_READ(PGTBL_ER);
  307. error->pipeastat = I915_READ(PIPEASTAT);
  308. error->pipebstat = I915_READ(PIPEBSTAT);
  309. error->instpm = I915_READ(INSTPM);
  310. if (!IS_I965G(dev)) {
  311. error->ipeir = I915_READ(IPEIR);
  312. error->ipehr = I915_READ(IPEHR);
  313. error->instdone = I915_READ(INSTDONE);
  314. error->acthd = I915_READ(ACTHD);
  315. } else {
  316. error->ipeir = I915_READ(IPEIR_I965);
  317. error->ipehr = I915_READ(IPEHR_I965);
  318. error->instdone = I915_READ(INSTDONE_I965);
  319. error->instps = I915_READ(INSTPS);
  320. error->instdone1 = I915_READ(INSTDONE1);
  321. error->acthd = I915_READ(ACTHD_I965);
  322. }
  323. do_gettimeofday(&error->time);
  324. dev_priv->first_error = error;
  325. out:
  326. spin_unlock_irqrestore(&dev_priv->error_lock, flags);
  327. }
  328. /**
  329. * i915_handle_error - handle an error interrupt
  330. * @dev: drm device
  331. *
  332. * Do some basic checking of regsiter state at error interrupt time and
  333. * dump it to the syslog. Also call i915_capture_error_state() to make
  334. * sure we get a record and make it available in debugfs. Fire a uevent
  335. * so userspace knows something bad happened (should trigger collection
  336. * of a ring dump etc.).
  337. */
  338. static void i915_handle_error(struct drm_device *dev, bool wedged)
  339. {
  340. struct drm_i915_private *dev_priv = dev->dev_private;
  341. u32 eir = I915_READ(EIR);
  342. u32 pipea_stats = I915_READ(PIPEASTAT);
  343. u32 pipeb_stats = I915_READ(PIPEBSTAT);
  344. i915_capture_error_state(dev);
  345. printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
  346. eir);
  347. if (IS_G4X(dev)) {
  348. if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
  349. u32 ipeir = I915_READ(IPEIR_I965);
  350. printk(KERN_ERR " IPEIR: 0x%08x\n",
  351. I915_READ(IPEIR_I965));
  352. printk(KERN_ERR " IPEHR: 0x%08x\n",
  353. I915_READ(IPEHR_I965));
  354. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  355. I915_READ(INSTDONE_I965));
  356. printk(KERN_ERR " INSTPS: 0x%08x\n",
  357. I915_READ(INSTPS));
  358. printk(KERN_ERR " INSTDONE1: 0x%08x\n",
  359. I915_READ(INSTDONE1));
  360. printk(KERN_ERR " ACTHD: 0x%08x\n",
  361. I915_READ(ACTHD_I965));
  362. I915_WRITE(IPEIR_I965, ipeir);
  363. (void)I915_READ(IPEIR_I965);
  364. }
  365. if (eir & GM45_ERROR_PAGE_TABLE) {
  366. u32 pgtbl_err = I915_READ(PGTBL_ER);
  367. printk(KERN_ERR "page table error\n");
  368. printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
  369. pgtbl_err);
  370. I915_WRITE(PGTBL_ER, pgtbl_err);
  371. (void)I915_READ(PGTBL_ER);
  372. }
  373. }
  374. if (IS_I9XX(dev)) {
  375. if (eir & I915_ERROR_PAGE_TABLE) {
  376. u32 pgtbl_err = I915_READ(PGTBL_ER);
  377. printk(KERN_ERR "page table error\n");
  378. printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
  379. pgtbl_err);
  380. I915_WRITE(PGTBL_ER, pgtbl_err);
  381. (void)I915_READ(PGTBL_ER);
  382. }
  383. }
  384. if (eir & I915_ERROR_MEMORY_REFRESH) {
  385. printk(KERN_ERR "memory refresh error\n");
  386. printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
  387. pipea_stats);
  388. printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
  389. pipeb_stats);
  390. /* pipestat has already been acked */
  391. }
  392. if (eir & I915_ERROR_INSTRUCTION) {
  393. printk(KERN_ERR "instruction error\n");
  394. printk(KERN_ERR " INSTPM: 0x%08x\n",
  395. I915_READ(INSTPM));
  396. if (!IS_I965G(dev)) {
  397. u32 ipeir = I915_READ(IPEIR);
  398. printk(KERN_ERR " IPEIR: 0x%08x\n",
  399. I915_READ(IPEIR));
  400. printk(KERN_ERR " IPEHR: 0x%08x\n",
  401. I915_READ(IPEHR));
  402. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  403. I915_READ(INSTDONE));
  404. printk(KERN_ERR " ACTHD: 0x%08x\n",
  405. I915_READ(ACTHD));
  406. I915_WRITE(IPEIR, ipeir);
  407. (void)I915_READ(IPEIR);
  408. } else {
  409. u32 ipeir = I915_READ(IPEIR_I965);
  410. printk(KERN_ERR " IPEIR: 0x%08x\n",
  411. I915_READ(IPEIR_I965));
  412. printk(KERN_ERR " IPEHR: 0x%08x\n",
  413. I915_READ(IPEHR_I965));
  414. printk(KERN_ERR " INSTDONE: 0x%08x\n",
  415. I915_READ(INSTDONE_I965));
  416. printk(KERN_ERR " INSTPS: 0x%08x\n",
  417. I915_READ(INSTPS));
  418. printk(KERN_ERR " INSTDONE1: 0x%08x\n",
  419. I915_READ(INSTDONE1));
  420. printk(KERN_ERR " ACTHD: 0x%08x\n",
  421. I915_READ(ACTHD_I965));
  422. I915_WRITE(IPEIR_I965, ipeir);
  423. (void)I915_READ(IPEIR_I965);
  424. }
  425. }
  426. I915_WRITE(EIR, eir);
  427. (void)I915_READ(EIR);
  428. eir = I915_READ(EIR);
  429. if (eir) {
  430. /*
  431. * some errors might have become stuck,
  432. * mask them.
  433. */
  434. DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
  435. I915_WRITE(EMR, I915_READ(EMR) | eir);
  436. I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
  437. }
  438. if (wedged) {
  439. atomic_set(&dev_priv->mm.wedged, 1);
  440. /*
  441. * Wakeup waiting processes so they don't hang
  442. */
  443. printk("i915: Waking up sleeping processes\n");
  444. DRM_WAKEUP(&dev_priv->irq_queue);
  445. }
  446. queue_work(dev_priv->wq, &dev_priv->error_work);
  447. }
  448. irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
  449. {
  450. struct drm_device *dev = (struct drm_device *) arg;
  451. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  452. struct drm_i915_master_private *master_priv;
  453. u32 iir, new_iir;
  454. u32 pipea_stats, pipeb_stats;
  455. u32 vblank_status;
  456. u32 vblank_enable;
  457. int vblank = 0;
  458. unsigned long irqflags;
  459. int irq_received;
  460. int ret = IRQ_NONE;
  461. atomic_inc(&dev_priv->irq_received);
  462. if (IS_IGDNG(dev))
  463. return igdng_irq_handler(dev);
  464. iir = I915_READ(IIR);
  465. if (IS_I965G(dev)) {
  466. vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
  467. vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
  468. } else {
  469. vblank_status = I915_VBLANK_INTERRUPT_STATUS;
  470. vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
  471. }
  472. for (;;) {
  473. irq_received = iir != 0;
  474. /* Can't rely on pipestat interrupt bit in iir as it might
  475. * have been cleared after the pipestat interrupt was received.
  476. * It doesn't set the bit in iir again, but it still produces
  477. * interrupts (for non-MSI).
  478. */
  479. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  480. pipea_stats = I915_READ(PIPEASTAT);
  481. pipeb_stats = I915_READ(PIPEBSTAT);
  482. if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  483. i915_handle_error(dev, false);
  484. /*
  485. * Clear the PIPE(A|B)STAT regs before the IIR
  486. */
  487. if (pipea_stats & 0x8000ffff) {
  488. if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
  489. DRM_DEBUG("pipe a underrun\n");
  490. I915_WRITE(PIPEASTAT, pipea_stats);
  491. irq_received = 1;
  492. }
  493. if (pipeb_stats & 0x8000ffff) {
  494. if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
  495. DRM_DEBUG("pipe b underrun\n");
  496. I915_WRITE(PIPEBSTAT, pipeb_stats);
  497. irq_received = 1;
  498. }
  499. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  500. if (!irq_received)
  501. break;
  502. ret = IRQ_HANDLED;
  503. /* Consume port. Then clear IIR or we'll miss events */
  504. if ((I915_HAS_HOTPLUG(dev)) &&
  505. (iir & I915_DISPLAY_PORT_INTERRUPT)) {
  506. u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
  507. DRM_DEBUG("hotplug event received, stat 0x%08x\n",
  508. hotplug_status);
  509. if (hotplug_status & dev_priv->hotplug_supported_mask)
  510. queue_work(dev_priv->wq,
  511. &dev_priv->hotplug_work);
  512. I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
  513. I915_READ(PORT_HOTPLUG_STAT);
  514. /* EOS interrupts occurs */
  515. if (IS_IGD(dev) &&
  516. (hotplug_status & CRT_EOS_INT_STATUS)) {
  517. u32 temp;
  518. DRM_DEBUG("EOS interrupt occurs\n");
  519. /* status is already cleared */
  520. temp = I915_READ(ADPA);
  521. temp &= ~ADPA_DAC_ENABLE;
  522. I915_WRITE(ADPA, temp);
  523. temp = I915_READ(PORT_HOTPLUG_EN);
  524. temp &= ~CRT_EOS_INT_EN;
  525. I915_WRITE(PORT_HOTPLUG_EN, temp);
  526. temp = I915_READ(PORT_HOTPLUG_STAT);
  527. if (temp & CRT_EOS_INT_STATUS)
  528. I915_WRITE(PORT_HOTPLUG_STAT,
  529. CRT_EOS_INT_STATUS);
  530. }
  531. }
  532. I915_WRITE(IIR, iir);
  533. new_iir = I915_READ(IIR); /* Flush posted writes */
  534. if (dev->primary->master) {
  535. master_priv = dev->primary->master->driver_priv;
  536. if (master_priv->sarea_priv)
  537. master_priv->sarea_priv->last_dispatch =
  538. READ_BREADCRUMB(dev_priv);
  539. }
  540. if (iir & I915_USER_INTERRUPT) {
  541. u32 seqno = i915_get_gem_seqno(dev);
  542. dev_priv->mm.irq_gem_seqno = seqno;
  543. trace_i915_gem_request_complete(dev, seqno);
  544. DRM_WAKEUP(&dev_priv->irq_queue);
  545. dev_priv->hangcheck_count = 0;
  546. mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
  547. }
  548. if (pipea_stats & vblank_status) {
  549. vblank++;
  550. drm_handle_vblank(dev, 0);
  551. }
  552. if (pipeb_stats & vblank_status) {
  553. vblank++;
  554. drm_handle_vblank(dev, 1);
  555. }
  556. if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
  557. (iir & I915_ASLE_INTERRUPT))
  558. opregion_asle_intr(dev);
  559. /* With MSI, interrupts are only generated when iir
  560. * transitions from zero to nonzero. If another bit got
  561. * set while we were handling the existing iir bits, then
  562. * we would never get another interrupt.
  563. *
  564. * This is fine on non-MSI as well, as if we hit this path
  565. * we avoid exiting the interrupt handler only to generate
  566. * another one.
  567. *
  568. * Note that for MSI this could cause a stray interrupt report
  569. * if an interrupt landed in the time between writing IIR and
  570. * the posting read. This should be rare enough to never
  571. * trigger the 99% of 100,000 interrupts test for disabling
  572. * stray interrupts.
  573. */
  574. iir = new_iir;
  575. }
  576. return ret;
  577. }
  578. static int i915_emit_irq(struct drm_device * dev)
  579. {
  580. drm_i915_private_t *dev_priv = dev->dev_private;
  581. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  582. RING_LOCALS;
  583. i915_kernel_lost_context(dev);
  584. DRM_DEBUG("\n");
  585. dev_priv->counter++;
  586. if (dev_priv->counter > 0x7FFFFFFFUL)
  587. dev_priv->counter = 1;
  588. if (master_priv->sarea_priv)
  589. master_priv->sarea_priv->last_enqueue = dev_priv->counter;
  590. BEGIN_LP_RING(4);
  591. OUT_RING(MI_STORE_DWORD_INDEX);
  592. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  593. OUT_RING(dev_priv->counter);
  594. OUT_RING(MI_USER_INTERRUPT);
  595. ADVANCE_LP_RING();
  596. return dev_priv->counter;
  597. }
  598. void i915_user_irq_get(struct drm_device *dev)
  599. {
  600. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  601. unsigned long irqflags;
  602. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  603. if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
  604. if (IS_IGDNG(dev))
  605. igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
  606. else
  607. i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
  608. }
  609. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  610. }
  611. void i915_user_irq_put(struct drm_device *dev)
  612. {
  613. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  614. unsigned long irqflags;
  615. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  616. BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
  617. if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
  618. if (IS_IGDNG(dev))
  619. igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
  620. else
  621. i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
  622. }
  623. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  624. }
  625. static int i915_wait_irq(struct drm_device * dev, int irq_nr)
  626. {
  627. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  628. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  629. int ret = 0;
  630. DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
  631. READ_BREADCRUMB(dev_priv));
  632. if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
  633. if (master_priv->sarea_priv)
  634. master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  635. return 0;
  636. }
  637. if (master_priv->sarea_priv)
  638. master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  639. i915_user_irq_get(dev);
  640. DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
  641. READ_BREADCRUMB(dev_priv) >= irq_nr);
  642. i915_user_irq_put(dev);
  643. if (ret == -EBUSY) {
  644. DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
  645. READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
  646. }
  647. return ret;
  648. }
  649. /* Needs the lock as it touches the ring.
  650. */
  651. int i915_irq_emit(struct drm_device *dev, void *data,
  652. struct drm_file *file_priv)
  653. {
  654. drm_i915_private_t *dev_priv = dev->dev_private;
  655. drm_i915_irq_emit_t *emit = data;
  656. int result;
  657. if (!dev_priv || !dev_priv->ring.virtual_start) {
  658. DRM_ERROR("called with no initialization\n");
  659. return -EINVAL;
  660. }
  661. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  662. mutex_lock(&dev->struct_mutex);
  663. result = i915_emit_irq(dev);
  664. mutex_unlock(&dev->struct_mutex);
  665. if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
  666. DRM_ERROR("copy_to_user\n");
  667. return -EFAULT;
  668. }
  669. return 0;
  670. }
  671. /* Doesn't need the hardware lock.
  672. */
  673. int i915_irq_wait(struct drm_device *dev, void *data,
  674. struct drm_file *file_priv)
  675. {
  676. drm_i915_private_t *dev_priv = dev->dev_private;
  677. drm_i915_irq_wait_t *irqwait = data;
  678. if (!dev_priv) {
  679. DRM_ERROR("called with no initialization\n");
  680. return -EINVAL;
  681. }
  682. return i915_wait_irq(dev, irqwait->irq_seq);
  683. }
  684. /* Called from drm generic code, passed 'crtc' which
  685. * we use as a pipe index
  686. */
  687. int i915_enable_vblank(struct drm_device *dev, int pipe)
  688. {
  689. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  690. unsigned long irqflags;
  691. int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
  692. u32 pipeconf;
  693. pipeconf = I915_READ(pipeconf_reg);
  694. if (!(pipeconf & PIPEACONF_ENABLE))
  695. return -EINVAL;
  696. if (IS_IGDNG(dev))
  697. return 0;
  698. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  699. if (IS_I965G(dev))
  700. i915_enable_pipestat(dev_priv, pipe,
  701. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  702. else
  703. i915_enable_pipestat(dev_priv, pipe,
  704. PIPE_VBLANK_INTERRUPT_ENABLE);
  705. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  706. return 0;
  707. }
  708. /* Called from drm generic code, passed 'crtc' which
  709. * we use as a pipe index
  710. */
  711. void i915_disable_vblank(struct drm_device *dev, int pipe)
  712. {
  713. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  714. unsigned long irqflags;
  715. if (IS_IGDNG(dev))
  716. return;
  717. spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
  718. i915_disable_pipestat(dev_priv, pipe,
  719. PIPE_VBLANK_INTERRUPT_ENABLE |
  720. PIPE_START_VBLANK_INTERRUPT_ENABLE);
  721. spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
  722. }
  723. void i915_enable_interrupt (struct drm_device *dev)
  724. {
  725. struct drm_i915_private *dev_priv = dev->dev_private;
  726. if (!IS_IGDNG(dev))
  727. opregion_enable_asle(dev);
  728. dev_priv->irq_enabled = 1;
  729. }
  730. /* Set the vblank monitor pipe
  731. */
  732. int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  733. struct drm_file *file_priv)
  734. {
  735. drm_i915_private_t *dev_priv = dev->dev_private;
  736. if (!dev_priv) {
  737. DRM_ERROR("called with no initialization\n");
  738. return -EINVAL;
  739. }
  740. return 0;
  741. }
  742. int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  743. struct drm_file *file_priv)
  744. {
  745. drm_i915_private_t *dev_priv = dev->dev_private;
  746. drm_i915_vblank_pipe_t *pipe = data;
  747. if (!dev_priv) {
  748. DRM_ERROR("called with no initialization\n");
  749. return -EINVAL;
  750. }
  751. pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  752. return 0;
  753. }
  754. /**
  755. * Schedule buffer swap at given vertical blank.
  756. */
  757. int i915_vblank_swap(struct drm_device *dev, void *data,
  758. struct drm_file *file_priv)
  759. {
  760. /* The delayed swap mechanism was fundamentally racy, and has been
  761. * removed. The model was that the client requested a delayed flip/swap
  762. * from the kernel, then waited for vblank before continuing to perform
  763. * rendering. The problem was that the kernel might wake the client
  764. * up before it dispatched the vblank swap (since the lock has to be
  765. * held while touching the ringbuffer), in which case the client would
  766. * clear and start the next frame before the swap occurred, and
  767. * flicker would occur in addition to likely missing the vblank.
  768. *
  769. * In the absence of this ioctl, userland falls back to a correct path
  770. * of waiting for a vblank, then dispatching the swap on its own.
  771. * Context switching to userland and back is plenty fast enough for
  772. * meeting the requirements of vblank swapping.
  773. */
  774. return -EINVAL;
  775. }
  776. struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
  777. drm_i915_private_t *dev_priv = dev->dev_private;
  778. return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
  779. }
  780. /**
  781. * This is called when the chip hasn't reported back with completed
  782. * batchbuffers in a long time. The first time this is called we simply record
  783. * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
  784. * again, we assume the chip is wedged and try to fix it.
  785. */
  786. void i915_hangcheck_elapsed(unsigned long data)
  787. {
  788. struct drm_device *dev = (struct drm_device *)data;
  789. drm_i915_private_t *dev_priv = dev->dev_private;
  790. uint32_t acthd;
  791. if (!IS_I965G(dev))
  792. acthd = I915_READ(ACTHD);
  793. else
  794. acthd = I915_READ(ACTHD_I965);
  795. /* If all work is done then ACTHD clearly hasn't advanced. */
  796. if (list_empty(&dev_priv->mm.request_list) ||
  797. i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
  798. dev_priv->hangcheck_count = 0;
  799. return;
  800. }
  801. if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
  802. DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
  803. i915_handle_error(dev, true);
  804. return;
  805. }
  806. /* Reset timer case chip hangs without another request being added */
  807. mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
  808. if (acthd != dev_priv->last_acthd)
  809. dev_priv->hangcheck_count = 0;
  810. else
  811. dev_priv->hangcheck_count++;
  812. dev_priv->last_acthd = acthd;
  813. }
  814. /* drm_dma.h hooks
  815. */
  816. static void igdng_irq_preinstall(struct drm_device *dev)
  817. {
  818. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  819. I915_WRITE(HWSTAM, 0xeffe);
  820. /* XXX hotplug from PCH */
  821. I915_WRITE(DEIMR, 0xffffffff);
  822. I915_WRITE(DEIER, 0x0);
  823. (void) I915_READ(DEIER);
  824. /* and GT */
  825. I915_WRITE(GTIMR, 0xffffffff);
  826. I915_WRITE(GTIER, 0x0);
  827. (void) I915_READ(GTIER);
  828. }
  829. static int igdng_irq_postinstall(struct drm_device *dev)
  830. {
  831. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  832. /* enable kind of interrupts always enabled */
  833. u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
  834. u32 render_mask = GT_USER_INTERRUPT;
  835. dev_priv->irq_mask_reg = ~display_mask;
  836. dev_priv->de_irq_enable_reg = display_mask;
  837. /* should always can generate irq */
  838. I915_WRITE(DEIIR, I915_READ(DEIIR));
  839. I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  840. I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
  841. (void) I915_READ(DEIER);
  842. /* user interrupt should be enabled, but masked initial */
  843. dev_priv->gt_irq_mask_reg = 0xffffffff;
  844. dev_priv->gt_irq_enable_reg = render_mask;
  845. I915_WRITE(GTIIR, I915_READ(GTIIR));
  846. I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  847. I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
  848. (void) I915_READ(GTIER);
  849. return 0;
  850. }
  851. void i915_driver_irq_preinstall(struct drm_device * dev)
  852. {
  853. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  854. atomic_set(&dev_priv->irq_received, 0);
  855. INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
  856. INIT_WORK(&dev_priv->error_work, i915_error_work_func);
  857. if (IS_IGDNG(dev)) {
  858. igdng_irq_preinstall(dev);
  859. return;
  860. }
  861. if (I915_HAS_HOTPLUG(dev)) {
  862. I915_WRITE(PORT_HOTPLUG_EN, 0);
  863. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  864. }
  865. I915_WRITE(HWSTAM, 0xeffe);
  866. I915_WRITE(PIPEASTAT, 0);
  867. I915_WRITE(PIPEBSTAT, 0);
  868. I915_WRITE(IMR, 0xffffffff);
  869. I915_WRITE(IER, 0x0);
  870. (void) I915_READ(IER);
  871. }
  872. int i915_driver_irq_postinstall(struct drm_device *dev)
  873. {
  874. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  875. u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
  876. u32 error_mask;
  877. DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
  878. dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  879. if (IS_IGDNG(dev))
  880. return igdng_irq_postinstall(dev);
  881. /* Unmask the interrupts that we always want on. */
  882. dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
  883. dev_priv->pipestat[0] = 0;
  884. dev_priv->pipestat[1] = 0;
  885. if (I915_HAS_HOTPLUG(dev)) {
  886. u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
  887. /* Leave other bits alone */
  888. hotplug_en |= HOTPLUG_EN_MASK;
  889. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  890. dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS |
  891. TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS |
  892. SDVOB_HOTPLUG_INT_STATUS;
  893. if (IS_G4X(dev)) {
  894. dev_priv->hotplug_supported_mask |=
  895. HDMIB_HOTPLUG_INT_STATUS |
  896. HDMIC_HOTPLUG_INT_STATUS |
  897. HDMID_HOTPLUG_INT_STATUS;
  898. }
  899. /* Enable in IER... */
  900. enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
  901. /* and unmask in IMR */
  902. i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
  903. }
  904. /*
  905. * Enable some error detection, note the instruction error mask
  906. * bit is reserved, so we leave it masked.
  907. */
  908. if (IS_G4X(dev)) {
  909. error_mask = ~(GM45_ERROR_PAGE_TABLE |
  910. GM45_ERROR_MEM_PRIV |
  911. GM45_ERROR_CP_PRIV |
  912. I915_ERROR_MEMORY_REFRESH);
  913. } else {
  914. error_mask = ~(I915_ERROR_PAGE_TABLE |
  915. I915_ERROR_MEMORY_REFRESH);
  916. }
  917. I915_WRITE(EMR, error_mask);
  918. /* Disable pipe interrupt enables, clear pending pipe status */
  919. I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
  920. I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
  921. /* Clear pending interrupt status */
  922. I915_WRITE(IIR, I915_READ(IIR));
  923. I915_WRITE(IER, enable_mask);
  924. I915_WRITE(IMR, dev_priv->irq_mask_reg);
  925. (void) I915_READ(IER);
  926. opregion_enable_asle(dev);
  927. return 0;
  928. }
  929. static void igdng_irq_uninstall(struct drm_device *dev)
  930. {
  931. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  932. I915_WRITE(HWSTAM, 0xffffffff);
  933. I915_WRITE(DEIMR, 0xffffffff);
  934. I915_WRITE(DEIER, 0x0);
  935. I915_WRITE(DEIIR, I915_READ(DEIIR));
  936. I915_WRITE(GTIMR, 0xffffffff);
  937. I915_WRITE(GTIER, 0x0);
  938. I915_WRITE(GTIIR, I915_READ(GTIIR));
  939. }
  940. void i915_driver_irq_uninstall(struct drm_device * dev)
  941. {
  942. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  943. if (!dev_priv)
  944. return;
  945. dev_priv->vblank_pipe = 0;
  946. if (IS_IGDNG(dev)) {
  947. igdng_irq_uninstall(dev);
  948. return;
  949. }
  950. if (I915_HAS_HOTPLUG(dev)) {
  951. I915_WRITE(PORT_HOTPLUG_EN, 0);
  952. I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
  953. }
  954. I915_WRITE(HWSTAM, 0xffffffff);
  955. I915_WRITE(PIPEASTAT, 0);
  956. I915_WRITE(PIPEBSTAT, 0);
  957. I915_WRITE(IMR, 0xffffffff);
  958. I915_WRITE(IER, 0x0);
  959. I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
  960. I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
  961. I915_WRITE(IIR, I915_READ(IIR));
  962. }