sdhci-esdhc-imx.c 10 KB

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  1. /*
  2. * Freescale eSDHC i.MX controller driver for the platform bus.
  3. *
  4. * derived from the OF-version.
  5. *
  6. * Copyright (c) 2010 Pengutronix e.K.
  7. * Author: Wolfram Sang <w.sang@pengutronix.de>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License.
  12. */
  13. #include <linux/io.h>
  14. #include <linux/delay.h>
  15. #include <linux/err.h>
  16. #include <linux/clk.h>
  17. #include <linux/gpio.h>
  18. #include <linux/slab.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/mmc.h>
  21. #include <linux/mmc/sdio.h>
  22. #include <mach/hardware.h>
  23. #include <mach/esdhc.h>
  24. #include "sdhci.h"
  25. #include "sdhci-pltfm.h"
  26. #include "sdhci-esdhc.h"
  27. /* VENDOR SPEC register */
  28. #define SDHCI_VENDOR_SPEC 0xC0
  29. #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002
  30. #define ESDHC_FLAG_GPIO_FOR_CD_WP (1 << 0)
  31. /*
  32. * The CMDTYPE of the CMD register (offset 0xE) should be set to
  33. * "11" when the STOP CMD12 is issued on imx53 to abort one
  34. * open ended multi-blk IO. Otherwise the TC INT wouldn't
  35. * be generated.
  36. * In exact block transfer, the controller doesn't complete the
  37. * operations automatically as required at the end of the
  38. * transfer and remains on hold if the abort command is not sent.
  39. * As a result, the TC flag is not asserted and SW received timeout
  40. * exeception. Bit1 of Vendor Spec registor is used to fix it.
  41. */
  42. #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
  43. struct pltfm_imx_data {
  44. int flags;
  45. u32 scratchpad;
  46. };
  47. static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
  48. {
  49. void __iomem *base = host->ioaddr + (reg & ~0x3);
  50. u32 shift = (reg & 0x3) * 8;
  51. writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
  52. }
  53. static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
  54. {
  55. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  56. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  57. /* fake CARD_PRESENT flag on mx25/35 */
  58. u32 val = readl(host->ioaddr + reg);
  59. if (unlikely((reg == SDHCI_PRESENT_STATE)
  60. && (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP))) {
  61. struct esdhc_platform_data *boarddata =
  62. host->mmc->parent->platform_data;
  63. if (boarddata && gpio_is_valid(boarddata->cd_gpio)
  64. && gpio_get_value(boarddata->cd_gpio))
  65. /* no card, if a valid gpio says so... */
  66. val &= SDHCI_CARD_PRESENT;
  67. else
  68. /* ... in all other cases assume card is present */
  69. val |= SDHCI_CARD_PRESENT;
  70. }
  71. return val;
  72. }
  73. static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
  74. {
  75. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  76. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  77. if (unlikely((reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)
  78. && (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP)))
  79. /*
  80. * these interrupts won't work with a custom card_detect gpio
  81. * (only applied to mx25/35)
  82. */
  83. val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
  84. if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  85. && (reg == SDHCI_INT_STATUS)
  86. && (val & SDHCI_INT_DATA_END))) {
  87. u32 v;
  88. v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
  89. v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
  90. writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
  91. }
  92. writel(val, host->ioaddr + reg);
  93. }
  94. static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
  95. {
  96. if (unlikely(reg == SDHCI_HOST_VERSION))
  97. reg ^= 2;
  98. return readw(host->ioaddr + reg);
  99. }
  100. static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
  101. {
  102. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  103. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  104. switch (reg) {
  105. case SDHCI_TRANSFER_MODE:
  106. /*
  107. * Postpone this write, we must do it together with a
  108. * command write that is down below.
  109. */
  110. if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
  111. && (host->cmd->opcode == SD_IO_RW_EXTENDED)
  112. && (host->cmd->data->blocks > 1)
  113. && (host->cmd->data->flags & MMC_DATA_READ)) {
  114. u32 v;
  115. v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
  116. v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
  117. writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
  118. }
  119. imx_data->scratchpad = val;
  120. return;
  121. case SDHCI_COMMAND:
  122. if ((host->cmd->opcode == MMC_STOP_TRANSMISSION)
  123. && (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
  124. val |= SDHCI_CMD_ABORTCMD;
  125. writel(val << 16 | imx_data->scratchpad,
  126. host->ioaddr + SDHCI_TRANSFER_MODE);
  127. return;
  128. case SDHCI_BLOCK_SIZE:
  129. val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
  130. break;
  131. }
  132. esdhc_clrset_le(host, 0xffff, val, reg);
  133. }
  134. static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
  135. {
  136. u32 new_val;
  137. switch (reg) {
  138. case SDHCI_POWER_CONTROL:
  139. /*
  140. * FSL put some DMA bits here
  141. * If your board has a regulator, code should be here
  142. */
  143. return;
  144. case SDHCI_HOST_CONTROL:
  145. /* FSL messed up here, so we can just keep those two */
  146. new_val = val & (SDHCI_CTRL_LED | SDHCI_CTRL_4BITBUS);
  147. /* ensure the endianess */
  148. new_val |= ESDHC_HOST_CONTROL_LE;
  149. /* DMA mode bits are shifted */
  150. new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
  151. esdhc_clrset_le(host, 0xffff, new_val, reg);
  152. return;
  153. }
  154. esdhc_clrset_le(host, 0xff, val, reg);
  155. }
  156. static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
  157. {
  158. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  159. return clk_get_rate(pltfm_host->clk);
  160. }
  161. static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
  162. {
  163. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  164. return clk_get_rate(pltfm_host->clk) / 256 / 16;
  165. }
  166. static struct sdhci_ops sdhci_esdhc_ops = {
  167. .read_l = esdhc_readl_le,
  168. .read_w = esdhc_readw_le,
  169. .write_l = esdhc_writel_le,
  170. .write_w = esdhc_writew_le,
  171. .write_b = esdhc_writeb_le,
  172. .set_clock = esdhc_set_clock,
  173. .get_max_clock = esdhc_pltfm_get_max_clock,
  174. .get_min_clock = esdhc_pltfm_get_min_clock,
  175. };
  176. static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
  177. .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_ADMA
  178. | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  179. /* ADMA has issues. Might be fixable */
  180. .ops = &sdhci_esdhc_ops,
  181. };
  182. static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
  183. {
  184. struct esdhc_platform_data *boarddata =
  185. host->mmc->parent->platform_data;
  186. if (boarddata && gpio_is_valid(boarddata->wp_gpio))
  187. return gpio_get_value(boarddata->wp_gpio);
  188. else
  189. return -ENOSYS;
  190. }
  191. static irqreturn_t cd_irq(int irq, void *data)
  192. {
  193. struct sdhci_host *sdhost = (struct sdhci_host *)data;
  194. tasklet_schedule(&sdhost->card_tasklet);
  195. return IRQ_HANDLED;
  196. };
  197. static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
  198. {
  199. struct sdhci_pltfm_host *pltfm_host;
  200. struct sdhci_host *host;
  201. struct esdhc_platform_data *boarddata;
  202. struct clk *clk;
  203. int err;
  204. struct pltfm_imx_data *imx_data;
  205. host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
  206. if (IS_ERR(host))
  207. return PTR_ERR(host);
  208. pltfm_host = sdhci_priv(host);
  209. imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
  210. if (!imx_data)
  211. return -ENOMEM;
  212. pltfm_host->priv = imx_data;
  213. clk = clk_get(mmc_dev(host->mmc), NULL);
  214. if (IS_ERR(clk)) {
  215. dev_err(mmc_dev(host->mmc), "clk err\n");
  216. err = PTR_ERR(clk);
  217. goto err_clk_get;
  218. }
  219. clk_enable(clk);
  220. pltfm_host->clk = clk;
  221. if (!cpu_is_mx25())
  222. host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
  223. if (cpu_is_mx25() || cpu_is_mx35()) {
  224. /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
  225. host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK;
  226. /* write_protect can't be routed to controller, use gpio */
  227. sdhci_esdhc_ops.get_ro = esdhc_pltfm_get_ro;
  228. }
  229. if (!(cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51()))
  230. imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
  231. boarddata = host->mmc->parent->platform_data;
  232. if (boarddata) {
  233. err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP");
  234. if (err) {
  235. dev_warn(mmc_dev(host->mmc),
  236. "no write-protect pin available!\n");
  237. boarddata->wp_gpio = err;
  238. }
  239. err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD");
  240. if (err) {
  241. dev_warn(mmc_dev(host->mmc),
  242. "no card-detect pin available!\n");
  243. goto no_card_detect_pin;
  244. }
  245. /* i.MX5x has issues to be researched */
  246. if (!cpu_is_mx25() && !cpu_is_mx35())
  247. goto not_supported;
  248. err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq,
  249. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
  250. mmc_hostname(host->mmc), host);
  251. if (err) {
  252. dev_warn(mmc_dev(host->mmc), "request irq error\n");
  253. goto no_card_detect_irq;
  254. }
  255. imx_data->flags |= ESDHC_FLAG_GPIO_FOR_CD_WP;
  256. /* Now we have a working card_detect again */
  257. host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
  258. }
  259. err = sdhci_add_host(host);
  260. if (err)
  261. goto err_add_host;
  262. return 0;
  263. no_card_detect_irq:
  264. gpio_free(boarddata->cd_gpio);
  265. no_card_detect_pin:
  266. boarddata->cd_gpio = err;
  267. not_supported:
  268. kfree(imx_data);
  269. err_add_host:
  270. clk_disable(pltfm_host->clk);
  271. clk_put(pltfm_host->clk);
  272. err_clk_get:
  273. sdhci_pltfm_free(pdev);
  274. return err;
  275. }
  276. static int __devexit sdhci_esdhc_imx_remove(struct platform_device *pdev)
  277. {
  278. struct sdhci_host *host = platform_get_drvdata(pdev);
  279. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  280. struct esdhc_platform_data *boarddata = host->mmc->parent->platform_data;
  281. struct pltfm_imx_data *imx_data = pltfm_host->priv;
  282. int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
  283. sdhci_remove_host(host, dead);
  284. if (boarddata && gpio_is_valid(boarddata->wp_gpio))
  285. gpio_free(boarddata->wp_gpio);
  286. if (boarddata && gpio_is_valid(boarddata->cd_gpio)) {
  287. gpio_free(boarddata->cd_gpio);
  288. if (!(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION))
  289. free_irq(gpio_to_irq(boarddata->cd_gpio), host);
  290. }
  291. clk_disable(pltfm_host->clk);
  292. clk_put(pltfm_host->clk);
  293. kfree(imx_data);
  294. sdhci_pltfm_free(pdev);
  295. return 0;
  296. }
  297. static struct platform_driver sdhci_esdhc_imx_driver = {
  298. .driver = {
  299. .name = "sdhci-esdhc-imx",
  300. .owner = THIS_MODULE,
  301. },
  302. .probe = sdhci_esdhc_imx_probe,
  303. .remove = __devexit_p(sdhci_esdhc_imx_remove),
  304. #ifdef CONFIG_PM
  305. .suspend = sdhci_pltfm_suspend,
  306. .resume = sdhci_pltfm_resume,
  307. #endif
  308. };
  309. static int __init sdhci_esdhc_imx_init(void)
  310. {
  311. return platform_driver_register(&sdhci_esdhc_imx_driver);
  312. }
  313. module_init(sdhci_esdhc_imx_init);
  314. static void __exit sdhci_esdhc_imx_exit(void)
  315. {
  316. platform_driver_unregister(&sdhci_esdhc_imx_driver);
  317. }
  318. module_exit(sdhci_esdhc_imx_exit);
  319. MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
  320. MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
  321. MODULE_LICENSE("GPL v2");