nouveau_drv.c 14 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #include <linux/console.h>
  25. #include <linux/module.h>
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include "drm_crtc_helper.h"
  29. #include "nouveau_drv.h"
  30. #include "nouveau_agp.h"
  31. #include "nouveau_abi16.h"
  32. #include "nouveau_hw.h"
  33. #include "nouveau_fb.h"
  34. #include "nouveau_fbcon.h"
  35. #include "nouveau_pm.h"
  36. #include <engine/fifo.h>
  37. #include "nv50_display.h"
  38. #include "drm_pciids.h"
  39. MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  40. int nouveau_modeset = -1;
  41. module_param_named(modeset, nouveau_modeset, int, 0400);
  42. MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  43. char *nouveau_vbios;
  44. module_param_named(vbios, nouveau_vbios, charp, 0400);
  45. MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  46. int nouveau_vram_pushbuf;
  47. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  48. MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  49. int nouveau_vram_notify = 0;
  50. module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  51. MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
  52. char *nouveau_vram_type;
  53. module_param_named(vram_type, nouveau_vram_type, charp, 0400);
  54. MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  55. int nouveau_duallink = 1;
  56. module_param_named(duallink, nouveau_duallink, int, 0400);
  57. MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  58. int nouveau_uscript_lvds = -1;
  59. module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  60. MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  61. int nouveau_uscript_tmds = -1;
  62. module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  63. MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  64. int nouveau_ignorelid = 0;
  65. module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  66. MODULE_PARM_DESC(noaccel, "Disable all acceleration");
  67. int nouveau_noaccel = -1;
  68. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  69. MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
  70. int nouveau_nofbaccel = 0;
  71. module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  72. MODULE_PARM_DESC(force_post, "Force POST");
  73. int nouveau_force_post = 0;
  74. module_param_named(force_post, nouveau_force_post, int, 0400);
  75. MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
  76. int nouveau_override_conntype = 0;
  77. module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
  78. MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
  79. int nouveau_tv_disable = 0;
  80. module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
  81. MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  82. "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  83. "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  84. "\t\tDefault: PAL\n"
  85. "\t\t*NOTE* Ignored for cards with external TV encoders.");
  86. char *nouveau_tv_norm;
  87. module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  88. MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  89. "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  90. "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  91. "\t\t0x100 vgaattr, 0x200 EVO (G80+)");
  92. int nouveau_reg_debug;
  93. module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  94. MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
  95. char *nouveau_perflvl;
  96. module_param_named(perflvl, nouveau_perflvl, charp, 0400);
  97. MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
  98. int nouveau_perflvl_wr;
  99. module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
  100. MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
  101. int nouveau_msi;
  102. module_param_named(msi, nouveau_msi, int, 0400);
  103. MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
  104. int nouveau_ctxfw;
  105. module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  106. MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
  107. int nouveau_mxmdcb = 1;
  108. module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
  109. int nouveau_fbpercrtc;
  110. #if 0
  111. module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  112. #endif
  113. static struct drm_driver driver;
  114. int __devinit
  115. nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  116. {
  117. return drm_get_pci_dev(pdev, ent, &driver);
  118. }
  119. void
  120. nouveau_pci_remove(struct pci_dev *pdev)
  121. {
  122. struct drm_device *dev = pci_get_drvdata(pdev);
  123. drm_put_dev(dev);
  124. }
  125. int
  126. nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
  127. {
  128. struct drm_device *dev = pci_get_drvdata(pdev);
  129. struct drm_nouveau_private *dev_priv = dev->dev_private;
  130. struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  131. struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
  132. struct nouveau_channel *chan;
  133. struct drm_crtc *crtc;
  134. int ret, i, e;
  135. NV_INFO(dev, "Disabling display...\n");
  136. nouveau_display_fini(dev);
  137. NV_INFO(dev, "Disabling fbcon...\n");
  138. nouveau_fbcon_set_suspend(dev, 1);
  139. NV_INFO(dev, "Unpinning framebuffer(s)...\n");
  140. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  141. struct nouveau_framebuffer *nouveau_fb;
  142. nouveau_fb = nouveau_framebuffer(crtc->fb);
  143. if (!nouveau_fb || !nouveau_fb->nvbo)
  144. continue;
  145. nouveau_bo_unpin(nouveau_fb->nvbo);
  146. }
  147. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  148. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  149. nouveau_bo_unmap(nv_crtc->cursor.nvbo);
  150. nouveau_bo_unpin(nv_crtc->cursor.nvbo);
  151. }
  152. NV_INFO(dev, "Evicting buffers...\n");
  153. ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  154. NV_INFO(dev, "Idling channels...\n");
  155. for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
  156. chan = dev_priv->channels.ptr[i];
  157. if (chan && chan->pushbuf_bo)
  158. nouveau_channel_idle(chan);
  159. }
  160. for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
  161. if (!dev_priv->eng[e])
  162. continue;
  163. ret = dev_priv->eng[e]->fini(dev, e, true);
  164. if (ret) {
  165. NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
  166. goto out_abort;
  167. }
  168. }
  169. ret = pinstmem->suspend(dev);
  170. if (ret) {
  171. NV_ERROR(dev, "... failed: %d\n", ret);
  172. goto out_abort;
  173. }
  174. NV_INFO(dev, "Suspending GPU objects...\n");
  175. ret = nouveau_gpuobj_suspend(dev);
  176. if (ret) {
  177. NV_ERROR(dev, "... failed: %d\n", ret);
  178. pinstmem->resume(dev);
  179. goto out_abort;
  180. }
  181. nouveau_agp_fini(dev);
  182. return 0;
  183. out_abort:
  184. NV_INFO(dev, "Re-enabling acceleration..\n");
  185. for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
  186. if (dev_priv->eng[e])
  187. dev_priv->eng[e]->init(dev, e);
  188. }
  189. return ret;
  190. }
  191. int
  192. nouveau_pci_resume(struct pci_dev *pdev)
  193. {
  194. struct drm_device *dev = pci_get_drvdata(pdev);
  195. struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
  196. struct drm_nouveau_private *dev_priv = dev->dev_private;
  197. struct nouveau_engine *engine = &dev_priv->engine;
  198. struct drm_crtc *crtc;
  199. int ret, i;
  200. /* Make sure the AGP controller is in a consistent state */
  201. nouveau_agp_reset(dev);
  202. /* Make the CRTCs accessible */
  203. engine->display.early_init(dev);
  204. NV_INFO(dev, "POSTing device...\n");
  205. ret = nouveau_run_vbios_init(dev);
  206. if (ret)
  207. return ret;
  208. nouveau_agp_init(dev);
  209. NV_INFO(dev, "Restoring GPU objects...\n");
  210. nouveau_gpuobj_resume(dev);
  211. NV_INFO(dev, "Reinitialising engines...\n");
  212. engine->instmem.resume(dev);
  213. engine->mc.init(dev);
  214. engine->timer.init(dev);
  215. engine->fb.init(dev);
  216. for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
  217. if (dev_priv->eng[i])
  218. dev_priv->eng[i]->init(dev, i);
  219. }
  220. nouveau_irq_postinstall(dev);
  221. /* Re-write SKIPS, they'll have been lost over the suspend */
  222. if (nouveau_vram_pushbuf) {
  223. struct nouveau_channel *chan;
  224. int j;
  225. for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
  226. chan = dev_priv->channels.ptr[i];
  227. if (!chan || !chan->pushbuf_bo)
  228. continue;
  229. for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
  230. nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
  231. }
  232. }
  233. nouveau_pm_resume(dev);
  234. NV_INFO(dev, "Restoring mode...\n");
  235. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  236. struct nouveau_framebuffer *nouveau_fb;
  237. nouveau_fb = nouveau_framebuffer(crtc->fb);
  238. if (!nouveau_fb || !nouveau_fb->nvbo)
  239. continue;
  240. nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
  241. }
  242. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  243. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  244. ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
  245. if (!ret)
  246. ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
  247. if (ret)
  248. NV_ERROR(dev, "Could not pin/map cursor.\n");
  249. }
  250. nouveau_fbcon_set_suspend(dev, 0);
  251. nouveau_fbcon_zfill_all(dev);
  252. nouveau_display_init(dev);
  253. /* Force CLUT to get re-loaded during modeset */
  254. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  255. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  256. nv_crtc->lut.depth = 0;
  257. }
  258. drm_helper_resume_force_mode(dev);
  259. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  260. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  261. u32 offset = nv_crtc->cursor.nvbo->bo.offset;
  262. nv_crtc->cursor.set_offset(nv_crtc, offset);
  263. nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
  264. nv_crtc->cursor_saved_y);
  265. }
  266. return 0;
  267. }
  268. static struct drm_ioctl_desc nouveau_ioctls[] = {
  269. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
  270. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  271. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
  272. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
  273. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
  274. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
  275. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
  276. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
  277. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
  278. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
  279. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
  280. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
  281. };
  282. static const struct file_operations nouveau_driver_fops = {
  283. .owner = THIS_MODULE,
  284. .open = drm_open,
  285. .release = drm_release,
  286. .unlocked_ioctl = drm_ioctl,
  287. .mmap = nouveau_ttm_mmap,
  288. .poll = drm_poll,
  289. .fasync = drm_fasync,
  290. .read = drm_read,
  291. #if defined(CONFIG_COMPAT)
  292. .compat_ioctl = nouveau_compat_ioctl,
  293. #endif
  294. .llseek = noop_llseek,
  295. };
  296. int nouveau_drm_load(struct drm_device *, unsigned long);
  297. int nouveau_drm_unload(struct drm_device *);
  298. static struct drm_driver driver = {
  299. .driver_features =
  300. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  301. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
  302. DRIVER_MODESET | DRIVER_PRIME,
  303. .load = nouveau_drm_load,
  304. .firstopen = nouveau_firstopen,
  305. .lastclose = nouveau_lastclose,
  306. .unload = nouveau_drm_unload,
  307. .open = nouveau_open,
  308. .preclose = nouveau_preclose,
  309. .postclose = nouveau_postclose,
  310. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  311. .debugfs_init = nouveau_debugfs_init,
  312. .debugfs_cleanup = nouveau_debugfs_takedown,
  313. #endif
  314. .irq_preinstall = nouveau_irq_preinstall,
  315. .irq_postinstall = nouveau_irq_postinstall,
  316. .irq_uninstall = nouveau_irq_uninstall,
  317. .irq_handler = nouveau_irq_handler,
  318. .get_vblank_counter = drm_vblank_count,
  319. .enable_vblank = nouveau_vblank_enable,
  320. .disable_vblank = nouveau_vblank_disable,
  321. .ioctls = nouveau_ioctls,
  322. .fops = &nouveau_driver_fops,
  323. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  324. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  325. .gem_prime_export = nouveau_gem_prime_export,
  326. .gem_prime_import = nouveau_gem_prime_import,
  327. .gem_init_object = nouveau_gem_object_new,
  328. .gem_free_object = nouveau_gem_object_del,
  329. .gem_open_object = nouveau_gem_object_open,
  330. .gem_close_object = nouveau_gem_object_close,
  331. .dumb_create = nouveau_display_dumb_create,
  332. .dumb_map_offset = nouveau_display_dumb_map_offset,
  333. .dumb_destroy = nouveau_display_dumb_destroy,
  334. .name = DRIVER_NAME,
  335. .desc = DRIVER_DESC,
  336. #ifdef GIT_REVISION
  337. .date = GIT_REVISION,
  338. #else
  339. .date = DRIVER_DATE,
  340. #endif
  341. .major = DRIVER_MAJOR,
  342. .minor = DRIVER_MINOR,
  343. .patchlevel = DRIVER_PATCHLEVEL,
  344. };
  345. int __init nouveau_init(struct pci_driver *pdrv)
  346. {
  347. driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
  348. if (nouveau_modeset == -1) {
  349. #ifdef CONFIG_VGA_CONSOLE
  350. if (vgacon_text_force())
  351. nouveau_modeset = 0;
  352. else
  353. #endif
  354. nouveau_modeset = 1;
  355. }
  356. if (!nouveau_modeset)
  357. return 0;
  358. nouveau_register_dsm_handler();
  359. return drm_pci_init(&driver, pdrv);
  360. }
  361. void __exit nouveau_exit(struct pci_driver *pdrv)
  362. {
  363. if (!nouveau_modeset)
  364. return;
  365. drm_pci_exit(&driver, pdrv);
  366. nouveau_unregister_dsm_handler();
  367. }