atmel-mci.c 27 KB

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  1. /*
  2. * Atmel MultiMedia Card Interface driver
  3. *
  4. * Copyright (C) 2004-2008 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/blkdev.h>
  11. #include <linux/clk.h>
  12. #include <linux/debugfs.h>
  13. #include <linux/device.h>
  14. #include <linux/err.h>
  15. #include <linux/gpio.h>
  16. #include <linux/init.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/ioport.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/scatterlist.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/stat.h>
  24. #include <linux/mmc/host.h>
  25. #include <asm/atmel-mci.h>
  26. #include <asm/io.h>
  27. #include <asm/unaligned.h>
  28. #include <mach/board.h>
  29. #include "atmel-mci-regs.h"
  30. #define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE)
  31. enum {
  32. EVENT_CMD_COMPLETE = 0,
  33. EVENT_XFER_COMPLETE,
  34. EVENT_DATA_COMPLETE,
  35. EVENT_DATA_ERROR,
  36. };
  37. enum atmel_mci_state {
  38. STATE_SENDING_CMD = 0,
  39. STATE_SENDING_DATA,
  40. STATE_DATA_BUSY,
  41. STATE_SENDING_STOP,
  42. STATE_DATA_ERROR,
  43. };
  44. struct atmel_mci {
  45. struct mmc_host *mmc;
  46. void __iomem *regs;
  47. struct scatterlist *sg;
  48. unsigned int pio_offset;
  49. struct mmc_request *mrq;
  50. struct mmc_command *cmd;
  51. struct mmc_data *data;
  52. u32 cmd_status;
  53. u32 data_status;
  54. u32 stop_cmdr;
  55. u32 mode_reg;
  56. u32 sdc_reg;
  57. struct tasklet_struct tasklet;
  58. unsigned long pending_events;
  59. unsigned long completed_events;
  60. enum atmel_mci_state state;
  61. int present;
  62. int detect_pin;
  63. int wp_pin;
  64. /* For detect pin debouncing */
  65. struct timer_list detect_timer;
  66. unsigned long bus_hz;
  67. unsigned long mapbase;
  68. struct clk *mck;
  69. struct platform_device *pdev;
  70. };
  71. #define atmci_test_and_clear_pending(host, event) \
  72. test_and_clear_bit(event, &host->pending_events)
  73. #define atmci_set_completed(host, event) \
  74. set_bit(event, &host->completed_events)
  75. #define atmci_set_pending(host, event) \
  76. set_bit(event, &host->pending_events)
  77. /*
  78. * The debugfs stuff below is mostly optimized away when
  79. * CONFIG_DEBUG_FS is not set.
  80. */
  81. static int atmci_req_show(struct seq_file *s, void *v)
  82. {
  83. struct atmel_mci *host = s->private;
  84. struct mmc_request *mrq = host->mrq;
  85. struct mmc_command *cmd;
  86. struct mmc_command *stop;
  87. struct mmc_data *data;
  88. /* Make sure we get a consistent snapshot */
  89. spin_lock_irq(&host->mmc->lock);
  90. if (mrq) {
  91. cmd = mrq->cmd;
  92. data = mrq->data;
  93. stop = mrq->stop;
  94. if (cmd)
  95. seq_printf(s,
  96. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  97. cmd->opcode, cmd->arg, cmd->flags,
  98. cmd->resp[0], cmd->resp[1], cmd->resp[2],
  99. cmd->resp[2], cmd->error);
  100. if (data)
  101. seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
  102. data->bytes_xfered, data->blocks,
  103. data->blksz, data->flags, data->error);
  104. if (stop)
  105. seq_printf(s,
  106. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  107. stop->opcode, stop->arg, stop->flags,
  108. stop->resp[0], stop->resp[1], stop->resp[2],
  109. stop->resp[2], stop->error);
  110. }
  111. spin_unlock_irq(&host->mmc->lock);
  112. return 0;
  113. }
  114. static int atmci_req_open(struct inode *inode, struct file *file)
  115. {
  116. return single_open(file, atmci_req_show, inode->i_private);
  117. }
  118. static const struct file_operations atmci_req_fops = {
  119. .owner = THIS_MODULE,
  120. .open = atmci_req_open,
  121. .read = seq_read,
  122. .llseek = seq_lseek,
  123. .release = single_release,
  124. };
  125. static void atmci_show_status_reg(struct seq_file *s,
  126. const char *regname, u32 value)
  127. {
  128. static const char *sr_bit[] = {
  129. [0] = "CMDRDY",
  130. [1] = "RXRDY",
  131. [2] = "TXRDY",
  132. [3] = "BLKE",
  133. [4] = "DTIP",
  134. [5] = "NOTBUSY",
  135. [8] = "SDIOIRQA",
  136. [9] = "SDIOIRQB",
  137. [16] = "RINDE",
  138. [17] = "RDIRE",
  139. [18] = "RCRCE",
  140. [19] = "RENDE",
  141. [20] = "RTOE",
  142. [21] = "DCRCE",
  143. [22] = "DTOE",
  144. [30] = "OVRE",
  145. [31] = "UNRE",
  146. };
  147. unsigned int i;
  148. seq_printf(s, "%s:\t0x%08x", regname, value);
  149. for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
  150. if (value & (1 << i)) {
  151. if (sr_bit[i])
  152. seq_printf(s, " %s", sr_bit[i]);
  153. else
  154. seq_puts(s, " UNKNOWN");
  155. }
  156. }
  157. seq_putc(s, '\n');
  158. }
  159. static int atmci_regs_show(struct seq_file *s, void *v)
  160. {
  161. struct atmel_mci *host = s->private;
  162. u32 *buf;
  163. buf = kmalloc(MCI_REGS_SIZE, GFP_KERNEL);
  164. if (!buf)
  165. return -ENOMEM;
  166. /* Grab a more or less consistent snapshot */
  167. spin_lock_irq(&host->mmc->lock);
  168. clk_enable(host->mck);
  169. memcpy_fromio(buf, host->regs, MCI_REGS_SIZE);
  170. clk_disable(host->mck);
  171. spin_unlock_irq(&host->mmc->lock);
  172. seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
  173. buf[MCI_MR / 4],
  174. buf[MCI_MR / 4] & MCI_MR_RDPROOF ? " RDPROOF" : "",
  175. buf[MCI_MR / 4] & MCI_MR_WRPROOF ? " WRPROOF" : "",
  176. buf[MCI_MR / 4] & 0xff);
  177. seq_printf(s, "DTOR:\t0x%08x\n", buf[MCI_DTOR / 4]);
  178. seq_printf(s, "SDCR:\t0x%08x\n", buf[MCI_SDCR / 4]);
  179. seq_printf(s, "ARGR:\t0x%08x\n", buf[MCI_ARGR / 4]);
  180. seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
  181. buf[MCI_BLKR / 4],
  182. buf[MCI_BLKR / 4] & 0xffff,
  183. (buf[MCI_BLKR / 4] >> 16) & 0xffff);
  184. /* Don't read RSPR and RDR; it will consume the data there */
  185. atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]);
  186. atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]);
  187. kfree(buf);
  188. return 0;
  189. }
  190. static int atmci_regs_open(struct inode *inode, struct file *file)
  191. {
  192. return single_open(file, atmci_regs_show, inode->i_private);
  193. }
  194. static const struct file_operations atmci_regs_fops = {
  195. .owner = THIS_MODULE,
  196. .open = atmci_regs_open,
  197. .read = seq_read,
  198. .llseek = seq_lseek,
  199. .release = single_release,
  200. };
  201. static void atmci_init_debugfs(struct atmel_mci *host)
  202. {
  203. struct mmc_host *mmc;
  204. struct dentry *root;
  205. struct dentry *node;
  206. mmc = host->mmc;
  207. root = mmc->debugfs_root;
  208. if (!root)
  209. return;
  210. node = debugfs_create_file("regs", S_IRUSR, root, host,
  211. &atmci_regs_fops);
  212. if (IS_ERR(node))
  213. return;
  214. if (!node)
  215. goto err;
  216. node = debugfs_create_file("req", S_IRUSR, root, host, &atmci_req_fops);
  217. if (!node)
  218. goto err;
  219. node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
  220. if (!node)
  221. goto err;
  222. node = debugfs_create_x32("pending_events", S_IRUSR, root,
  223. (u32 *)&host->pending_events);
  224. if (!node)
  225. goto err;
  226. node = debugfs_create_x32("completed_events", S_IRUSR, root,
  227. (u32 *)&host->completed_events);
  228. if (!node)
  229. goto err;
  230. return;
  231. err:
  232. dev_err(&host->pdev->dev,
  233. "failed to initialize debugfs for controller\n");
  234. }
  235. static inline unsigned int ns_to_clocks(struct atmel_mci *host,
  236. unsigned int ns)
  237. {
  238. return (ns * (host->bus_hz / 1000000) + 999) / 1000;
  239. }
  240. static void atmci_set_timeout(struct atmel_mci *host,
  241. struct mmc_data *data)
  242. {
  243. static unsigned dtomul_to_shift[] = {
  244. 0, 4, 7, 8, 10, 12, 16, 20
  245. };
  246. unsigned timeout;
  247. unsigned dtocyc;
  248. unsigned dtomul;
  249. timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
  250. for (dtomul = 0; dtomul < 8; dtomul++) {
  251. unsigned shift = dtomul_to_shift[dtomul];
  252. dtocyc = (timeout + (1 << shift) - 1) >> shift;
  253. if (dtocyc < 15)
  254. break;
  255. }
  256. if (dtomul >= 8) {
  257. dtomul = 7;
  258. dtocyc = 15;
  259. }
  260. dev_vdbg(&host->mmc->class_dev, "setting timeout to %u cycles\n",
  261. dtocyc << dtomul_to_shift[dtomul]);
  262. mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc)));
  263. }
  264. /*
  265. * Return mask with command flags to be enabled for this command.
  266. */
  267. static u32 atmci_prepare_command(struct mmc_host *mmc,
  268. struct mmc_command *cmd)
  269. {
  270. struct mmc_data *data;
  271. u32 cmdr;
  272. cmd->error = -EINPROGRESS;
  273. cmdr = MCI_CMDR_CMDNB(cmd->opcode);
  274. if (cmd->flags & MMC_RSP_PRESENT) {
  275. if (cmd->flags & MMC_RSP_136)
  276. cmdr |= MCI_CMDR_RSPTYP_136BIT;
  277. else
  278. cmdr |= MCI_CMDR_RSPTYP_48BIT;
  279. }
  280. /*
  281. * This should really be MAXLAT_5 for CMD2 and ACMD41, but
  282. * it's too difficult to determine whether this is an ACMD or
  283. * not. Better make it 64.
  284. */
  285. cmdr |= MCI_CMDR_MAXLAT_64CYC;
  286. if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
  287. cmdr |= MCI_CMDR_OPDCMD;
  288. data = cmd->data;
  289. if (data) {
  290. cmdr |= MCI_CMDR_START_XFER;
  291. if (data->flags & MMC_DATA_STREAM)
  292. cmdr |= MCI_CMDR_STREAM;
  293. else if (data->blocks > 1)
  294. cmdr |= MCI_CMDR_MULTI_BLOCK;
  295. else
  296. cmdr |= MCI_CMDR_BLOCK;
  297. if (data->flags & MMC_DATA_READ)
  298. cmdr |= MCI_CMDR_TRDIR_READ;
  299. }
  300. return cmdr;
  301. }
  302. static void atmci_start_command(struct atmel_mci *host,
  303. struct mmc_command *cmd,
  304. u32 cmd_flags)
  305. {
  306. WARN_ON(host->cmd);
  307. host->cmd = cmd;
  308. dev_vdbg(&host->mmc->class_dev,
  309. "start command: ARGR=0x%08x CMDR=0x%08x\n",
  310. cmd->arg, cmd_flags);
  311. mci_writel(host, ARGR, cmd->arg);
  312. mci_writel(host, CMDR, cmd_flags);
  313. }
  314. static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data)
  315. {
  316. struct atmel_mci *host = mmc_priv(mmc);
  317. atmci_start_command(host, data->stop, host->stop_cmdr);
  318. mci_writel(host, IER, MCI_CMDRDY);
  319. }
  320. static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
  321. {
  322. struct atmel_mci *host = mmc_priv(mmc);
  323. WARN_ON(host->cmd || host->data);
  324. host->mrq = NULL;
  325. mmc_request_done(mmc, mrq);
  326. }
  327. /*
  328. * Returns a mask of interrupt flags to be enabled after the whole
  329. * request has been prepared.
  330. */
  331. static u32 atmci_submit_data(struct mmc_host *mmc, struct mmc_data *data)
  332. {
  333. struct atmel_mci *host = mmc_priv(mmc);
  334. u32 iflags;
  335. data->error = -EINPROGRESS;
  336. WARN_ON(host->data);
  337. host->sg = NULL;
  338. host->data = data;
  339. dev_vdbg(&mmc->class_dev, "BLKR=0x%08x\n",
  340. MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
  341. iflags = ATMCI_DATA_ERROR_FLAGS;
  342. host->sg = data->sg;
  343. host->pio_offset = 0;
  344. if (data->flags & MMC_DATA_READ)
  345. iflags |= MCI_RXRDY;
  346. else
  347. iflags |= MCI_TXRDY;
  348. return iflags;
  349. }
  350. static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  351. {
  352. struct atmel_mci *host = mmc_priv(mmc);
  353. struct mmc_data *data;
  354. struct mmc_command *cmd;
  355. u32 iflags;
  356. u32 cmdflags = 0;
  357. iflags = mci_readl(host, IMR);
  358. if (iflags)
  359. dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n",
  360. mci_readl(host, IMR));
  361. WARN_ON(host->mrq != NULL);
  362. /*
  363. * We may "know" the card is gone even though there's still an
  364. * electrical connection. If so, we really need to communicate
  365. * this to the MMC core since there won't be any more
  366. * interrupts as the card is completely removed. Otherwise,
  367. * the MMC core might believe the card is still there even
  368. * though the card was just removed very slowly.
  369. */
  370. if (!host->present) {
  371. mrq->cmd->error = -ENOMEDIUM;
  372. mmc_request_done(mmc, mrq);
  373. return;
  374. }
  375. host->mrq = mrq;
  376. host->pending_events = 0;
  377. host->completed_events = 0;
  378. host->state = STATE_SENDING_CMD;
  379. /* We don't support multiple blocks of weird lengths. */
  380. data = mrq->data;
  381. if (data) {
  382. if (data->blocks > 1 && data->blksz & 3)
  383. goto fail;
  384. atmci_set_timeout(host, data);
  385. /* Must set block count/size before sending command */
  386. mci_writel(host, BLKR, MCI_BCNT(data->blocks)
  387. | MCI_BLKLEN(data->blksz));
  388. }
  389. iflags = MCI_CMDRDY;
  390. cmd = mrq->cmd;
  391. cmdflags = atmci_prepare_command(mmc, cmd);
  392. atmci_start_command(host, cmd, cmdflags);
  393. if (data)
  394. iflags |= atmci_submit_data(mmc, data);
  395. if (mrq->stop) {
  396. host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop);
  397. host->stop_cmdr |= MCI_CMDR_STOP_XFER;
  398. if (!(data->flags & MMC_DATA_WRITE))
  399. host->stop_cmdr |= MCI_CMDR_TRDIR_READ;
  400. if (data->flags & MMC_DATA_STREAM)
  401. host->stop_cmdr |= MCI_CMDR_STREAM;
  402. else
  403. host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK;
  404. }
  405. /*
  406. * We could have enabled interrupts earlier, but I suspect
  407. * that would open up a nice can of interesting race
  408. * conditions (e.g. command and data complete, but stop not
  409. * prepared yet.)
  410. */
  411. mci_writel(host, IER, iflags);
  412. return;
  413. fail:
  414. host->mrq = NULL;
  415. mrq->cmd->error = -EINVAL;
  416. mmc_request_done(mmc, mrq);
  417. }
  418. static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  419. {
  420. struct atmel_mci *host = mmc_priv(mmc);
  421. switch (ios->bus_width) {
  422. case MMC_BUS_WIDTH_1:
  423. host->sdc_reg = 0;
  424. break;
  425. case MMC_BUS_WIDTH_4:
  426. host->sdc_reg = MCI_SDCBUS_4BIT;
  427. break;
  428. }
  429. if (ios->clock) {
  430. u32 clkdiv;
  431. if (!host->mode_reg)
  432. clk_enable(host->mck);
  433. /* Set clock rate */
  434. clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * ios->clock) - 1;
  435. if (clkdiv > 255) {
  436. dev_warn(&mmc->class_dev,
  437. "clock %u too slow; using %lu\n",
  438. ios->clock, host->bus_hz / (2 * 256));
  439. clkdiv = 255;
  440. }
  441. host->mode_reg = MCI_MR_CLKDIV(clkdiv) | MCI_MR_WRPROOF
  442. | MCI_MR_RDPROOF;
  443. mci_writel(host, CR, MCI_CR_MCIEN);
  444. mci_writel(host, MR, host->mode_reg);
  445. mci_writel(host, SDCR, host->sdc_reg);
  446. } else {
  447. mci_writel(host, CR, MCI_CR_MCIDIS);
  448. if (host->mode_reg) {
  449. mci_readl(host, MR);
  450. clk_disable(host->mck);
  451. }
  452. host->mode_reg = 0;
  453. }
  454. switch (ios->power_mode) {
  455. default:
  456. /*
  457. * TODO: None of the currently available AVR32-based
  458. * boards allow MMC power to be turned off. Implement
  459. * power control when this can be tested properly.
  460. */
  461. break;
  462. }
  463. }
  464. static int atmci_get_ro(struct mmc_host *mmc)
  465. {
  466. int read_only = 0;
  467. struct atmel_mci *host = mmc_priv(mmc);
  468. if (gpio_is_valid(host->wp_pin)) {
  469. read_only = gpio_get_value(host->wp_pin);
  470. dev_dbg(&mmc->class_dev, "card is %s\n",
  471. read_only ? "read-only" : "read-write");
  472. } else {
  473. dev_dbg(&mmc->class_dev,
  474. "no pin for checking read-only switch."
  475. " Assuming write-enable.\n");
  476. }
  477. return read_only;
  478. }
  479. static struct mmc_host_ops atmci_ops = {
  480. .request = atmci_request,
  481. .set_ios = atmci_set_ios,
  482. .get_ro = atmci_get_ro,
  483. };
  484. static void atmci_command_complete(struct atmel_mci *host,
  485. struct mmc_command *cmd)
  486. {
  487. u32 status = host->cmd_status;
  488. /* Read the response from the card (up to 16 bytes) */
  489. cmd->resp[0] = mci_readl(host, RSPR);
  490. cmd->resp[1] = mci_readl(host, RSPR);
  491. cmd->resp[2] = mci_readl(host, RSPR);
  492. cmd->resp[3] = mci_readl(host, RSPR);
  493. if (status & MCI_RTOE)
  494. cmd->error = -ETIMEDOUT;
  495. else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE))
  496. cmd->error = -EILSEQ;
  497. else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE))
  498. cmd->error = -EIO;
  499. else
  500. cmd->error = 0;
  501. if (cmd->error) {
  502. dev_dbg(&host->mmc->class_dev,
  503. "command error: status=0x%08x\n", status);
  504. if (cmd->data) {
  505. host->data = NULL;
  506. mci_writel(host, IDR, MCI_NOTBUSY
  507. | MCI_TXRDY | MCI_RXRDY
  508. | ATMCI_DATA_ERROR_FLAGS);
  509. }
  510. }
  511. }
  512. static void atmci_detect_change(unsigned long data)
  513. {
  514. struct atmel_mci *host = (struct atmel_mci *)data;
  515. struct mmc_request *mrq = host->mrq;
  516. int present;
  517. /*
  518. * atmci_remove() sets detect_pin to -1 before freeing the
  519. * interrupt. We must not re-enable the interrupt if it has
  520. * been freed.
  521. */
  522. smp_rmb();
  523. if (!gpio_is_valid(host->detect_pin))
  524. return;
  525. enable_irq(gpio_to_irq(host->detect_pin));
  526. present = !gpio_get_value(host->detect_pin);
  527. dev_vdbg(&host->pdev->dev, "detect change: %d (was %d)\n",
  528. present, host->present);
  529. if (present != host->present) {
  530. dev_dbg(&host->mmc->class_dev, "card %s\n",
  531. present ? "inserted" : "removed");
  532. host->present = present;
  533. /* Reset controller if card is gone */
  534. if (!present) {
  535. mci_writel(host, CR, MCI_CR_SWRST);
  536. mci_writel(host, IDR, ~0UL);
  537. mci_writel(host, CR, MCI_CR_MCIEN);
  538. }
  539. /* Clean up queue if present */
  540. if (mrq) {
  541. /*
  542. * Reset controller to terminate any ongoing
  543. * commands or data transfers.
  544. */
  545. mci_writel(host, CR, MCI_CR_SWRST);
  546. mci_readl(host, SR);
  547. host->data = NULL;
  548. host->cmd = NULL;
  549. switch (host->state) {
  550. case STATE_SENDING_CMD:
  551. mrq->cmd->error = -ENOMEDIUM;
  552. if (!mrq->data)
  553. break;
  554. /* fall through */
  555. case STATE_SENDING_DATA:
  556. mrq->data->error = -ENOMEDIUM;
  557. break;
  558. case STATE_DATA_BUSY:
  559. case STATE_DATA_ERROR:
  560. if (mrq->data->error == -EINPROGRESS)
  561. mrq->data->error = -ENOMEDIUM;
  562. if (!mrq->stop)
  563. break;
  564. /* fall through */
  565. case STATE_SENDING_STOP:
  566. mrq->stop->error = -ENOMEDIUM;
  567. break;
  568. }
  569. atmci_request_end(host->mmc, mrq);
  570. }
  571. mmc_detect_change(host->mmc, 0);
  572. }
  573. }
  574. static void atmci_tasklet_func(unsigned long priv)
  575. {
  576. struct mmc_host *mmc = (struct mmc_host *)priv;
  577. struct atmel_mci *host = mmc_priv(mmc);
  578. struct mmc_request *mrq = host->mrq;
  579. struct mmc_data *data = host->data;
  580. struct mmc_command *cmd = host->cmd;
  581. enum atmel_mci_state state = host->state;
  582. enum atmel_mci_state prev_state;
  583. u32 status;
  584. state = host->state;
  585. dev_vdbg(&mmc->class_dev,
  586. "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
  587. state, host->pending_events, host->completed_events,
  588. mci_readl(host, IMR));
  589. do {
  590. prev_state = state;
  591. switch (state) {
  592. case STATE_SENDING_CMD:
  593. if (!atmci_test_and_clear_pending(host,
  594. EVENT_CMD_COMPLETE))
  595. break;
  596. host->cmd = NULL;
  597. atmci_set_completed(host, EVENT_CMD_COMPLETE);
  598. atmci_command_complete(host, mrq->cmd);
  599. if (!mrq->data || cmd->error) {
  600. atmci_request_end(mmc, host->mrq);
  601. break;
  602. }
  603. prev_state = state = STATE_SENDING_DATA;
  604. /* fall through */
  605. case STATE_SENDING_DATA:
  606. if (atmci_test_and_clear_pending(host,
  607. EVENT_DATA_ERROR)) {
  608. if (data->stop)
  609. send_stop_cmd(host->mmc, data);
  610. state = STATE_DATA_ERROR;
  611. break;
  612. }
  613. if (!atmci_test_and_clear_pending(host,
  614. EVENT_XFER_COMPLETE))
  615. break;
  616. atmci_set_completed(host, EVENT_XFER_COMPLETE);
  617. prev_state = state = STATE_DATA_BUSY;
  618. /* fall through */
  619. case STATE_DATA_BUSY:
  620. if (!atmci_test_and_clear_pending(host,
  621. EVENT_DATA_COMPLETE))
  622. break;
  623. host->data = NULL;
  624. atmci_set_completed(host, EVENT_DATA_COMPLETE);
  625. status = host->data_status;
  626. if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
  627. if (status & MCI_DTOE) {
  628. dev_dbg(&mmc->class_dev,
  629. "data timeout error\n");
  630. data->error = -ETIMEDOUT;
  631. } else if (status & MCI_DCRCE) {
  632. dev_dbg(&mmc->class_dev,
  633. "data CRC error\n");
  634. data->error = -EILSEQ;
  635. } else {
  636. dev_dbg(&mmc->class_dev,
  637. "data FIFO error (status=%08x)\n",
  638. status);
  639. data->error = -EIO;
  640. }
  641. } else {
  642. data->bytes_xfered = data->blocks * data->blksz;
  643. data->error = 0;
  644. }
  645. if (!data->stop) {
  646. atmci_request_end(mmc, host->mrq);
  647. prev_state = state;
  648. break;
  649. }
  650. prev_state = state = STATE_SENDING_STOP;
  651. if (!data->error)
  652. send_stop_cmd(host->mmc, data);
  653. /* fall through */
  654. case STATE_SENDING_STOP:
  655. if (!atmci_test_and_clear_pending(host,
  656. EVENT_CMD_COMPLETE))
  657. break;
  658. host->cmd = NULL;
  659. atmci_command_complete(host, mrq->stop);
  660. atmci_request_end(mmc, host->mrq);
  661. prev_state = state;
  662. break;
  663. case STATE_DATA_ERROR:
  664. if (!atmci_test_and_clear_pending(host,
  665. EVENT_XFER_COMPLETE))
  666. break;
  667. state = STATE_DATA_BUSY;
  668. break;
  669. }
  670. } while (state != prev_state);
  671. host->state = state;
  672. }
  673. static void atmci_read_data_pio(struct atmel_mci *host)
  674. {
  675. struct scatterlist *sg = host->sg;
  676. void *buf = sg_virt(sg);
  677. unsigned int offset = host->pio_offset;
  678. struct mmc_data *data = host->data;
  679. u32 value;
  680. u32 status;
  681. unsigned int nbytes = 0;
  682. do {
  683. value = mci_readl(host, RDR);
  684. if (likely(offset + 4 <= sg->length)) {
  685. put_unaligned(value, (u32 *)(buf + offset));
  686. offset += 4;
  687. nbytes += 4;
  688. if (offset == sg->length) {
  689. host->sg = sg = sg_next(sg);
  690. if (!sg)
  691. goto done;
  692. offset = 0;
  693. buf = sg_virt(sg);
  694. }
  695. } else {
  696. unsigned int remaining = sg->length - offset;
  697. memcpy(buf + offset, &value, remaining);
  698. nbytes += remaining;
  699. flush_dcache_page(sg_page(sg));
  700. host->sg = sg = sg_next(sg);
  701. if (!sg)
  702. goto done;
  703. offset = 4 - remaining;
  704. buf = sg_virt(sg);
  705. memcpy(buf, (u8 *)&value + remaining, offset);
  706. nbytes += offset;
  707. }
  708. status = mci_readl(host, SR);
  709. if (status & ATMCI_DATA_ERROR_FLAGS) {
  710. mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY
  711. | ATMCI_DATA_ERROR_FLAGS));
  712. host->data_status = status;
  713. atmci_set_pending(host, EVENT_DATA_ERROR);
  714. tasklet_schedule(&host->tasklet);
  715. break;
  716. }
  717. } while (status & MCI_RXRDY);
  718. host->pio_offset = offset;
  719. data->bytes_xfered += nbytes;
  720. return;
  721. done:
  722. mci_writel(host, IDR, MCI_RXRDY);
  723. mci_writel(host, IER, MCI_NOTBUSY);
  724. data->bytes_xfered += nbytes;
  725. atmci_set_pending(host, EVENT_XFER_COMPLETE);
  726. }
  727. static void atmci_write_data_pio(struct atmel_mci *host)
  728. {
  729. struct scatterlist *sg = host->sg;
  730. void *buf = sg_virt(sg);
  731. unsigned int offset = host->pio_offset;
  732. struct mmc_data *data = host->data;
  733. u32 value;
  734. u32 status;
  735. unsigned int nbytes = 0;
  736. do {
  737. if (likely(offset + 4 <= sg->length)) {
  738. value = get_unaligned((u32 *)(buf + offset));
  739. mci_writel(host, TDR, value);
  740. offset += 4;
  741. nbytes += 4;
  742. if (offset == sg->length) {
  743. host->sg = sg = sg_next(sg);
  744. if (!sg)
  745. goto done;
  746. offset = 0;
  747. buf = sg_virt(sg);
  748. }
  749. } else {
  750. unsigned int remaining = sg->length - offset;
  751. value = 0;
  752. memcpy(&value, buf + offset, remaining);
  753. nbytes += remaining;
  754. host->sg = sg = sg_next(sg);
  755. if (!sg) {
  756. mci_writel(host, TDR, value);
  757. goto done;
  758. }
  759. offset = 4 - remaining;
  760. buf = sg_virt(sg);
  761. memcpy((u8 *)&value + remaining, buf, offset);
  762. mci_writel(host, TDR, value);
  763. nbytes += offset;
  764. }
  765. status = mci_readl(host, SR);
  766. if (status & ATMCI_DATA_ERROR_FLAGS) {
  767. mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY
  768. | ATMCI_DATA_ERROR_FLAGS));
  769. host->data_status = status;
  770. atmci_set_pending(host, EVENT_DATA_ERROR);
  771. tasklet_schedule(&host->tasklet);
  772. break;
  773. }
  774. } while (status & MCI_TXRDY);
  775. host->pio_offset = offset;
  776. data->bytes_xfered += nbytes;
  777. return;
  778. done:
  779. mci_writel(host, IDR, MCI_TXRDY);
  780. mci_writel(host, IER, MCI_NOTBUSY);
  781. data->bytes_xfered += nbytes;
  782. atmci_set_pending(host, EVENT_XFER_COMPLETE);
  783. }
  784. static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
  785. {
  786. struct atmel_mci *host = mmc_priv(mmc);
  787. mci_writel(host, IDR, MCI_CMDRDY);
  788. host->cmd_status = status;
  789. atmci_set_pending(host, EVENT_CMD_COMPLETE);
  790. tasklet_schedule(&host->tasklet);
  791. }
  792. static irqreturn_t atmci_interrupt(int irq, void *dev_id)
  793. {
  794. struct mmc_host *mmc = dev_id;
  795. struct atmel_mci *host = mmc_priv(mmc);
  796. u32 status, mask, pending;
  797. unsigned int pass_count = 0;
  798. spin_lock(&mmc->lock);
  799. do {
  800. status = mci_readl(host, SR);
  801. mask = mci_readl(host, IMR);
  802. pending = status & mask;
  803. if (!pending)
  804. break;
  805. if (pending & ATMCI_DATA_ERROR_FLAGS) {
  806. mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS
  807. | MCI_RXRDY | MCI_TXRDY);
  808. pending &= mci_readl(host, IMR);
  809. host->data_status = status;
  810. atmci_set_pending(host, EVENT_DATA_ERROR);
  811. tasklet_schedule(&host->tasklet);
  812. }
  813. if (pending & MCI_NOTBUSY) {
  814. mci_writel(host, IDR,
  815. ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY);
  816. host->data_status = status;
  817. atmci_set_pending(host, EVENT_DATA_COMPLETE);
  818. tasklet_schedule(&host->tasklet);
  819. }
  820. if (pending & MCI_RXRDY)
  821. atmci_read_data_pio(host);
  822. if (pending & MCI_TXRDY)
  823. atmci_write_data_pio(host);
  824. if (pending & MCI_CMDRDY)
  825. atmci_cmd_interrupt(mmc, status);
  826. } while (pass_count++ < 5);
  827. spin_unlock(&mmc->lock);
  828. return pass_count ? IRQ_HANDLED : IRQ_NONE;
  829. }
  830. static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
  831. {
  832. struct mmc_host *mmc = dev_id;
  833. struct atmel_mci *host = mmc_priv(mmc);
  834. /*
  835. * Disable interrupts until the pin has stabilized and check
  836. * the state then. Use mod_timer() since we may be in the
  837. * middle of the timer routine when this interrupt triggers.
  838. */
  839. disable_irq_nosync(irq);
  840. mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20));
  841. return IRQ_HANDLED;
  842. }
  843. static int __init atmci_probe(struct platform_device *pdev)
  844. {
  845. struct mci_platform_data *pdata;
  846. struct atmel_mci *host;
  847. struct mmc_host *mmc;
  848. struct resource *regs;
  849. int irq;
  850. int ret;
  851. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  852. if (!regs)
  853. return -ENXIO;
  854. pdata = pdev->dev.platform_data;
  855. if (!pdata)
  856. return -ENXIO;
  857. irq = platform_get_irq(pdev, 0);
  858. if (irq < 0)
  859. return irq;
  860. mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
  861. if (!mmc)
  862. return -ENOMEM;
  863. host = mmc_priv(mmc);
  864. host->pdev = pdev;
  865. host->mmc = mmc;
  866. host->detect_pin = pdata->detect_pin;
  867. host->wp_pin = pdata->wp_pin;
  868. host->mck = clk_get(&pdev->dev, "mci_clk");
  869. if (IS_ERR(host->mck)) {
  870. ret = PTR_ERR(host->mck);
  871. goto err_clk_get;
  872. }
  873. ret = -ENOMEM;
  874. host->regs = ioremap(regs->start, regs->end - regs->start + 1);
  875. if (!host->regs)
  876. goto err_ioremap;
  877. clk_enable(host->mck);
  878. mci_writel(host, CR, MCI_CR_SWRST);
  879. host->bus_hz = clk_get_rate(host->mck);
  880. clk_disable(host->mck);
  881. host->mapbase = regs->start;
  882. mmc->ops = &atmci_ops;
  883. mmc->f_min = (host->bus_hz + 511) / 512;
  884. mmc->f_max = host->bus_hz / 2;
  885. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  886. mmc->caps |= MMC_CAP_4_BIT_DATA;
  887. mmc->max_hw_segs = 64;
  888. mmc->max_phys_segs = 64;
  889. mmc->max_req_size = 32768 * 512;
  890. mmc->max_blk_size = 32768;
  891. mmc->max_blk_count = 512;
  892. tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
  893. ret = request_irq(irq, atmci_interrupt, 0, pdev->dev.bus_id, mmc);
  894. if (ret)
  895. goto err_request_irq;
  896. /* Assume card is present if we don't have a detect pin */
  897. host->present = 1;
  898. if (gpio_is_valid(host->detect_pin)) {
  899. if (gpio_request(host->detect_pin, "mmc_detect")) {
  900. dev_dbg(&mmc->class_dev, "no detect pin available\n");
  901. host->detect_pin = -1;
  902. } else {
  903. host->present = !gpio_get_value(host->detect_pin);
  904. }
  905. }
  906. if (!gpio_is_valid(host->detect_pin))
  907. mmc->caps |= MMC_CAP_NEEDS_POLL;
  908. if (gpio_is_valid(host->wp_pin)) {
  909. if (gpio_request(host->wp_pin, "mmc_wp")) {
  910. dev_dbg(&mmc->class_dev, "no WP pin available\n");
  911. host->wp_pin = -1;
  912. }
  913. }
  914. platform_set_drvdata(pdev, host);
  915. mmc_add_host(mmc);
  916. if (gpio_is_valid(host->detect_pin)) {
  917. setup_timer(&host->detect_timer, atmci_detect_change,
  918. (unsigned long)host);
  919. ret = request_irq(gpio_to_irq(host->detect_pin),
  920. atmci_detect_interrupt,
  921. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
  922. "mmc-detect", mmc);
  923. if (ret) {
  924. dev_dbg(&mmc->class_dev,
  925. "could not request IRQ %d for detect pin\n",
  926. gpio_to_irq(host->detect_pin));
  927. gpio_free(host->detect_pin);
  928. host->detect_pin = -1;
  929. }
  930. }
  931. dev_info(&mmc->class_dev,
  932. "Atmel MCI controller at 0x%08lx irq %d\n",
  933. host->mapbase, irq);
  934. atmci_init_debugfs(host);
  935. return 0;
  936. err_request_irq:
  937. iounmap(host->regs);
  938. err_ioremap:
  939. clk_put(host->mck);
  940. err_clk_get:
  941. mmc_free_host(mmc);
  942. return ret;
  943. }
  944. static int __exit atmci_remove(struct platform_device *pdev)
  945. {
  946. struct atmel_mci *host = platform_get_drvdata(pdev);
  947. platform_set_drvdata(pdev, NULL);
  948. if (host) {
  949. /* Debugfs stuff is cleaned up by mmc core */
  950. if (gpio_is_valid(host->detect_pin)) {
  951. int pin = host->detect_pin;
  952. /* Make sure the timer doesn't enable the interrupt */
  953. host->detect_pin = -1;
  954. smp_wmb();
  955. free_irq(gpio_to_irq(pin), host->mmc);
  956. del_timer_sync(&host->detect_timer);
  957. gpio_free(pin);
  958. }
  959. mmc_remove_host(host->mmc);
  960. clk_enable(host->mck);
  961. mci_writel(host, IDR, ~0UL);
  962. mci_writel(host, CR, MCI_CR_MCIDIS);
  963. mci_readl(host, SR);
  964. clk_disable(host->mck);
  965. if (gpio_is_valid(host->wp_pin))
  966. gpio_free(host->wp_pin);
  967. free_irq(platform_get_irq(pdev, 0), host->mmc);
  968. iounmap(host->regs);
  969. clk_put(host->mck);
  970. mmc_free_host(host->mmc);
  971. }
  972. return 0;
  973. }
  974. static struct platform_driver atmci_driver = {
  975. .remove = __exit_p(atmci_remove),
  976. .driver = {
  977. .name = "atmel_mci",
  978. },
  979. };
  980. static int __init atmci_init(void)
  981. {
  982. return platform_driver_probe(&atmci_driver, atmci_probe);
  983. }
  984. static void __exit atmci_exit(void)
  985. {
  986. platform_driver_unregister(&atmci_driver);
  987. }
  988. module_init(atmci_init);
  989. module_exit(atmci_exit);
  990. MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
  991. MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
  992. MODULE_LICENSE("GPL v2");