apply.c 34 KB

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  1. /*
  2. * Copyright (C) 2011 Texas Instruments
  3. * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #define DSS_SUBSYS_NAME "APPLY"
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/jiffies.h>
  23. #include <video/omapdss.h>
  24. #include "dss.h"
  25. #include "dss_features.h"
  26. #include "dispc-compat.h"
  27. /*
  28. * We have 4 levels of cache for the dispc settings. First two are in SW and
  29. * the latter two in HW.
  30. *
  31. * set_info()
  32. * v
  33. * +--------------------+
  34. * | user_info |
  35. * +--------------------+
  36. * v
  37. * apply()
  38. * v
  39. * +--------------------+
  40. * | info |
  41. * +--------------------+
  42. * v
  43. * write_regs()
  44. * v
  45. * +--------------------+
  46. * | shadow registers |
  47. * +--------------------+
  48. * v
  49. * VFP or lcd/digit_enable
  50. * v
  51. * +--------------------+
  52. * | registers |
  53. * +--------------------+
  54. */
  55. struct ovl_priv_data {
  56. bool user_info_dirty;
  57. struct omap_overlay_info user_info;
  58. bool info_dirty;
  59. struct omap_overlay_info info;
  60. bool shadow_info_dirty;
  61. bool extra_info_dirty;
  62. bool shadow_extra_info_dirty;
  63. bool enabled;
  64. u32 fifo_low, fifo_high;
  65. /*
  66. * True if overlay is to be enabled. Used to check and calculate configs
  67. * for the overlay before it is enabled in the HW.
  68. */
  69. bool enabling;
  70. };
  71. struct mgr_priv_data {
  72. bool user_info_dirty;
  73. struct omap_overlay_manager_info user_info;
  74. bool info_dirty;
  75. struct omap_overlay_manager_info info;
  76. bool shadow_info_dirty;
  77. /* If true, GO bit is up and shadow registers cannot be written.
  78. * Never true for manual update displays */
  79. bool busy;
  80. /* If true, dispc output is enabled */
  81. bool updating;
  82. /* If true, a display is enabled using this manager */
  83. bool enabled;
  84. bool extra_info_dirty;
  85. bool shadow_extra_info_dirty;
  86. struct omap_video_timings timings;
  87. struct dss_lcd_mgr_config lcd_config;
  88. void (*framedone_handler)(void *);
  89. void *framedone_handler_data;
  90. };
  91. static struct {
  92. struct ovl_priv_data ovl_priv_data_array[MAX_DSS_OVERLAYS];
  93. struct mgr_priv_data mgr_priv_data_array[MAX_DSS_MANAGERS];
  94. bool irq_enabled;
  95. } dss_data;
  96. /* protects dss_data */
  97. static spinlock_t data_lock;
  98. /* lock for blocking functions */
  99. static DEFINE_MUTEX(apply_lock);
  100. static DECLARE_COMPLETION(extra_updated_completion);
  101. static void dss_register_vsync_isr(void);
  102. static struct ovl_priv_data *get_ovl_priv(struct omap_overlay *ovl)
  103. {
  104. return &dss_data.ovl_priv_data_array[ovl->id];
  105. }
  106. static struct mgr_priv_data *get_mgr_priv(struct omap_overlay_manager *mgr)
  107. {
  108. return &dss_data.mgr_priv_data_array[mgr->id];
  109. }
  110. static void apply_init_priv(void)
  111. {
  112. const int num_ovls = dss_feat_get_num_ovls();
  113. struct mgr_priv_data *mp;
  114. int i;
  115. spin_lock_init(&data_lock);
  116. for (i = 0; i < num_ovls; ++i) {
  117. struct ovl_priv_data *op;
  118. op = &dss_data.ovl_priv_data_array[i];
  119. op->info.global_alpha = 255;
  120. switch (i) {
  121. case 0:
  122. op->info.zorder = 0;
  123. break;
  124. case 1:
  125. op->info.zorder =
  126. dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 3 : 0;
  127. break;
  128. case 2:
  129. op->info.zorder =
  130. dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 2 : 0;
  131. break;
  132. case 3:
  133. op->info.zorder =
  134. dss_has_feature(FEAT_ALPHA_FREE_ZORDER) ? 1 : 0;
  135. break;
  136. }
  137. op->user_info = op->info;
  138. }
  139. /*
  140. * Initialize some of the lcd_config fields for TV manager, this lets
  141. * us prevent checking if the manager is LCD or TV at some places
  142. */
  143. mp = &dss_data.mgr_priv_data_array[OMAP_DSS_CHANNEL_DIGIT];
  144. mp->lcd_config.video_port_width = 24;
  145. mp->lcd_config.clock_info.lck_div = 1;
  146. mp->lcd_config.clock_info.pck_div = 1;
  147. }
  148. /*
  149. * A LCD manager's stallmode decides whether it is in manual or auto update. TV
  150. * manager is always auto update, stallmode field for TV manager is false by
  151. * default
  152. */
  153. static bool ovl_manual_update(struct omap_overlay *ovl)
  154. {
  155. struct mgr_priv_data *mp = get_mgr_priv(ovl->manager);
  156. return mp->lcd_config.stallmode;
  157. }
  158. static bool mgr_manual_update(struct omap_overlay_manager *mgr)
  159. {
  160. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  161. return mp->lcd_config.stallmode;
  162. }
  163. static int dss_check_settings_low(struct omap_overlay_manager *mgr,
  164. bool applying)
  165. {
  166. struct omap_overlay_info *oi;
  167. struct omap_overlay_manager_info *mi;
  168. struct omap_overlay *ovl;
  169. struct omap_overlay_info *ois[MAX_DSS_OVERLAYS];
  170. struct ovl_priv_data *op;
  171. struct mgr_priv_data *mp;
  172. mp = get_mgr_priv(mgr);
  173. if (!mp->enabled)
  174. return 0;
  175. if (applying && mp->user_info_dirty)
  176. mi = &mp->user_info;
  177. else
  178. mi = &mp->info;
  179. /* collect the infos to be tested into the array */
  180. list_for_each_entry(ovl, &mgr->overlays, list) {
  181. op = get_ovl_priv(ovl);
  182. if (!op->enabled && !op->enabling)
  183. oi = NULL;
  184. else if (applying && op->user_info_dirty)
  185. oi = &op->user_info;
  186. else
  187. oi = &op->info;
  188. ois[ovl->id] = oi;
  189. }
  190. return dss_mgr_check(mgr, mi, &mp->timings, &mp->lcd_config, ois);
  191. }
  192. /*
  193. * check manager and overlay settings using overlay_info from data->info
  194. */
  195. static int dss_check_settings(struct omap_overlay_manager *mgr)
  196. {
  197. return dss_check_settings_low(mgr, false);
  198. }
  199. /*
  200. * check manager and overlay settings using overlay_info from ovl->info if
  201. * dirty and from data->info otherwise
  202. */
  203. static int dss_check_settings_apply(struct omap_overlay_manager *mgr)
  204. {
  205. return dss_check_settings_low(mgr, true);
  206. }
  207. static bool need_isr(void)
  208. {
  209. const int num_mgrs = dss_feat_get_num_mgrs();
  210. int i;
  211. for (i = 0; i < num_mgrs; ++i) {
  212. struct omap_overlay_manager *mgr;
  213. struct mgr_priv_data *mp;
  214. struct omap_overlay *ovl;
  215. mgr = omap_dss_get_overlay_manager(i);
  216. mp = get_mgr_priv(mgr);
  217. if (!mp->enabled)
  218. continue;
  219. if (mgr_manual_update(mgr)) {
  220. /* to catch FRAMEDONE */
  221. if (mp->updating)
  222. return true;
  223. } else {
  224. /* to catch GO bit going down */
  225. if (mp->busy)
  226. return true;
  227. /* to write new values to registers */
  228. if (mp->info_dirty)
  229. return true;
  230. /* to set GO bit */
  231. if (mp->shadow_info_dirty)
  232. return true;
  233. /*
  234. * NOTE: we don't check extra_info flags for disabled
  235. * managers, once the manager is enabled, the extra_info
  236. * related manager changes will be taken in by HW.
  237. */
  238. /* to write new values to registers */
  239. if (mp->extra_info_dirty)
  240. return true;
  241. /* to set GO bit */
  242. if (mp->shadow_extra_info_dirty)
  243. return true;
  244. list_for_each_entry(ovl, &mgr->overlays, list) {
  245. struct ovl_priv_data *op;
  246. op = get_ovl_priv(ovl);
  247. /*
  248. * NOTE: we check extra_info flags even for
  249. * disabled overlays, as extra_infos need to be
  250. * always written.
  251. */
  252. /* to write new values to registers */
  253. if (op->extra_info_dirty)
  254. return true;
  255. /* to set GO bit */
  256. if (op->shadow_extra_info_dirty)
  257. return true;
  258. if (!op->enabled)
  259. continue;
  260. /* to write new values to registers */
  261. if (op->info_dirty)
  262. return true;
  263. /* to set GO bit */
  264. if (op->shadow_info_dirty)
  265. return true;
  266. }
  267. }
  268. }
  269. return false;
  270. }
  271. static bool need_go(struct omap_overlay_manager *mgr)
  272. {
  273. struct omap_overlay *ovl;
  274. struct mgr_priv_data *mp;
  275. struct ovl_priv_data *op;
  276. mp = get_mgr_priv(mgr);
  277. if (mp->shadow_info_dirty || mp->shadow_extra_info_dirty)
  278. return true;
  279. list_for_each_entry(ovl, &mgr->overlays, list) {
  280. op = get_ovl_priv(ovl);
  281. if (op->shadow_info_dirty || op->shadow_extra_info_dirty)
  282. return true;
  283. }
  284. return false;
  285. }
  286. /* returns true if an extra_info field is currently being updated */
  287. static bool extra_info_update_ongoing(void)
  288. {
  289. const int num_mgrs = dss_feat_get_num_mgrs();
  290. int i;
  291. for (i = 0; i < num_mgrs; ++i) {
  292. struct omap_overlay_manager *mgr;
  293. struct omap_overlay *ovl;
  294. struct mgr_priv_data *mp;
  295. mgr = omap_dss_get_overlay_manager(i);
  296. mp = get_mgr_priv(mgr);
  297. if (!mp->enabled)
  298. continue;
  299. if (!mp->updating)
  300. continue;
  301. if (mp->extra_info_dirty || mp->shadow_extra_info_dirty)
  302. return true;
  303. list_for_each_entry(ovl, &mgr->overlays, list) {
  304. struct ovl_priv_data *op = get_ovl_priv(ovl);
  305. if (op->extra_info_dirty || op->shadow_extra_info_dirty)
  306. return true;
  307. }
  308. }
  309. return false;
  310. }
  311. /* wait until no extra_info updates are pending */
  312. static void wait_pending_extra_info_updates(void)
  313. {
  314. bool updating;
  315. unsigned long flags;
  316. unsigned long t;
  317. int r;
  318. spin_lock_irqsave(&data_lock, flags);
  319. updating = extra_info_update_ongoing();
  320. if (!updating) {
  321. spin_unlock_irqrestore(&data_lock, flags);
  322. return;
  323. }
  324. init_completion(&extra_updated_completion);
  325. spin_unlock_irqrestore(&data_lock, flags);
  326. t = msecs_to_jiffies(500);
  327. r = wait_for_completion_timeout(&extra_updated_completion, t);
  328. if (r == 0)
  329. DSSWARN("timeout in wait_pending_extra_info_updates\n");
  330. }
  331. static struct omap_dss_device *dss_mgr_get_device(struct omap_overlay_manager *mgr)
  332. {
  333. return mgr->output ? mgr->output->device : NULL;
  334. }
  335. static struct omap_dss_device *dss_ovl_get_device(struct omap_overlay *ovl)
  336. {
  337. return ovl->manager ? dss_mgr_get_device(ovl->manager) : NULL;
  338. }
  339. static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr)
  340. {
  341. unsigned long timeout = msecs_to_jiffies(500);
  342. u32 irq;
  343. int r;
  344. if (mgr->output == NULL)
  345. return -ENODEV;
  346. r = dispc_runtime_get();
  347. if (r)
  348. return r;
  349. switch (mgr->output->id) {
  350. case OMAP_DSS_OUTPUT_VENC:
  351. irq = DISPC_IRQ_EVSYNC_ODD;
  352. break;
  353. case OMAP_DSS_OUTPUT_HDMI:
  354. irq = DISPC_IRQ_EVSYNC_EVEN;
  355. break;
  356. default:
  357. irq = dispc_mgr_get_vsync_irq(mgr->id);
  358. break;
  359. }
  360. r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
  361. dispc_runtime_put();
  362. return r;
  363. }
  364. static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr)
  365. {
  366. unsigned long timeout = msecs_to_jiffies(500);
  367. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  368. u32 irq;
  369. unsigned long flags;
  370. int r;
  371. int i;
  372. spin_lock_irqsave(&data_lock, flags);
  373. if (mgr_manual_update(mgr)) {
  374. spin_unlock_irqrestore(&data_lock, flags);
  375. return 0;
  376. }
  377. if (!mp->enabled) {
  378. spin_unlock_irqrestore(&data_lock, flags);
  379. return 0;
  380. }
  381. spin_unlock_irqrestore(&data_lock, flags);
  382. r = dispc_runtime_get();
  383. if (r)
  384. return r;
  385. irq = dispc_mgr_get_vsync_irq(mgr->id);
  386. i = 0;
  387. while (1) {
  388. bool shadow_dirty, dirty;
  389. spin_lock_irqsave(&data_lock, flags);
  390. dirty = mp->info_dirty;
  391. shadow_dirty = mp->shadow_info_dirty;
  392. spin_unlock_irqrestore(&data_lock, flags);
  393. if (!dirty && !shadow_dirty) {
  394. r = 0;
  395. break;
  396. }
  397. /* 4 iterations is the worst case:
  398. * 1 - initial iteration, dirty = true (between VFP and VSYNC)
  399. * 2 - first VSYNC, dirty = true
  400. * 3 - dirty = false, shadow_dirty = true
  401. * 4 - shadow_dirty = false */
  402. if (i++ == 3) {
  403. DSSERR("mgr(%d)->wait_for_go() not finishing\n",
  404. mgr->id);
  405. r = 0;
  406. break;
  407. }
  408. r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
  409. if (r == -ERESTARTSYS)
  410. break;
  411. if (r) {
  412. DSSERR("mgr(%d)->wait_for_go() timeout\n", mgr->id);
  413. break;
  414. }
  415. }
  416. dispc_runtime_put();
  417. return r;
  418. }
  419. static int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl)
  420. {
  421. unsigned long timeout = msecs_to_jiffies(500);
  422. struct ovl_priv_data *op;
  423. struct mgr_priv_data *mp;
  424. u32 irq;
  425. unsigned long flags;
  426. int r;
  427. int i;
  428. if (!ovl->manager)
  429. return 0;
  430. mp = get_mgr_priv(ovl->manager);
  431. spin_lock_irqsave(&data_lock, flags);
  432. if (ovl_manual_update(ovl)) {
  433. spin_unlock_irqrestore(&data_lock, flags);
  434. return 0;
  435. }
  436. if (!mp->enabled) {
  437. spin_unlock_irqrestore(&data_lock, flags);
  438. return 0;
  439. }
  440. spin_unlock_irqrestore(&data_lock, flags);
  441. r = dispc_runtime_get();
  442. if (r)
  443. return r;
  444. irq = dispc_mgr_get_vsync_irq(ovl->manager->id);
  445. op = get_ovl_priv(ovl);
  446. i = 0;
  447. while (1) {
  448. bool shadow_dirty, dirty;
  449. spin_lock_irqsave(&data_lock, flags);
  450. dirty = op->info_dirty;
  451. shadow_dirty = op->shadow_info_dirty;
  452. spin_unlock_irqrestore(&data_lock, flags);
  453. if (!dirty && !shadow_dirty) {
  454. r = 0;
  455. break;
  456. }
  457. /* 4 iterations is the worst case:
  458. * 1 - initial iteration, dirty = true (between VFP and VSYNC)
  459. * 2 - first VSYNC, dirty = true
  460. * 3 - dirty = false, shadow_dirty = true
  461. * 4 - shadow_dirty = false */
  462. if (i++ == 3) {
  463. DSSERR("ovl(%d)->wait_for_go() not finishing\n",
  464. ovl->id);
  465. r = 0;
  466. break;
  467. }
  468. r = omap_dispc_wait_for_irq_interruptible_timeout(irq, timeout);
  469. if (r == -ERESTARTSYS)
  470. break;
  471. if (r) {
  472. DSSERR("ovl(%d)->wait_for_go() timeout\n", ovl->id);
  473. break;
  474. }
  475. }
  476. dispc_runtime_put();
  477. return r;
  478. }
  479. static void dss_ovl_write_regs(struct omap_overlay *ovl)
  480. {
  481. struct ovl_priv_data *op = get_ovl_priv(ovl);
  482. struct omap_overlay_info *oi;
  483. bool replication;
  484. struct mgr_priv_data *mp;
  485. int r;
  486. DSSDBG("writing ovl %d regs", ovl->id);
  487. if (!op->enabled || !op->info_dirty)
  488. return;
  489. oi = &op->info;
  490. mp = get_mgr_priv(ovl->manager);
  491. replication = dss_ovl_use_replication(mp->lcd_config, oi->color_mode);
  492. r = dispc_ovl_setup(ovl->id, oi, replication, &mp->timings, false);
  493. if (r) {
  494. /*
  495. * We can't do much here, as this function can be called from
  496. * vsync interrupt.
  497. */
  498. DSSERR("dispc_ovl_setup failed for ovl %d\n", ovl->id);
  499. /* This will leave fifo configurations in a nonoptimal state */
  500. op->enabled = false;
  501. dispc_ovl_enable(ovl->id, false);
  502. return;
  503. }
  504. op->info_dirty = false;
  505. if (mp->updating)
  506. op->shadow_info_dirty = true;
  507. }
  508. static void dss_ovl_write_regs_extra(struct omap_overlay *ovl)
  509. {
  510. struct ovl_priv_data *op = get_ovl_priv(ovl);
  511. struct mgr_priv_data *mp;
  512. DSSDBG("writing ovl %d regs extra", ovl->id);
  513. if (!op->extra_info_dirty)
  514. return;
  515. /* note: write also when op->enabled == false, so that the ovl gets
  516. * disabled */
  517. dispc_ovl_enable(ovl->id, op->enabled);
  518. dispc_ovl_set_fifo_threshold(ovl->id, op->fifo_low, op->fifo_high);
  519. mp = get_mgr_priv(ovl->manager);
  520. op->extra_info_dirty = false;
  521. if (mp->updating)
  522. op->shadow_extra_info_dirty = true;
  523. }
  524. static void dss_mgr_write_regs(struct omap_overlay_manager *mgr)
  525. {
  526. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  527. struct omap_overlay *ovl;
  528. DSSDBG("writing mgr %d regs", mgr->id);
  529. if (!mp->enabled)
  530. return;
  531. WARN_ON(mp->busy);
  532. /* Commit overlay settings */
  533. list_for_each_entry(ovl, &mgr->overlays, list) {
  534. dss_ovl_write_regs(ovl);
  535. dss_ovl_write_regs_extra(ovl);
  536. }
  537. if (mp->info_dirty) {
  538. dispc_mgr_setup(mgr->id, &mp->info);
  539. mp->info_dirty = false;
  540. if (mp->updating)
  541. mp->shadow_info_dirty = true;
  542. }
  543. }
  544. static void dss_mgr_write_regs_extra(struct omap_overlay_manager *mgr)
  545. {
  546. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  547. DSSDBG("writing mgr %d regs extra", mgr->id);
  548. if (!mp->extra_info_dirty)
  549. return;
  550. dispc_mgr_set_timings(mgr->id, &mp->timings);
  551. /* lcd_config parameters */
  552. if (dss_mgr_is_lcd(mgr->id))
  553. dispc_mgr_set_lcd_config(mgr->id, &mp->lcd_config);
  554. mp->extra_info_dirty = false;
  555. if (mp->updating)
  556. mp->shadow_extra_info_dirty = true;
  557. }
  558. static void dss_write_regs(void)
  559. {
  560. const int num_mgrs = omap_dss_get_num_overlay_managers();
  561. int i;
  562. for (i = 0; i < num_mgrs; ++i) {
  563. struct omap_overlay_manager *mgr;
  564. struct mgr_priv_data *mp;
  565. int r;
  566. mgr = omap_dss_get_overlay_manager(i);
  567. mp = get_mgr_priv(mgr);
  568. if (!mp->enabled || mgr_manual_update(mgr) || mp->busy)
  569. continue;
  570. r = dss_check_settings(mgr);
  571. if (r) {
  572. DSSERR("cannot write registers for manager %s: "
  573. "illegal configuration\n", mgr->name);
  574. continue;
  575. }
  576. dss_mgr_write_regs(mgr);
  577. dss_mgr_write_regs_extra(mgr);
  578. }
  579. }
  580. static void dss_set_go_bits(void)
  581. {
  582. const int num_mgrs = omap_dss_get_num_overlay_managers();
  583. int i;
  584. for (i = 0; i < num_mgrs; ++i) {
  585. struct omap_overlay_manager *mgr;
  586. struct mgr_priv_data *mp;
  587. mgr = omap_dss_get_overlay_manager(i);
  588. mp = get_mgr_priv(mgr);
  589. if (!mp->enabled || mgr_manual_update(mgr) || mp->busy)
  590. continue;
  591. if (!need_go(mgr))
  592. continue;
  593. mp->busy = true;
  594. if (!dss_data.irq_enabled && need_isr())
  595. dss_register_vsync_isr();
  596. dispc_mgr_go(mgr->id);
  597. }
  598. }
  599. static void mgr_clear_shadow_dirty(struct omap_overlay_manager *mgr)
  600. {
  601. struct omap_overlay *ovl;
  602. struct mgr_priv_data *mp;
  603. struct ovl_priv_data *op;
  604. mp = get_mgr_priv(mgr);
  605. mp->shadow_info_dirty = false;
  606. mp->shadow_extra_info_dirty = false;
  607. list_for_each_entry(ovl, &mgr->overlays, list) {
  608. op = get_ovl_priv(ovl);
  609. op->shadow_info_dirty = false;
  610. op->shadow_extra_info_dirty = false;
  611. }
  612. }
  613. static int dss_mgr_connect_compat(struct omap_overlay_manager *mgr,
  614. struct omap_dss_output *dst)
  615. {
  616. return mgr->set_output(mgr, dst);
  617. }
  618. static void dss_mgr_disconnect_compat(struct omap_overlay_manager *mgr,
  619. struct omap_dss_output *dst)
  620. {
  621. mgr->unset_output(mgr);
  622. }
  623. static void dss_mgr_start_update_compat(struct omap_overlay_manager *mgr)
  624. {
  625. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  626. unsigned long flags;
  627. int r;
  628. spin_lock_irqsave(&data_lock, flags);
  629. WARN_ON(mp->updating);
  630. r = dss_check_settings(mgr);
  631. if (r) {
  632. DSSERR("cannot start manual update: illegal configuration\n");
  633. spin_unlock_irqrestore(&data_lock, flags);
  634. return;
  635. }
  636. dss_mgr_write_regs(mgr);
  637. dss_mgr_write_regs_extra(mgr);
  638. mp->updating = true;
  639. if (!dss_data.irq_enabled && need_isr())
  640. dss_register_vsync_isr();
  641. dispc_mgr_enable_sync(mgr->id);
  642. spin_unlock_irqrestore(&data_lock, flags);
  643. }
  644. static void dss_apply_irq_handler(void *data, u32 mask);
  645. static void dss_register_vsync_isr(void)
  646. {
  647. const int num_mgrs = dss_feat_get_num_mgrs();
  648. u32 mask;
  649. int r, i;
  650. mask = 0;
  651. for (i = 0; i < num_mgrs; ++i)
  652. mask |= dispc_mgr_get_vsync_irq(i);
  653. for (i = 0; i < num_mgrs; ++i)
  654. mask |= dispc_mgr_get_framedone_irq(i);
  655. r = omap_dispc_register_isr(dss_apply_irq_handler, NULL, mask);
  656. WARN_ON(r);
  657. dss_data.irq_enabled = true;
  658. }
  659. static void dss_unregister_vsync_isr(void)
  660. {
  661. const int num_mgrs = dss_feat_get_num_mgrs();
  662. u32 mask;
  663. int r, i;
  664. mask = 0;
  665. for (i = 0; i < num_mgrs; ++i)
  666. mask |= dispc_mgr_get_vsync_irq(i);
  667. for (i = 0; i < num_mgrs; ++i)
  668. mask |= dispc_mgr_get_framedone_irq(i);
  669. r = omap_dispc_unregister_isr(dss_apply_irq_handler, NULL, mask);
  670. WARN_ON(r);
  671. dss_data.irq_enabled = false;
  672. }
  673. static void dss_apply_irq_handler(void *data, u32 mask)
  674. {
  675. const int num_mgrs = dss_feat_get_num_mgrs();
  676. int i;
  677. bool extra_updating;
  678. spin_lock(&data_lock);
  679. /* clear busy, updating flags, shadow_dirty flags */
  680. for (i = 0; i < num_mgrs; i++) {
  681. struct omap_overlay_manager *mgr;
  682. struct mgr_priv_data *mp;
  683. mgr = omap_dss_get_overlay_manager(i);
  684. mp = get_mgr_priv(mgr);
  685. if (!mp->enabled)
  686. continue;
  687. mp->updating = dispc_mgr_is_enabled(i);
  688. if (!mgr_manual_update(mgr)) {
  689. bool was_busy = mp->busy;
  690. mp->busy = dispc_mgr_go_busy(i);
  691. if (was_busy && !mp->busy)
  692. mgr_clear_shadow_dirty(mgr);
  693. }
  694. }
  695. dss_write_regs();
  696. dss_set_go_bits();
  697. extra_updating = extra_info_update_ongoing();
  698. if (!extra_updating)
  699. complete_all(&extra_updated_completion);
  700. /* call framedone handlers for manual update displays */
  701. for (i = 0; i < num_mgrs; i++) {
  702. struct omap_overlay_manager *mgr;
  703. struct mgr_priv_data *mp;
  704. mgr = omap_dss_get_overlay_manager(i);
  705. mp = get_mgr_priv(mgr);
  706. if (!mgr_manual_update(mgr) || !mp->framedone_handler)
  707. continue;
  708. if (mask & dispc_mgr_get_framedone_irq(i))
  709. mp->framedone_handler(mp->framedone_handler_data);
  710. }
  711. if (!need_isr())
  712. dss_unregister_vsync_isr();
  713. spin_unlock(&data_lock);
  714. }
  715. static void omap_dss_mgr_apply_ovl(struct omap_overlay *ovl)
  716. {
  717. struct ovl_priv_data *op;
  718. op = get_ovl_priv(ovl);
  719. if (!op->user_info_dirty)
  720. return;
  721. op->user_info_dirty = false;
  722. op->info_dirty = true;
  723. op->info = op->user_info;
  724. }
  725. static void omap_dss_mgr_apply_mgr(struct omap_overlay_manager *mgr)
  726. {
  727. struct mgr_priv_data *mp;
  728. mp = get_mgr_priv(mgr);
  729. if (!mp->user_info_dirty)
  730. return;
  731. mp->user_info_dirty = false;
  732. mp->info_dirty = true;
  733. mp->info = mp->user_info;
  734. }
  735. static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr)
  736. {
  737. unsigned long flags;
  738. struct omap_overlay *ovl;
  739. int r;
  740. DSSDBG("omap_dss_mgr_apply(%s)\n", mgr->name);
  741. spin_lock_irqsave(&data_lock, flags);
  742. r = dss_check_settings_apply(mgr);
  743. if (r) {
  744. spin_unlock_irqrestore(&data_lock, flags);
  745. DSSERR("failed to apply settings: illegal configuration.\n");
  746. return r;
  747. }
  748. /* Configure overlays */
  749. list_for_each_entry(ovl, &mgr->overlays, list)
  750. omap_dss_mgr_apply_ovl(ovl);
  751. /* Configure manager */
  752. omap_dss_mgr_apply_mgr(mgr);
  753. dss_write_regs();
  754. dss_set_go_bits();
  755. spin_unlock_irqrestore(&data_lock, flags);
  756. return 0;
  757. }
  758. static void dss_apply_ovl_enable(struct omap_overlay *ovl, bool enable)
  759. {
  760. struct ovl_priv_data *op;
  761. op = get_ovl_priv(ovl);
  762. if (op->enabled == enable)
  763. return;
  764. op->enabled = enable;
  765. op->extra_info_dirty = true;
  766. }
  767. static void dss_apply_ovl_fifo_thresholds(struct omap_overlay *ovl,
  768. u32 fifo_low, u32 fifo_high)
  769. {
  770. struct ovl_priv_data *op = get_ovl_priv(ovl);
  771. if (op->fifo_low == fifo_low && op->fifo_high == fifo_high)
  772. return;
  773. op->fifo_low = fifo_low;
  774. op->fifo_high = fifo_high;
  775. op->extra_info_dirty = true;
  776. }
  777. static void dss_ovl_setup_fifo(struct omap_overlay *ovl)
  778. {
  779. struct ovl_priv_data *op = get_ovl_priv(ovl);
  780. u32 fifo_low, fifo_high;
  781. bool use_fifo_merge = false;
  782. if (!op->enabled && !op->enabling)
  783. return;
  784. dispc_ovl_compute_fifo_thresholds(ovl->id, &fifo_low, &fifo_high,
  785. use_fifo_merge, ovl_manual_update(ovl));
  786. dss_apply_ovl_fifo_thresholds(ovl, fifo_low, fifo_high);
  787. }
  788. static void dss_mgr_setup_fifos(struct omap_overlay_manager *mgr)
  789. {
  790. struct omap_overlay *ovl;
  791. struct mgr_priv_data *mp;
  792. mp = get_mgr_priv(mgr);
  793. if (!mp->enabled)
  794. return;
  795. list_for_each_entry(ovl, &mgr->overlays, list)
  796. dss_ovl_setup_fifo(ovl);
  797. }
  798. static void dss_setup_fifos(void)
  799. {
  800. const int num_mgrs = omap_dss_get_num_overlay_managers();
  801. struct omap_overlay_manager *mgr;
  802. int i;
  803. for (i = 0; i < num_mgrs; ++i) {
  804. mgr = omap_dss_get_overlay_manager(i);
  805. dss_mgr_setup_fifos(mgr);
  806. }
  807. }
  808. static int dss_mgr_enable_compat(struct omap_overlay_manager *mgr)
  809. {
  810. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  811. unsigned long flags;
  812. int r;
  813. mutex_lock(&apply_lock);
  814. if (mp->enabled)
  815. goto out;
  816. spin_lock_irqsave(&data_lock, flags);
  817. mp->enabled = true;
  818. r = dss_check_settings(mgr);
  819. if (r) {
  820. DSSERR("failed to enable manager %d: check_settings failed\n",
  821. mgr->id);
  822. goto err;
  823. }
  824. dss_setup_fifos();
  825. dss_write_regs();
  826. dss_set_go_bits();
  827. if (!mgr_manual_update(mgr))
  828. mp->updating = true;
  829. if (!dss_data.irq_enabled && need_isr())
  830. dss_register_vsync_isr();
  831. spin_unlock_irqrestore(&data_lock, flags);
  832. if (!mgr_manual_update(mgr))
  833. dispc_mgr_enable_sync(mgr->id);
  834. out:
  835. mutex_unlock(&apply_lock);
  836. return 0;
  837. err:
  838. mp->enabled = false;
  839. spin_unlock_irqrestore(&data_lock, flags);
  840. mutex_unlock(&apply_lock);
  841. return r;
  842. }
  843. static void dss_mgr_disable_compat(struct omap_overlay_manager *mgr)
  844. {
  845. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  846. unsigned long flags;
  847. mutex_lock(&apply_lock);
  848. if (!mp->enabled)
  849. goto out;
  850. if (!mgr_manual_update(mgr))
  851. dispc_mgr_disable_sync(mgr->id);
  852. spin_lock_irqsave(&data_lock, flags);
  853. mp->updating = false;
  854. mp->enabled = false;
  855. spin_unlock_irqrestore(&data_lock, flags);
  856. out:
  857. mutex_unlock(&apply_lock);
  858. }
  859. static int dss_mgr_set_info(struct omap_overlay_manager *mgr,
  860. struct omap_overlay_manager_info *info)
  861. {
  862. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  863. unsigned long flags;
  864. int r;
  865. r = dss_mgr_simple_check(mgr, info);
  866. if (r)
  867. return r;
  868. spin_lock_irqsave(&data_lock, flags);
  869. mp->user_info = *info;
  870. mp->user_info_dirty = true;
  871. spin_unlock_irqrestore(&data_lock, flags);
  872. return 0;
  873. }
  874. static void dss_mgr_get_info(struct omap_overlay_manager *mgr,
  875. struct omap_overlay_manager_info *info)
  876. {
  877. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  878. unsigned long flags;
  879. spin_lock_irqsave(&data_lock, flags);
  880. *info = mp->user_info;
  881. spin_unlock_irqrestore(&data_lock, flags);
  882. }
  883. static int dss_mgr_set_output(struct omap_overlay_manager *mgr,
  884. struct omap_dss_output *output)
  885. {
  886. int r;
  887. mutex_lock(&apply_lock);
  888. if (mgr->output) {
  889. DSSERR("manager %s is already connected to an output\n",
  890. mgr->name);
  891. r = -EINVAL;
  892. goto err;
  893. }
  894. if ((mgr->supported_outputs & output->id) == 0) {
  895. DSSERR("output does not support manager %s\n",
  896. mgr->name);
  897. r = -EINVAL;
  898. goto err;
  899. }
  900. output->manager = mgr;
  901. mgr->output = output;
  902. mutex_unlock(&apply_lock);
  903. return 0;
  904. err:
  905. mutex_unlock(&apply_lock);
  906. return r;
  907. }
  908. static int dss_mgr_unset_output(struct omap_overlay_manager *mgr)
  909. {
  910. int r;
  911. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  912. unsigned long flags;
  913. mutex_lock(&apply_lock);
  914. if (!mgr->output) {
  915. DSSERR("failed to unset output, output not set\n");
  916. r = -EINVAL;
  917. goto err;
  918. }
  919. spin_lock_irqsave(&data_lock, flags);
  920. if (mp->enabled) {
  921. DSSERR("output can't be unset when manager is enabled\n");
  922. r = -EINVAL;
  923. goto err1;
  924. }
  925. spin_unlock_irqrestore(&data_lock, flags);
  926. mgr->output->manager = NULL;
  927. mgr->output = NULL;
  928. mutex_unlock(&apply_lock);
  929. return 0;
  930. err1:
  931. spin_unlock_irqrestore(&data_lock, flags);
  932. err:
  933. mutex_unlock(&apply_lock);
  934. return r;
  935. }
  936. static void dss_apply_mgr_timings(struct omap_overlay_manager *mgr,
  937. const struct omap_video_timings *timings)
  938. {
  939. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  940. mp->timings = *timings;
  941. mp->extra_info_dirty = true;
  942. }
  943. static void dss_mgr_set_timings_compat(struct omap_overlay_manager *mgr,
  944. const struct omap_video_timings *timings)
  945. {
  946. unsigned long flags;
  947. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  948. spin_lock_irqsave(&data_lock, flags);
  949. if (mp->updating) {
  950. DSSERR("cannot set timings for %s: manager needs to be disabled\n",
  951. mgr->name);
  952. goto out;
  953. }
  954. dss_apply_mgr_timings(mgr, timings);
  955. out:
  956. spin_unlock_irqrestore(&data_lock, flags);
  957. }
  958. static void dss_apply_mgr_lcd_config(struct omap_overlay_manager *mgr,
  959. const struct dss_lcd_mgr_config *config)
  960. {
  961. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  962. mp->lcd_config = *config;
  963. mp->extra_info_dirty = true;
  964. }
  965. static void dss_mgr_set_lcd_config_compat(struct omap_overlay_manager *mgr,
  966. const struct dss_lcd_mgr_config *config)
  967. {
  968. unsigned long flags;
  969. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  970. spin_lock_irqsave(&data_lock, flags);
  971. if (mp->enabled) {
  972. DSSERR("cannot apply lcd config for %s: manager needs to be disabled\n",
  973. mgr->name);
  974. goto out;
  975. }
  976. dss_apply_mgr_lcd_config(mgr, config);
  977. out:
  978. spin_unlock_irqrestore(&data_lock, flags);
  979. }
  980. static int dss_ovl_set_info(struct omap_overlay *ovl,
  981. struct omap_overlay_info *info)
  982. {
  983. struct ovl_priv_data *op = get_ovl_priv(ovl);
  984. unsigned long flags;
  985. int r;
  986. r = dss_ovl_simple_check(ovl, info);
  987. if (r)
  988. return r;
  989. spin_lock_irqsave(&data_lock, flags);
  990. op->user_info = *info;
  991. op->user_info_dirty = true;
  992. spin_unlock_irqrestore(&data_lock, flags);
  993. return 0;
  994. }
  995. static void dss_ovl_get_info(struct omap_overlay *ovl,
  996. struct omap_overlay_info *info)
  997. {
  998. struct ovl_priv_data *op = get_ovl_priv(ovl);
  999. unsigned long flags;
  1000. spin_lock_irqsave(&data_lock, flags);
  1001. *info = op->user_info;
  1002. spin_unlock_irqrestore(&data_lock, flags);
  1003. }
  1004. static int dss_ovl_set_manager(struct omap_overlay *ovl,
  1005. struct omap_overlay_manager *mgr)
  1006. {
  1007. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1008. unsigned long flags;
  1009. int r;
  1010. if (!mgr)
  1011. return -EINVAL;
  1012. mutex_lock(&apply_lock);
  1013. if (ovl->manager) {
  1014. DSSERR("overlay '%s' already has a manager '%s'\n",
  1015. ovl->name, ovl->manager->name);
  1016. r = -EINVAL;
  1017. goto err;
  1018. }
  1019. r = dispc_runtime_get();
  1020. if (r)
  1021. goto err;
  1022. spin_lock_irqsave(&data_lock, flags);
  1023. if (op->enabled) {
  1024. spin_unlock_irqrestore(&data_lock, flags);
  1025. DSSERR("overlay has to be disabled to change the manager\n");
  1026. r = -EINVAL;
  1027. goto err1;
  1028. }
  1029. dispc_ovl_set_channel_out(ovl->id, mgr->id);
  1030. ovl->manager = mgr;
  1031. list_add_tail(&ovl->list, &mgr->overlays);
  1032. spin_unlock_irqrestore(&data_lock, flags);
  1033. dispc_runtime_put();
  1034. mutex_unlock(&apply_lock);
  1035. return 0;
  1036. err1:
  1037. dispc_runtime_put();
  1038. err:
  1039. mutex_unlock(&apply_lock);
  1040. return r;
  1041. }
  1042. static int dss_ovl_unset_manager(struct omap_overlay *ovl)
  1043. {
  1044. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1045. unsigned long flags;
  1046. int r;
  1047. mutex_lock(&apply_lock);
  1048. if (!ovl->manager) {
  1049. DSSERR("failed to detach overlay: manager not set\n");
  1050. r = -EINVAL;
  1051. goto err;
  1052. }
  1053. spin_lock_irqsave(&data_lock, flags);
  1054. if (op->enabled) {
  1055. spin_unlock_irqrestore(&data_lock, flags);
  1056. DSSERR("overlay has to be disabled to unset the manager\n");
  1057. r = -EINVAL;
  1058. goto err;
  1059. }
  1060. spin_unlock_irqrestore(&data_lock, flags);
  1061. /* wait for pending extra_info updates to ensure the ovl is disabled */
  1062. wait_pending_extra_info_updates();
  1063. /*
  1064. * For a manual update display, there is no guarantee that the overlay
  1065. * is really disabled in HW, we may need an extra update from this
  1066. * manager before the configurations can go in. Return an error if the
  1067. * overlay needed an update from the manager.
  1068. *
  1069. * TODO: Instead of returning an error, try to do a dummy manager update
  1070. * here to disable the overlay in hardware. Use the *GATED fields in
  1071. * the DISPC_CONFIG registers to do a dummy update.
  1072. */
  1073. spin_lock_irqsave(&data_lock, flags);
  1074. if (ovl_manual_update(ovl) && op->extra_info_dirty) {
  1075. spin_unlock_irqrestore(&data_lock, flags);
  1076. DSSERR("need an update to change the manager\n");
  1077. r = -EINVAL;
  1078. goto err;
  1079. }
  1080. ovl->manager = NULL;
  1081. list_del(&ovl->list);
  1082. spin_unlock_irqrestore(&data_lock, flags);
  1083. mutex_unlock(&apply_lock);
  1084. return 0;
  1085. err:
  1086. mutex_unlock(&apply_lock);
  1087. return r;
  1088. }
  1089. static bool dss_ovl_is_enabled(struct omap_overlay *ovl)
  1090. {
  1091. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1092. unsigned long flags;
  1093. bool e;
  1094. spin_lock_irqsave(&data_lock, flags);
  1095. e = op->enabled;
  1096. spin_unlock_irqrestore(&data_lock, flags);
  1097. return e;
  1098. }
  1099. static int dss_ovl_enable(struct omap_overlay *ovl)
  1100. {
  1101. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1102. unsigned long flags;
  1103. int r;
  1104. mutex_lock(&apply_lock);
  1105. if (op->enabled) {
  1106. r = 0;
  1107. goto err1;
  1108. }
  1109. if (ovl->manager == NULL || ovl->manager->output == NULL) {
  1110. r = -EINVAL;
  1111. goto err1;
  1112. }
  1113. spin_lock_irqsave(&data_lock, flags);
  1114. op->enabling = true;
  1115. r = dss_check_settings(ovl->manager);
  1116. if (r) {
  1117. DSSERR("failed to enable overlay %d: check_settings failed\n",
  1118. ovl->id);
  1119. goto err2;
  1120. }
  1121. dss_setup_fifos();
  1122. op->enabling = false;
  1123. dss_apply_ovl_enable(ovl, true);
  1124. dss_write_regs();
  1125. dss_set_go_bits();
  1126. spin_unlock_irqrestore(&data_lock, flags);
  1127. mutex_unlock(&apply_lock);
  1128. return 0;
  1129. err2:
  1130. op->enabling = false;
  1131. spin_unlock_irqrestore(&data_lock, flags);
  1132. err1:
  1133. mutex_unlock(&apply_lock);
  1134. return r;
  1135. }
  1136. static int dss_ovl_disable(struct omap_overlay *ovl)
  1137. {
  1138. struct ovl_priv_data *op = get_ovl_priv(ovl);
  1139. unsigned long flags;
  1140. int r;
  1141. mutex_lock(&apply_lock);
  1142. if (!op->enabled) {
  1143. r = 0;
  1144. goto err;
  1145. }
  1146. if (ovl->manager == NULL || ovl->manager->output == NULL) {
  1147. r = -EINVAL;
  1148. goto err;
  1149. }
  1150. spin_lock_irqsave(&data_lock, flags);
  1151. dss_apply_ovl_enable(ovl, false);
  1152. dss_write_regs();
  1153. dss_set_go_bits();
  1154. spin_unlock_irqrestore(&data_lock, flags);
  1155. mutex_unlock(&apply_lock);
  1156. return 0;
  1157. err:
  1158. mutex_unlock(&apply_lock);
  1159. return r;
  1160. }
  1161. static int dss_mgr_register_framedone_handler_compat(struct omap_overlay_manager *mgr,
  1162. void (*handler)(void *), void *data)
  1163. {
  1164. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  1165. if (mp->framedone_handler)
  1166. return -EBUSY;
  1167. mp->framedone_handler = handler;
  1168. mp->framedone_handler_data = data;
  1169. return 0;
  1170. }
  1171. static void dss_mgr_unregister_framedone_handler_compat(struct omap_overlay_manager *mgr,
  1172. void (*handler)(void *), void *data)
  1173. {
  1174. struct mgr_priv_data *mp = get_mgr_priv(mgr);
  1175. WARN_ON(mp->framedone_handler != handler ||
  1176. mp->framedone_handler_data != data);
  1177. mp->framedone_handler = NULL;
  1178. mp->framedone_handler_data = NULL;
  1179. }
  1180. static const struct dss_mgr_ops apply_mgr_ops = {
  1181. .connect = dss_mgr_connect_compat,
  1182. .disconnect = dss_mgr_disconnect_compat,
  1183. .start_update = dss_mgr_start_update_compat,
  1184. .enable = dss_mgr_enable_compat,
  1185. .disable = dss_mgr_disable_compat,
  1186. .set_timings = dss_mgr_set_timings_compat,
  1187. .set_lcd_config = dss_mgr_set_lcd_config_compat,
  1188. .register_framedone_handler = dss_mgr_register_framedone_handler_compat,
  1189. .unregister_framedone_handler = dss_mgr_unregister_framedone_handler_compat,
  1190. };
  1191. static int compat_refcnt;
  1192. static DEFINE_MUTEX(compat_init_lock);
  1193. int omapdss_compat_init(void)
  1194. {
  1195. struct platform_device *pdev = dss_get_core_pdev();
  1196. int i, r;
  1197. mutex_lock(&compat_init_lock);
  1198. if (compat_refcnt++ > 0)
  1199. goto out;
  1200. apply_init_priv();
  1201. dss_init_overlay_managers_sysfs(pdev);
  1202. dss_init_overlays(pdev);
  1203. for (i = 0; i < omap_dss_get_num_overlay_managers(); i++) {
  1204. struct omap_overlay_manager *mgr;
  1205. mgr = omap_dss_get_overlay_manager(i);
  1206. mgr->set_output = &dss_mgr_set_output;
  1207. mgr->unset_output = &dss_mgr_unset_output;
  1208. mgr->apply = &omap_dss_mgr_apply;
  1209. mgr->set_manager_info = &dss_mgr_set_info;
  1210. mgr->get_manager_info = &dss_mgr_get_info;
  1211. mgr->wait_for_go = &dss_mgr_wait_for_go;
  1212. mgr->wait_for_vsync = &dss_mgr_wait_for_vsync;
  1213. mgr->get_device = &dss_mgr_get_device;
  1214. }
  1215. for (i = 0; i < omap_dss_get_num_overlays(); i++) {
  1216. struct omap_overlay *ovl = omap_dss_get_overlay(i);
  1217. ovl->is_enabled = &dss_ovl_is_enabled;
  1218. ovl->enable = &dss_ovl_enable;
  1219. ovl->disable = &dss_ovl_disable;
  1220. ovl->set_manager = &dss_ovl_set_manager;
  1221. ovl->unset_manager = &dss_ovl_unset_manager;
  1222. ovl->set_overlay_info = &dss_ovl_set_info;
  1223. ovl->get_overlay_info = &dss_ovl_get_info;
  1224. ovl->wait_for_go = &dss_mgr_wait_for_go_ovl;
  1225. ovl->get_device = &dss_ovl_get_device;
  1226. }
  1227. r = dss_install_mgr_ops(&apply_mgr_ops);
  1228. if (r)
  1229. goto err_mgr_ops;
  1230. r = display_init_sysfs(pdev);
  1231. if (r)
  1232. goto err_disp_sysfs;
  1233. dispc_runtime_get();
  1234. r = dss_dispc_initialize_irq();
  1235. if (r)
  1236. goto err_init_irq;
  1237. dispc_runtime_put();
  1238. out:
  1239. mutex_unlock(&compat_init_lock);
  1240. return 0;
  1241. err_init_irq:
  1242. dispc_runtime_put();
  1243. display_uninit_sysfs(pdev);
  1244. err_disp_sysfs:
  1245. dss_uninstall_mgr_ops();
  1246. err_mgr_ops:
  1247. dss_uninit_overlay_managers_sysfs(pdev);
  1248. dss_uninit_overlays(pdev);
  1249. compat_refcnt--;
  1250. mutex_unlock(&compat_init_lock);
  1251. return r;
  1252. }
  1253. EXPORT_SYMBOL(omapdss_compat_init);
  1254. void omapdss_compat_uninit(void)
  1255. {
  1256. struct platform_device *pdev = dss_get_core_pdev();
  1257. mutex_lock(&compat_init_lock);
  1258. if (--compat_refcnt > 0)
  1259. goto out;
  1260. dss_dispc_uninitialize_irq();
  1261. display_uninit_sysfs(pdev);
  1262. dss_uninstall_mgr_ops();
  1263. dss_uninit_overlay_managers_sysfs(pdev);
  1264. dss_uninit_overlays(pdev);
  1265. out:
  1266. mutex_unlock(&compat_init_lock);
  1267. }
  1268. EXPORT_SYMBOL(omapdss_compat_uninit);