ymfpci_main.c 66 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * BUGS:
  6. * --
  7. *
  8. * TODO:
  9. * --
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. */
  26. #include <sound/driver.h>
  27. #include <linux/delay.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/pci.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/vmalloc.h>
  34. #include <sound/core.h>
  35. #include <sound/control.h>
  36. #include <sound/info.h>
  37. #include <sound/ymfpci.h>
  38. #include <sound/asoundef.h>
  39. #include <sound/mpu401.h>
  40. #include <asm/io.h>
  41. /*
  42. * constants
  43. */
  44. /*
  45. * common I/O routines
  46. */
  47. static void snd_ymfpci_irq_wait(ymfpci_t *chip);
  48. static inline u8 snd_ymfpci_readb(ymfpci_t *chip, u32 offset)
  49. {
  50. return readb(chip->reg_area_virt + offset);
  51. }
  52. static inline void snd_ymfpci_writeb(ymfpci_t *chip, u32 offset, u8 val)
  53. {
  54. writeb(val, chip->reg_area_virt + offset);
  55. }
  56. static inline u16 snd_ymfpci_readw(ymfpci_t *chip, u32 offset)
  57. {
  58. return readw(chip->reg_area_virt + offset);
  59. }
  60. static inline void snd_ymfpci_writew(ymfpci_t *chip, u32 offset, u16 val)
  61. {
  62. writew(val, chip->reg_area_virt + offset);
  63. }
  64. static inline u32 snd_ymfpci_readl(ymfpci_t *chip, u32 offset)
  65. {
  66. return readl(chip->reg_area_virt + offset);
  67. }
  68. static inline void snd_ymfpci_writel(ymfpci_t *chip, u32 offset, u32 val)
  69. {
  70. writel(val, chip->reg_area_virt + offset);
  71. }
  72. static int snd_ymfpci_codec_ready(ymfpci_t *chip, int secondary)
  73. {
  74. unsigned long end_time;
  75. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  76. end_time = jiffies + msecs_to_jiffies(750);
  77. do {
  78. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  79. return 0;
  80. set_current_state(TASK_UNINTERRUPTIBLE);
  81. schedule_timeout(1);
  82. } while (time_before(jiffies, end_time));
  83. snd_printk("codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  84. return -EBUSY;
  85. }
  86. static void snd_ymfpci_codec_write(ac97_t *ac97, u16 reg, u16 val)
  87. {
  88. ymfpci_t *chip = ac97->private_data;
  89. u32 cmd;
  90. snd_ymfpci_codec_ready(chip, 0);
  91. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  92. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  93. }
  94. static u16 snd_ymfpci_codec_read(ac97_t *ac97, u16 reg)
  95. {
  96. ymfpci_t *chip = ac97->private_data;
  97. if (snd_ymfpci_codec_ready(chip, 0))
  98. return ~0;
  99. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  100. if (snd_ymfpci_codec_ready(chip, 0))
  101. return ~0;
  102. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  103. int i;
  104. for (i = 0; i < 600; i++)
  105. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  106. }
  107. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  108. }
  109. /*
  110. * Misc routines
  111. */
  112. static u32 snd_ymfpci_calc_delta(u32 rate)
  113. {
  114. switch (rate) {
  115. case 8000: return 0x02aaab00;
  116. case 11025: return 0x03accd00;
  117. case 16000: return 0x05555500;
  118. case 22050: return 0x07599a00;
  119. case 32000: return 0x0aaaab00;
  120. case 44100: return 0x0eb33300;
  121. default: return ((rate << 16) / 375) << 5;
  122. }
  123. }
  124. static u32 def_rate[8] = {
  125. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  126. };
  127. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  128. {
  129. u32 i;
  130. static u32 val[8] = {
  131. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  132. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  133. };
  134. if (rate == 44100)
  135. return 0x40000000; /* FIXME: What's the right value? */
  136. for (i = 0; i < 8; i++)
  137. if (rate <= def_rate[i])
  138. return val[i];
  139. return val[0];
  140. }
  141. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  142. {
  143. u32 i;
  144. static u32 val[8] = {
  145. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  146. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  147. };
  148. if (rate == 44100)
  149. return 0x370A0000;
  150. for (i = 0; i < 8; i++)
  151. if (rate <= def_rate[i])
  152. return val[i];
  153. return val[0];
  154. }
  155. /*
  156. * Hardware start management
  157. */
  158. static void snd_ymfpci_hw_start(ymfpci_t *chip)
  159. {
  160. unsigned long flags;
  161. spin_lock_irqsave(&chip->reg_lock, flags);
  162. if (chip->start_count++ > 0)
  163. goto __end;
  164. snd_ymfpci_writel(chip, YDSXGR_MODE,
  165. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  166. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  167. __end:
  168. spin_unlock_irqrestore(&chip->reg_lock, flags);
  169. }
  170. static void snd_ymfpci_hw_stop(ymfpci_t *chip)
  171. {
  172. unsigned long flags;
  173. long timeout = 1000;
  174. spin_lock_irqsave(&chip->reg_lock, flags);
  175. if (--chip->start_count > 0)
  176. goto __end;
  177. snd_ymfpci_writel(chip, YDSXGR_MODE,
  178. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  179. while (timeout-- > 0) {
  180. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  181. break;
  182. }
  183. if (atomic_read(&chip->interrupt_sleep_count)) {
  184. atomic_set(&chip->interrupt_sleep_count, 0);
  185. wake_up(&chip->interrupt_sleep);
  186. }
  187. __end:
  188. spin_unlock_irqrestore(&chip->reg_lock, flags);
  189. }
  190. /*
  191. * Playback voice management
  192. */
  193. static int voice_alloc(ymfpci_t *chip, ymfpci_voice_type_t type, int pair, ymfpci_voice_t **rvoice)
  194. {
  195. ymfpci_voice_t *voice, *voice2;
  196. int idx;
  197. *rvoice = NULL;
  198. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  199. voice = &chip->voices[idx];
  200. voice2 = pair ? &chip->voices[idx+1] : NULL;
  201. if (voice->use || (voice2 && voice2->use))
  202. continue;
  203. voice->use = 1;
  204. if (voice2)
  205. voice2->use = 1;
  206. switch (type) {
  207. case YMFPCI_PCM:
  208. voice->pcm = 1;
  209. if (voice2)
  210. voice2->pcm = 1;
  211. break;
  212. case YMFPCI_SYNTH:
  213. voice->synth = 1;
  214. break;
  215. case YMFPCI_MIDI:
  216. voice->midi = 1;
  217. break;
  218. }
  219. snd_ymfpci_hw_start(chip);
  220. if (voice2)
  221. snd_ymfpci_hw_start(chip);
  222. *rvoice = voice;
  223. return 0;
  224. }
  225. return -ENOMEM;
  226. }
  227. static int snd_ymfpci_voice_alloc(ymfpci_t *chip, ymfpci_voice_type_t type, int pair, ymfpci_voice_t **rvoice)
  228. {
  229. unsigned long flags;
  230. int result;
  231. snd_assert(rvoice != NULL, return -EINVAL);
  232. snd_assert(!pair || type == YMFPCI_PCM, return -EINVAL);
  233. spin_lock_irqsave(&chip->voice_lock, flags);
  234. for (;;) {
  235. result = voice_alloc(chip, type, pair, rvoice);
  236. if (result == 0 || type != YMFPCI_PCM)
  237. break;
  238. /* TODO: synth/midi voice deallocation */
  239. break;
  240. }
  241. spin_unlock_irqrestore(&chip->voice_lock, flags);
  242. return result;
  243. }
  244. static int snd_ymfpci_voice_free(ymfpci_t *chip, ymfpci_voice_t *pvoice)
  245. {
  246. unsigned long flags;
  247. snd_assert(pvoice != NULL, return -EINVAL);
  248. snd_ymfpci_hw_stop(chip);
  249. spin_lock_irqsave(&chip->voice_lock, flags);
  250. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  251. pvoice->ypcm = NULL;
  252. pvoice->interrupt = NULL;
  253. spin_unlock_irqrestore(&chip->voice_lock, flags);
  254. return 0;
  255. }
  256. /*
  257. * PCM part
  258. */
  259. static void snd_ymfpci_pcm_interrupt(ymfpci_t *chip, ymfpci_voice_t *voice)
  260. {
  261. ymfpci_pcm_t *ypcm;
  262. u32 pos, delta;
  263. if ((ypcm = voice->ypcm) == NULL)
  264. return;
  265. if (ypcm->substream == NULL)
  266. return;
  267. spin_lock(&chip->reg_lock);
  268. if (ypcm->running) {
  269. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  270. if (pos < ypcm->last_pos)
  271. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  272. else
  273. delta = pos - ypcm->last_pos;
  274. ypcm->period_pos += delta;
  275. ypcm->last_pos = pos;
  276. if (ypcm->period_pos >= ypcm->period_size) {
  277. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  278. ypcm->period_pos %= ypcm->period_size;
  279. spin_unlock(&chip->reg_lock);
  280. snd_pcm_period_elapsed(ypcm->substream);
  281. spin_lock(&chip->reg_lock);
  282. }
  283. if (unlikely(ypcm->update_pcm_vol)) {
  284. unsigned int subs = ypcm->substream->number;
  285. unsigned int next_bank = 1 - chip->active_bank;
  286. snd_ymfpci_playback_bank_t *bank;
  287. u32 volume;
  288. bank = &voice->bank[next_bank];
  289. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  290. bank->left_gain_end = volume;
  291. if (ypcm->output_rear)
  292. bank->eff2_gain_end = volume;
  293. if (ypcm->voices[1])
  294. bank = &ypcm->voices[1]->bank[next_bank];
  295. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  296. bank->right_gain_end = volume;
  297. if (ypcm->output_rear)
  298. bank->eff3_gain_end = volume;
  299. ypcm->update_pcm_vol--;
  300. }
  301. }
  302. spin_unlock(&chip->reg_lock);
  303. }
  304. static void snd_ymfpci_pcm_capture_interrupt(snd_pcm_substream_t *substream)
  305. {
  306. snd_pcm_runtime_t *runtime = substream->runtime;
  307. ymfpci_pcm_t *ypcm = runtime->private_data;
  308. ymfpci_t *chip = ypcm->chip;
  309. u32 pos, delta;
  310. spin_lock(&chip->reg_lock);
  311. if (ypcm->running) {
  312. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  313. if (pos < ypcm->last_pos)
  314. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  315. else
  316. delta = pos - ypcm->last_pos;
  317. ypcm->period_pos += delta;
  318. ypcm->last_pos = pos;
  319. if (ypcm->period_pos >= ypcm->period_size) {
  320. ypcm->period_pos %= ypcm->period_size;
  321. // printk("done - active_bank = 0x%x, start = 0x%x\n", chip->active_bank, voice->bank[chip->active_bank].start);
  322. spin_unlock(&chip->reg_lock);
  323. snd_pcm_period_elapsed(substream);
  324. spin_lock(&chip->reg_lock);
  325. }
  326. }
  327. spin_unlock(&chip->reg_lock);
  328. }
  329. static int snd_ymfpci_playback_trigger(snd_pcm_substream_t * substream,
  330. int cmd)
  331. {
  332. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  333. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  334. int result = 0;
  335. spin_lock(&chip->reg_lock);
  336. if (ypcm->voices[0] == NULL) {
  337. result = -EINVAL;
  338. goto __unlock;
  339. }
  340. switch (cmd) {
  341. case SNDRV_PCM_TRIGGER_START:
  342. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  343. case SNDRV_PCM_TRIGGER_RESUME:
  344. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  345. if (ypcm->voices[1] != NULL)
  346. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  347. ypcm->running = 1;
  348. break;
  349. case SNDRV_PCM_TRIGGER_STOP:
  350. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  351. case SNDRV_PCM_TRIGGER_SUSPEND:
  352. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  353. if (ypcm->voices[1] != NULL)
  354. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  355. ypcm->running = 0;
  356. break;
  357. default:
  358. result = -EINVAL;
  359. break;
  360. }
  361. __unlock:
  362. spin_unlock(&chip->reg_lock);
  363. return result;
  364. }
  365. static int snd_ymfpci_capture_trigger(snd_pcm_substream_t * substream,
  366. int cmd)
  367. {
  368. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  369. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  370. int result = 0;
  371. u32 tmp;
  372. spin_lock(&chip->reg_lock);
  373. switch (cmd) {
  374. case SNDRV_PCM_TRIGGER_START:
  375. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  376. case SNDRV_PCM_TRIGGER_RESUME:
  377. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  378. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  379. ypcm->running = 1;
  380. break;
  381. case SNDRV_PCM_TRIGGER_STOP:
  382. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  383. case SNDRV_PCM_TRIGGER_SUSPEND:
  384. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  385. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  386. ypcm->running = 0;
  387. break;
  388. default:
  389. result = -EINVAL;
  390. break;
  391. }
  392. spin_unlock(&chip->reg_lock);
  393. return result;
  394. }
  395. static int snd_ymfpci_pcm_voice_alloc(ymfpci_pcm_t *ypcm, int voices)
  396. {
  397. int err;
  398. if (ypcm->voices[1] != NULL && voices < 2) {
  399. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  400. ypcm->voices[1] = NULL;
  401. }
  402. if (voices == 1 && ypcm->voices[0] != NULL)
  403. return 0; /* already allocated */
  404. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  405. return 0; /* already allocated */
  406. if (voices > 1) {
  407. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  408. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  409. ypcm->voices[0] = NULL;
  410. }
  411. }
  412. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  413. if (err < 0)
  414. return err;
  415. ypcm->voices[0]->ypcm = ypcm;
  416. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  417. if (voices > 1) {
  418. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  419. ypcm->voices[1]->ypcm = ypcm;
  420. }
  421. return 0;
  422. }
  423. static void snd_ymfpci_pcm_init_voice(ymfpci_pcm_t *ypcm, unsigned int voiceidx,
  424. snd_pcm_runtime_t *runtime,
  425. int has_pcm_volume)
  426. {
  427. ymfpci_voice_t *voice = ypcm->voices[voiceidx];
  428. u32 format;
  429. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  430. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  431. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  432. snd_ymfpci_playback_bank_t *bank;
  433. unsigned int nbank;
  434. u32 vol_left, vol_right;
  435. u8 use_left, use_right;
  436. snd_assert(voice != NULL, return);
  437. if (runtime->channels == 1) {
  438. use_left = 1;
  439. use_right = 1;
  440. } else {
  441. use_left = (voiceidx & 1) == 0;
  442. use_right = !use_left;
  443. }
  444. if (has_pcm_volume) {
  445. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  446. [ypcm->substream->number].left << 15);
  447. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  448. [ypcm->substream->number].right << 15);
  449. } else {
  450. vol_left = cpu_to_le32(0x40000000);
  451. vol_right = cpu_to_le32(0x40000000);
  452. }
  453. format = runtime->channels == 2 ? 0x00010000 : 0;
  454. if (snd_pcm_format_width(runtime->format) == 8)
  455. format |= 0x80000000;
  456. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  457. format |= 1;
  458. for (nbank = 0; nbank < 2; nbank++) {
  459. bank = &voice->bank[nbank];
  460. memset(bank, 0, sizeof(*bank));
  461. bank->format = cpu_to_le32(format);
  462. bank->base = cpu_to_le32(runtime->dma_addr);
  463. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  464. bank->lpfQ = cpu_to_le32(lpfQ);
  465. bank->delta =
  466. bank->delta_end = cpu_to_le32(delta);
  467. bank->lpfK =
  468. bank->lpfK_end = cpu_to_le32(lpfK);
  469. bank->eg_gain =
  470. bank->eg_gain_end = cpu_to_le32(0x40000000);
  471. if (ypcm->output_front) {
  472. if (use_left) {
  473. bank->left_gain =
  474. bank->left_gain_end = vol_left;
  475. }
  476. if (use_right) {
  477. bank->right_gain =
  478. bank->right_gain_end = vol_right;
  479. }
  480. }
  481. if (ypcm->output_rear) {
  482. if (use_left) {
  483. bank->eff2_gain =
  484. bank->eff2_gain_end = vol_left;
  485. }
  486. if (use_right) {
  487. bank->eff3_gain =
  488. bank->eff3_gain_end = vol_right;
  489. }
  490. }
  491. }
  492. }
  493. static int __devinit snd_ymfpci_ac3_init(ymfpci_t *chip)
  494. {
  495. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  496. 4096, &chip->ac3_tmp_base) < 0)
  497. return -ENOMEM;
  498. chip->bank_effect[3][0]->base =
  499. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  500. chip->bank_effect[3][0]->loop_end =
  501. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  502. chip->bank_effect[4][0]->base =
  503. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  504. chip->bank_effect[4][0]->loop_end =
  505. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  506. spin_lock_irq(&chip->reg_lock);
  507. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  508. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  509. spin_unlock_irq(&chip->reg_lock);
  510. return 0;
  511. }
  512. static int snd_ymfpci_ac3_done(ymfpci_t *chip)
  513. {
  514. spin_lock_irq(&chip->reg_lock);
  515. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  516. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  517. spin_unlock_irq(&chip->reg_lock);
  518. // snd_ymfpci_irq_wait(chip);
  519. if (chip->ac3_tmp_base.area) {
  520. snd_dma_free_pages(&chip->ac3_tmp_base);
  521. chip->ac3_tmp_base.area = NULL;
  522. }
  523. return 0;
  524. }
  525. static int snd_ymfpci_playback_hw_params(snd_pcm_substream_t * substream,
  526. snd_pcm_hw_params_t * hw_params)
  527. {
  528. snd_pcm_runtime_t *runtime = substream->runtime;
  529. ymfpci_pcm_t *ypcm = runtime->private_data;
  530. int err;
  531. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  532. return err;
  533. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  534. return err;
  535. return 0;
  536. }
  537. static int snd_ymfpci_playback_hw_free(snd_pcm_substream_t * substream)
  538. {
  539. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  540. snd_pcm_runtime_t *runtime = substream->runtime;
  541. ymfpci_pcm_t *ypcm;
  542. if (runtime->private_data == NULL)
  543. return 0;
  544. ypcm = runtime->private_data;
  545. /* wait, until the PCI operations are not finished */
  546. snd_ymfpci_irq_wait(chip);
  547. snd_pcm_lib_free_pages(substream);
  548. if (ypcm->voices[1]) {
  549. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  550. ypcm->voices[1] = NULL;
  551. }
  552. if (ypcm->voices[0]) {
  553. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  554. ypcm->voices[0] = NULL;
  555. }
  556. return 0;
  557. }
  558. static int snd_ymfpci_playback_prepare(snd_pcm_substream_t * substream)
  559. {
  560. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  561. snd_pcm_runtime_t *runtime = substream->runtime;
  562. ymfpci_pcm_t *ypcm = runtime->private_data;
  563. unsigned int nvoice;
  564. ypcm->period_size = runtime->period_size;
  565. ypcm->buffer_size = runtime->buffer_size;
  566. ypcm->period_pos = 0;
  567. ypcm->last_pos = 0;
  568. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  569. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  570. substream->pcm == chip->pcm);
  571. return 0;
  572. }
  573. static int snd_ymfpci_capture_hw_params(snd_pcm_substream_t * substream,
  574. snd_pcm_hw_params_t * hw_params)
  575. {
  576. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  577. }
  578. static int snd_ymfpci_capture_hw_free(snd_pcm_substream_t * substream)
  579. {
  580. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  581. /* wait, until the PCI operations are not finished */
  582. snd_ymfpci_irq_wait(chip);
  583. return snd_pcm_lib_free_pages(substream);
  584. }
  585. static int snd_ymfpci_capture_prepare(snd_pcm_substream_t * substream)
  586. {
  587. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  588. snd_pcm_runtime_t *runtime = substream->runtime;
  589. ymfpci_pcm_t *ypcm = runtime->private_data;
  590. snd_ymfpci_capture_bank_t * bank;
  591. int nbank;
  592. u32 rate, format;
  593. ypcm->period_size = runtime->period_size;
  594. ypcm->buffer_size = runtime->buffer_size;
  595. ypcm->period_pos = 0;
  596. ypcm->last_pos = 0;
  597. ypcm->shift = 0;
  598. rate = ((48000 * 4096) / runtime->rate) - 1;
  599. format = 0;
  600. if (runtime->channels == 2) {
  601. format |= 2;
  602. ypcm->shift++;
  603. }
  604. if (snd_pcm_format_width(runtime->format) == 8)
  605. format |= 1;
  606. else
  607. ypcm->shift++;
  608. switch (ypcm->capture_bank_number) {
  609. case 0:
  610. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  611. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  612. break;
  613. case 1:
  614. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  615. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  616. break;
  617. }
  618. for (nbank = 0; nbank < 2; nbank++) {
  619. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  620. bank->base = cpu_to_le32(runtime->dma_addr);
  621. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  622. bank->start = 0;
  623. bank->num_of_loops = 0;
  624. }
  625. return 0;
  626. }
  627. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(snd_pcm_substream_t * substream)
  628. {
  629. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  630. snd_pcm_runtime_t *runtime = substream->runtime;
  631. ymfpci_pcm_t *ypcm = runtime->private_data;
  632. ymfpci_voice_t *voice = ypcm->voices[0];
  633. if (!(ypcm->running && voice))
  634. return 0;
  635. return le32_to_cpu(voice->bank[chip->active_bank].start);
  636. }
  637. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(snd_pcm_substream_t * substream)
  638. {
  639. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  640. snd_pcm_runtime_t *runtime = substream->runtime;
  641. ymfpci_pcm_t *ypcm = runtime->private_data;
  642. if (!ypcm->running)
  643. return 0;
  644. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  645. }
  646. static void snd_ymfpci_irq_wait(ymfpci_t *chip)
  647. {
  648. wait_queue_t wait;
  649. int loops = 4;
  650. while (loops-- > 0) {
  651. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  652. continue;
  653. init_waitqueue_entry(&wait, current);
  654. add_wait_queue(&chip->interrupt_sleep, &wait);
  655. atomic_inc(&chip->interrupt_sleep_count);
  656. set_current_state(TASK_UNINTERRUPTIBLE);
  657. schedule_timeout(HZ/20);
  658. remove_wait_queue(&chip->interrupt_sleep, &wait);
  659. }
  660. }
  661. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  662. {
  663. ymfpci_t *chip = dev_id;
  664. u32 status, nvoice, mode;
  665. ymfpci_voice_t *voice;
  666. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  667. if (status & 0x80000000) {
  668. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  669. spin_lock(&chip->voice_lock);
  670. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  671. voice = &chip->voices[nvoice];
  672. if (voice->interrupt)
  673. voice->interrupt(chip, voice);
  674. }
  675. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  676. if (chip->capture_substream[nvoice])
  677. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  678. }
  679. #if 0
  680. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  681. if (chip->effect_substream[nvoice])
  682. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  683. }
  684. #endif
  685. spin_unlock(&chip->voice_lock);
  686. spin_lock(&chip->reg_lock);
  687. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  688. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  689. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  690. spin_unlock(&chip->reg_lock);
  691. if (atomic_read(&chip->interrupt_sleep_count)) {
  692. atomic_set(&chip->interrupt_sleep_count, 0);
  693. wake_up(&chip->interrupt_sleep);
  694. }
  695. }
  696. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  697. if (status & 1) {
  698. if (chip->timer)
  699. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  700. }
  701. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  702. if (chip->rawmidi)
  703. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data, regs);
  704. return IRQ_HANDLED;
  705. }
  706. static snd_pcm_hardware_t snd_ymfpci_playback =
  707. {
  708. .info = (SNDRV_PCM_INFO_MMAP |
  709. SNDRV_PCM_INFO_MMAP_VALID |
  710. SNDRV_PCM_INFO_INTERLEAVED |
  711. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  712. SNDRV_PCM_INFO_PAUSE |
  713. SNDRV_PCM_INFO_RESUME),
  714. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  715. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  716. .rate_min = 8000,
  717. .rate_max = 48000,
  718. .channels_min = 1,
  719. .channels_max = 2,
  720. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  721. .period_bytes_min = 64,
  722. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  723. .periods_min = 3,
  724. .periods_max = 1024,
  725. .fifo_size = 0,
  726. };
  727. static snd_pcm_hardware_t snd_ymfpci_capture =
  728. {
  729. .info = (SNDRV_PCM_INFO_MMAP |
  730. SNDRV_PCM_INFO_MMAP_VALID |
  731. SNDRV_PCM_INFO_INTERLEAVED |
  732. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  733. SNDRV_PCM_INFO_PAUSE |
  734. SNDRV_PCM_INFO_RESUME),
  735. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  736. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  737. .rate_min = 8000,
  738. .rate_max = 48000,
  739. .channels_min = 1,
  740. .channels_max = 2,
  741. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  742. .period_bytes_min = 64,
  743. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  744. .periods_min = 3,
  745. .periods_max = 1024,
  746. .fifo_size = 0,
  747. };
  748. static void snd_ymfpci_pcm_free_substream(snd_pcm_runtime_t *runtime)
  749. {
  750. kfree(runtime->private_data);
  751. }
  752. static int snd_ymfpci_playback_open_1(snd_pcm_substream_t * substream)
  753. {
  754. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  755. snd_pcm_runtime_t *runtime = substream->runtime;
  756. ymfpci_pcm_t *ypcm;
  757. ypcm = kcalloc(1, sizeof(*ypcm), GFP_KERNEL);
  758. if (ypcm == NULL)
  759. return -ENOMEM;
  760. ypcm->chip = chip;
  761. ypcm->type = PLAYBACK_VOICE;
  762. ypcm->substream = substream;
  763. runtime->hw = snd_ymfpci_playback;
  764. runtime->private_data = ypcm;
  765. runtime->private_free = snd_ymfpci_pcm_free_substream;
  766. /* FIXME? True value is 256/48 = 5.33333 ms */
  767. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  768. return 0;
  769. }
  770. /* call with spinlock held */
  771. static void ymfpci_open_extension(ymfpci_t *chip)
  772. {
  773. if (! chip->rear_opened) {
  774. if (! chip->spdif_opened) /* set AC3 */
  775. snd_ymfpci_writel(chip, YDSXGR_MODE,
  776. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  777. /* enable second codec (4CHEN) */
  778. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  779. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  780. }
  781. }
  782. /* call with spinlock held */
  783. static void ymfpci_close_extension(ymfpci_t *chip)
  784. {
  785. if (! chip->rear_opened) {
  786. if (! chip->spdif_opened)
  787. snd_ymfpci_writel(chip, YDSXGR_MODE,
  788. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  789. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  790. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  791. }
  792. }
  793. static int snd_ymfpci_playback_open(snd_pcm_substream_t * substream)
  794. {
  795. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  796. snd_pcm_runtime_t *runtime = substream->runtime;
  797. ymfpci_pcm_t *ypcm;
  798. snd_kcontrol_t *kctl;
  799. int err;
  800. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  801. return err;
  802. ypcm = runtime->private_data;
  803. ypcm->output_front = 1;
  804. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  805. spin_lock_irq(&chip->reg_lock);
  806. if (ypcm->output_rear) {
  807. ymfpci_open_extension(chip);
  808. chip->rear_opened++;
  809. }
  810. spin_unlock_irq(&chip->reg_lock);
  811. kctl = chip->pcm_mixer[substream->number].ctl;
  812. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  813. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  814. return 0;
  815. }
  816. static int snd_ymfpci_playback_spdif_open(snd_pcm_substream_t * substream)
  817. {
  818. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  819. snd_pcm_runtime_t *runtime = substream->runtime;
  820. ymfpci_pcm_t *ypcm;
  821. int err;
  822. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  823. return err;
  824. ypcm = runtime->private_data;
  825. ypcm->output_front = 0;
  826. ypcm->output_rear = 1;
  827. spin_lock_irq(&chip->reg_lock);
  828. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  829. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  830. ymfpci_open_extension(chip);
  831. chip->spdif_pcm_bits = chip->spdif_bits;
  832. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  833. chip->spdif_opened++;
  834. spin_unlock_irq(&chip->reg_lock);
  835. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  836. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  837. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  838. return 0;
  839. }
  840. static int snd_ymfpci_playback_4ch_open(snd_pcm_substream_t * substream)
  841. {
  842. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  843. snd_pcm_runtime_t *runtime = substream->runtime;
  844. ymfpci_pcm_t *ypcm;
  845. int err;
  846. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  847. return err;
  848. ypcm = runtime->private_data;
  849. ypcm->output_front = 0;
  850. ypcm->output_rear = 1;
  851. spin_lock_irq(&chip->reg_lock);
  852. ymfpci_open_extension(chip);
  853. chip->rear_opened++;
  854. spin_unlock_irq(&chip->reg_lock);
  855. return 0;
  856. }
  857. static int snd_ymfpci_capture_open(snd_pcm_substream_t * substream,
  858. u32 capture_bank_number)
  859. {
  860. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  861. snd_pcm_runtime_t *runtime = substream->runtime;
  862. ymfpci_pcm_t *ypcm;
  863. ypcm = kcalloc(1, sizeof(*ypcm), GFP_KERNEL);
  864. if (ypcm == NULL)
  865. return -ENOMEM;
  866. ypcm->chip = chip;
  867. ypcm->type = capture_bank_number + CAPTURE_REC;
  868. ypcm->substream = substream;
  869. ypcm->capture_bank_number = capture_bank_number;
  870. chip->capture_substream[capture_bank_number] = substream;
  871. runtime->hw = snd_ymfpci_capture;
  872. /* FIXME? True value is 256/48 = 5.33333 ms */
  873. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 5333, UINT_MAX);
  874. runtime->private_data = ypcm;
  875. runtime->private_free = snd_ymfpci_pcm_free_substream;
  876. snd_ymfpci_hw_start(chip);
  877. return 0;
  878. }
  879. static int snd_ymfpci_capture_rec_open(snd_pcm_substream_t * substream)
  880. {
  881. return snd_ymfpci_capture_open(substream, 0);
  882. }
  883. static int snd_ymfpci_capture_ac97_open(snd_pcm_substream_t * substream)
  884. {
  885. return snd_ymfpci_capture_open(substream, 1);
  886. }
  887. static int snd_ymfpci_playback_close_1(snd_pcm_substream_t * substream)
  888. {
  889. return 0;
  890. }
  891. static int snd_ymfpci_playback_close(snd_pcm_substream_t * substream)
  892. {
  893. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  894. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  895. snd_kcontrol_t *kctl;
  896. spin_lock_irq(&chip->reg_lock);
  897. if (ypcm->output_rear && chip->rear_opened > 0) {
  898. chip->rear_opened--;
  899. ymfpci_close_extension(chip);
  900. }
  901. spin_unlock_irq(&chip->reg_lock);
  902. kctl = chip->pcm_mixer[substream->number].ctl;
  903. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  904. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  905. return snd_ymfpci_playback_close_1(substream);
  906. }
  907. static int snd_ymfpci_playback_spdif_close(snd_pcm_substream_t * substream)
  908. {
  909. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  910. spin_lock_irq(&chip->reg_lock);
  911. chip->spdif_opened = 0;
  912. ymfpci_close_extension(chip);
  913. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  914. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  915. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  916. spin_unlock_irq(&chip->reg_lock);
  917. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  918. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  919. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  920. return snd_ymfpci_playback_close_1(substream);
  921. }
  922. static int snd_ymfpci_playback_4ch_close(snd_pcm_substream_t * substream)
  923. {
  924. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  925. spin_lock_irq(&chip->reg_lock);
  926. if (chip->rear_opened > 0) {
  927. chip->rear_opened--;
  928. ymfpci_close_extension(chip);
  929. }
  930. spin_unlock_irq(&chip->reg_lock);
  931. return snd_ymfpci_playback_close_1(substream);
  932. }
  933. static int snd_ymfpci_capture_close(snd_pcm_substream_t * substream)
  934. {
  935. ymfpci_t *chip = snd_pcm_substream_chip(substream);
  936. snd_pcm_runtime_t *runtime = substream->runtime;
  937. ymfpci_pcm_t *ypcm = runtime->private_data;
  938. if (ypcm != NULL) {
  939. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  940. snd_ymfpci_hw_stop(chip);
  941. }
  942. return 0;
  943. }
  944. static snd_pcm_ops_t snd_ymfpci_playback_ops = {
  945. .open = snd_ymfpci_playback_open,
  946. .close = snd_ymfpci_playback_close,
  947. .ioctl = snd_pcm_lib_ioctl,
  948. .hw_params = snd_ymfpci_playback_hw_params,
  949. .hw_free = snd_ymfpci_playback_hw_free,
  950. .prepare = snd_ymfpci_playback_prepare,
  951. .trigger = snd_ymfpci_playback_trigger,
  952. .pointer = snd_ymfpci_playback_pointer,
  953. };
  954. static snd_pcm_ops_t snd_ymfpci_capture_rec_ops = {
  955. .open = snd_ymfpci_capture_rec_open,
  956. .close = snd_ymfpci_capture_close,
  957. .ioctl = snd_pcm_lib_ioctl,
  958. .hw_params = snd_ymfpci_capture_hw_params,
  959. .hw_free = snd_ymfpci_capture_hw_free,
  960. .prepare = snd_ymfpci_capture_prepare,
  961. .trigger = snd_ymfpci_capture_trigger,
  962. .pointer = snd_ymfpci_capture_pointer,
  963. };
  964. static void snd_ymfpci_pcm_free(snd_pcm_t *pcm)
  965. {
  966. ymfpci_t *chip = pcm->private_data;
  967. chip->pcm = NULL;
  968. snd_pcm_lib_preallocate_free_for_all(pcm);
  969. }
  970. int __devinit snd_ymfpci_pcm(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  971. {
  972. snd_pcm_t *pcm;
  973. int err;
  974. if (rpcm)
  975. *rpcm = NULL;
  976. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  977. return err;
  978. pcm->private_data = chip;
  979. pcm->private_free = snd_ymfpci_pcm_free;
  980. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  981. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  982. /* global setup */
  983. pcm->info_flags = 0;
  984. strcpy(pcm->name, "YMFPCI");
  985. chip->pcm = pcm;
  986. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  987. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  988. if (rpcm)
  989. *rpcm = pcm;
  990. return 0;
  991. }
  992. static snd_pcm_ops_t snd_ymfpci_capture_ac97_ops = {
  993. .open = snd_ymfpci_capture_ac97_open,
  994. .close = snd_ymfpci_capture_close,
  995. .ioctl = snd_pcm_lib_ioctl,
  996. .hw_params = snd_ymfpci_capture_hw_params,
  997. .hw_free = snd_ymfpci_capture_hw_free,
  998. .prepare = snd_ymfpci_capture_prepare,
  999. .trigger = snd_ymfpci_capture_trigger,
  1000. .pointer = snd_ymfpci_capture_pointer,
  1001. };
  1002. static void snd_ymfpci_pcm2_free(snd_pcm_t *pcm)
  1003. {
  1004. ymfpci_t *chip = pcm->private_data;
  1005. chip->pcm2 = NULL;
  1006. snd_pcm_lib_preallocate_free_for_all(pcm);
  1007. }
  1008. int __devinit snd_ymfpci_pcm2(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1009. {
  1010. snd_pcm_t *pcm;
  1011. int err;
  1012. if (rpcm)
  1013. *rpcm = NULL;
  1014. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1015. return err;
  1016. pcm->private_data = chip;
  1017. pcm->private_free = snd_ymfpci_pcm2_free;
  1018. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1019. /* global setup */
  1020. pcm->info_flags = 0;
  1021. sprintf(pcm->name, "YMFPCI - %s",
  1022. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1023. chip->pcm2 = pcm;
  1024. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1025. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1026. if (rpcm)
  1027. *rpcm = pcm;
  1028. return 0;
  1029. }
  1030. static snd_pcm_ops_t snd_ymfpci_playback_spdif_ops = {
  1031. .open = snd_ymfpci_playback_spdif_open,
  1032. .close = snd_ymfpci_playback_spdif_close,
  1033. .ioctl = snd_pcm_lib_ioctl,
  1034. .hw_params = snd_ymfpci_playback_hw_params,
  1035. .hw_free = snd_ymfpci_playback_hw_free,
  1036. .prepare = snd_ymfpci_playback_prepare,
  1037. .trigger = snd_ymfpci_playback_trigger,
  1038. .pointer = snd_ymfpci_playback_pointer,
  1039. };
  1040. static void snd_ymfpci_pcm_spdif_free(snd_pcm_t *pcm)
  1041. {
  1042. ymfpci_t *chip = pcm->private_data;
  1043. chip->pcm_spdif = NULL;
  1044. snd_pcm_lib_preallocate_free_for_all(pcm);
  1045. }
  1046. int __devinit snd_ymfpci_pcm_spdif(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1047. {
  1048. snd_pcm_t *pcm;
  1049. int err;
  1050. if (rpcm)
  1051. *rpcm = NULL;
  1052. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1053. return err;
  1054. pcm->private_data = chip;
  1055. pcm->private_free = snd_ymfpci_pcm_spdif_free;
  1056. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1057. /* global setup */
  1058. pcm->info_flags = 0;
  1059. strcpy(pcm->name, "YMFPCI - IEC958");
  1060. chip->pcm_spdif = pcm;
  1061. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1062. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1063. if (rpcm)
  1064. *rpcm = pcm;
  1065. return 0;
  1066. }
  1067. static snd_pcm_ops_t snd_ymfpci_playback_4ch_ops = {
  1068. .open = snd_ymfpci_playback_4ch_open,
  1069. .close = snd_ymfpci_playback_4ch_close,
  1070. .ioctl = snd_pcm_lib_ioctl,
  1071. .hw_params = snd_ymfpci_playback_hw_params,
  1072. .hw_free = snd_ymfpci_playback_hw_free,
  1073. .prepare = snd_ymfpci_playback_prepare,
  1074. .trigger = snd_ymfpci_playback_trigger,
  1075. .pointer = snd_ymfpci_playback_pointer,
  1076. };
  1077. static void snd_ymfpci_pcm_4ch_free(snd_pcm_t *pcm)
  1078. {
  1079. ymfpci_t *chip = pcm->private_data;
  1080. chip->pcm_4ch = NULL;
  1081. snd_pcm_lib_preallocate_free_for_all(pcm);
  1082. }
  1083. int __devinit snd_ymfpci_pcm_4ch(ymfpci_t *chip, int device, snd_pcm_t ** rpcm)
  1084. {
  1085. snd_pcm_t *pcm;
  1086. int err;
  1087. if (rpcm)
  1088. *rpcm = NULL;
  1089. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1090. return err;
  1091. pcm->private_data = chip;
  1092. pcm->private_free = snd_ymfpci_pcm_4ch_free;
  1093. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1094. /* global setup */
  1095. pcm->info_flags = 0;
  1096. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1097. chip->pcm_4ch = pcm;
  1098. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1099. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1100. if (rpcm)
  1101. *rpcm = pcm;
  1102. return 0;
  1103. }
  1104. static int snd_ymfpci_spdif_default_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1105. {
  1106. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1107. uinfo->count = 1;
  1108. return 0;
  1109. }
  1110. static int snd_ymfpci_spdif_default_get(snd_kcontrol_t * kcontrol,
  1111. snd_ctl_elem_value_t * ucontrol)
  1112. {
  1113. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1114. spin_lock_irq(&chip->reg_lock);
  1115. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1116. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1117. spin_unlock_irq(&chip->reg_lock);
  1118. return 0;
  1119. }
  1120. static int snd_ymfpci_spdif_default_put(snd_kcontrol_t * kcontrol,
  1121. snd_ctl_elem_value_t * ucontrol)
  1122. {
  1123. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1124. unsigned int val;
  1125. int change;
  1126. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1127. (ucontrol->value.iec958.status[1] << 8);
  1128. spin_lock_irq(&chip->reg_lock);
  1129. change = chip->spdif_bits != val;
  1130. chip->spdif_bits = val;
  1131. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1132. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1133. spin_unlock_irq(&chip->reg_lock);
  1134. return change;
  1135. }
  1136. static snd_kcontrol_new_t snd_ymfpci_spdif_default __devinitdata =
  1137. {
  1138. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1139. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1140. .info = snd_ymfpci_spdif_default_info,
  1141. .get = snd_ymfpci_spdif_default_get,
  1142. .put = snd_ymfpci_spdif_default_put
  1143. };
  1144. static int snd_ymfpci_spdif_mask_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1145. {
  1146. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1147. uinfo->count = 1;
  1148. return 0;
  1149. }
  1150. static int snd_ymfpci_spdif_mask_get(snd_kcontrol_t * kcontrol,
  1151. snd_ctl_elem_value_t * ucontrol)
  1152. {
  1153. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1154. spin_lock_irq(&chip->reg_lock);
  1155. ucontrol->value.iec958.status[0] = 0x3e;
  1156. ucontrol->value.iec958.status[1] = 0xff;
  1157. spin_unlock_irq(&chip->reg_lock);
  1158. return 0;
  1159. }
  1160. static snd_kcontrol_new_t snd_ymfpci_spdif_mask __devinitdata =
  1161. {
  1162. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1163. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1164. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1165. .info = snd_ymfpci_spdif_mask_info,
  1166. .get = snd_ymfpci_spdif_mask_get,
  1167. };
  1168. static int snd_ymfpci_spdif_stream_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1169. {
  1170. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1171. uinfo->count = 1;
  1172. return 0;
  1173. }
  1174. static int snd_ymfpci_spdif_stream_get(snd_kcontrol_t * kcontrol,
  1175. snd_ctl_elem_value_t * ucontrol)
  1176. {
  1177. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1178. spin_lock_irq(&chip->reg_lock);
  1179. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1180. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1181. spin_unlock_irq(&chip->reg_lock);
  1182. return 0;
  1183. }
  1184. static int snd_ymfpci_spdif_stream_put(snd_kcontrol_t * kcontrol,
  1185. snd_ctl_elem_value_t * ucontrol)
  1186. {
  1187. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1188. unsigned int val;
  1189. int change;
  1190. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1191. (ucontrol->value.iec958.status[1] << 8);
  1192. spin_lock_irq(&chip->reg_lock);
  1193. change = chip->spdif_pcm_bits != val;
  1194. chip->spdif_pcm_bits = val;
  1195. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1196. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1197. spin_unlock_irq(&chip->reg_lock);
  1198. return change;
  1199. }
  1200. static snd_kcontrol_new_t snd_ymfpci_spdif_stream __devinitdata =
  1201. {
  1202. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1203. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1204. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1205. .info = snd_ymfpci_spdif_stream_info,
  1206. .get = snd_ymfpci_spdif_stream_get,
  1207. .put = snd_ymfpci_spdif_stream_put
  1208. };
  1209. static int snd_ymfpci_drec_source_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *info)
  1210. {
  1211. static char *texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1212. info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1213. info->count = 1;
  1214. info->value.enumerated.items = 3;
  1215. if (info->value.enumerated.item > 2)
  1216. info->value.enumerated.item = 2;
  1217. strcpy(info->value.enumerated.name, texts[info->value.enumerated.item]);
  1218. return 0;
  1219. }
  1220. static int snd_ymfpci_drec_source_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  1221. {
  1222. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1223. u16 reg;
  1224. spin_lock_irq(&chip->reg_lock);
  1225. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1226. spin_unlock_irq(&chip->reg_lock);
  1227. if (!(reg & 0x100))
  1228. value->value.enumerated.item[0] = 0;
  1229. else
  1230. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1231. return 0;
  1232. }
  1233. static int snd_ymfpci_drec_source_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  1234. {
  1235. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1236. u16 reg, old_reg;
  1237. spin_lock_irq(&chip->reg_lock);
  1238. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1239. if (value->value.enumerated.item[0] == 0)
  1240. reg = old_reg & ~0x100;
  1241. else
  1242. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1243. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1244. spin_unlock_irq(&chip->reg_lock);
  1245. return reg != old_reg;
  1246. }
  1247. static snd_kcontrol_new_t snd_ymfpci_drec_source __devinitdata = {
  1248. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1249. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1250. .name = "Direct Recording Source",
  1251. .info = snd_ymfpci_drec_source_info,
  1252. .get = snd_ymfpci_drec_source_get,
  1253. .put = snd_ymfpci_drec_source_put
  1254. };
  1255. /*
  1256. * Mixer controls
  1257. */
  1258. #define YMFPCI_SINGLE(xname, xindex, reg) \
  1259. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1260. .info = snd_ymfpci_info_single, \
  1261. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1262. .private_value = reg }
  1263. static int snd_ymfpci_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1264. {
  1265. switch (kcontrol->private_value) {
  1266. case YDSXGR_SPDIFOUTCTRL: break;
  1267. case YDSXGR_SPDIFINCTRL: break;
  1268. default: return -EINVAL;
  1269. }
  1270. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1271. uinfo->count = 1;
  1272. uinfo->value.integer.min = 0;
  1273. uinfo->value.integer.max = 1;
  1274. return 0;
  1275. }
  1276. static int snd_ymfpci_get_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1277. {
  1278. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1279. int reg = kcontrol->private_value;
  1280. unsigned int shift = 0, mask = 1;
  1281. switch (kcontrol->private_value) {
  1282. case YDSXGR_SPDIFOUTCTRL: break;
  1283. case YDSXGR_SPDIFINCTRL: break;
  1284. default: return -EINVAL;
  1285. }
  1286. ucontrol->value.integer.value[0] = (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1287. return 0;
  1288. }
  1289. static int snd_ymfpci_put_single(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1290. {
  1291. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1292. int reg = kcontrol->private_value;
  1293. unsigned int shift = 0, mask = 1;
  1294. int change;
  1295. unsigned int val, oval;
  1296. switch (kcontrol->private_value) {
  1297. case YDSXGR_SPDIFOUTCTRL: break;
  1298. case YDSXGR_SPDIFINCTRL: break;
  1299. default: return -EINVAL;
  1300. }
  1301. val = (ucontrol->value.integer.value[0] & mask);
  1302. val <<= shift;
  1303. spin_lock_irq(&chip->reg_lock);
  1304. oval = snd_ymfpci_readl(chip, reg);
  1305. val = (oval & ~(mask << shift)) | val;
  1306. change = val != oval;
  1307. snd_ymfpci_writel(chip, reg, val);
  1308. spin_unlock_irq(&chip->reg_lock);
  1309. return change;
  1310. }
  1311. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1312. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1313. .info = snd_ymfpci_info_double, \
  1314. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1315. .private_value = reg }
  1316. static int snd_ymfpci_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1317. {
  1318. unsigned int reg = kcontrol->private_value;
  1319. if (reg < 0x80 || reg >= 0xc0)
  1320. return -EINVAL;
  1321. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1322. uinfo->count = 2;
  1323. uinfo->value.integer.min = 0;
  1324. uinfo->value.integer.max = 16383;
  1325. return 0;
  1326. }
  1327. static int snd_ymfpci_get_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1328. {
  1329. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1330. unsigned int reg = kcontrol->private_value;
  1331. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1332. unsigned int val;
  1333. if (reg < 0x80 || reg >= 0xc0)
  1334. return -EINVAL;
  1335. spin_lock_irq(&chip->reg_lock);
  1336. val = snd_ymfpci_readl(chip, reg);
  1337. spin_unlock_irq(&chip->reg_lock);
  1338. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1339. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1340. return 0;
  1341. }
  1342. static int snd_ymfpci_put_double(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1343. {
  1344. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1345. unsigned int reg = kcontrol->private_value;
  1346. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1347. int change;
  1348. unsigned int val1, val2, oval;
  1349. if (reg < 0x80 || reg >= 0xc0)
  1350. return -EINVAL;
  1351. val1 = ucontrol->value.integer.value[0] & mask;
  1352. val2 = ucontrol->value.integer.value[1] & mask;
  1353. val1 <<= shift_left;
  1354. val2 <<= shift_right;
  1355. spin_lock_irq(&chip->reg_lock);
  1356. oval = snd_ymfpci_readl(chip, reg);
  1357. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1358. change = val1 != oval;
  1359. snd_ymfpci_writel(chip, reg, val1);
  1360. spin_unlock_irq(&chip->reg_lock);
  1361. return change;
  1362. }
  1363. /*
  1364. * 4ch duplication
  1365. */
  1366. static int snd_ymfpci_info_dup4ch(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo)
  1367. {
  1368. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1369. uinfo->count = 1;
  1370. uinfo->value.integer.min = 0;
  1371. uinfo->value.integer.max = 1;
  1372. return 0;
  1373. }
  1374. static int snd_ymfpci_get_dup4ch(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1375. {
  1376. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1377. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1378. return 0;
  1379. }
  1380. static int snd_ymfpci_put_dup4ch(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol)
  1381. {
  1382. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1383. int change;
  1384. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1385. if (change)
  1386. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1387. return change;
  1388. }
  1389. static snd_kcontrol_new_t snd_ymfpci_controls[] __devinitdata = {
  1390. YMFPCI_DOUBLE("Wave Playback Volume", 0, YDSXGR_NATIVEDACOUTVOL),
  1391. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1392. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1393. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1394. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1395. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1396. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1397. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1398. YMFPCI_DOUBLE("FM Legacy Volume", 0, YDSXGR_LEGACYOUTVOL),
  1399. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1400. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1401. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1402. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1403. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL),
  1404. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL),
  1405. {
  1406. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1407. .name = "4ch Duplication",
  1408. .info = snd_ymfpci_info_dup4ch,
  1409. .get = snd_ymfpci_get_dup4ch,
  1410. .put = snd_ymfpci_put_dup4ch,
  1411. },
  1412. };
  1413. /*
  1414. * GPIO
  1415. */
  1416. static int snd_ymfpci_get_gpio_out(ymfpci_t *chip, int pin)
  1417. {
  1418. u16 reg, mode;
  1419. unsigned long flags;
  1420. spin_lock_irqsave(&chip->reg_lock, flags);
  1421. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1422. reg &= ~(1 << (pin + 8));
  1423. reg |= (1 << pin);
  1424. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1425. /* set the level mode for input line */
  1426. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1427. mode &= ~(3 << (pin * 2));
  1428. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1429. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1430. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1431. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1432. return (mode >> pin) & 1;
  1433. }
  1434. static int snd_ymfpci_set_gpio_out(ymfpci_t *chip, int pin, int enable)
  1435. {
  1436. u16 reg;
  1437. unsigned long flags;
  1438. spin_lock_irqsave(&chip->reg_lock, flags);
  1439. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1440. reg &= ~(1 << pin);
  1441. reg &= ~(1 << (pin + 8));
  1442. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1443. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1444. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1445. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1446. return 0;
  1447. }
  1448. static int snd_ymfpci_gpio_sw_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo)
  1449. {
  1450. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1451. uinfo->count = 1;
  1452. uinfo->value.integer.min = 0;
  1453. uinfo->value.integer.max = 1;
  1454. return 0;
  1455. }
  1456. static int snd_ymfpci_gpio_sw_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1457. {
  1458. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1459. int pin = (int)kcontrol->private_value;
  1460. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1461. return 0;
  1462. }
  1463. static int snd_ymfpci_gpio_sw_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol)
  1464. {
  1465. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1466. int pin = (int)kcontrol->private_value;
  1467. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1468. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1469. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1470. return 1;
  1471. }
  1472. return 0;
  1473. }
  1474. static snd_kcontrol_new_t snd_ymfpci_rear_shared __devinitdata = {
  1475. .name = "Shared Rear/Line-In Switch",
  1476. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1477. .info = snd_ymfpci_gpio_sw_info,
  1478. .get = snd_ymfpci_gpio_sw_get,
  1479. .put = snd_ymfpci_gpio_sw_put,
  1480. .private_value = 2,
  1481. };
  1482. /*
  1483. * PCM voice volume
  1484. */
  1485. static int snd_ymfpci_pcm_vol_info(snd_kcontrol_t *kcontrol,
  1486. snd_ctl_elem_info_t *uinfo)
  1487. {
  1488. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1489. uinfo->count = 2;
  1490. uinfo->value.integer.min = 0;
  1491. uinfo->value.integer.max = 0x8000;
  1492. return 0;
  1493. }
  1494. static int snd_ymfpci_pcm_vol_get(snd_kcontrol_t *kcontrol,
  1495. snd_ctl_elem_value_t *ucontrol)
  1496. {
  1497. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1498. unsigned int subs = kcontrol->id.subdevice;
  1499. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1500. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1501. return 0;
  1502. }
  1503. static int snd_ymfpci_pcm_vol_put(snd_kcontrol_t *kcontrol,
  1504. snd_ctl_elem_value_t *ucontrol)
  1505. {
  1506. ymfpci_t *chip = snd_kcontrol_chip(kcontrol);
  1507. unsigned int subs = kcontrol->id.subdevice;
  1508. snd_pcm_substream_t *substream;
  1509. unsigned long flags;
  1510. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1511. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1512. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1513. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1514. substream = (snd_pcm_substream_t *)kcontrol->private_value;
  1515. spin_lock_irqsave(&chip->voice_lock, flags);
  1516. if (substream->runtime && substream->runtime->private_data) {
  1517. ymfpci_pcm_t *ypcm = substream->runtime->private_data;
  1518. ypcm->update_pcm_vol = 2;
  1519. }
  1520. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1521. return 1;
  1522. }
  1523. return 0;
  1524. }
  1525. static snd_kcontrol_new_t snd_ymfpci_pcm_volume __devinitdata = {
  1526. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1527. .name = "PCM Playback Volume",
  1528. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1529. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1530. .info = snd_ymfpci_pcm_vol_info,
  1531. .get = snd_ymfpci_pcm_vol_get,
  1532. .put = snd_ymfpci_pcm_vol_put,
  1533. };
  1534. /*
  1535. * Mixer routines
  1536. */
  1537. static void snd_ymfpci_mixer_free_ac97_bus(ac97_bus_t *bus)
  1538. {
  1539. ymfpci_t *chip = bus->private_data;
  1540. chip->ac97_bus = NULL;
  1541. }
  1542. static void snd_ymfpci_mixer_free_ac97(ac97_t *ac97)
  1543. {
  1544. ymfpci_t *chip = ac97->private_data;
  1545. chip->ac97 = NULL;
  1546. }
  1547. int __devinit snd_ymfpci_mixer(ymfpci_t *chip, int rear_switch)
  1548. {
  1549. ac97_template_t ac97;
  1550. snd_kcontrol_t *kctl;
  1551. snd_pcm_substream_t *substream;
  1552. unsigned int idx;
  1553. int err;
  1554. static ac97_bus_ops_t ops = {
  1555. .write = snd_ymfpci_codec_write,
  1556. .read = snd_ymfpci_codec_read,
  1557. };
  1558. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1559. return err;
  1560. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1561. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1562. memset(&ac97, 0, sizeof(ac97));
  1563. ac97.private_data = chip;
  1564. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1565. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1566. return err;
  1567. /* to be sure */
  1568. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1569. AC97_EA_VRA|AC97_EA_VRM, 0);
  1570. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1571. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1572. return err;
  1573. }
  1574. /* add S/PDIF control */
  1575. snd_assert(chip->pcm_spdif != NULL, return -EIO);
  1576. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1577. return err;
  1578. kctl->id.device = chip->pcm_spdif->device;
  1579. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1580. return err;
  1581. kctl->id.device = chip->pcm_spdif->device;
  1582. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1583. return err;
  1584. kctl->id.device = chip->pcm_spdif->device;
  1585. chip->spdif_pcm_ctl = kctl;
  1586. /* direct recording source */
  1587. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1588. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1589. return err;
  1590. /*
  1591. * shared rear/line-in
  1592. */
  1593. if (rear_switch) {
  1594. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1595. return err;
  1596. }
  1597. /* per-voice volume */
  1598. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1599. for (idx = 0; idx < 32; ++idx) {
  1600. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1601. if (!kctl)
  1602. return -ENOMEM;
  1603. kctl->id.device = chip->pcm->device;
  1604. kctl->id.subdevice = idx;
  1605. kctl->private_value = (unsigned long)substream;
  1606. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1607. return err;
  1608. chip->pcm_mixer[idx].left = 0x8000;
  1609. chip->pcm_mixer[idx].right = 0x8000;
  1610. chip->pcm_mixer[idx].ctl = kctl;
  1611. substream = substream->next;
  1612. }
  1613. return 0;
  1614. }
  1615. /*
  1616. * timer
  1617. */
  1618. static int snd_ymfpci_timer_start(snd_timer_t *timer)
  1619. {
  1620. ymfpci_t *chip;
  1621. unsigned long flags;
  1622. unsigned int count;
  1623. chip = snd_timer_chip(timer);
  1624. count = timer->sticks - 1;
  1625. if (count == 0) /* minimum time is 20.8 us */
  1626. count = 1;
  1627. spin_lock_irqsave(&chip->reg_lock, flags);
  1628. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1629. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1630. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1631. return 0;
  1632. }
  1633. static int snd_ymfpci_timer_stop(snd_timer_t *timer)
  1634. {
  1635. ymfpci_t *chip;
  1636. unsigned long flags;
  1637. chip = snd_timer_chip(timer);
  1638. spin_lock_irqsave(&chip->reg_lock, flags);
  1639. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1640. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1641. return 0;
  1642. }
  1643. static int snd_ymfpci_timer_precise_resolution(snd_timer_t *timer,
  1644. unsigned long *num, unsigned long *den)
  1645. {
  1646. *num = 1;
  1647. *den = 96000;
  1648. return 0;
  1649. }
  1650. static struct _snd_timer_hardware snd_ymfpci_timer_hw = {
  1651. .flags = SNDRV_TIMER_HW_AUTO,
  1652. .resolution = 10417, /* 1/2fs = 10.41666...us */
  1653. .ticks = 65536,
  1654. .start = snd_ymfpci_timer_start,
  1655. .stop = snd_ymfpci_timer_stop,
  1656. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1657. };
  1658. int __devinit snd_ymfpci_timer(ymfpci_t *chip, int device)
  1659. {
  1660. snd_timer_t *timer = NULL;
  1661. snd_timer_id_t tid;
  1662. int err;
  1663. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1664. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1665. tid.card = chip->card->number;
  1666. tid.device = device;
  1667. tid.subdevice = 0;
  1668. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1669. strcpy(timer->name, "YMFPCI timer");
  1670. timer->private_data = chip;
  1671. timer->hw = snd_ymfpci_timer_hw;
  1672. }
  1673. chip->timer = timer;
  1674. return err;
  1675. }
  1676. /*
  1677. * proc interface
  1678. */
  1679. static void snd_ymfpci_proc_read(snd_info_entry_t *entry,
  1680. snd_info_buffer_t * buffer)
  1681. {
  1682. ymfpci_t *chip = entry->private_data;
  1683. int i;
  1684. snd_iprintf(buffer, "YMFPCI\n\n");
  1685. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1686. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1687. }
  1688. static int __devinit snd_ymfpci_proc_init(snd_card_t * card, ymfpci_t *chip)
  1689. {
  1690. snd_info_entry_t *entry;
  1691. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1692. snd_info_set_text_ops(entry, chip, 1024, snd_ymfpci_proc_read);
  1693. return 0;
  1694. }
  1695. /*
  1696. * initialization routines
  1697. */
  1698. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1699. {
  1700. u8 cmd;
  1701. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1702. #if 0 // force to reset
  1703. if (cmd & 0x03) {
  1704. #endif
  1705. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1706. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1707. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1708. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1709. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1710. #if 0
  1711. }
  1712. #endif
  1713. }
  1714. static void snd_ymfpci_enable_dsp(ymfpci_t *chip)
  1715. {
  1716. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1717. }
  1718. static void snd_ymfpci_disable_dsp(ymfpci_t *chip)
  1719. {
  1720. u32 val;
  1721. int timeout = 1000;
  1722. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1723. if (val)
  1724. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1725. while (timeout-- > 0) {
  1726. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1727. if ((val & 0x00000002) == 0)
  1728. break;
  1729. }
  1730. }
  1731. #include "ymfpci_image.h"
  1732. static void snd_ymfpci_download_image(ymfpci_t *chip)
  1733. {
  1734. int i;
  1735. u16 ctrl;
  1736. unsigned long *inst;
  1737. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1738. snd_ymfpci_disable_dsp(chip);
  1739. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1740. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1741. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1742. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1743. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1744. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1745. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1746. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1747. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1748. /* setup DSP instruction code */
  1749. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1750. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2), DspInst[i]);
  1751. /* setup control instruction code */
  1752. switch (chip->device_id) {
  1753. case PCI_DEVICE_ID_YAMAHA_724F:
  1754. case PCI_DEVICE_ID_YAMAHA_740C:
  1755. case PCI_DEVICE_ID_YAMAHA_744:
  1756. case PCI_DEVICE_ID_YAMAHA_754:
  1757. inst = CntrlInst1E;
  1758. break;
  1759. default:
  1760. inst = CntrlInst;
  1761. break;
  1762. }
  1763. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1764. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2), inst[i]);
  1765. snd_ymfpci_enable_dsp(chip);
  1766. }
  1767. static int __devinit snd_ymfpci_memalloc(ymfpci_t *chip)
  1768. {
  1769. long size, playback_ctrl_size;
  1770. int voice, bank, reg;
  1771. u8 *ptr;
  1772. dma_addr_t ptr_addr;
  1773. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1774. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1775. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1776. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1777. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1778. size = ((playback_ctrl_size + 0x00ff) & ~0x00ff) +
  1779. ((chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES + 0x00ff) & ~0x00ff) +
  1780. ((chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES + 0x00ff) & ~0x00ff) +
  1781. ((chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES + 0x00ff) & ~0x00ff) +
  1782. chip->work_size;
  1783. /* work_ptr must be aligned to 256 bytes, but it's already
  1784. covered with the kernel page allocation mechanism */
  1785. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1786. size, &chip->work_ptr) < 0)
  1787. return -ENOMEM;
  1788. ptr = chip->work_ptr.area;
  1789. ptr_addr = chip->work_ptr.addr;
  1790. memset(ptr, 0, size); /* for sure */
  1791. chip->bank_base_playback = ptr;
  1792. chip->bank_base_playback_addr = ptr_addr;
  1793. chip->ctrl_playback = (u32 *)ptr;
  1794. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1795. ptr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
  1796. ptr_addr += (playback_ctrl_size + 0x00ff) & ~0x00ff;
  1797. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1798. chip->voices[voice].number = voice;
  1799. chip->voices[voice].bank = (snd_ymfpci_playback_bank_t *)ptr;
  1800. chip->voices[voice].bank_addr = ptr_addr;
  1801. for (bank = 0; bank < 2; bank++) {
  1802. chip->bank_playback[voice][bank] = (snd_ymfpci_playback_bank_t *)ptr;
  1803. ptr += chip->bank_size_playback;
  1804. ptr_addr += chip->bank_size_playback;
  1805. }
  1806. }
  1807. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1808. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1809. chip->bank_base_capture = ptr;
  1810. chip->bank_base_capture_addr = ptr_addr;
  1811. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1812. for (bank = 0; bank < 2; bank++) {
  1813. chip->bank_capture[voice][bank] = (snd_ymfpci_capture_bank_t *)ptr;
  1814. ptr += chip->bank_size_capture;
  1815. ptr_addr += chip->bank_size_capture;
  1816. }
  1817. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1818. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1819. chip->bank_base_effect = ptr;
  1820. chip->bank_base_effect_addr = ptr_addr;
  1821. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1822. for (bank = 0; bank < 2; bank++) {
  1823. chip->bank_effect[voice][bank] = (snd_ymfpci_effect_bank_t *)ptr;
  1824. ptr += chip->bank_size_effect;
  1825. ptr_addr += chip->bank_size_effect;
  1826. }
  1827. ptr = (char *)(((unsigned long)ptr + 0x00ff) & ~0x00ff);
  1828. ptr_addr = (ptr_addr + 0x00ff) & ~0x00ff;
  1829. chip->work_base = ptr;
  1830. chip->work_base_addr = ptr_addr;
  1831. snd_assert(ptr + chip->work_size == chip->work_ptr.area + chip->work_ptr.bytes, );
  1832. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1833. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1834. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1835. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1836. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1837. /* S/PDIF output initialization */
  1838. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1839. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1840. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1841. /* S/PDIF input initialization */
  1842. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1843. /* digital mixer setup */
  1844. for (reg = 0x80; reg < 0xc0; reg += 4)
  1845. snd_ymfpci_writel(chip, reg, 0);
  1846. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1847. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1848. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1849. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1850. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1851. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1852. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1853. return 0;
  1854. }
  1855. static int snd_ymfpci_free(ymfpci_t *chip)
  1856. {
  1857. u16 ctrl;
  1858. snd_assert(chip != NULL, return -EINVAL);
  1859. if (chip->res_reg_area) { /* don't touch busy hardware */
  1860. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1861. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1862. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1863. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1864. snd_ymfpci_disable_dsp(chip);
  1865. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1866. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1867. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1868. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1869. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1870. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1871. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1872. }
  1873. snd_ymfpci_ac3_done(chip);
  1874. /* Set PCI device to D3 state */
  1875. #if 0
  1876. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1877. * the chip again unless reboot. ACPI bug?
  1878. */
  1879. pci_set_power_state(chip->pci, 3);
  1880. #endif
  1881. #ifdef CONFIG_PM
  1882. vfree(chip->saved_regs);
  1883. #endif
  1884. if (chip->mpu_res) {
  1885. release_resource(chip->mpu_res);
  1886. kfree_nocheck(chip->mpu_res);
  1887. }
  1888. if (chip->fm_res) {
  1889. release_resource(chip->fm_res);
  1890. kfree_nocheck(chip->fm_res);
  1891. }
  1892. snd_ymfpci_free_gameport(chip);
  1893. if (chip->reg_area_virt)
  1894. iounmap(chip->reg_area_virt);
  1895. if (chip->work_ptr.area)
  1896. snd_dma_free_pages(&chip->work_ptr);
  1897. if (chip->irq >= 0)
  1898. free_irq(chip->irq, (void *)chip);
  1899. if (chip->res_reg_area) {
  1900. release_resource(chip->res_reg_area);
  1901. kfree_nocheck(chip->res_reg_area);
  1902. }
  1903. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1904. pci_disable_device(chip->pci);
  1905. kfree(chip);
  1906. return 0;
  1907. }
  1908. static int snd_ymfpci_dev_free(snd_device_t *device)
  1909. {
  1910. ymfpci_t *chip = device->device_data;
  1911. return snd_ymfpci_free(chip);
  1912. }
  1913. #ifdef CONFIG_PM
  1914. static int saved_regs_index[] = {
  1915. /* spdif */
  1916. YDSXGR_SPDIFOUTCTRL,
  1917. YDSXGR_SPDIFOUTSTATUS,
  1918. YDSXGR_SPDIFINCTRL,
  1919. /* volumes */
  1920. YDSXGR_PRIADCLOOPVOL,
  1921. YDSXGR_NATIVEDACINVOL,
  1922. YDSXGR_NATIVEDACOUTVOL,
  1923. // YDSXGR_BUF441OUTVOL,
  1924. YDSXGR_NATIVEADCINVOL,
  1925. YDSXGR_SPDIFLOOPVOL,
  1926. YDSXGR_SPDIFOUTVOL,
  1927. YDSXGR_ZVOUTVOL,
  1928. YDSXGR_LEGACYOUTVOL,
  1929. /* address bases */
  1930. YDSXGR_PLAYCTRLBASE,
  1931. YDSXGR_RECCTRLBASE,
  1932. YDSXGR_EFFCTRLBASE,
  1933. YDSXGR_WORKBASE,
  1934. /* capture set up */
  1935. YDSXGR_MAPOFREC,
  1936. YDSXGR_RECFORMAT,
  1937. YDSXGR_RECSLOTSR,
  1938. YDSXGR_ADCFORMAT,
  1939. YDSXGR_ADCSLOTSR,
  1940. };
  1941. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  1942. static int snd_ymfpci_suspend(snd_card_t *card, pm_message_t state)
  1943. {
  1944. ymfpci_t *chip = card->pm_private_data;
  1945. unsigned int i;
  1946. snd_pcm_suspend_all(chip->pcm);
  1947. snd_pcm_suspend_all(chip->pcm2);
  1948. snd_pcm_suspend_all(chip->pcm_spdif);
  1949. snd_pcm_suspend_all(chip->pcm_4ch);
  1950. snd_ac97_suspend(chip->ac97);
  1951. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1952. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  1953. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  1954. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1955. snd_ymfpci_disable_dsp(chip);
  1956. pci_disable_device(chip->pci);
  1957. return 0;
  1958. }
  1959. static int snd_ymfpci_resume(snd_card_t *card)
  1960. {
  1961. ymfpci_t *chip = card->pm_private_data;
  1962. unsigned int i;
  1963. pci_enable_device(chip->pci);
  1964. pci_set_master(chip->pci);
  1965. snd_ymfpci_aclink_reset(chip->pci);
  1966. snd_ymfpci_codec_ready(chip, 0);
  1967. snd_ymfpci_download_image(chip);
  1968. udelay(100);
  1969. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  1970. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  1971. snd_ac97_resume(chip->ac97);
  1972. /* start hw again */
  1973. if (chip->start_count > 0) {
  1974. spin_lock_irq(&chip->reg_lock);
  1975. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  1976. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  1977. spin_unlock_irq(&chip->reg_lock);
  1978. }
  1979. return 0;
  1980. }
  1981. #endif /* CONFIG_PM */
  1982. int __devinit snd_ymfpci_create(snd_card_t * card,
  1983. struct pci_dev * pci,
  1984. unsigned short old_legacy_ctrl,
  1985. ymfpci_t ** rchip)
  1986. {
  1987. ymfpci_t *chip;
  1988. int err;
  1989. static snd_device_ops_t ops = {
  1990. .dev_free = snd_ymfpci_dev_free,
  1991. };
  1992. *rchip = NULL;
  1993. /* enable PCI device */
  1994. if ((err = pci_enable_device(pci)) < 0)
  1995. return err;
  1996. chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
  1997. if (chip == NULL) {
  1998. pci_disable_device(pci);
  1999. return -ENOMEM;
  2000. }
  2001. chip->old_legacy_ctrl = old_legacy_ctrl;
  2002. spin_lock_init(&chip->reg_lock);
  2003. spin_lock_init(&chip->voice_lock);
  2004. init_waitqueue_head(&chip->interrupt_sleep);
  2005. atomic_set(&chip->interrupt_sleep_count, 0);
  2006. chip->card = card;
  2007. chip->pci = pci;
  2008. chip->irq = -1;
  2009. chip->device_id = pci->device;
  2010. pci_read_config_byte(pci, PCI_REVISION_ID, (u8 *)&chip->rev);
  2011. chip->reg_area_phys = pci_resource_start(pci, 0);
  2012. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2013. pci_set_master(pci);
  2014. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2015. snd_printk("unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2016. snd_ymfpci_free(chip);
  2017. return -EBUSY;
  2018. }
  2019. if (request_irq(pci->irq, snd_ymfpci_interrupt, SA_INTERRUPT|SA_SHIRQ, "YMFPCI", (void *) chip)) {
  2020. snd_printk("unable to grab IRQ %d\n", pci->irq);
  2021. snd_ymfpci_free(chip);
  2022. return -EBUSY;
  2023. }
  2024. chip->irq = pci->irq;
  2025. snd_ymfpci_aclink_reset(pci);
  2026. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2027. snd_ymfpci_free(chip);
  2028. return -EIO;
  2029. }
  2030. snd_ymfpci_download_image(chip);
  2031. udelay(100); /* seems we need a delay after downloading image.. */
  2032. if (snd_ymfpci_memalloc(chip) < 0) {
  2033. snd_ymfpci_free(chip);
  2034. return -EIO;
  2035. }
  2036. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2037. snd_ymfpci_free(chip);
  2038. return err;
  2039. }
  2040. #ifdef CONFIG_PM
  2041. chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
  2042. if (chip->saved_regs == NULL) {
  2043. snd_ymfpci_free(chip);
  2044. return -ENOMEM;
  2045. }
  2046. snd_card_set_pm_callback(card, snd_ymfpci_suspend, snd_ymfpci_resume, chip);
  2047. #endif
  2048. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2049. snd_ymfpci_free(chip);
  2050. return err;
  2051. }
  2052. snd_ymfpci_proc_init(card, chip);
  2053. snd_card_set_dev(card, &pci->dev);
  2054. *rchip = chip;
  2055. return 0;
  2056. }