rme32.c 58 KB

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  1. /*
  2. * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
  3. *
  4. * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
  5. * Pilo Chambert <pilo.c@wanadoo.fr>
  6. *
  7. * Thanks to : Anders Torger <torger@ludd.luth.se>,
  8. * Henk Hesselink <henk@anda.nl>
  9. * for writing the digi96-driver
  10. * and RME for all informations.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25. *
  26. *
  27. * ****************************************************************************
  28. *
  29. * Note #1 "Sek'd models" ................................... martin 2002-12-07
  30. *
  31. * Identical soundcards by Sek'd were labeled:
  32. * RME Digi 32 = Sek'd Prodif 32
  33. * RME Digi 32 Pro = Sek'd Prodif 96
  34. * RME Digi 32/8 = Sek'd Prodif Gold
  35. *
  36. * ****************************************************************************
  37. *
  38. * Note #2 "full duplex mode" ............................... martin 2002-12-07
  39. *
  40. * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
  41. * in this mode. Rec data and play data are using the same buffer therefore. At
  42. * first you have got the playing bits in the buffer and then (after playing
  43. * them) they were overwitten by the captured sound of the CS8412/14. Both
  44. * modes (play/record) are running harmonically hand in hand in the same buffer
  45. * and you have only one start bit plus one interrupt bit to control this
  46. * paired action.
  47. * This is opposite to the latter rme96 where playing and capturing is totally
  48. * separated and so their full duplex mode is supported by alsa (using two
  49. * start bits and two interrupts for two different buffers).
  50. * But due to the wrong sequence of playing and capturing ALSA shows no solved
  51. * full duplex support for the rme32 at the moment. That's bad, but I'm not
  52. * able to solve it. Are you motivated enough to solve this problem now? Your
  53. * patch would be welcome!
  54. *
  55. * ****************************************************************************
  56. *
  57. * "The story after the long seeking" -- tiwai
  58. *
  59. * Ok, the situation regarding the full duplex is now improved a bit.
  60. * In the fullduplex mode (given by the module parameter), the hardware buffer
  61. * is split to halves for read and write directions at the DMA pointer.
  62. * That is, the half above the current DMA pointer is used for write, and
  63. * the half below is used for read. To mangle this strange behavior, an
  64. * software intermediate buffer is introduced. This is, of course, not good
  65. * from the viewpoint of the data transfer efficiency. However, this allows
  66. * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
  67. *
  68. * ****************************************************************************
  69. */
  70. #include <sound/driver.h>
  71. #include <linux/delay.h>
  72. #include <linux/init.h>
  73. #include <linux/interrupt.h>
  74. #include <linux/pci.h>
  75. #include <linux/slab.h>
  76. #include <linux/moduleparam.h>
  77. #include <sound/core.h>
  78. #include <sound/info.h>
  79. #include <sound/control.h>
  80. #include <sound/pcm.h>
  81. #include <sound/pcm_params.h>
  82. #include <sound/pcm-indirect.h>
  83. #include <sound/asoundef.h>
  84. #include <sound/initval.h>
  85. #include <asm/io.h>
  86. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  87. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  88. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  89. static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
  90. module_param_array(index, int, NULL, 0444);
  91. MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
  92. module_param_array(id, charp, NULL, 0444);
  93. MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
  94. module_param_array(enable, bool, NULL, 0444);
  95. MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
  96. module_param_array(fullduplex, bool, NULL, 0444);
  97. MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
  98. MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
  99. MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
  100. MODULE_LICENSE("GPL");
  101. MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
  102. /* Defines for RME Digi32 series */
  103. #define RME32_SPDIF_NCHANNELS 2
  104. /* Playback and capture buffer size */
  105. #define RME32_BUFFER_SIZE 0x20000
  106. /* IO area size */
  107. #define RME32_IO_SIZE 0x30000
  108. /* IO area offsets */
  109. #define RME32_IO_DATA_BUFFER 0x0
  110. #define RME32_IO_CONTROL_REGISTER 0x20000
  111. #define RME32_IO_GET_POS 0x20000
  112. #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
  113. #define RME32_IO_RESET_POS 0x20100
  114. /* Write control register bits */
  115. #define RME32_WCR_START (1 << 0) /* startbit */
  116. #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
  117. Setting the whole card to mono
  118. doesn't seem to be very useful.
  119. A software-solution can handle
  120. full-duplex with one direction in
  121. stereo and the other way in mono.
  122. So, the hardware should work all
  123. the time in stereo! */
  124. #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
  125. #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
  126. #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
  127. #define RME32_WCR_FREQ_1 (1 << 5)
  128. #define RME32_WCR_INP_0 (1 << 6) /* input switch */
  129. #define RME32_WCR_INP_1 (1 << 7)
  130. #define RME32_WCR_RESET (1 << 8) /* Reset address */
  131. #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
  132. #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
  133. #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
  134. #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
  135. #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
  136. #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
  137. #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
  138. #define RME32_WCR_BITPOS_FREQ_0 4
  139. #define RME32_WCR_BITPOS_FREQ_1 5
  140. #define RME32_WCR_BITPOS_INP_0 6
  141. #define RME32_WCR_BITPOS_INP_1 7
  142. /* Read control register bits */
  143. #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
  144. #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
  145. #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
  146. #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
  147. #define RME32_RCR_FREQ_1 (1 << 28)
  148. #define RME32_RCR_FREQ_2 (1 << 29)
  149. #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
  150. #define RME32_RCR_IRQ (1 << 31) /* interrupt */
  151. #define RME32_RCR_BITPOS_F0 27
  152. #define RME32_RCR_BITPOS_F1 28
  153. #define RME32_RCR_BITPOS_F2 29
  154. /* Input types */
  155. #define RME32_INPUT_OPTICAL 0
  156. #define RME32_INPUT_COAXIAL 1
  157. #define RME32_INPUT_INTERNAL 2
  158. #define RME32_INPUT_XLR 3
  159. /* Clock modes */
  160. #define RME32_CLOCKMODE_SLAVE 0
  161. #define RME32_CLOCKMODE_MASTER_32 1
  162. #define RME32_CLOCKMODE_MASTER_44 2
  163. #define RME32_CLOCKMODE_MASTER_48 3
  164. /* Block sizes in bytes */
  165. #define RME32_BLOCK_SIZE 8192
  166. /* Software intermediate buffer (max) size */
  167. #define RME32_MID_BUFFER_SIZE (1024*1024)
  168. /* Hardware revisions */
  169. #define RME32_32_REVISION 192
  170. #define RME32_328_REVISION_OLD 100
  171. #define RME32_328_REVISION_NEW 101
  172. #define RME32_PRO_REVISION_WITH_8412 192
  173. #define RME32_PRO_REVISION_WITH_8414 150
  174. /* PCI vendor/device ID's */
  175. #ifndef PCI_VENDOR_ID_XILINX_RME
  176. # define PCI_VENDOR_ID_XILINX_RME 0xea60
  177. #endif
  178. #ifndef PCI_DEVICE_ID_DIGI32
  179. # define PCI_DEVICE_ID_DIGI32 0x9896
  180. #endif
  181. #ifndef PCI_DEVICE_ID_DIGI32_PRO
  182. # define PCI_DEVICE_ID_DIGI32_PRO 0x9897
  183. #endif
  184. #ifndef PCI_DEVICE_ID_DIGI32_8
  185. # define PCI_DEVICE_ID_DIGI32_8 0x9898
  186. #endif
  187. typedef struct snd_rme32 {
  188. spinlock_t lock;
  189. int irq;
  190. unsigned long port;
  191. void __iomem *iobase;
  192. u32 wcreg; /* cached write control register value */
  193. u32 wcreg_spdif; /* S/PDIF setup */
  194. u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
  195. u32 rcreg; /* cached read control register value */
  196. u8 rev; /* card revision number */
  197. snd_pcm_substream_t *playback_substream;
  198. snd_pcm_substream_t *capture_substream;
  199. int playback_frlog; /* log2 of framesize */
  200. int capture_frlog;
  201. size_t playback_periodsize; /* in bytes, zero if not used */
  202. size_t capture_periodsize; /* in bytes, zero if not used */
  203. unsigned int fullduplex_mode;
  204. int running;
  205. snd_pcm_indirect_t playback_pcm;
  206. snd_pcm_indirect_t capture_pcm;
  207. snd_card_t *card;
  208. snd_pcm_t *spdif_pcm;
  209. snd_pcm_t *adat_pcm;
  210. struct pci_dev *pci;
  211. snd_kcontrol_t *spdif_ctl;
  212. } rme32_t;
  213. static struct pci_device_id snd_rme32_ids[] = {
  214. {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32,
  215. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
  216. {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32_8,
  217. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
  218. {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_DIGI32_PRO,
  219. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
  220. {0,}
  221. };
  222. MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
  223. #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
  224. #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
  225. static int snd_rme32_playback_prepare(snd_pcm_substream_t * substream);
  226. static int snd_rme32_capture_prepare(snd_pcm_substream_t * substream);
  227. static int snd_rme32_pcm_trigger(snd_pcm_substream_t * substream, int cmd);
  228. static void snd_rme32_proc_init(rme32_t * rme32);
  229. static int snd_rme32_create_switches(snd_card_t * card, rme32_t * rme32);
  230. static inline unsigned int snd_rme32_pcm_byteptr(rme32_t * rme32)
  231. {
  232. return (readl(rme32->iobase + RME32_IO_GET_POS)
  233. & RME32_RCR_AUDIO_ADDR_MASK);
  234. }
  235. static int snd_rme32_ratecode(int rate)
  236. {
  237. switch (rate) {
  238. case 32000: return SNDRV_PCM_RATE_32000;
  239. case 44100: return SNDRV_PCM_RATE_44100;
  240. case 48000: return SNDRV_PCM_RATE_48000;
  241. case 64000: return SNDRV_PCM_RATE_64000;
  242. case 88200: return SNDRV_PCM_RATE_88200;
  243. case 96000: return SNDRV_PCM_RATE_96000;
  244. }
  245. return 0;
  246. }
  247. /* silence callback for halfduplex mode */
  248. static int snd_rme32_playback_silence(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
  249. snd_pcm_uframes_t pos,
  250. snd_pcm_uframes_t count)
  251. {
  252. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  253. count <<= rme32->playback_frlog;
  254. pos <<= rme32->playback_frlog;
  255. memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
  256. return 0;
  257. }
  258. /* copy callback for halfduplex mode */
  259. static int snd_rme32_playback_copy(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
  260. snd_pcm_uframes_t pos,
  261. void __user *src, snd_pcm_uframes_t count)
  262. {
  263. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  264. count <<= rme32->playback_frlog;
  265. pos <<= rme32->playback_frlog;
  266. if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
  267. src, count))
  268. return -EFAULT;
  269. return 0;
  270. }
  271. /* copy callback for halfduplex mode */
  272. static int snd_rme32_capture_copy(snd_pcm_substream_t * substream, int channel, /* not used (interleaved data) */
  273. snd_pcm_uframes_t pos,
  274. void __user *dst, snd_pcm_uframes_t count)
  275. {
  276. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  277. count <<= rme32->capture_frlog;
  278. pos <<= rme32->capture_frlog;
  279. if (copy_to_user_fromio(dst,
  280. rme32->iobase + RME32_IO_DATA_BUFFER + pos,
  281. count))
  282. return -EFAULT;
  283. return 0;
  284. }
  285. /*
  286. * SPDIF I/O capabilites (half-duplex mode)
  287. */
  288. static snd_pcm_hardware_t snd_rme32_spdif_info = {
  289. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  290. SNDRV_PCM_INFO_MMAP_VALID |
  291. SNDRV_PCM_INFO_INTERLEAVED |
  292. SNDRV_PCM_INFO_PAUSE |
  293. SNDRV_PCM_INFO_SYNC_START),
  294. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  295. SNDRV_PCM_FMTBIT_S32_LE),
  296. .rates = (SNDRV_PCM_RATE_32000 |
  297. SNDRV_PCM_RATE_44100 |
  298. SNDRV_PCM_RATE_48000),
  299. .rate_min = 32000,
  300. .rate_max = 48000,
  301. .channels_min = 2,
  302. .channels_max = 2,
  303. .buffer_bytes_max = RME32_BUFFER_SIZE,
  304. .period_bytes_min = RME32_BLOCK_SIZE,
  305. .period_bytes_max = RME32_BLOCK_SIZE,
  306. .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  307. .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  308. .fifo_size = 0,
  309. };
  310. /*
  311. * ADAT I/O capabilites (half-duplex mode)
  312. */
  313. static snd_pcm_hardware_t snd_rme32_adat_info =
  314. {
  315. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  316. SNDRV_PCM_INFO_MMAP_VALID |
  317. SNDRV_PCM_INFO_INTERLEAVED |
  318. SNDRV_PCM_INFO_PAUSE |
  319. SNDRV_PCM_INFO_SYNC_START),
  320. .formats= SNDRV_PCM_FMTBIT_S16_LE,
  321. .rates = (SNDRV_PCM_RATE_44100 |
  322. SNDRV_PCM_RATE_48000),
  323. .rate_min = 44100,
  324. .rate_max = 48000,
  325. .channels_min = 8,
  326. .channels_max = 8,
  327. .buffer_bytes_max = RME32_BUFFER_SIZE,
  328. .period_bytes_min = RME32_BLOCK_SIZE,
  329. .period_bytes_max = RME32_BLOCK_SIZE,
  330. .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  331. .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  332. .fifo_size = 0,
  333. };
  334. /*
  335. * SPDIF I/O capabilites (full-duplex mode)
  336. */
  337. static snd_pcm_hardware_t snd_rme32_spdif_fd_info = {
  338. .info = (SNDRV_PCM_INFO_MMAP |
  339. SNDRV_PCM_INFO_MMAP_VALID |
  340. SNDRV_PCM_INFO_INTERLEAVED |
  341. SNDRV_PCM_INFO_PAUSE |
  342. SNDRV_PCM_INFO_SYNC_START),
  343. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  344. SNDRV_PCM_FMTBIT_S32_LE),
  345. .rates = (SNDRV_PCM_RATE_32000 |
  346. SNDRV_PCM_RATE_44100 |
  347. SNDRV_PCM_RATE_48000),
  348. .rate_min = 32000,
  349. .rate_max = 48000,
  350. .channels_min = 2,
  351. .channels_max = 2,
  352. .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
  353. .period_bytes_min = RME32_BLOCK_SIZE,
  354. .period_bytes_max = RME32_BLOCK_SIZE,
  355. .periods_min = 2,
  356. .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
  357. .fifo_size = 0,
  358. };
  359. /*
  360. * ADAT I/O capabilites (full-duplex mode)
  361. */
  362. static snd_pcm_hardware_t snd_rme32_adat_fd_info =
  363. {
  364. .info = (SNDRV_PCM_INFO_MMAP |
  365. SNDRV_PCM_INFO_MMAP_VALID |
  366. SNDRV_PCM_INFO_INTERLEAVED |
  367. SNDRV_PCM_INFO_PAUSE |
  368. SNDRV_PCM_INFO_SYNC_START),
  369. .formats= SNDRV_PCM_FMTBIT_S16_LE,
  370. .rates = (SNDRV_PCM_RATE_44100 |
  371. SNDRV_PCM_RATE_48000),
  372. .rate_min = 44100,
  373. .rate_max = 48000,
  374. .channels_min = 8,
  375. .channels_max = 8,
  376. .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
  377. .period_bytes_min = RME32_BLOCK_SIZE,
  378. .period_bytes_max = RME32_BLOCK_SIZE,
  379. .periods_min = 2,
  380. .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
  381. .fifo_size = 0,
  382. };
  383. static void snd_rme32_reset_dac(rme32_t *rme32)
  384. {
  385. writel(rme32->wcreg | RME32_WCR_PD,
  386. rme32->iobase + RME32_IO_CONTROL_REGISTER);
  387. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  388. }
  389. static int snd_rme32_playback_getrate(rme32_t * rme32)
  390. {
  391. int rate;
  392. rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
  393. (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
  394. switch (rate) {
  395. case 1:
  396. rate = 32000;
  397. break;
  398. case 2:
  399. rate = 44100;
  400. break;
  401. case 3:
  402. rate = 48000;
  403. break;
  404. default:
  405. return -1;
  406. }
  407. return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
  408. }
  409. static int snd_rme32_capture_getrate(rme32_t * rme32, int *is_adat)
  410. {
  411. int n;
  412. *is_adat = 0;
  413. if (rme32->rcreg & RME32_RCR_LOCK) {
  414. /* ADAT rate */
  415. *is_adat = 1;
  416. }
  417. if (rme32->rcreg & RME32_RCR_ERF) {
  418. return -1;
  419. }
  420. /* S/PDIF rate */
  421. n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
  422. (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
  423. (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
  424. if (RME32_PRO_WITH_8414(rme32))
  425. switch (n) { /* supporting the CS8414 */
  426. case 0:
  427. case 1:
  428. case 2:
  429. return -1;
  430. case 3:
  431. return 96000;
  432. case 4:
  433. return 88200;
  434. case 5:
  435. return 48000;
  436. case 6:
  437. return 44100;
  438. case 7:
  439. return 32000;
  440. default:
  441. return -1;
  442. break;
  443. }
  444. else
  445. switch (n) { /* supporting the CS8412 */
  446. case 0:
  447. return -1;
  448. case 1:
  449. return 48000;
  450. case 2:
  451. return 44100;
  452. case 3:
  453. return 32000;
  454. case 4:
  455. return 48000;
  456. case 5:
  457. return 44100;
  458. case 6:
  459. return 44056;
  460. case 7:
  461. return 32000;
  462. default:
  463. break;
  464. }
  465. return -1;
  466. }
  467. static int snd_rme32_playback_setrate(rme32_t * rme32, int rate)
  468. {
  469. int ds;
  470. ds = rme32->wcreg & RME32_WCR_DS_BM;
  471. switch (rate) {
  472. case 32000:
  473. rme32->wcreg &= ~RME32_WCR_DS_BM;
  474. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  475. ~RME32_WCR_FREQ_1;
  476. break;
  477. case 44100:
  478. rme32->wcreg &= ~RME32_WCR_DS_BM;
  479. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
  480. ~RME32_WCR_FREQ_0;
  481. break;
  482. case 48000:
  483. rme32->wcreg &= ~RME32_WCR_DS_BM;
  484. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  485. RME32_WCR_FREQ_1;
  486. break;
  487. case 64000:
  488. if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
  489. return -EINVAL;
  490. rme32->wcreg |= RME32_WCR_DS_BM;
  491. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  492. ~RME32_WCR_FREQ_1;
  493. break;
  494. case 88200:
  495. if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
  496. return -EINVAL;
  497. rme32->wcreg |= RME32_WCR_DS_BM;
  498. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
  499. ~RME32_WCR_FREQ_0;
  500. break;
  501. case 96000:
  502. if (rme32->pci->device != PCI_DEVICE_ID_DIGI32_PRO)
  503. return -EINVAL;
  504. rme32->wcreg |= RME32_WCR_DS_BM;
  505. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  506. RME32_WCR_FREQ_1;
  507. break;
  508. default:
  509. return -EINVAL;
  510. }
  511. if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
  512. (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
  513. {
  514. /* change to/from double-speed: reset the DAC (if available) */
  515. snd_rme32_reset_dac(rme32);
  516. } else {
  517. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  518. }
  519. return 0;
  520. }
  521. static int snd_rme32_setclockmode(rme32_t * rme32, int mode)
  522. {
  523. switch (mode) {
  524. case RME32_CLOCKMODE_SLAVE:
  525. /* AutoSync */
  526. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
  527. ~RME32_WCR_FREQ_1;
  528. break;
  529. case RME32_CLOCKMODE_MASTER_32:
  530. /* Internal 32.0kHz */
  531. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  532. ~RME32_WCR_FREQ_1;
  533. break;
  534. case RME32_CLOCKMODE_MASTER_44:
  535. /* Internal 44.1kHz */
  536. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
  537. RME32_WCR_FREQ_1;
  538. break;
  539. case RME32_CLOCKMODE_MASTER_48:
  540. /* Internal 48.0kHz */
  541. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  542. RME32_WCR_FREQ_1;
  543. break;
  544. default:
  545. return -EINVAL;
  546. }
  547. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  548. return 0;
  549. }
  550. static int snd_rme32_getclockmode(rme32_t * rme32)
  551. {
  552. return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
  553. (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
  554. }
  555. static int snd_rme32_setinputtype(rme32_t * rme32, int type)
  556. {
  557. switch (type) {
  558. case RME32_INPUT_OPTICAL:
  559. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
  560. ~RME32_WCR_INP_1;
  561. break;
  562. case RME32_INPUT_COAXIAL:
  563. rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
  564. ~RME32_WCR_INP_1;
  565. break;
  566. case RME32_INPUT_INTERNAL:
  567. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
  568. RME32_WCR_INP_1;
  569. break;
  570. case RME32_INPUT_XLR:
  571. rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
  572. RME32_WCR_INP_1;
  573. break;
  574. default:
  575. return -EINVAL;
  576. }
  577. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  578. return 0;
  579. }
  580. static int snd_rme32_getinputtype(rme32_t * rme32)
  581. {
  582. return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
  583. (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
  584. }
  585. static void
  586. snd_rme32_setframelog(rme32_t * rme32, int n_channels, int is_playback)
  587. {
  588. int frlog;
  589. if (n_channels == 2) {
  590. frlog = 1;
  591. } else {
  592. /* assume 8 channels */
  593. frlog = 3;
  594. }
  595. if (is_playback) {
  596. frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
  597. rme32->playback_frlog = frlog;
  598. } else {
  599. frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
  600. rme32->capture_frlog = frlog;
  601. }
  602. }
  603. static int snd_rme32_setformat(rme32_t * rme32, int format)
  604. {
  605. switch (format) {
  606. case SNDRV_PCM_FORMAT_S16_LE:
  607. rme32->wcreg &= ~RME32_WCR_MODE24;
  608. break;
  609. case SNDRV_PCM_FORMAT_S32_LE:
  610. rme32->wcreg |= RME32_WCR_MODE24;
  611. break;
  612. default:
  613. return -EINVAL;
  614. }
  615. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  616. return 0;
  617. }
  618. static int
  619. snd_rme32_playback_hw_params(snd_pcm_substream_t * substream,
  620. snd_pcm_hw_params_t * params)
  621. {
  622. int err, rate, dummy;
  623. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  624. snd_pcm_runtime_t *runtime = substream->runtime;
  625. if (rme32->fullduplex_mode) {
  626. err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
  627. if (err < 0)
  628. return err;
  629. } else {
  630. runtime->dma_area = (void *)(rme32->iobase + RME32_IO_DATA_BUFFER);
  631. runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
  632. runtime->dma_bytes = RME32_BUFFER_SIZE;
  633. }
  634. spin_lock_irq(&rme32->lock);
  635. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  636. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  637. /* AutoSync */
  638. if ((int)params_rate(params) != rate) {
  639. spin_unlock_irq(&rme32->lock);
  640. return -EIO;
  641. }
  642. } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
  643. spin_unlock_irq(&rme32->lock);
  644. return err;
  645. }
  646. if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
  647. spin_unlock_irq(&rme32->lock);
  648. return err;
  649. }
  650. snd_rme32_setframelog(rme32, params_channels(params), 1);
  651. if (rme32->capture_periodsize != 0) {
  652. if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
  653. spin_unlock_irq(&rme32->lock);
  654. return -EBUSY;
  655. }
  656. }
  657. rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
  658. /* S/PDIF setup */
  659. if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
  660. rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
  661. rme32->wcreg |= rme32->wcreg_spdif_stream;
  662. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  663. }
  664. spin_unlock_irq(&rme32->lock);
  665. return 0;
  666. }
  667. static int
  668. snd_rme32_capture_hw_params(snd_pcm_substream_t * substream,
  669. snd_pcm_hw_params_t * params)
  670. {
  671. int err, isadat, rate;
  672. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  673. snd_pcm_runtime_t *runtime = substream->runtime;
  674. if (rme32->fullduplex_mode) {
  675. err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
  676. if (err < 0)
  677. return err;
  678. } else {
  679. runtime->dma_area = (void *)rme32->iobase + RME32_IO_DATA_BUFFER;
  680. runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
  681. runtime->dma_bytes = RME32_BUFFER_SIZE;
  682. }
  683. spin_lock_irq(&rme32->lock);
  684. /* enable AutoSync for record-preparing */
  685. rme32->wcreg |= RME32_WCR_AUTOSYNC;
  686. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  687. if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
  688. spin_unlock_irq(&rme32->lock);
  689. return err;
  690. }
  691. if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
  692. spin_unlock_irq(&rme32->lock);
  693. return err;
  694. }
  695. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  696. if ((int)params_rate(params) != rate) {
  697. spin_unlock_irq(&rme32->lock);
  698. return -EIO;
  699. }
  700. if ((isadat && runtime->hw.channels_min == 2) ||
  701. (!isadat && runtime->hw.channels_min == 8)) {
  702. spin_unlock_irq(&rme32->lock);
  703. return -EIO;
  704. }
  705. }
  706. /* AutoSync off for recording */
  707. rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
  708. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  709. snd_rme32_setframelog(rme32, params_channels(params), 0);
  710. if (rme32->playback_periodsize != 0) {
  711. if (params_period_size(params) << rme32->capture_frlog !=
  712. rme32->playback_periodsize) {
  713. spin_unlock_irq(&rme32->lock);
  714. return -EBUSY;
  715. }
  716. }
  717. rme32->capture_periodsize =
  718. params_period_size(params) << rme32->capture_frlog;
  719. spin_unlock_irq(&rme32->lock);
  720. return 0;
  721. }
  722. static int snd_rme32_pcm_hw_free(snd_pcm_substream_t * substream)
  723. {
  724. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  725. if (! rme32->fullduplex_mode)
  726. return 0;
  727. return snd_pcm_lib_free_pages(substream);
  728. }
  729. static void snd_rme32_pcm_start(rme32_t * rme32, int from_pause)
  730. {
  731. if (!from_pause) {
  732. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  733. }
  734. rme32->wcreg |= RME32_WCR_START;
  735. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  736. }
  737. static void snd_rme32_pcm_stop(rme32_t * rme32, int to_pause)
  738. {
  739. /*
  740. * Check if there is an unconfirmed IRQ, if so confirm it, or else
  741. * the hardware will not stop generating interrupts
  742. */
  743. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  744. if (rme32->rcreg & RME32_RCR_IRQ) {
  745. writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
  746. }
  747. rme32->wcreg &= ~RME32_WCR_START;
  748. if (rme32->wcreg & RME32_WCR_SEL)
  749. rme32->wcreg |= RME32_WCR_MUTE;
  750. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  751. if (! to_pause)
  752. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  753. }
  754. static irqreturn_t
  755. snd_rme32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  756. {
  757. rme32_t *rme32 = (rme32_t *) dev_id;
  758. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  759. if (!(rme32->rcreg & RME32_RCR_IRQ)) {
  760. return IRQ_NONE;
  761. } else {
  762. if (rme32->capture_substream) {
  763. snd_pcm_period_elapsed(rme32->capture_substream);
  764. }
  765. if (rme32->playback_substream) {
  766. snd_pcm_period_elapsed(rme32->playback_substream);
  767. }
  768. writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
  769. }
  770. return IRQ_HANDLED;
  771. }
  772. static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
  773. static snd_pcm_hw_constraint_list_t hw_constraints_period_bytes = {
  774. .count = ARRAY_SIZE(period_bytes),
  775. .list = period_bytes,
  776. .mask = 0
  777. };
  778. static void snd_rme32_set_buffer_constraint(rme32_t *rme32, snd_pcm_runtime_t *runtime)
  779. {
  780. if (! rme32->fullduplex_mode) {
  781. snd_pcm_hw_constraint_minmax(runtime,
  782. SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  783. RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
  784. snd_pcm_hw_constraint_list(runtime, 0,
  785. SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  786. &hw_constraints_period_bytes);
  787. }
  788. }
  789. static int snd_rme32_playback_spdif_open(snd_pcm_substream_t * substream)
  790. {
  791. int rate, dummy;
  792. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  793. snd_pcm_runtime_t *runtime = substream->runtime;
  794. snd_pcm_set_sync(substream);
  795. spin_lock_irq(&rme32->lock);
  796. if (rme32->playback_substream != NULL) {
  797. spin_unlock_irq(&rme32->lock);
  798. return -EBUSY;
  799. }
  800. rme32->wcreg &= ~RME32_WCR_ADAT;
  801. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  802. rme32->playback_substream = substream;
  803. spin_unlock_irq(&rme32->lock);
  804. if (rme32->fullduplex_mode)
  805. runtime->hw = snd_rme32_spdif_fd_info;
  806. else
  807. runtime->hw = snd_rme32_spdif_info;
  808. if (rme32->pci->device == PCI_DEVICE_ID_DIGI32_PRO) {
  809. runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
  810. runtime->hw.rate_max = 96000;
  811. }
  812. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  813. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  814. /* AutoSync */
  815. runtime->hw.rates = snd_rme32_ratecode(rate);
  816. runtime->hw.rate_min = rate;
  817. runtime->hw.rate_max = rate;
  818. }
  819. snd_rme32_set_buffer_constraint(rme32, runtime);
  820. rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
  821. rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  822. snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
  823. SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
  824. return 0;
  825. }
  826. static int snd_rme32_capture_spdif_open(snd_pcm_substream_t * substream)
  827. {
  828. int isadat, rate;
  829. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  830. snd_pcm_runtime_t *runtime = substream->runtime;
  831. snd_pcm_set_sync(substream);
  832. spin_lock_irq(&rme32->lock);
  833. if (rme32->capture_substream != NULL) {
  834. spin_unlock_irq(&rme32->lock);
  835. return -EBUSY;
  836. }
  837. rme32->capture_substream = substream;
  838. spin_unlock_irq(&rme32->lock);
  839. if (rme32->fullduplex_mode)
  840. runtime->hw = snd_rme32_spdif_fd_info;
  841. else
  842. runtime->hw = snd_rme32_spdif_info;
  843. if (RME32_PRO_WITH_8414(rme32)) {
  844. runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
  845. runtime->hw.rate_max = 96000;
  846. }
  847. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  848. if (isadat) {
  849. return -EIO;
  850. }
  851. runtime->hw.rates = snd_rme32_ratecode(rate);
  852. runtime->hw.rate_min = rate;
  853. runtime->hw.rate_max = rate;
  854. }
  855. snd_rme32_set_buffer_constraint(rme32, runtime);
  856. return 0;
  857. }
  858. static int
  859. snd_rme32_playback_adat_open(snd_pcm_substream_t *substream)
  860. {
  861. int rate, dummy;
  862. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  863. snd_pcm_runtime_t *runtime = substream->runtime;
  864. snd_pcm_set_sync(substream);
  865. spin_lock_irq(&rme32->lock);
  866. if (rme32->playback_substream != NULL) {
  867. spin_unlock_irq(&rme32->lock);
  868. return -EBUSY;
  869. }
  870. rme32->wcreg |= RME32_WCR_ADAT;
  871. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  872. rme32->playback_substream = substream;
  873. spin_unlock_irq(&rme32->lock);
  874. if (rme32->fullduplex_mode)
  875. runtime->hw = snd_rme32_adat_fd_info;
  876. else
  877. runtime->hw = snd_rme32_adat_info;
  878. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  879. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  880. /* AutoSync */
  881. runtime->hw.rates = snd_rme32_ratecode(rate);
  882. runtime->hw.rate_min = rate;
  883. runtime->hw.rate_max = rate;
  884. }
  885. snd_rme32_set_buffer_constraint(rme32, runtime);
  886. return 0;
  887. }
  888. static int
  889. snd_rme32_capture_adat_open(snd_pcm_substream_t *substream)
  890. {
  891. int isadat, rate;
  892. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  893. snd_pcm_runtime_t *runtime = substream->runtime;
  894. if (rme32->fullduplex_mode)
  895. runtime->hw = snd_rme32_adat_fd_info;
  896. else
  897. runtime->hw = snd_rme32_adat_info;
  898. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  899. if (!isadat) {
  900. return -EIO;
  901. }
  902. runtime->hw.rates = snd_rme32_ratecode(rate);
  903. runtime->hw.rate_min = rate;
  904. runtime->hw.rate_max = rate;
  905. }
  906. snd_pcm_set_sync(substream);
  907. spin_lock_irq(&rme32->lock);
  908. if (rme32->capture_substream != NULL) {
  909. spin_unlock_irq(&rme32->lock);
  910. return -EBUSY;
  911. }
  912. rme32->capture_substream = substream;
  913. spin_unlock_irq(&rme32->lock);
  914. snd_rme32_set_buffer_constraint(rme32, runtime);
  915. return 0;
  916. }
  917. static int snd_rme32_playback_close(snd_pcm_substream_t * substream)
  918. {
  919. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  920. int spdif = 0;
  921. spin_lock_irq(&rme32->lock);
  922. rme32->playback_substream = NULL;
  923. rme32->playback_periodsize = 0;
  924. spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
  925. spin_unlock_irq(&rme32->lock);
  926. if (spdif) {
  927. rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  928. snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
  929. SNDRV_CTL_EVENT_MASK_INFO,
  930. &rme32->spdif_ctl->id);
  931. }
  932. return 0;
  933. }
  934. static int snd_rme32_capture_close(snd_pcm_substream_t * substream)
  935. {
  936. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  937. spin_lock_irq(&rme32->lock);
  938. rme32->capture_substream = NULL;
  939. rme32->capture_periodsize = 0;
  940. spin_unlock(&rme32->lock);
  941. return 0;
  942. }
  943. static int snd_rme32_playback_prepare(snd_pcm_substream_t * substream)
  944. {
  945. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  946. spin_lock_irq(&rme32->lock);
  947. if (rme32->fullduplex_mode) {
  948. memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
  949. rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
  950. rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
  951. } else {
  952. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  953. }
  954. if (rme32->wcreg & RME32_WCR_SEL)
  955. rme32->wcreg &= ~RME32_WCR_MUTE;
  956. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  957. spin_unlock_irq(&rme32->lock);
  958. return 0;
  959. }
  960. static int snd_rme32_capture_prepare(snd_pcm_substream_t * substream)
  961. {
  962. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  963. spin_lock_irq(&rme32->lock);
  964. if (rme32->fullduplex_mode) {
  965. memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
  966. rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
  967. rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
  968. rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
  969. } else {
  970. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  971. }
  972. spin_unlock_irq(&rme32->lock);
  973. return 0;
  974. }
  975. static int
  976. snd_rme32_pcm_trigger(snd_pcm_substream_t * substream, int cmd)
  977. {
  978. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  979. struct list_head *pos;
  980. snd_pcm_substream_t *s;
  981. spin_lock(&rme32->lock);
  982. snd_pcm_group_for_each(pos, substream) {
  983. s = snd_pcm_group_substream_entry(pos);
  984. if (s != rme32->playback_substream &&
  985. s != rme32->capture_substream)
  986. continue;
  987. switch (cmd) {
  988. case SNDRV_PCM_TRIGGER_START:
  989. rme32->running |= (1 << s->stream);
  990. if (rme32->fullduplex_mode) {
  991. /* remember the current DMA position */
  992. if (s == rme32->playback_substream) {
  993. rme32->playback_pcm.hw_io =
  994. rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
  995. } else {
  996. rme32->capture_pcm.hw_io =
  997. rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
  998. }
  999. }
  1000. break;
  1001. case SNDRV_PCM_TRIGGER_STOP:
  1002. rme32->running &= ~(1 << s->stream);
  1003. break;
  1004. }
  1005. snd_pcm_trigger_done(s, substream);
  1006. }
  1007. /* prefill playback buffer */
  1008. if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
  1009. snd_pcm_group_for_each(pos, substream) {
  1010. s = snd_pcm_group_substream_entry(pos);
  1011. if (s == rme32->playback_substream) {
  1012. s->ops->ack(s);
  1013. break;
  1014. }
  1015. }
  1016. }
  1017. switch (cmd) {
  1018. case SNDRV_PCM_TRIGGER_START:
  1019. if (rme32->running && ! RME32_ISWORKING(rme32))
  1020. snd_rme32_pcm_start(rme32, 0);
  1021. break;
  1022. case SNDRV_PCM_TRIGGER_STOP:
  1023. if (! rme32->running && RME32_ISWORKING(rme32))
  1024. snd_rme32_pcm_stop(rme32, 0);
  1025. break;
  1026. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1027. if (rme32->running && RME32_ISWORKING(rme32))
  1028. snd_rme32_pcm_stop(rme32, 1);
  1029. break;
  1030. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1031. if (rme32->running && ! RME32_ISWORKING(rme32))
  1032. snd_rme32_pcm_start(rme32, 1);
  1033. break;
  1034. }
  1035. spin_unlock(&rme32->lock);
  1036. return 0;
  1037. }
  1038. /* pointer callback for halfduplex mode */
  1039. static snd_pcm_uframes_t
  1040. snd_rme32_playback_pointer(snd_pcm_substream_t * substream)
  1041. {
  1042. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  1043. return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
  1044. }
  1045. static snd_pcm_uframes_t
  1046. snd_rme32_capture_pointer(snd_pcm_substream_t * substream)
  1047. {
  1048. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  1049. return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
  1050. }
  1051. /* ack and pointer callbacks for fullduplex mode */
  1052. static void snd_rme32_pb_trans_copy(snd_pcm_substream_t *substream,
  1053. snd_pcm_indirect_t *rec, size_t bytes)
  1054. {
  1055. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  1056. memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
  1057. substream->runtime->dma_area + rec->sw_data, bytes);
  1058. }
  1059. static int snd_rme32_playback_fd_ack(snd_pcm_substream_t *substream)
  1060. {
  1061. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  1062. snd_pcm_indirect_t *rec, *cprec;
  1063. rec = &rme32->playback_pcm;
  1064. cprec = &rme32->capture_pcm;
  1065. spin_lock(&rme32->lock);
  1066. rec->hw_queue_size = RME32_BUFFER_SIZE;
  1067. if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
  1068. rec->hw_queue_size -= cprec->hw_ready;
  1069. spin_unlock(&rme32->lock);
  1070. snd_pcm_indirect_playback_transfer(substream, rec,
  1071. snd_rme32_pb_trans_copy);
  1072. return 0;
  1073. }
  1074. static void snd_rme32_cp_trans_copy(snd_pcm_substream_t *substream,
  1075. snd_pcm_indirect_t *rec, size_t bytes)
  1076. {
  1077. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  1078. memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
  1079. rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
  1080. bytes);
  1081. }
  1082. static int snd_rme32_capture_fd_ack(snd_pcm_substream_t *substream)
  1083. {
  1084. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  1085. snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
  1086. snd_rme32_cp_trans_copy);
  1087. return 0;
  1088. }
  1089. static snd_pcm_uframes_t
  1090. snd_rme32_playback_fd_pointer(snd_pcm_substream_t * substream)
  1091. {
  1092. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  1093. return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
  1094. snd_rme32_pcm_byteptr(rme32));
  1095. }
  1096. static snd_pcm_uframes_t
  1097. snd_rme32_capture_fd_pointer(snd_pcm_substream_t * substream)
  1098. {
  1099. rme32_t *rme32 = snd_pcm_substream_chip(substream);
  1100. return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
  1101. snd_rme32_pcm_byteptr(rme32));
  1102. }
  1103. /* for halfduplex mode */
  1104. static snd_pcm_ops_t snd_rme32_playback_spdif_ops = {
  1105. .open = snd_rme32_playback_spdif_open,
  1106. .close = snd_rme32_playback_close,
  1107. .ioctl = snd_pcm_lib_ioctl,
  1108. .hw_params = snd_rme32_playback_hw_params,
  1109. .hw_free = snd_rme32_pcm_hw_free,
  1110. .prepare = snd_rme32_playback_prepare,
  1111. .trigger = snd_rme32_pcm_trigger,
  1112. .pointer = snd_rme32_playback_pointer,
  1113. .copy = snd_rme32_playback_copy,
  1114. .silence = snd_rme32_playback_silence,
  1115. .mmap = snd_pcm_lib_mmap_iomem,
  1116. };
  1117. static snd_pcm_ops_t snd_rme32_capture_spdif_ops = {
  1118. .open = snd_rme32_capture_spdif_open,
  1119. .close = snd_rme32_capture_close,
  1120. .ioctl = snd_pcm_lib_ioctl,
  1121. .hw_params = snd_rme32_capture_hw_params,
  1122. .hw_free = snd_rme32_pcm_hw_free,
  1123. .prepare = snd_rme32_capture_prepare,
  1124. .trigger = snd_rme32_pcm_trigger,
  1125. .pointer = snd_rme32_capture_pointer,
  1126. .copy = snd_rme32_capture_copy,
  1127. .mmap = snd_pcm_lib_mmap_iomem,
  1128. };
  1129. static snd_pcm_ops_t snd_rme32_playback_adat_ops = {
  1130. .open = snd_rme32_playback_adat_open,
  1131. .close = snd_rme32_playback_close,
  1132. .ioctl = snd_pcm_lib_ioctl,
  1133. .hw_params = snd_rme32_playback_hw_params,
  1134. .prepare = snd_rme32_playback_prepare,
  1135. .trigger = snd_rme32_pcm_trigger,
  1136. .pointer = snd_rme32_playback_pointer,
  1137. .copy = snd_rme32_playback_copy,
  1138. .silence = snd_rme32_playback_silence,
  1139. .mmap = snd_pcm_lib_mmap_iomem,
  1140. };
  1141. static snd_pcm_ops_t snd_rme32_capture_adat_ops = {
  1142. .open = snd_rme32_capture_adat_open,
  1143. .close = snd_rme32_capture_close,
  1144. .ioctl = snd_pcm_lib_ioctl,
  1145. .hw_params = snd_rme32_capture_hw_params,
  1146. .prepare = snd_rme32_capture_prepare,
  1147. .trigger = snd_rme32_pcm_trigger,
  1148. .pointer = snd_rme32_capture_pointer,
  1149. .copy = snd_rme32_capture_copy,
  1150. .mmap = snd_pcm_lib_mmap_iomem,
  1151. };
  1152. /* for fullduplex mode */
  1153. static snd_pcm_ops_t snd_rme32_playback_spdif_fd_ops = {
  1154. .open = snd_rme32_playback_spdif_open,
  1155. .close = snd_rme32_playback_close,
  1156. .ioctl = snd_pcm_lib_ioctl,
  1157. .hw_params = snd_rme32_playback_hw_params,
  1158. .hw_free = snd_rme32_pcm_hw_free,
  1159. .prepare = snd_rme32_playback_prepare,
  1160. .trigger = snd_rme32_pcm_trigger,
  1161. .pointer = snd_rme32_playback_fd_pointer,
  1162. .ack = snd_rme32_playback_fd_ack,
  1163. };
  1164. static snd_pcm_ops_t snd_rme32_capture_spdif_fd_ops = {
  1165. .open = snd_rme32_capture_spdif_open,
  1166. .close = snd_rme32_capture_close,
  1167. .ioctl = snd_pcm_lib_ioctl,
  1168. .hw_params = snd_rme32_capture_hw_params,
  1169. .hw_free = snd_rme32_pcm_hw_free,
  1170. .prepare = snd_rme32_capture_prepare,
  1171. .trigger = snd_rme32_pcm_trigger,
  1172. .pointer = snd_rme32_capture_fd_pointer,
  1173. .ack = snd_rme32_capture_fd_ack,
  1174. };
  1175. static snd_pcm_ops_t snd_rme32_playback_adat_fd_ops = {
  1176. .open = snd_rme32_playback_adat_open,
  1177. .close = snd_rme32_playback_close,
  1178. .ioctl = snd_pcm_lib_ioctl,
  1179. .hw_params = snd_rme32_playback_hw_params,
  1180. .prepare = snd_rme32_playback_prepare,
  1181. .trigger = snd_rme32_pcm_trigger,
  1182. .pointer = snd_rme32_playback_fd_pointer,
  1183. .ack = snd_rme32_playback_fd_ack,
  1184. };
  1185. static snd_pcm_ops_t snd_rme32_capture_adat_fd_ops = {
  1186. .open = snd_rme32_capture_adat_open,
  1187. .close = snd_rme32_capture_close,
  1188. .ioctl = snd_pcm_lib_ioctl,
  1189. .hw_params = snd_rme32_capture_hw_params,
  1190. .prepare = snd_rme32_capture_prepare,
  1191. .trigger = snd_rme32_pcm_trigger,
  1192. .pointer = snd_rme32_capture_fd_pointer,
  1193. .ack = snd_rme32_capture_fd_ack,
  1194. };
  1195. static void snd_rme32_free(void *private_data)
  1196. {
  1197. rme32_t *rme32 = (rme32_t *) private_data;
  1198. if (rme32 == NULL) {
  1199. return;
  1200. }
  1201. if (rme32->irq >= 0) {
  1202. snd_rme32_pcm_stop(rme32, 0);
  1203. free_irq(rme32->irq, (void *) rme32);
  1204. rme32->irq = -1;
  1205. }
  1206. if (rme32->iobase) {
  1207. iounmap(rme32->iobase);
  1208. rme32->iobase = NULL;
  1209. }
  1210. if (rme32->port) {
  1211. pci_release_regions(rme32->pci);
  1212. rme32->port = 0;
  1213. }
  1214. pci_disable_device(rme32->pci);
  1215. }
  1216. static void snd_rme32_free_spdif_pcm(snd_pcm_t * pcm)
  1217. {
  1218. rme32_t *rme32 = (rme32_t *) pcm->private_data;
  1219. rme32->spdif_pcm = NULL;
  1220. }
  1221. static void
  1222. snd_rme32_free_adat_pcm(snd_pcm_t *pcm)
  1223. {
  1224. rme32_t *rme32 = (rme32_t *) pcm->private_data;
  1225. rme32->adat_pcm = NULL;
  1226. }
  1227. static int __devinit snd_rme32_create(rme32_t * rme32)
  1228. {
  1229. struct pci_dev *pci = rme32->pci;
  1230. int err;
  1231. rme32->irq = -1;
  1232. spin_lock_init(&rme32->lock);
  1233. if ((err = pci_enable_device(pci)) < 0)
  1234. return err;
  1235. if ((err = pci_request_regions(pci, "RME32")) < 0)
  1236. return err;
  1237. rme32->port = pci_resource_start(rme32->pci, 0);
  1238. if (request_irq(pci->irq, snd_rme32_interrupt, SA_INTERRUPT | SA_SHIRQ, "RME32", (void *) rme32)) {
  1239. snd_printk("unable to grab IRQ %d\n", pci->irq);
  1240. return -EBUSY;
  1241. }
  1242. rme32->irq = pci->irq;
  1243. if ((rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE)) == 0) {
  1244. snd_printk("unable to remap memory region 0x%lx-0x%lx\n",
  1245. rme32->port, rme32->port + RME32_IO_SIZE - 1);
  1246. return -ENOMEM;
  1247. }
  1248. /* read the card's revision number */
  1249. pci_read_config_byte(pci, 8, &rme32->rev);
  1250. /* set up ALSA pcm device for S/PDIF */
  1251. if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
  1252. return err;
  1253. }
  1254. rme32->spdif_pcm->private_data = rme32;
  1255. rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
  1256. strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
  1257. if (rme32->fullduplex_mode) {
  1258. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1259. &snd_rme32_playback_spdif_fd_ops);
  1260. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1261. &snd_rme32_capture_spdif_fd_ops);
  1262. snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
  1263. snd_dma_continuous_data(GFP_KERNEL),
  1264. 0, RME32_MID_BUFFER_SIZE);
  1265. rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1266. } else {
  1267. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1268. &snd_rme32_playback_spdif_ops);
  1269. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1270. &snd_rme32_capture_spdif_ops);
  1271. rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  1272. }
  1273. /* set up ALSA pcm device for ADAT */
  1274. if ((pci->device == PCI_DEVICE_ID_DIGI32) ||
  1275. (pci->device == PCI_DEVICE_ID_DIGI32_PRO)) {
  1276. /* ADAT is not available on DIGI32 and DIGI32 Pro */
  1277. rme32->adat_pcm = NULL;
  1278. }
  1279. else {
  1280. if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
  1281. 1, 1, &rme32->adat_pcm)) < 0)
  1282. {
  1283. return err;
  1284. }
  1285. rme32->adat_pcm->private_data = rme32;
  1286. rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
  1287. strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
  1288. if (rme32->fullduplex_mode) {
  1289. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1290. &snd_rme32_playback_adat_fd_ops);
  1291. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1292. &snd_rme32_capture_adat_fd_ops);
  1293. snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
  1294. snd_dma_continuous_data(GFP_KERNEL),
  1295. 0, RME32_MID_BUFFER_SIZE);
  1296. rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1297. } else {
  1298. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1299. &snd_rme32_playback_adat_ops);
  1300. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1301. &snd_rme32_capture_adat_ops);
  1302. rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  1303. }
  1304. }
  1305. rme32->playback_periodsize = 0;
  1306. rme32->capture_periodsize = 0;
  1307. /* make sure playback/capture is stopped, if by some reason active */
  1308. snd_rme32_pcm_stop(rme32, 0);
  1309. /* reset DAC */
  1310. snd_rme32_reset_dac(rme32);
  1311. /* reset buffer pointer */
  1312. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  1313. /* set default values in registers */
  1314. rme32->wcreg = RME32_WCR_SEL | /* normal playback */
  1315. RME32_WCR_INP_0 | /* input select */
  1316. RME32_WCR_MUTE; /* muting on */
  1317. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1318. /* init switch interface */
  1319. if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
  1320. return err;
  1321. }
  1322. /* init proc interface */
  1323. snd_rme32_proc_init(rme32);
  1324. rme32->capture_substream = NULL;
  1325. rme32->playback_substream = NULL;
  1326. return 0;
  1327. }
  1328. /*
  1329. * proc interface
  1330. */
  1331. static void
  1332. snd_rme32_proc_read(snd_info_entry_t * entry, snd_info_buffer_t * buffer)
  1333. {
  1334. int n;
  1335. rme32_t *rme32 = (rme32_t *) entry->private_data;
  1336. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1337. snd_iprintf(buffer, rme32->card->longname);
  1338. snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
  1339. snd_iprintf(buffer, "\nGeneral settings\n");
  1340. if (rme32->fullduplex_mode)
  1341. snd_iprintf(buffer, " Full-duplex mode\n");
  1342. else
  1343. snd_iprintf(buffer, " Half-duplex mode\n");
  1344. if (RME32_PRO_WITH_8414(rme32)) {
  1345. snd_iprintf(buffer, " receiver: CS8414\n");
  1346. } else {
  1347. snd_iprintf(buffer, " receiver: CS8412\n");
  1348. }
  1349. if (rme32->wcreg & RME32_WCR_MODE24) {
  1350. snd_iprintf(buffer, " format: 24 bit");
  1351. } else {
  1352. snd_iprintf(buffer, " format: 16 bit");
  1353. }
  1354. if (rme32->wcreg & RME32_WCR_MONO) {
  1355. snd_iprintf(buffer, ", Mono\n");
  1356. } else {
  1357. snd_iprintf(buffer, ", Stereo\n");
  1358. }
  1359. snd_iprintf(buffer, "\nInput settings\n");
  1360. switch (snd_rme32_getinputtype(rme32)) {
  1361. case RME32_INPUT_OPTICAL:
  1362. snd_iprintf(buffer, " input: optical");
  1363. break;
  1364. case RME32_INPUT_COAXIAL:
  1365. snd_iprintf(buffer, " input: coaxial");
  1366. break;
  1367. case RME32_INPUT_INTERNAL:
  1368. snd_iprintf(buffer, " input: internal");
  1369. break;
  1370. case RME32_INPUT_XLR:
  1371. snd_iprintf(buffer, " input: XLR");
  1372. break;
  1373. }
  1374. if (snd_rme32_capture_getrate(rme32, &n) < 0) {
  1375. snd_iprintf(buffer, "\n sample rate: no valid signal\n");
  1376. } else {
  1377. if (n) {
  1378. snd_iprintf(buffer, " (8 channels)\n");
  1379. } else {
  1380. snd_iprintf(buffer, " (2 channels)\n");
  1381. }
  1382. snd_iprintf(buffer, " sample rate: %d Hz\n",
  1383. snd_rme32_capture_getrate(rme32, &n));
  1384. }
  1385. snd_iprintf(buffer, "\nOutput settings\n");
  1386. if (rme32->wcreg & RME32_WCR_SEL) {
  1387. snd_iprintf(buffer, " output signal: normal playback");
  1388. } else {
  1389. snd_iprintf(buffer, " output signal: same as input");
  1390. }
  1391. if (rme32->wcreg & RME32_WCR_MUTE) {
  1392. snd_iprintf(buffer, " (muted)\n");
  1393. } else {
  1394. snd_iprintf(buffer, "\n");
  1395. }
  1396. /* master output frequency */
  1397. if (!
  1398. ((!(rme32->wcreg & RME32_WCR_FREQ_0))
  1399. && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
  1400. snd_iprintf(buffer, " sample rate: %d Hz\n",
  1401. snd_rme32_playback_getrate(rme32));
  1402. }
  1403. if (rme32->rcreg & RME32_RCR_KMODE) {
  1404. snd_iprintf(buffer, " sample clock source: AutoSync\n");
  1405. } else {
  1406. snd_iprintf(buffer, " sample clock source: Internal\n");
  1407. }
  1408. if (rme32->wcreg & RME32_WCR_PRO) {
  1409. snd_iprintf(buffer, " format: AES/EBU (professional)\n");
  1410. } else {
  1411. snd_iprintf(buffer, " format: IEC958 (consumer)\n");
  1412. }
  1413. if (rme32->wcreg & RME32_WCR_EMP) {
  1414. snd_iprintf(buffer, " emphasis: on\n");
  1415. } else {
  1416. snd_iprintf(buffer, " emphasis: off\n");
  1417. }
  1418. }
  1419. static void __devinit snd_rme32_proc_init(rme32_t * rme32)
  1420. {
  1421. snd_info_entry_t *entry;
  1422. if (! snd_card_proc_new(rme32->card, "rme32", &entry))
  1423. snd_info_set_text_ops(entry, rme32, 1024, snd_rme32_proc_read);
  1424. }
  1425. /*
  1426. * control interface
  1427. */
  1428. static int
  1429. snd_rme32_info_loopback_control(snd_kcontrol_t * kcontrol,
  1430. snd_ctl_elem_info_t * uinfo)
  1431. {
  1432. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1433. uinfo->count = 1;
  1434. uinfo->value.integer.min = 0;
  1435. uinfo->value.integer.max = 1;
  1436. return 0;
  1437. }
  1438. static int
  1439. snd_rme32_get_loopback_control(snd_kcontrol_t * kcontrol,
  1440. snd_ctl_elem_value_t * ucontrol)
  1441. {
  1442. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1443. spin_lock_irq(&rme32->lock);
  1444. ucontrol->value.integer.value[0] =
  1445. rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
  1446. spin_unlock_irq(&rme32->lock);
  1447. return 0;
  1448. }
  1449. static int
  1450. snd_rme32_put_loopback_control(snd_kcontrol_t * kcontrol,
  1451. snd_ctl_elem_value_t * ucontrol)
  1452. {
  1453. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1454. unsigned int val;
  1455. int change;
  1456. val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
  1457. spin_lock_irq(&rme32->lock);
  1458. val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
  1459. change = val != rme32->wcreg;
  1460. if (ucontrol->value.integer.value[0])
  1461. val &= ~RME32_WCR_MUTE;
  1462. else
  1463. val |= RME32_WCR_MUTE;
  1464. rme32->wcreg = val;
  1465. writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1466. spin_unlock_irq(&rme32->lock);
  1467. return change;
  1468. }
  1469. static int
  1470. snd_rme32_info_inputtype_control(snd_kcontrol_t * kcontrol,
  1471. snd_ctl_elem_info_t * uinfo)
  1472. {
  1473. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1474. static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
  1475. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1476. uinfo->count = 1;
  1477. switch (rme32->pci->device) {
  1478. case PCI_DEVICE_ID_DIGI32:
  1479. case PCI_DEVICE_ID_DIGI32_8:
  1480. uinfo->value.enumerated.items = 3;
  1481. break;
  1482. case PCI_DEVICE_ID_DIGI32_PRO:
  1483. uinfo->value.enumerated.items = 4;
  1484. break;
  1485. default:
  1486. snd_BUG();
  1487. break;
  1488. }
  1489. if (uinfo->value.enumerated.item >
  1490. uinfo->value.enumerated.items - 1) {
  1491. uinfo->value.enumerated.item =
  1492. uinfo->value.enumerated.items - 1;
  1493. }
  1494. strcpy(uinfo->value.enumerated.name,
  1495. texts[uinfo->value.enumerated.item]);
  1496. return 0;
  1497. }
  1498. static int
  1499. snd_rme32_get_inputtype_control(snd_kcontrol_t * kcontrol,
  1500. snd_ctl_elem_value_t * ucontrol)
  1501. {
  1502. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1503. unsigned int items = 3;
  1504. spin_lock_irq(&rme32->lock);
  1505. ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
  1506. switch (rme32->pci->device) {
  1507. case PCI_DEVICE_ID_DIGI32:
  1508. case PCI_DEVICE_ID_DIGI32_8:
  1509. items = 3;
  1510. break;
  1511. case PCI_DEVICE_ID_DIGI32_PRO:
  1512. items = 4;
  1513. break;
  1514. default:
  1515. snd_BUG();
  1516. break;
  1517. }
  1518. if (ucontrol->value.enumerated.item[0] >= items) {
  1519. ucontrol->value.enumerated.item[0] = items - 1;
  1520. }
  1521. spin_unlock_irq(&rme32->lock);
  1522. return 0;
  1523. }
  1524. static int
  1525. snd_rme32_put_inputtype_control(snd_kcontrol_t * kcontrol,
  1526. snd_ctl_elem_value_t * ucontrol)
  1527. {
  1528. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1529. unsigned int val;
  1530. int change, items = 3;
  1531. switch (rme32->pci->device) {
  1532. case PCI_DEVICE_ID_DIGI32:
  1533. case PCI_DEVICE_ID_DIGI32_8:
  1534. items = 3;
  1535. break;
  1536. case PCI_DEVICE_ID_DIGI32_PRO:
  1537. items = 4;
  1538. break;
  1539. default:
  1540. snd_BUG();
  1541. break;
  1542. }
  1543. val = ucontrol->value.enumerated.item[0] % items;
  1544. spin_lock_irq(&rme32->lock);
  1545. change = val != (unsigned int)snd_rme32_getinputtype(rme32);
  1546. snd_rme32_setinputtype(rme32, val);
  1547. spin_unlock_irq(&rme32->lock);
  1548. return change;
  1549. }
  1550. static int
  1551. snd_rme32_info_clockmode_control(snd_kcontrol_t * kcontrol,
  1552. snd_ctl_elem_info_t * uinfo)
  1553. {
  1554. static char *texts[4] = { "AutoSync",
  1555. "Internal 32.0kHz",
  1556. "Internal 44.1kHz",
  1557. "Internal 48.0kHz" };
  1558. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1559. uinfo->count = 1;
  1560. uinfo->value.enumerated.items = 4;
  1561. if (uinfo->value.enumerated.item > 3) {
  1562. uinfo->value.enumerated.item = 3;
  1563. }
  1564. strcpy(uinfo->value.enumerated.name,
  1565. texts[uinfo->value.enumerated.item]);
  1566. return 0;
  1567. }
  1568. static int
  1569. snd_rme32_get_clockmode_control(snd_kcontrol_t * kcontrol,
  1570. snd_ctl_elem_value_t * ucontrol)
  1571. {
  1572. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1573. spin_lock_irq(&rme32->lock);
  1574. ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
  1575. spin_unlock_irq(&rme32->lock);
  1576. return 0;
  1577. }
  1578. static int
  1579. snd_rme32_put_clockmode_control(snd_kcontrol_t * kcontrol,
  1580. snd_ctl_elem_value_t * ucontrol)
  1581. {
  1582. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1583. unsigned int val;
  1584. int change;
  1585. val = ucontrol->value.enumerated.item[0] % 3;
  1586. spin_lock_irq(&rme32->lock);
  1587. change = val != (unsigned int)snd_rme32_getclockmode(rme32);
  1588. snd_rme32_setclockmode(rme32, val);
  1589. spin_unlock_irq(&rme32->lock);
  1590. return change;
  1591. }
  1592. static u32 snd_rme32_convert_from_aes(snd_aes_iec958_t * aes)
  1593. {
  1594. u32 val = 0;
  1595. val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
  1596. if (val & RME32_WCR_PRO)
  1597. val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
  1598. else
  1599. val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
  1600. return val;
  1601. }
  1602. static void snd_rme32_convert_to_aes(snd_aes_iec958_t * aes, u32 val)
  1603. {
  1604. aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
  1605. if (val & RME32_WCR_PRO)
  1606. aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
  1607. else
  1608. aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
  1609. }
  1610. static int snd_rme32_control_spdif_info(snd_kcontrol_t * kcontrol,
  1611. snd_ctl_elem_info_t * uinfo)
  1612. {
  1613. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1614. uinfo->count = 1;
  1615. return 0;
  1616. }
  1617. static int snd_rme32_control_spdif_get(snd_kcontrol_t * kcontrol,
  1618. snd_ctl_elem_value_t * ucontrol)
  1619. {
  1620. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1621. snd_rme32_convert_to_aes(&ucontrol->value.iec958,
  1622. rme32->wcreg_spdif);
  1623. return 0;
  1624. }
  1625. static int snd_rme32_control_spdif_put(snd_kcontrol_t * kcontrol,
  1626. snd_ctl_elem_value_t * ucontrol)
  1627. {
  1628. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1629. int change;
  1630. u32 val;
  1631. val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
  1632. spin_lock_irq(&rme32->lock);
  1633. change = val != rme32->wcreg_spdif;
  1634. rme32->wcreg_spdif = val;
  1635. spin_unlock_irq(&rme32->lock);
  1636. return change;
  1637. }
  1638. static int snd_rme32_control_spdif_stream_info(snd_kcontrol_t * kcontrol,
  1639. snd_ctl_elem_info_t * uinfo)
  1640. {
  1641. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1642. uinfo->count = 1;
  1643. return 0;
  1644. }
  1645. static int snd_rme32_control_spdif_stream_get(snd_kcontrol_t * kcontrol,
  1646. snd_ctl_elem_value_t *
  1647. ucontrol)
  1648. {
  1649. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1650. snd_rme32_convert_to_aes(&ucontrol->value.iec958,
  1651. rme32->wcreg_spdif_stream);
  1652. return 0;
  1653. }
  1654. static int snd_rme32_control_spdif_stream_put(snd_kcontrol_t * kcontrol,
  1655. snd_ctl_elem_value_t *
  1656. ucontrol)
  1657. {
  1658. rme32_t *rme32 = snd_kcontrol_chip(kcontrol);
  1659. int change;
  1660. u32 val;
  1661. val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
  1662. spin_lock_irq(&rme32->lock);
  1663. change = val != rme32->wcreg_spdif_stream;
  1664. rme32->wcreg_spdif_stream = val;
  1665. rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
  1666. rme32->wcreg |= val;
  1667. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1668. spin_unlock_irq(&rme32->lock);
  1669. return change;
  1670. }
  1671. static int snd_rme32_control_spdif_mask_info(snd_kcontrol_t * kcontrol,
  1672. snd_ctl_elem_info_t * uinfo)
  1673. {
  1674. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1675. uinfo->count = 1;
  1676. return 0;
  1677. }
  1678. static int snd_rme32_control_spdif_mask_get(snd_kcontrol_t * kcontrol,
  1679. snd_ctl_elem_value_t *
  1680. ucontrol)
  1681. {
  1682. ucontrol->value.iec958.status[0] = kcontrol->private_value;
  1683. return 0;
  1684. }
  1685. static snd_kcontrol_new_t snd_rme32_controls[] = {
  1686. {
  1687. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1688. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1689. .info = snd_rme32_control_spdif_info,
  1690. .get = snd_rme32_control_spdif_get,
  1691. .put = snd_rme32_control_spdif_put
  1692. },
  1693. {
  1694. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1695. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1696. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
  1697. .info = snd_rme32_control_spdif_stream_info,
  1698. .get = snd_rme32_control_spdif_stream_get,
  1699. .put = snd_rme32_control_spdif_stream_put
  1700. },
  1701. {
  1702. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1703. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1704. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1705. .info = snd_rme32_control_spdif_mask_info,
  1706. .get = snd_rme32_control_spdif_mask_get,
  1707. .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
  1708. },
  1709. {
  1710. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1711. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1712. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1713. .info = snd_rme32_control_spdif_mask_info,
  1714. .get = snd_rme32_control_spdif_mask_get,
  1715. .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
  1716. },
  1717. {
  1718. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1719. .name = "Input Connector",
  1720. .info = snd_rme32_info_inputtype_control,
  1721. .get = snd_rme32_get_inputtype_control,
  1722. .put = snd_rme32_put_inputtype_control
  1723. },
  1724. {
  1725. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1726. .name = "Loopback Input",
  1727. .info = snd_rme32_info_loopback_control,
  1728. .get = snd_rme32_get_loopback_control,
  1729. .put = snd_rme32_put_loopback_control
  1730. },
  1731. {
  1732. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1733. .name = "Sample Clock Source",
  1734. .info = snd_rme32_info_clockmode_control,
  1735. .get = snd_rme32_get_clockmode_control,
  1736. .put = snd_rme32_put_clockmode_control
  1737. }
  1738. };
  1739. static int snd_rme32_create_switches(snd_card_t * card, rme32_t * rme32)
  1740. {
  1741. int idx, err;
  1742. snd_kcontrol_t *kctl;
  1743. for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
  1744. if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
  1745. return err;
  1746. if (idx == 1) /* IEC958 (S/PDIF) Stream */
  1747. rme32->spdif_ctl = kctl;
  1748. }
  1749. return 0;
  1750. }
  1751. /*
  1752. * Card initialisation
  1753. */
  1754. static void snd_rme32_card_free(snd_card_t * card)
  1755. {
  1756. snd_rme32_free(card->private_data);
  1757. }
  1758. static int __devinit
  1759. snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1760. {
  1761. static int dev;
  1762. rme32_t *rme32;
  1763. snd_card_t *card;
  1764. int err;
  1765. if (dev >= SNDRV_CARDS) {
  1766. return -ENODEV;
  1767. }
  1768. if (!enable[dev]) {
  1769. dev++;
  1770. return -ENOENT;
  1771. }
  1772. if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
  1773. sizeof(rme32_t))) == NULL)
  1774. return -ENOMEM;
  1775. card->private_free = snd_rme32_card_free;
  1776. rme32 = (rme32_t *) card->private_data;
  1777. rme32->card = card;
  1778. rme32->pci = pci;
  1779. snd_card_set_dev(card, &pci->dev);
  1780. if (fullduplex[dev])
  1781. rme32->fullduplex_mode = 1;
  1782. if ((err = snd_rme32_create(rme32)) < 0) {
  1783. snd_card_free(card);
  1784. return err;
  1785. }
  1786. strcpy(card->driver, "Digi32");
  1787. switch (rme32->pci->device) {
  1788. case PCI_DEVICE_ID_DIGI32:
  1789. strcpy(card->shortname, "RME Digi32");
  1790. break;
  1791. case PCI_DEVICE_ID_DIGI32_8:
  1792. strcpy(card->shortname, "RME Digi32/8");
  1793. break;
  1794. case PCI_DEVICE_ID_DIGI32_PRO:
  1795. strcpy(card->shortname, "RME Digi32 PRO");
  1796. break;
  1797. }
  1798. sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
  1799. card->shortname, rme32->rev, rme32->port, rme32->irq);
  1800. if ((err = snd_card_register(card)) < 0) {
  1801. snd_card_free(card);
  1802. return err;
  1803. }
  1804. pci_set_drvdata(pci, card);
  1805. dev++;
  1806. return 0;
  1807. }
  1808. static void __devexit snd_rme32_remove(struct pci_dev *pci)
  1809. {
  1810. snd_card_free(pci_get_drvdata(pci));
  1811. pci_set_drvdata(pci, NULL);
  1812. }
  1813. static struct pci_driver driver = {
  1814. .name = "RME Digi32",
  1815. .id_table = snd_rme32_ids,
  1816. .probe = snd_rme32_probe,
  1817. .remove = __devexit_p(snd_rme32_remove),
  1818. };
  1819. static int __init alsa_card_rme32_init(void)
  1820. {
  1821. return pci_register_driver(&driver);
  1822. }
  1823. static void __exit alsa_card_rme32_exit(void)
  1824. {
  1825. pci_unregister_driver(&driver);
  1826. }
  1827. module_init(alsa_card_rme32_init)
  1828. module_exit(alsa_card_rme32_exit)