bt87x.c 27 KB

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  1. /*
  2. * bt87x.c - Brooktree Bt878/Bt879 driver for ALSA
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. *
  6. * based on btaudio.c by Gerd Knorr <kraxel@bytesex.org>
  7. *
  8. *
  9. * This driver is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This driver is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <sound/driver.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/pci.h>
  27. #include <linux/slab.h>
  28. #include <linux/moduleparam.h>
  29. #include <linux/bitops.h>
  30. #include <asm/io.h>
  31. #include <sound/core.h>
  32. #include <sound/pcm.h>
  33. #include <sound/pcm_params.h>
  34. #include <sound/control.h>
  35. #include <sound/initval.h>
  36. MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
  37. MODULE_DESCRIPTION("Brooktree Bt87x audio driver");
  38. MODULE_LICENSE("GPL");
  39. MODULE_SUPPORTED_DEVICE("{{Brooktree,Bt878},"
  40. "{Brooktree,Bt879}}");
  41. static int index[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -2}; /* Exclude the first card */
  42. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  43. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  44. static int digital_rate[SNDRV_CARDS] = { [0 ... (SNDRV_CARDS-1)] = 0 }; /* digital input rate */
  45. static int load_all; /* allow to load the non-whitelisted cards */
  46. module_param_array(index, int, NULL, 0444);
  47. MODULE_PARM_DESC(index, "Index value for Bt87x soundcard");
  48. module_param_array(id, charp, NULL, 0444);
  49. MODULE_PARM_DESC(id, "ID string for Bt87x soundcard");
  50. module_param_array(enable, bool, NULL, 0444);
  51. MODULE_PARM_DESC(enable, "Enable Bt87x soundcard");
  52. module_param_array(digital_rate, int, NULL, 0444);
  53. MODULE_PARM_DESC(digital_rate, "Digital input rate for Bt87x soundcard");
  54. module_param(load_all, bool, 0444);
  55. MODULE_PARM_DESC(load_all, "Allow to load the non-whitelisted cards");
  56. #ifndef PCI_VENDOR_ID_BROOKTREE
  57. #define PCI_VENDOR_ID_BROOKTREE 0x109e
  58. #endif
  59. #ifndef PCI_DEVICE_ID_BROOKTREE_878
  60. #define PCI_DEVICE_ID_BROOKTREE_878 0x0878
  61. #endif
  62. #ifndef PCI_DEVICE_ID_BROOKTREE_879
  63. #define PCI_DEVICE_ID_BROOKTREE_879 0x0879
  64. #endif
  65. /* register offsets */
  66. #define REG_INT_STAT 0x100 /* interrupt status */
  67. #define REG_INT_MASK 0x104 /* interrupt mask */
  68. #define REG_GPIO_DMA_CTL 0x10c /* audio control */
  69. #define REG_PACKET_LEN 0x110 /* audio packet lengths */
  70. #define REG_RISC_STRT_ADD 0x114 /* RISC program start address */
  71. #define REG_RISC_COUNT 0x120 /* RISC program counter */
  72. /* interrupt bits */
  73. #define INT_OFLOW (1 << 3) /* audio A/D overflow */
  74. #define INT_RISCI (1 << 11) /* RISC instruction IRQ bit set */
  75. #define INT_FBUS (1 << 12) /* FIFO overrun due to bus access latency */
  76. #define INT_FTRGT (1 << 13) /* FIFO overrun due to target latency */
  77. #define INT_FDSR (1 << 14) /* FIFO data stream resynchronization */
  78. #define INT_PPERR (1 << 15) /* PCI parity error */
  79. #define INT_RIPERR (1 << 16) /* RISC instruction parity error */
  80. #define INT_PABORT (1 << 17) /* PCI master or target abort */
  81. #define INT_OCERR (1 << 18) /* invalid opcode */
  82. #define INT_SCERR (1 << 19) /* sync counter overflow */
  83. #define INT_RISC_EN (1 << 27) /* DMA controller running */
  84. #define INT_RISCS_SHIFT 28 /* RISC status bits */
  85. /* audio control bits */
  86. #define CTL_FIFO_ENABLE (1 << 0) /* enable audio data FIFO */
  87. #define CTL_RISC_ENABLE (1 << 1) /* enable audio DMA controller */
  88. #define CTL_PKTP_4 (0 << 2) /* packet mode FIFO trigger point - 4 DWORDs */
  89. #define CTL_PKTP_8 (1 << 2) /* 8 DWORDs */
  90. #define CTL_PKTP_16 (2 << 2) /* 16 DWORDs */
  91. #define CTL_ACAP_EN (1 << 4) /* enable audio capture */
  92. #define CTL_DA_APP (1 << 5) /* GPIO input */
  93. #define CTL_DA_IOM_AFE (0 << 6) /* audio A/D input */
  94. #define CTL_DA_IOM_DA (1 << 6) /* digital audio input */
  95. #define CTL_DA_SDR_SHIFT 8 /* DDF first stage decimation rate */
  96. #define CTL_DA_SDR_MASK (0xf<< 8)
  97. #define CTL_DA_LMT (1 << 12) /* limit audio data values */
  98. #define CTL_DA_ES2 (1 << 13) /* enable DDF stage 2 */
  99. #define CTL_DA_SBR (1 << 14) /* samples rounded to 8 bits */
  100. #define CTL_DA_DPM (1 << 15) /* data packet mode */
  101. #define CTL_DA_LRD_SHIFT 16 /* ALRCK delay */
  102. #define CTL_DA_MLB (1 << 21) /* MSB/LSB format */
  103. #define CTL_DA_LRI (1 << 22) /* left/right indication */
  104. #define CTL_DA_SCE (1 << 23) /* sample clock edge */
  105. #define CTL_A_SEL_STV (0 << 24) /* TV tuner audio input */
  106. #define CTL_A_SEL_SFM (1 << 24) /* FM audio input */
  107. #define CTL_A_SEL_SML (2 << 24) /* mic/line audio input */
  108. #define CTL_A_SEL_SMXC (3 << 24) /* MUX bypass */
  109. #define CTL_A_SEL_SHIFT 24
  110. #define CTL_A_SEL_MASK (3 << 24)
  111. #define CTL_A_PWRDN (1 << 26) /* analog audio power-down */
  112. #define CTL_A_G2X (1 << 27) /* audio gain boost */
  113. #define CTL_A_GAIN_SHIFT 28 /* audio input gain */
  114. #define CTL_A_GAIN_MASK (0xf<<28)
  115. /* RISC instruction opcodes */
  116. #define RISC_WRITE (0x1 << 28) /* write FIFO data to memory at address */
  117. #define RISC_WRITEC (0x5 << 28) /* write FIFO data to memory at current address */
  118. #define RISC_SKIP (0x2 << 28) /* skip FIFO data */
  119. #define RISC_JUMP (0x7 << 28) /* jump to address */
  120. #define RISC_SYNC (0x8 << 28) /* synchronize with FIFO */
  121. /* RISC instruction bits */
  122. #define RISC_BYTES_ENABLE (0xf << 12) /* byte enable bits */
  123. #define RISC_RESYNC ( 1 << 15) /* disable FDSR errors */
  124. #define RISC_SET_STATUS_SHIFT 16 /* set status bits */
  125. #define RISC_RESET_STATUS_SHIFT 20 /* clear status bits */
  126. #define RISC_IRQ ( 1 << 24) /* interrupt */
  127. #define RISC_EOL ( 1 << 26) /* end of line */
  128. #define RISC_SOL ( 1 << 27) /* start of line */
  129. /* SYNC status bits values */
  130. #define RISC_SYNC_FM1 0x6
  131. #define RISC_SYNC_VRO 0xc
  132. #define ANALOG_CLOCK 1792000
  133. #ifdef CONFIG_SND_BT87X_OVERCLOCK
  134. #define CLOCK_DIV_MIN 1
  135. #else
  136. #define CLOCK_DIV_MIN 4
  137. #endif
  138. #define CLOCK_DIV_MAX 15
  139. #define ERROR_INTERRUPTS (INT_FBUS | INT_FTRGT | INT_PPERR | \
  140. INT_RIPERR | INT_PABORT | INT_OCERR)
  141. #define MY_INTERRUPTS (INT_RISCI | ERROR_INTERRUPTS)
  142. /* SYNC, one WRITE per line, one extra WRITE per page boundary, SYNC, JUMP */
  143. #define MAX_RISC_SIZE ((1 + 255 + (PAGE_ALIGN(255 * 4092) / PAGE_SIZE - 1) + 1 + 1) * 8)
  144. typedef struct snd_bt87x bt87x_t;
  145. struct snd_bt87x {
  146. snd_card_t *card;
  147. struct pci_dev *pci;
  148. void __iomem *mmio;
  149. int irq;
  150. int dig_rate;
  151. spinlock_t reg_lock;
  152. long opened;
  153. snd_pcm_substream_t *substream;
  154. struct snd_dma_buffer dma_risc;
  155. unsigned int line_bytes;
  156. unsigned int lines;
  157. u32 reg_control;
  158. u32 interrupt_mask;
  159. int current_line;
  160. int pci_parity_errors;
  161. };
  162. enum { DEVICE_DIGITAL, DEVICE_ANALOG };
  163. static inline u32 snd_bt87x_readl(bt87x_t *chip, u32 reg)
  164. {
  165. return readl(chip->mmio + reg);
  166. }
  167. static inline void snd_bt87x_writel(bt87x_t *chip, u32 reg, u32 value)
  168. {
  169. writel(value, chip->mmio + reg);
  170. }
  171. static int snd_bt87x_create_risc(bt87x_t *chip, snd_pcm_substream_t *substream,
  172. unsigned int periods, unsigned int period_bytes)
  173. {
  174. struct snd_sg_buf *sgbuf = snd_pcm_substream_sgbuf(substream);
  175. unsigned int i, offset;
  176. u32 *risc;
  177. if (chip->dma_risc.area == NULL) {
  178. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  179. PAGE_ALIGN(MAX_RISC_SIZE), &chip->dma_risc) < 0)
  180. return -ENOMEM;
  181. }
  182. risc = (u32 *)chip->dma_risc.area;
  183. offset = 0;
  184. *risc++ = cpu_to_le32(RISC_SYNC | RISC_SYNC_FM1);
  185. *risc++ = cpu_to_le32(0);
  186. for (i = 0; i < periods; ++i) {
  187. u32 rest;
  188. rest = period_bytes;
  189. do {
  190. u32 cmd, len;
  191. len = PAGE_SIZE - (offset % PAGE_SIZE);
  192. if (len > rest)
  193. len = rest;
  194. cmd = RISC_WRITE | len;
  195. if (rest == period_bytes) {
  196. u32 block = i * 16 / periods;
  197. cmd |= RISC_SOL;
  198. cmd |= block << RISC_SET_STATUS_SHIFT;
  199. cmd |= (~block & 0xf) << RISC_RESET_STATUS_SHIFT;
  200. }
  201. if (len == rest)
  202. cmd |= RISC_EOL | RISC_IRQ;
  203. *risc++ = cpu_to_le32(cmd);
  204. *risc++ = cpu_to_le32((u32)snd_pcm_sgbuf_get_addr(sgbuf, offset));
  205. offset += len;
  206. rest -= len;
  207. } while (rest > 0);
  208. }
  209. *risc++ = cpu_to_le32(RISC_SYNC | RISC_SYNC_VRO);
  210. *risc++ = cpu_to_le32(0);
  211. *risc++ = cpu_to_le32(RISC_JUMP);
  212. *risc++ = cpu_to_le32(chip->dma_risc.addr);
  213. chip->line_bytes = period_bytes;
  214. chip->lines = periods;
  215. return 0;
  216. }
  217. static void snd_bt87x_free_risc(bt87x_t *chip)
  218. {
  219. if (chip->dma_risc.area) {
  220. snd_dma_free_pages(&chip->dma_risc);
  221. chip->dma_risc.area = NULL;
  222. }
  223. }
  224. static void snd_bt87x_pci_error(bt87x_t *chip, unsigned int status)
  225. {
  226. u16 pci_status;
  227. pci_read_config_word(chip->pci, PCI_STATUS, &pci_status);
  228. pci_status &= PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
  229. PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
  230. PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY;
  231. pci_write_config_word(chip->pci, PCI_STATUS, pci_status);
  232. if (pci_status != PCI_STATUS_DETECTED_PARITY)
  233. snd_printk(KERN_ERR "Aieee - PCI error! status %#08x, PCI status %#04x\n",
  234. status & ERROR_INTERRUPTS, pci_status);
  235. else {
  236. snd_printk(KERN_ERR "Aieee - PCI parity error detected!\n");
  237. /* error 'handling' similar to aic7xxx_pci.c: */
  238. chip->pci_parity_errors++;
  239. if (chip->pci_parity_errors > 20) {
  240. snd_printk(KERN_ERR "Too many PCI parity errors observed.\n");
  241. snd_printk(KERN_ERR "Some device on this bus is generating bad parity.\n");
  242. snd_printk(KERN_ERR "This is an error *observed by*, not *generated by*, this card.\n");
  243. snd_printk(KERN_ERR "PCI parity error checking has been disabled.\n");
  244. chip->interrupt_mask &= ~(INT_PPERR | INT_RIPERR);
  245. snd_bt87x_writel(chip, REG_INT_MASK, chip->interrupt_mask);
  246. }
  247. }
  248. }
  249. static irqreturn_t snd_bt87x_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  250. {
  251. bt87x_t *chip = dev_id;
  252. unsigned int status, irq_status;
  253. status = snd_bt87x_readl(chip, REG_INT_STAT);
  254. irq_status = status & chip->interrupt_mask;
  255. if (!irq_status)
  256. return IRQ_NONE;
  257. snd_bt87x_writel(chip, REG_INT_STAT, irq_status);
  258. if (irq_status & ERROR_INTERRUPTS) {
  259. if (irq_status & (INT_FBUS | INT_FTRGT))
  260. snd_printk(KERN_WARNING "FIFO overrun, status %#08x\n", status);
  261. if (irq_status & INT_OCERR)
  262. snd_printk(KERN_ERR "internal RISC error, status %#08x\n", status);
  263. if (irq_status & (INT_PPERR | INT_RIPERR | INT_PABORT))
  264. snd_bt87x_pci_error(chip, irq_status);
  265. }
  266. if ((irq_status & INT_RISCI) && (chip->reg_control & CTL_ACAP_EN)) {
  267. int current_block, irq_block;
  268. /* assume that exactly one line has been recorded */
  269. chip->current_line = (chip->current_line + 1) % chip->lines;
  270. /* but check if some interrupts have been skipped */
  271. current_block = chip->current_line * 16 / chip->lines;
  272. irq_block = status >> INT_RISCS_SHIFT;
  273. if (current_block != irq_block)
  274. chip->current_line = (irq_block * chip->lines + 15) / 16;
  275. snd_pcm_period_elapsed(chip->substream);
  276. }
  277. return IRQ_HANDLED;
  278. }
  279. static snd_pcm_hardware_t snd_bt87x_digital_hw = {
  280. .info = SNDRV_PCM_INFO_MMAP |
  281. SNDRV_PCM_INFO_INTERLEAVED |
  282. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  283. SNDRV_PCM_INFO_MMAP_VALID,
  284. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  285. .rates = 0, /* set at runtime */
  286. .channels_min = 2,
  287. .channels_max = 2,
  288. .buffer_bytes_max = 255 * 4092,
  289. .period_bytes_min = 32,
  290. .period_bytes_max = 4092,
  291. .periods_min = 2,
  292. .periods_max = 255,
  293. };
  294. static snd_pcm_hardware_t snd_bt87x_analog_hw = {
  295. .info = SNDRV_PCM_INFO_MMAP |
  296. SNDRV_PCM_INFO_INTERLEAVED |
  297. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  298. SNDRV_PCM_INFO_MMAP_VALID,
  299. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  300. .rates = SNDRV_PCM_RATE_KNOT,
  301. .rate_min = ANALOG_CLOCK / CLOCK_DIV_MAX,
  302. .rate_max = ANALOG_CLOCK / CLOCK_DIV_MIN,
  303. .channels_min = 1,
  304. .channels_max = 1,
  305. .buffer_bytes_max = 255 * 4092,
  306. .period_bytes_min = 32,
  307. .period_bytes_max = 4092,
  308. .periods_min = 2,
  309. .periods_max = 255,
  310. };
  311. static int snd_bt87x_set_digital_hw(bt87x_t *chip, snd_pcm_runtime_t *runtime)
  312. {
  313. static struct {
  314. int rate;
  315. unsigned int bit;
  316. } ratebits[] = {
  317. {8000, SNDRV_PCM_RATE_8000},
  318. {11025, SNDRV_PCM_RATE_11025},
  319. {16000, SNDRV_PCM_RATE_16000},
  320. {22050, SNDRV_PCM_RATE_22050},
  321. {32000, SNDRV_PCM_RATE_32000},
  322. {44100, SNDRV_PCM_RATE_44100},
  323. {48000, SNDRV_PCM_RATE_48000}
  324. };
  325. int i;
  326. chip->reg_control |= CTL_DA_IOM_DA;
  327. runtime->hw = snd_bt87x_digital_hw;
  328. runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
  329. for (i = 0; i < ARRAY_SIZE(ratebits); ++i)
  330. if (chip->dig_rate == ratebits[i].rate) {
  331. runtime->hw.rates = ratebits[i].bit;
  332. break;
  333. }
  334. runtime->hw.rate_min = chip->dig_rate;
  335. runtime->hw.rate_max = chip->dig_rate;
  336. return 0;
  337. }
  338. static int snd_bt87x_set_analog_hw(bt87x_t *chip, snd_pcm_runtime_t *runtime)
  339. {
  340. static ratnum_t analog_clock = {
  341. .num = ANALOG_CLOCK,
  342. .den_min = CLOCK_DIV_MIN,
  343. .den_max = CLOCK_DIV_MAX,
  344. .den_step = 1
  345. };
  346. static snd_pcm_hw_constraint_ratnums_t constraint_rates = {
  347. .nrats = 1,
  348. .rats = &analog_clock
  349. };
  350. chip->reg_control &= ~CTL_DA_IOM_DA;
  351. runtime->hw = snd_bt87x_analog_hw;
  352. return snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  353. &constraint_rates);
  354. }
  355. static int snd_bt87x_pcm_open(snd_pcm_substream_t *substream)
  356. {
  357. bt87x_t *chip = snd_pcm_substream_chip(substream);
  358. snd_pcm_runtime_t *runtime = substream->runtime;
  359. int err;
  360. if (test_and_set_bit(0, &chip->opened))
  361. return -EBUSY;
  362. if (substream->pcm->device == DEVICE_DIGITAL)
  363. err = snd_bt87x_set_digital_hw(chip, runtime);
  364. else
  365. err = snd_bt87x_set_analog_hw(chip, runtime);
  366. if (err < 0)
  367. goto _error;
  368. err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  369. if (err < 0)
  370. goto _error;
  371. chip->substream = substream;
  372. return 0;
  373. _error:
  374. clear_bit(0, &chip->opened);
  375. smp_mb__after_clear_bit();
  376. return err;
  377. }
  378. static int snd_bt87x_close(snd_pcm_substream_t *substream)
  379. {
  380. bt87x_t *chip = snd_pcm_substream_chip(substream);
  381. chip->substream = NULL;
  382. clear_bit(0, &chip->opened);
  383. smp_mb__after_clear_bit();
  384. return 0;
  385. }
  386. static int snd_bt87x_hw_params(snd_pcm_substream_t *substream,
  387. snd_pcm_hw_params_t *hw_params)
  388. {
  389. bt87x_t *chip = snd_pcm_substream_chip(substream);
  390. int err;
  391. err = snd_pcm_lib_malloc_pages(substream,
  392. params_buffer_bytes(hw_params));
  393. if (err < 0)
  394. return err;
  395. return snd_bt87x_create_risc(chip, substream,
  396. params_periods(hw_params),
  397. params_period_bytes(hw_params));
  398. }
  399. static int snd_bt87x_hw_free(snd_pcm_substream_t *substream)
  400. {
  401. bt87x_t *chip = snd_pcm_substream_chip(substream);
  402. snd_bt87x_free_risc(chip);
  403. snd_pcm_lib_free_pages(substream);
  404. return 0;
  405. }
  406. static int snd_bt87x_prepare(snd_pcm_substream_t *substream)
  407. {
  408. bt87x_t *chip = snd_pcm_substream_chip(substream);
  409. snd_pcm_runtime_t *runtime = substream->runtime;
  410. int decimation;
  411. spin_lock_irq(&chip->reg_lock);
  412. chip->reg_control &= ~(CTL_DA_SDR_MASK | CTL_DA_SBR);
  413. decimation = (ANALOG_CLOCK + runtime->rate / 4) / runtime->rate;
  414. chip->reg_control |= decimation << CTL_DA_SDR_SHIFT;
  415. if (runtime->format == SNDRV_PCM_FORMAT_S8)
  416. chip->reg_control |= CTL_DA_SBR;
  417. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  418. spin_unlock_irq(&chip->reg_lock);
  419. return 0;
  420. }
  421. static int snd_bt87x_start(bt87x_t *chip)
  422. {
  423. spin_lock(&chip->reg_lock);
  424. chip->current_line = 0;
  425. chip->reg_control |= CTL_FIFO_ENABLE | CTL_RISC_ENABLE | CTL_ACAP_EN;
  426. snd_bt87x_writel(chip, REG_RISC_STRT_ADD, chip->dma_risc.addr);
  427. snd_bt87x_writel(chip, REG_PACKET_LEN,
  428. chip->line_bytes | (chip->lines << 16));
  429. snd_bt87x_writel(chip, REG_INT_MASK, chip->interrupt_mask);
  430. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  431. spin_unlock(&chip->reg_lock);
  432. return 0;
  433. }
  434. static int snd_bt87x_stop(bt87x_t *chip)
  435. {
  436. spin_lock(&chip->reg_lock);
  437. chip->reg_control &= ~(CTL_FIFO_ENABLE | CTL_RISC_ENABLE | CTL_ACAP_EN);
  438. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  439. snd_bt87x_writel(chip, REG_INT_MASK, 0);
  440. snd_bt87x_writel(chip, REG_INT_STAT, MY_INTERRUPTS);
  441. spin_unlock(&chip->reg_lock);
  442. return 0;
  443. }
  444. static int snd_bt87x_trigger(snd_pcm_substream_t *substream, int cmd)
  445. {
  446. bt87x_t *chip = snd_pcm_substream_chip(substream);
  447. switch (cmd) {
  448. case SNDRV_PCM_TRIGGER_START:
  449. return snd_bt87x_start(chip);
  450. case SNDRV_PCM_TRIGGER_STOP:
  451. return snd_bt87x_stop(chip);
  452. default:
  453. return -EINVAL;
  454. }
  455. }
  456. static snd_pcm_uframes_t snd_bt87x_pointer(snd_pcm_substream_t *substream)
  457. {
  458. bt87x_t *chip = snd_pcm_substream_chip(substream);
  459. snd_pcm_runtime_t *runtime = substream->runtime;
  460. return (snd_pcm_uframes_t)bytes_to_frames(runtime, chip->current_line * chip->line_bytes);
  461. }
  462. static snd_pcm_ops_t snd_bt87x_pcm_ops = {
  463. .open = snd_bt87x_pcm_open,
  464. .close = snd_bt87x_close,
  465. .ioctl = snd_pcm_lib_ioctl,
  466. .hw_params = snd_bt87x_hw_params,
  467. .hw_free = snd_bt87x_hw_free,
  468. .prepare = snd_bt87x_prepare,
  469. .trigger = snd_bt87x_trigger,
  470. .pointer = snd_bt87x_pointer,
  471. .page = snd_pcm_sgbuf_ops_page,
  472. };
  473. static int snd_bt87x_capture_volume_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *info)
  474. {
  475. info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  476. info->count = 1;
  477. info->value.integer.min = 0;
  478. info->value.integer.max = 15;
  479. return 0;
  480. }
  481. static int snd_bt87x_capture_volume_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  482. {
  483. bt87x_t *chip = snd_kcontrol_chip(kcontrol);
  484. value->value.integer.value[0] = (chip->reg_control & CTL_A_GAIN_MASK) >> CTL_A_GAIN_SHIFT;
  485. return 0;
  486. }
  487. static int snd_bt87x_capture_volume_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  488. {
  489. bt87x_t *chip = snd_kcontrol_chip(kcontrol);
  490. u32 old_control;
  491. int changed;
  492. spin_lock_irq(&chip->reg_lock);
  493. old_control = chip->reg_control;
  494. chip->reg_control = (chip->reg_control & ~CTL_A_GAIN_MASK)
  495. | (value->value.integer.value[0] << CTL_A_GAIN_SHIFT);
  496. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  497. changed = old_control != chip->reg_control;
  498. spin_unlock_irq(&chip->reg_lock);
  499. return changed;
  500. }
  501. static snd_kcontrol_new_t snd_bt87x_capture_volume = {
  502. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  503. .name = "Capture Volume",
  504. .info = snd_bt87x_capture_volume_info,
  505. .get = snd_bt87x_capture_volume_get,
  506. .put = snd_bt87x_capture_volume_put,
  507. };
  508. static int snd_bt87x_capture_boost_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *info)
  509. {
  510. info->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  511. info->count = 1;
  512. info->value.integer.min = 0;
  513. info->value.integer.max = 1;
  514. return 0;
  515. }
  516. static int snd_bt87x_capture_boost_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  517. {
  518. bt87x_t *chip = snd_kcontrol_chip(kcontrol);
  519. value->value.integer.value[0] = !! (chip->reg_control & CTL_A_G2X);
  520. return 0;
  521. }
  522. static int snd_bt87x_capture_boost_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  523. {
  524. bt87x_t *chip = snd_kcontrol_chip(kcontrol);
  525. u32 old_control;
  526. int changed;
  527. spin_lock_irq(&chip->reg_lock);
  528. old_control = chip->reg_control;
  529. chip->reg_control = (chip->reg_control & ~CTL_A_G2X)
  530. | (value->value.integer.value[0] ? CTL_A_G2X : 0);
  531. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  532. changed = chip->reg_control != old_control;
  533. spin_unlock_irq(&chip->reg_lock);
  534. return changed;
  535. }
  536. static snd_kcontrol_new_t snd_bt87x_capture_boost = {
  537. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  538. .name = "Capture Boost",
  539. .info = snd_bt87x_capture_boost_info,
  540. .get = snd_bt87x_capture_boost_get,
  541. .put = snd_bt87x_capture_boost_put,
  542. };
  543. static int snd_bt87x_capture_source_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *info)
  544. {
  545. static char *texts[3] = {"TV Tuner", "FM", "Mic/Line"};
  546. info->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  547. info->count = 1;
  548. info->value.enumerated.items = 3;
  549. if (info->value.enumerated.item > 2)
  550. info->value.enumerated.item = 2;
  551. strcpy(info->value.enumerated.name, texts[info->value.enumerated.item]);
  552. return 0;
  553. }
  554. static int snd_bt87x_capture_source_get(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  555. {
  556. bt87x_t *chip = snd_kcontrol_chip(kcontrol);
  557. value->value.enumerated.item[0] = (chip->reg_control & CTL_A_SEL_MASK) >> CTL_A_SEL_SHIFT;
  558. return 0;
  559. }
  560. static int snd_bt87x_capture_source_put(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *value)
  561. {
  562. bt87x_t *chip = snd_kcontrol_chip(kcontrol);
  563. u32 old_control;
  564. int changed;
  565. spin_lock_irq(&chip->reg_lock);
  566. old_control = chip->reg_control;
  567. chip->reg_control = (chip->reg_control & ~CTL_A_SEL_MASK)
  568. | (value->value.enumerated.item[0] << CTL_A_SEL_SHIFT);
  569. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  570. changed = chip->reg_control != old_control;
  571. spin_unlock_irq(&chip->reg_lock);
  572. return changed;
  573. }
  574. static snd_kcontrol_new_t snd_bt87x_capture_source = {
  575. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  576. .name = "Capture Source",
  577. .info = snd_bt87x_capture_source_info,
  578. .get = snd_bt87x_capture_source_get,
  579. .put = snd_bt87x_capture_source_put,
  580. };
  581. static int snd_bt87x_free(bt87x_t *chip)
  582. {
  583. if (chip->mmio) {
  584. snd_bt87x_stop(chip);
  585. if (chip->irq >= 0)
  586. synchronize_irq(chip->irq);
  587. iounmap(chip->mmio);
  588. }
  589. if (chip->irq >= 0)
  590. free_irq(chip->irq, chip);
  591. pci_release_regions(chip->pci);
  592. pci_disable_device(chip->pci);
  593. kfree(chip);
  594. return 0;
  595. }
  596. static int snd_bt87x_dev_free(snd_device_t *device)
  597. {
  598. bt87x_t *chip = device->device_data;
  599. return snd_bt87x_free(chip);
  600. }
  601. static int __devinit snd_bt87x_pcm(bt87x_t *chip, int device, char *name)
  602. {
  603. int err;
  604. snd_pcm_t *pcm;
  605. err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
  606. if (err < 0)
  607. return err;
  608. pcm->private_data = chip;
  609. strcpy(pcm->name, name);
  610. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_bt87x_pcm_ops);
  611. return snd_pcm_lib_preallocate_pages_for_all(pcm,
  612. SNDRV_DMA_TYPE_DEV_SG,
  613. snd_dma_pci_data(chip->pci),
  614. 128 * 1024,
  615. (255 * 4092 + 1023) & ~1023);
  616. }
  617. static int __devinit snd_bt87x_create(snd_card_t *card,
  618. struct pci_dev *pci,
  619. bt87x_t **rchip)
  620. {
  621. bt87x_t *chip;
  622. int err;
  623. static snd_device_ops_t ops = {
  624. .dev_free = snd_bt87x_dev_free
  625. };
  626. *rchip = NULL;
  627. err = pci_enable_device(pci);
  628. if (err < 0)
  629. return err;
  630. chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
  631. if (!chip) {
  632. pci_disable_device(pci);
  633. return -ENOMEM;
  634. }
  635. chip->card = card;
  636. chip->pci = pci;
  637. chip->irq = -1;
  638. spin_lock_init(&chip->reg_lock);
  639. if ((err = pci_request_regions(pci, "Bt87x audio")) < 0) {
  640. kfree(chip);
  641. pci_disable_device(pci);
  642. return err;
  643. }
  644. chip->mmio = ioremap_nocache(pci_resource_start(pci, 0),
  645. pci_resource_len(pci, 0));
  646. if (!chip->mmio) {
  647. snd_bt87x_free(chip);
  648. snd_printk(KERN_ERR "cannot remap io memory\n");
  649. return -ENOMEM;
  650. }
  651. chip->reg_control = CTL_DA_ES2 | CTL_PKTP_16 | (15 << CTL_DA_SDR_SHIFT);
  652. chip->interrupt_mask = MY_INTERRUPTS;
  653. snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
  654. snd_bt87x_writel(chip, REG_INT_MASK, 0);
  655. snd_bt87x_writel(chip, REG_INT_STAT, MY_INTERRUPTS);
  656. if (request_irq(pci->irq, snd_bt87x_interrupt, SA_INTERRUPT | SA_SHIRQ,
  657. "Bt87x audio", chip)) {
  658. snd_bt87x_free(chip);
  659. snd_printk(KERN_ERR "cannot grab irq\n");
  660. return -EBUSY;
  661. }
  662. chip->irq = pci->irq;
  663. pci_set_master(pci);
  664. synchronize_irq(chip->irq);
  665. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
  666. if (err < 0) {
  667. snd_bt87x_free(chip);
  668. return err;
  669. }
  670. snd_card_set_dev(card, &pci->dev);
  671. *rchip = chip;
  672. return 0;
  673. }
  674. #define BT_DEVICE(chip, subvend, subdev, rate) \
  675. { .vendor = PCI_VENDOR_ID_BROOKTREE, \
  676. .device = PCI_DEVICE_ID_BROOKTREE_##chip, \
  677. .subvendor = subvend, .subdevice = subdev, \
  678. .driver_data = rate }
  679. /* driver_data is the default digital_rate value for that device */
  680. static struct pci_device_id snd_bt87x_ids[] = {
  681. BT_DEVICE(878, 0x0070, 0x13eb, 32000), /* Hauppauge WinTV series */
  682. BT_DEVICE(879, 0x0070, 0x13eb, 32000), /* Hauppauge WinTV series */
  683. BT_DEVICE(878, 0x0070, 0xff01, 44100), /* Viewcast Osprey 200 */
  684. { }
  685. };
  686. MODULE_DEVICE_TABLE(pci, snd_bt87x_ids);
  687. /* cards known not to have audio
  688. * (DVB cards use the audio function to transfer MPEG data) */
  689. static struct {
  690. unsigned short subvendor, subdevice;
  691. } blacklist[] __devinitdata = {
  692. {0x0071, 0x0101}, /* Nebula Electronics DigiTV */
  693. {0x11bd, 0x0026}, /* Pinnacle PCTV SAT CI */
  694. {0x1461, 0x0761}, /* AVermedia AverTV DVB-T */
  695. {0x1461, 0x0771}, /* AVermedia DVB-T 771 */
  696. {0x1822, 0x0001}, /* Twinhan VisionPlus DVB-T */
  697. {0x18ac, 0xdb10}, /* DVICO FusionHDTV DVB-T Lite */
  698. {0x270f, 0xfc00}, /* Chaintech Digitop DST-1000 DVB-S */
  699. };
  700. static struct pci_driver driver;
  701. /* return the rate of the card, or a negative value if it's blacklisted */
  702. static int __devinit snd_bt87x_detect_card(struct pci_dev *pci)
  703. {
  704. int i;
  705. const struct pci_device_id *supported;
  706. supported = pci_match_device(&driver, pci);
  707. if (supported)
  708. return supported->driver_data;
  709. for (i = 0; i < ARRAY_SIZE(blacklist); ++i)
  710. if (blacklist[i].subvendor == pci->subsystem_vendor &&
  711. blacklist[i].subdevice == pci->subsystem_device) {
  712. snd_printdd(KERN_INFO "card %#04x:%#04x has no audio\n",
  713. pci->subsystem_vendor, pci->subsystem_device);
  714. return -EBUSY;
  715. }
  716. snd_printk(KERN_INFO "unknown card %#04x:%#04x, using default rate 32000\n",
  717. pci->subsystem_vendor, pci->subsystem_device);
  718. snd_printk(KERN_DEBUG "please mail id, board name, and, "
  719. "if it works, the correct digital_rate option to "
  720. "<alsa-devel@lists.sf.net>\n");
  721. return 32000; /* default rate */
  722. }
  723. static int __devinit snd_bt87x_probe(struct pci_dev *pci,
  724. const struct pci_device_id *pci_id)
  725. {
  726. static int dev;
  727. snd_card_t *card;
  728. bt87x_t *chip;
  729. int err, rate;
  730. rate = pci_id->driver_data;
  731. if (! rate)
  732. if ((rate = snd_bt87x_detect_card(pci)) <= 0)
  733. return -ENODEV;
  734. if (dev >= SNDRV_CARDS)
  735. return -ENODEV;
  736. if (!enable[dev]) {
  737. ++dev;
  738. return -ENOENT;
  739. }
  740. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  741. if (!card)
  742. return -ENOMEM;
  743. err = snd_bt87x_create(card, pci, &chip);
  744. if (err < 0)
  745. goto _error;
  746. if (digital_rate[dev] > 0)
  747. chip->dig_rate = digital_rate[dev];
  748. else
  749. chip->dig_rate = rate;
  750. err = snd_bt87x_pcm(chip, DEVICE_DIGITAL, "Bt87x Digital");
  751. if (err < 0)
  752. goto _error;
  753. err = snd_bt87x_pcm(chip, DEVICE_ANALOG, "Bt87x Analog");
  754. if (err < 0)
  755. goto _error;
  756. err = snd_ctl_add(card, snd_ctl_new1(&snd_bt87x_capture_volume, chip));
  757. if (err < 0)
  758. goto _error;
  759. err = snd_ctl_add(card, snd_ctl_new1(&snd_bt87x_capture_boost, chip));
  760. if (err < 0)
  761. goto _error;
  762. err = snd_ctl_add(card, snd_ctl_new1(&snd_bt87x_capture_source, chip));
  763. if (err < 0)
  764. goto _error;
  765. strcpy(card->driver, "Bt87x");
  766. sprintf(card->shortname, "Brooktree Bt%x", pci->device);
  767. sprintf(card->longname, "%s at %#lx, irq %i",
  768. card->shortname, pci_resource_start(pci, 0), chip->irq);
  769. strcpy(card->mixername, "Bt87x");
  770. err = snd_card_register(card);
  771. if (err < 0)
  772. goto _error;
  773. pci_set_drvdata(pci, card);
  774. ++dev;
  775. return 0;
  776. _error:
  777. snd_card_free(card);
  778. return err;
  779. }
  780. static void __devexit snd_bt87x_remove(struct pci_dev *pci)
  781. {
  782. snd_card_free(pci_get_drvdata(pci));
  783. pci_set_drvdata(pci, NULL);
  784. }
  785. /* default entries for all Bt87x cards - it's not exported */
  786. /* driver_data is set to 0 to call detection */
  787. static struct pci_device_id snd_bt87x_default_ids[] = {
  788. BT_DEVICE(878, PCI_ANY_ID, PCI_ANY_ID, 0),
  789. BT_DEVICE(879, PCI_ANY_ID, PCI_ANY_ID, 0),
  790. { }
  791. };
  792. static struct pci_driver driver = {
  793. .name = "Bt87x",
  794. .id_table = snd_bt87x_ids,
  795. .probe = snd_bt87x_probe,
  796. .remove = __devexit_p(snd_bt87x_remove),
  797. };
  798. static int __init alsa_card_bt87x_init(void)
  799. {
  800. if (load_all)
  801. driver.id_table = snd_bt87x_default_ids;
  802. return pci_register_driver(&driver);
  803. }
  804. static void __exit alsa_card_bt87x_exit(void)
  805. {
  806. pci_unregister_driver(&driver);
  807. }
  808. module_init(alsa_card_bt87x_init)
  809. module_exit(alsa_card_bt87x_exit)