opl3_lib.c 14 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
  3. * Hannu Savolainen 1993-1996,
  4. * Rob Hooft
  5. *
  6. * Routines for control of AdLib FM cards (OPL2/OPL3/OPL4 chips)
  7. *
  8. * Most if code is ported from OSS/Lite.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. */
  25. #include <sound/opl3.h>
  26. #include <asm/io.h>
  27. #include <linux/delay.h>
  28. #include <linux/init.h>
  29. #include <linux/slab.h>
  30. #include <linux/ioport.h>
  31. #include <sound/minors.h>
  32. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Hannu Savolainen 1993-1996, Rob Hooft");
  33. MODULE_DESCRIPTION("Routines for control of AdLib FM cards (OPL2/OPL3/OPL4 chips)");
  34. MODULE_LICENSE("GPL");
  35. extern char snd_opl3_regmap[MAX_OPL2_VOICES][4];
  36. static void snd_opl2_command(opl3_t * opl3, unsigned short cmd, unsigned char val)
  37. {
  38. unsigned long flags;
  39. unsigned long port;
  40. /*
  41. * The original 2-OP synth requires a quite long delay
  42. * after writing to a register.
  43. */
  44. port = (cmd & OPL3_RIGHT) ? opl3->r_port : opl3->l_port;
  45. spin_lock_irqsave(&opl3->reg_lock, flags);
  46. outb((unsigned char) cmd, port);
  47. udelay(10);
  48. outb((unsigned char) val, port + 1);
  49. udelay(30);
  50. spin_unlock_irqrestore(&opl3->reg_lock, flags);
  51. }
  52. static void snd_opl3_command(opl3_t * opl3, unsigned short cmd, unsigned char val)
  53. {
  54. unsigned long flags;
  55. unsigned long port;
  56. /*
  57. * The OPL-3 survives with just two INBs
  58. * after writing to a register.
  59. */
  60. port = (cmd & OPL3_RIGHT) ? opl3->r_port : opl3->l_port;
  61. spin_lock_irqsave(&opl3->reg_lock, flags);
  62. outb((unsigned char) cmd, port);
  63. inb(opl3->l_port);
  64. inb(opl3->l_port);
  65. outb((unsigned char) val, port + 1);
  66. inb(opl3->l_port);
  67. inb(opl3->l_port);
  68. spin_unlock_irqrestore(&opl3->reg_lock, flags);
  69. }
  70. static int snd_opl3_detect(opl3_t * opl3)
  71. {
  72. /*
  73. * This function returns 1 if the FM chip is present at the given I/O port
  74. * The detection algorithm plays with the timer built in the FM chip and
  75. * looks for a change in the status register.
  76. *
  77. * Note! The timers of the FM chip are not connected to AdLib (and compatible)
  78. * boards.
  79. *
  80. * Note2! The chip is initialized if detected.
  81. */
  82. unsigned char stat1, stat2, signature;
  83. /* Reset timers 1 and 2 */
  84. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER1_MASK | OPL3_TIMER2_MASK);
  85. /* Reset the IRQ of the FM chip */
  86. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_IRQ_RESET);
  87. signature = stat1 = inb(opl3->l_port); /* Status register */
  88. if ((stat1 & 0xe0) != 0x00) { /* Should be 0x00 */
  89. snd_printd("OPL3: stat1 = 0x%x\n", stat1);
  90. return -ENODEV;
  91. }
  92. /* Set timer1 to 0xff */
  93. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER1, 0xff);
  94. /* Unmask and start timer 1 */
  95. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER2_MASK | OPL3_TIMER1_START);
  96. /* Now we have to delay at least 80us */
  97. udelay(200);
  98. /* Read status after timers have expired */
  99. stat2 = inb(opl3->l_port);
  100. /* Stop the timers */
  101. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER1_MASK | OPL3_TIMER2_MASK);
  102. /* Reset the IRQ of the FM chip */
  103. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_IRQ_RESET);
  104. if ((stat2 & 0xe0) != 0xc0) { /* There is no YM3812 */
  105. snd_printd("OPL3: stat2 = 0x%x\n", stat2);
  106. return -ENODEV;
  107. }
  108. /* If the toplevel code knows exactly the type of chip, don't try
  109. to detect it. */
  110. if (opl3->hardware != OPL3_HW_AUTO)
  111. return 0;
  112. /* There is a FM chip on this address. Detect the type (OPL2 to OPL4) */
  113. if (signature == 0x06) { /* OPL2 */
  114. opl3->hardware = OPL3_HW_OPL2;
  115. } else {
  116. /*
  117. * If we had an OPL4 chip, opl3->hardware would have been set
  118. * by the OPL4 driver; so we can assume OPL3 here.
  119. */
  120. snd_assert(opl3->r_port != 0, return -ENODEV);
  121. opl3->hardware = OPL3_HW_OPL3;
  122. }
  123. return 0;
  124. }
  125. /*
  126. * AdLib timers
  127. */
  128. /*
  129. * Timer 1 - 80us
  130. */
  131. static int snd_opl3_timer1_start(snd_timer_t * timer)
  132. {
  133. unsigned long flags;
  134. unsigned char tmp;
  135. unsigned int ticks;
  136. opl3_t *opl3;
  137. opl3 = snd_timer_chip(timer);
  138. spin_lock_irqsave(&opl3->timer_lock, flags);
  139. ticks = timer->sticks;
  140. tmp = (opl3->timer_enable | OPL3_TIMER1_START) & ~OPL3_TIMER1_MASK;
  141. opl3->timer_enable = tmp;
  142. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER1, 256 - ticks); /* timer 1 count */
  143. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp); /* enable timer 1 IRQ */
  144. spin_unlock_irqrestore(&opl3->timer_lock, flags);
  145. return 0;
  146. }
  147. static int snd_opl3_timer1_stop(snd_timer_t * timer)
  148. {
  149. unsigned long flags;
  150. unsigned char tmp;
  151. opl3_t *opl3;
  152. opl3 = snd_timer_chip(timer);
  153. spin_lock_irqsave(&opl3->timer_lock, flags);
  154. tmp = (opl3->timer_enable | OPL3_TIMER1_MASK) & ~OPL3_TIMER1_START;
  155. opl3->timer_enable = tmp;
  156. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp); /* disable timer #1 */
  157. spin_unlock_irqrestore(&opl3->timer_lock, flags);
  158. return 0;
  159. }
  160. /*
  161. * Timer 2 - 320us
  162. */
  163. static int snd_opl3_timer2_start(snd_timer_t * timer)
  164. {
  165. unsigned long flags;
  166. unsigned char tmp;
  167. unsigned int ticks;
  168. opl3_t *opl3;
  169. opl3 = snd_timer_chip(timer);
  170. spin_lock_irqsave(&opl3->timer_lock, flags);
  171. ticks = timer->sticks;
  172. tmp = (opl3->timer_enable | OPL3_TIMER2_START) & ~OPL3_TIMER2_MASK;
  173. opl3->timer_enable = tmp;
  174. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER2, 256 - ticks); /* timer 1 count */
  175. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp); /* enable timer 1 IRQ */
  176. spin_unlock_irqrestore(&opl3->timer_lock, flags);
  177. return 0;
  178. }
  179. static int snd_opl3_timer2_stop(snd_timer_t * timer)
  180. {
  181. unsigned long flags;
  182. unsigned char tmp;
  183. opl3_t *opl3;
  184. opl3 = snd_timer_chip(timer);
  185. spin_lock_irqsave(&opl3->timer_lock, flags);
  186. tmp = (opl3->timer_enable | OPL3_TIMER2_MASK) & ~OPL3_TIMER2_START;
  187. opl3->timer_enable = tmp;
  188. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp); /* disable timer #1 */
  189. spin_unlock_irqrestore(&opl3->timer_lock, flags);
  190. return 0;
  191. }
  192. /*
  193. */
  194. static struct _snd_timer_hardware snd_opl3_timer1 =
  195. {
  196. .flags = SNDRV_TIMER_HW_STOP,
  197. .resolution = 80000,
  198. .ticks = 256,
  199. .start = snd_opl3_timer1_start,
  200. .stop = snd_opl3_timer1_stop,
  201. };
  202. static struct _snd_timer_hardware snd_opl3_timer2 =
  203. {
  204. .flags = SNDRV_TIMER_HW_STOP,
  205. .resolution = 320000,
  206. .ticks = 256,
  207. .start = snd_opl3_timer2_start,
  208. .stop = snd_opl3_timer2_stop,
  209. };
  210. static int snd_opl3_timer1_init(opl3_t * opl3, int timer_no)
  211. {
  212. snd_timer_t *timer = NULL;
  213. snd_timer_id_t tid;
  214. int err;
  215. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  216. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  217. tid.card = opl3->card->number;
  218. tid.device = timer_no;
  219. tid.subdevice = 0;
  220. if ((err = snd_timer_new(opl3->card, "AdLib timer #1", &tid, &timer)) >= 0) {
  221. strcpy(timer->name, "AdLib timer #1");
  222. timer->private_data = opl3;
  223. timer->hw = snd_opl3_timer1;
  224. }
  225. opl3->timer1 = timer;
  226. return err;
  227. }
  228. static int snd_opl3_timer2_init(opl3_t * opl3, int timer_no)
  229. {
  230. snd_timer_t *timer = NULL;
  231. snd_timer_id_t tid;
  232. int err;
  233. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  234. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  235. tid.card = opl3->card->number;
  236. tid.device = timer_no;
  237. tid.subdevice = 0;
  238. if ((err = snd_timer_new(opl3->card, "AdLib timer #2", &tid, &timer)) >= 0) {
  239. strcpy(timer->name, "AdLib timer #2");
  240. timer->private_data = opl3;
  241. timer->hw = snd_opl3_timer2;
  242. }
  243. opl3->timer2 = timer;
  244. return err;
  245. }
  246. /*
  247. */
  248. void snd_opl3_interrupt(snd_hwdep_t * hw)
  249. {
  250. unsigned char status;
  251. opl3_t *opl3;
  252. snd_timer_t *timer;
  253. if (hw == NULL)
  254. return;
  255. opl3 = hw->private_data;
  256. status = inb(opl3->l_port);
  257. #if 0
  258. snd_printk("AdLib IRQ status = 0x%x\n", status);
  259. #endif
  260. if (!(status & 0x80))
  261. return;
  262. if (status & 0x40) {
  263. timer = opl3->timer1;
  264. snd_timer_interrupt(timer, timer->sticks);
  265. }
  266. if (status & 0x20) {
  267. timer = opl3->timer2;
  268. snd_timer_interrupt(timer, timer->sticks);
  269. }
  270. }
  271. /*
  272. */
  273. static int snd_opl3_free(opl3_t *opl3)
  274. {
  275. snd_assert(opl3 != NULL, return -ENXIO);
  276. if (opl3->private_free)
  277. opl3->private_free(opl3);
  278. if (opl3->res_l_port) {
  279. release_resource(opl3->res_l_port);
  280. kfree_nocheck(opl3->res_l_port);
  281. }
  282. if (opl3->res_r_port) {
  283. release_resource(opl3->res_r_port);
  284. kfree_nocheck(opl3->res_r_port);
  285. }
  286. kfree(opl3);
  287. return 0;
  288. }
  289. static int snd_opl3_dev_free(snd_device_t *device)
  290. {
  291. opl3_t *opl3 = device->device_data;
  292. return snd_opl3_free(opl3);
  293. }
  294. int snd_opl3_new(snd_card_t *card,
  295. unsigned short hardware,
  296. opl3_t **ropl3)
  297. {
  298. static snd_device_ops_t ops = {
  299. .dev_free = snd_opl3_dev_free,
  300. };
  301. opl3_t *opl3;
  302. int err;
  303. *ropl3 = NULL;
  304. opl3 = kcalloc(1, sizeof(*opl3), GFP_KERNEL);
  305. if (opl3 == NULL)
  306. return -ENOMEM;
  307. opl3->card = card;
  308. opl3->hardware = hardware;
  309. spin_lock_init(&opl3->reg_lock);
  310. spin_lock_init(&opl3->timer_lock);
  311. init_MUTEX(&opl3->access_mutex);
  312. if ((err = snd_device_new(card, SNDRV_DEV_CODEC, opl3, &ops)) < 0) {
  313. snd_opl3_free(opl3);
  314. return err;
  315. }
  316. *ropl3 = opl3;
  317. return 0;
  318. }
  319. int snd_opl3_init(opl3_t *opl3)
  320. {
  321. if (! opl3->command) {
  322. printk(KERN_ERR "snd_opl3_init: command not defined!\n");
  323. return -EINVAL;
  324. }
  325. opl3->command(opl3, OPL3_LEFT | OPL3_REG_TEST, OPL3_ENABLE_WAVE_SELECT);
  326. /* Melodic mode */
  327. opl3->command(opl3, OPL3_LEFT | OPL3_REG_PERCUSSION, 0x00);
  328. switch (opl3->hardware & OPL3_HW_MASK) {
  329. case OPL3_HW_OPL2:
  330. opl3->max_voices = MAX_OPL2_VOICES;
  331. break;
  332. case OPL3_HW_OPL3:
  333. case OPL3_HW_OPL4:
  334. opl3->max_voices = MAX_OPL3_VOICES;
  335. /* Enter OPL3 mode */
  336. opl3->command(opl3, OPL3_RIGHT | OPL3_REG_MODE, OPL3_OPL3_ENABLE);
  337. }
  338. return 0;
  339. }
  340. int snd_opl3_create(snd_card_t * card,
  341. unsigned long l_port,
  342. unsigned long r_port,
  343. unsigned short hardware,
  344. int integrated,
  345. opl3_t ** ropl3)
  346. {
  347. opl3_t *opl3;
  348. int err;
  349. *ropl3 = NULL;
  350. if ((err = snd_opl3_new(card, hardware, &opl3)) < 0)
  351. return err;
  352. if (! integrated) {
  353. if ((opl3->res_l_port = request_region(l_port, 2, "OPL2/3 (left)")) == NULL) {
  354. snd_printk(KERN_ERR "opl3: can't grab left port 0x%lx\n", l_port);
  355. snd_opl3_free(opl3);
  356. return -EBUSY;
  357. }
  358. if (r_port != 0 &&
  359. (opl3->res_r_port = request_region(r_port, 2, "OPL2/3 (right)")) == NULL) {
  360. snd_printk(KERN_ERR "opl3: can't grab right port 0x%lx\n", r_port);
  361. snd_opl3_free(opl3);
  362. return -EBUSY;
  363. }
  364. }
  365. opl3->l_port = l_port;
  366. opl3->r_port = r_port;
  367. switch (opl3->hardware) {
  368. /* some hardware doesn't support timers */
  369. case OPL3_HW_OPL3_SV:
  370. case OPL3_HW_OPL3_CS:
  371. case OPL3_HW_OPL3_FM801:
  372. opl3->command = &snd_opl3_command;
  373. break;
  374. default:
  375. opl3->command = &snd_opl2_command;
  376. if ((err = snd_opl3_detect(opl3)) < 0) {
  377. snd_printd("OPL2/3 chip not detected at 0x%lx/0x%lx\n",
  378. opl3->l_port, opl3->r_port);
  379. snd_opl3_free(opl3);
  380. return err;
  381. }
  382. /* detect routine returns correct hardware type */
  383. switch (opl3->hardware & OPL3_HW_MASK) {
  384. case OPL3_HW_OPL3:
  385. case OPL3_HW_OPL4:
  386. opl3->command = &snd_opl3_command;
  387. }
  388. }
  389. snd_opl3_init(opl3);
  390. *ropl3 = opl3;
  391. return 0;
  392. }
  393. int snd_opl3_timer_new(opl3_t * opl3, int timer1_dev, int timer2_dev)
  394. {
  395. int err;
  396. if (timer1_dev >= 0)
  397. if ((err = snd_opl3_timer1_init(opl3, timer1_dev)) < 0)
  398. return err;
  399. if (timer2_dev >= 0) {
  400. if ((err = snd_opl3_timer2_init(opl3, timer2_dev)) < 0) {
  401. snd_device_free(opl3->card, opl3->timer1);
  402. opl3->timer1 = NULL;
  403. return err;
  404. }
  405. }
  406. return 0;
  407. }
  408. int snd_opl3_hwdep_new(opl3_t * opl3,
  409. int device, int seq_device,
  410. snd_hwdep_t ** rhwdep)
  411. {
  412. snd_hwdep_t *hw;
  413. snd_card_t *card = opl3->card;
  414. int err;
  415. if (rhwdep)
  416. *rhwdep = NULL;
  417. /* create hardware dependent device (direct FM) */
  418. if ((err = snd_hwdep_new(card, "OPL2/OPL3", device, &hw)) < 0) {
  419. snd_device_free(card, opl3);
  420. return err;
  421. }
  422. hw->private_data = opl3;
  423. #ifdef CONFIG_SND_OSSEMUL
  424. if (device == 0) {
  425. hw->oss_type = SNDRV_OSS_DEVICE_TYPE_DMFM;
  426. sprintf(hw->oss_dev, "dmfm%i", card->number);
  427. }
  428. #endif
  429. strcpy(hw->name, hw->id);
  430. switch (opl3->hardware & OPL3_HW_MASK) {
  431. case OPL3_HW_OPL2:
  432. strcpy(hw->name, "OPL2 FM");
  433. hw->iface = SNDRV_HWDEP_IFACE_OPL2;
  434. break;
  435. case OPL3_HW_OPL3:
  436. strcpy(hw->name, "OPL3 FM");
  437. hw->iface = SNDRV_HWDEP_IFACE_OPL3;
  438. break;
  439. case OPL3_HW_OPL4:
  440. strcpy(hw->name, "OPL4 FM");
  441. hw->iface = SNDRV_HWDEP_IFACE_OPL4;
  442. break;
  443. }
  444. /* operators - only ioctl */
  445. hw->ops.open = snd_opl3_open;
  446. hw->ops.ioctl = snd_opl3_ioctl;
  447. hw->ops.release = snd_opl3_release;
  448. opl3->seq_dev_num = seq_device;
  449. #if defined(CONFIG_SND_SEQUENCER) || (defined(MODULE) && defined(CONFIG_SND_SEQUENCER_MODULE))
  450. if (snd_seq_device_new(card, seq_device, SNDRV_SEQ_DEV_ID_OPL3,
  451. sizeof(opl3_t*), &opl3->seq_dev) >= 0) {
  452. strcpy(opl3->seq_dev->name, hw->name);
  453. *(opl3_t**)SNDRV_SEQ_DEVICE_ARGPTR(opl3->seq_dev) = opl3;
  454. }
  455. #endif
  456. if (rhwdep)
  457. *rhwdep = hw;
  458. return 0;
  459. }
  460. EXPORT_SYMBOL(snd_opl3_interrupt);
  461. EXPORT_SYMBOL(snd_opl3_new);
  462. EXPORT_SYMBOL(snd_opl3_init);
  463. EXPORT_SYMBOL(snd_opl3_create);
  464. EXPORT_SYMBOL(snd_opl3_timer_new);
  465. EXPORT_SYMBOL(snd_opl3_hwdep_new);
  466. /* opl3_synth.c */
  467. EXPORT_SYMBOL(snd_opl3_regmap);
  468. EXPORT_SYMBOL(snd_opl3_reset);
  469. /*
  470. * INIT part
  471. */
  472. static int __init alsa_opl3_init(void)
  473. {
  474. return 0;
  475. }
  476. static void __exit alsa_opl3_exit(void)
  477. {
  478. }
  479. module_init(alsa_opl3_init)
  480. module_exit(alsa_opl3_exit)