pxa2xx-ac97.c 10.0 KB

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  1. /*
  2. * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: Dec 02, 2004
  6. * Copyright: MontaVista Software Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/device.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/wait.h>
  18. #include <linux/delay.h>
  19. #include <sound/driver.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/ac97_codec.h>
  23. #include <sound/initval.h>
  24. #include <asm/irq.h>
  25. #include <asm/semaphore.h>
  26. #include <asm/hardware.h>
  27. #include <asm/arch/pxa-regs.h>
  28. #include <asm/arch/audio.h>
  29. #include "pxa2xx-pcm.h"
  30. static DECLARE_MUTEX(car_mutex);
  31. static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  32. static volatile long gsr_bits;
  33. static unsigned short pxa2xx_ac97_read(ac97_t *ac97, unsigned short reg)
  34. {
  35. unsigned short val = -1;
  36. volatile u32 *reg_addr;
  37. down(&car_mutex);
  38. if (CAR & CAR_CAIP) {
  39. printk(KERN_CRIT"%s: CAR_CAIP already set\n", __FUNCTION__);
  40. goto out;
  41. }
  42. /* set up primary or secondary codec space */
  43. reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
  44. reg_addr += (reg >> 1);
  45. /* start read access across the ac97 link */
  46. gsr_bits = 0;
  47. val = *reg_addr;
  48. if (reg == AC97_GPIO_STATUS)
  49. goto out;
  50. wait_event_timeout(gsr_wq, gsr_bits & GSR_SDONE, 1);
  51. if (!gsr_bits & GSR_SDONE) {
  52. printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
  53. __FUNCTION__, reg, gsr_bits);
  54. val = -1;
  55. goto out;
  56. }
  57. /* valid data now */
  58. gsr_bits = 0;
  59. val = *reg_addr;
  60. /* but we've just started another cycle... */
  61. wait_event_timeout(gsr_wq, gsr_bits & GSR_SDONE, 1);
  62. out: up(&car_mutex);
  63. return val;
  64. }
  65. static void pxa2xx_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
  66. {
  67. volatile u32 *reg_addr;
  68. down(&car_mutex);
  69. if (CAR & CAR_CAIP) {
  70. printk(KERN_CRIT "%s: CAR_CAIP already set\n", __FUNCTION__);
  71. goto out;
  72. }
  73. /* set up primary or secondary codec space */
  74. reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
  75. reg_addr += (reg >> 1);
  76. gsr_bits = 0;
  77. *reg_addr = val;
  78. wait_event_timeout(gsr_wq, gsr_bits & GSR_CDONE, 1);
  79. if (!gsr_bits & GSR_SDONE)
  80. printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
  81. __FUNCTION__, reg, gsr_bits);
  82. out: up(&car_mutex);
  83. }
  84. static void pxa2xx_ac97_reset(ac97_t *ac97)
  85. {
  86. /* First, try cold reset */
  87. GCR &= GCR_COLD_RST; /* clear everything but nCRST */
  88. GCR &= ~GCR_COLD_RST; /* then assert nCRST */
  89. gsr_bits = 0;
  90. #ifdef CONFIG_PXA27x
  91. /* PXA27x Developers Manual section 13.5.2.2.1 */
  92. pxa_set_cken(1 << 31, 1);
  93. udelay(5);
  94. pxa_set_cken(1 << 31, 0);
  95. GCR = GCR_COLD_RST;
  96. udelay(50);
  97. #else
  98. GCR = GCR_COLD_RST;
  99. GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
  100. wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
  101. #endif
  102. if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
  103. printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
  104. __FUNCTION__, gsr_bits);
  105. /* let's try warm reset */
  106. gsr_bits = 0;
  107. #ifdef CONFIG_PXA27x
  108. /* warm reset broken on Bulverde,
  109. so manually keep AC97 reset high */
  110. pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
  111. udelay(10);
  112. GCR |= GCR_WARM_RST;
  113. pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
  114. udelay(500);
  115. #else
  116. GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN;
  117. wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
  118. #endif
  119. if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
  120. printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
  121. __FUNCTION__, gsr_bits);
  122. }
  123. GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
  124. GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
  125. }
  126. static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id, struct pt_regs *regs)
  127. {
  128. long status;
  129. status = GSR;
  130. if (status) {
  131. GSR = status;
  132. gsr_bits |= status;
  133. wake_up(&gsr_wq);
  134. #ifdef CONFIG_PXA27x
  135. /* Although we don't use those we still need to clear them
  136. since they tend to spuriously trigger when MMC is used
  137. (hardware bug? go figure)... */
  138. MISR = MISR_EOC;
  139. PISR = PISR_EOC;
  140. MCSR = MCSR_EOC;
  141. #endif
  142. return IRQ_HANDLED;
  143. }
  144. return IRQ_NONE;
  145. }
  146. static ac97_bus_ops_t pxa2xx_ac97_ops = {
  147. .read = pxa2xx_ac97_read,
  148. .write = pxa2xx_ac97_write,
  149. .reset = pxa2xx_ac97_reset,
  150. };
  151. static pxa2xx_pcm_dma_params_t pxa2xx_ac97_pcm_out = {
  152. .name = "AC97 PCM out",
  153. .dev_addr = __PREG(PCDR),
  154. .drcmr = &DRCMRTXPCDR,
  155. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  156. DCMD_BURST32 | DCMD_WIDTH4,
  157. };
  158. static pxa2xx_pcm_dma_params_t pxa2xx_ac97_pcm_in = {
  159. .name = "AC97 PCM in",
  160. .dev_addr = __PREG(PCDR),
  161. .drcmr = &DRCMRRXPCDR,
  162. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  163. DCMD_BURST32 | DCMD_WIDTH4,
  164. };
  165. static snd_pcm_t *pxa2xx_ac97_pcm;
  166. static ac97_t *pxa2xx_ac97_ac97;
  167. static int pxa2xx_ac97_pcm_startup(snd_pcm_substream_t *substream)
  168. {
  169. snd_pcm_runtime_t *runtime = substream->runtime;
  170. pxa2xx_audio_ops_t *platform_ops;
  171. int r;
  172. runtime->hw.channels_min = 2;
  173. runtime->hw.channels_max = 2;
  174. r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
  175. AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
  176. runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
  177. snd_pcm_limit_hw_rates(runtime);
  178. platform_ops = substream->pcm->card->dev->platform_data;
  179. if (platform_ops && platform_ops->startup)
  180. return platform_ops->startup(substream, platform_ops->priv);
  181. else
  182. return 0;
  183. }
  184. static void pxa2xx_ac97_pcm_shutdown(snd_pcm_substream_t *substream)
  185. {
  186. pxa2xx_audio_ops_t *platform_ops;
  187. platform_ops = substream->pcm->card->dev->platform_data;
  188. if (platform_ops && platform_ops->shutdown)
  189. platform_ops->shutdown(substream, platform_ops->priv);
  190. }
  191. static int pxa2xx_ac97_pcm_prepare(snd_pcm_substream_t *substream)
  192. {
  193. snd_pcm_runtime_t *runtime = substream->runtime;
  194. int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
  195. AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
  196. return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
  197. }
  198. static pxa2xx_pcm_client_t pxa2xx_ac97_pcm_client = {
  199. .playback_params = &pxa2xx_ac97_pcm_out,
  200. .capture_params = &pxa2xx_ac97_pcm_in,
  201. .startup = pxa2xx_ac97_pcm_startup,
  202. .shutdown = pxa2xx_ac97_pcm_shutdown,
  203. .prepare = pxa2xx_ac97_pcm_prepare,
  204. };
  205. #ifdef CONFIG_PM
  206. static int pxa2xx_ac97_do_suspend(snd_card_t *card, unsigned int state)
  207. {
  208. if (card->power_state != SNDRV_CTL_POWER_D3cold) {
  209. pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
  210. snd_pcm_suspend_all(pxa2xx_ac97_pcm);
  211. snd_ac97_suspend(pxa2xx_ac97_ac97);
  212. snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
  213. if (platform_ops && platform_ops->suspend)
  214. platform_ops->suspend(platform_ops->priv);
  215. GCR |= GCR_ACLINK_OFF;
  216. pxa_set_cken(CKEN2_AC97, 0);
  217. }
  218. return 0;
  219. }
  220. static int pxa2xx_ac97_do_resume(snd_card_t *card)
  221. {
  222. if (card->power_state != SNDRV_CTL_POWER_D0) {
  223. pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
  224. pxa_set_cken(CKEN2_AC97, 1);
  225. if (platform_ops && platform_ops->resume)
  226. platform_ops->resume(platform_ops->priv);
  227. snd_ac97_resume(pxa2xx_ac97_ac97);
  228. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  229. }
  230. return 0;
  231. }
  232. static int pxa2xx_ac97_suspend(struct device *_dev, pm_message_t state, u32 level)
  233. {
  234. snd_card_t *card = dev_get_drvdata(_dev);
  235. int ret = 0;
  236. if (card && level == SUSPEND_DISABLE)
  237. ret = pxa2xx_ac97_do_suspend(card, PMSG_SUSPEND);
  238. return ret;
  239. }
  240. static int pxa2xx_ac97_resume(struct device *_dev, u32 level)
  241. {
  242. snd_card_t *card = dev_get_drvdata(_dev);
  243. int ret = 0;
  244. if (card && level == RESUME_ENABLE)
  245. ret = pxa2xx_ac97_do_resume(card);
  246. return ret;
  247. }
  248. #else
  249. #define pxa2xx_ac97_suspend NULL
  250. #define pxa2xx_ac97_resume NULL
  251. #endif
  252. static int pxa2xx_ac97_probe(struct device *dev)
  253. {
  254. snd_card_t *card;
  255. ac97_bus_t *ac97_bus;
  256. ac97_template_t ac97_template;
  257. int ret;
  258. ret = -ENOMEM;
  259. card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  260. THIS_MODULE, 0);
  261. if (!card)
  262. goto err;
  263. card->dev = dev;
  264. strncpy(card->driver, dev->driver->name, sizeof(card->driver));
  265. ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
  266. if (ret)
  267. goto err;
  268. ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
  269. if (ret < 0)
  270. goto err;
  271. pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
  272. pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
  273. pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
  274. pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
  275. #ifdef CONFIG_PXA27x
  276. /* Use GPIO 113 as AC97 Reset on Bulverde */
  277. pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
  278. #endif
  279. pxa_set_cken(CKEN2_AC97, 1);
  280. ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
  281. if (ret)
  282. goto err;
  283. memset(&ac97_template, 0, sizeof(ac97_template));
  284. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
  285. if (ret)
  286. goto err;
  287. snprintf(card->shortname, sizeof(card->shortname),
  288. "%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
  289. snprintf(card->longname, sizeof(card->longname),
  290. "%s (%s)", dev->driver->name, card->mixername);
  291. snd_card_set_pm_callback(card, pxa2xx_ac97_do_suspend,
  292. pxa2xx_ac97_do_resume, NULL);
  293. ret = snd_card_register(card);
  294. if (ret == 0) {
  295. dev_set_drvdata(dev, card);
  296. return 0;
  297. }
  298. err:
  299. if (card)
  300. snd_card_free(card);
  301. if (CKEN & CKEN2_AC97) {
  302. GCR |= GCR_ACLINK_OFF;
  303. free_irq(IRQ_AC97, NULL);
  304. pxa_set_cken(CKEN2_AC97, 0);
  305. }
  306. return ret;
  307. }
  308. static int pxa2xx_ac97_remove(struct device *dev)
  309. {
  310. snd_card_t *card = dev_get_drvdata(dev);
  311. if (card) {
  312. snd_card_free(card);
  313. dev_set_drvdata(dev, NULL);
  314. GCR |= GCR_ACLINK_OFF;
  315. free_irq(IRQ_AC97, NULL);
  316. pxa_set_cken(CKEN2_AC97, 0);
  317. }
  318. return 0;
  319. }
  320. static struct device_driver pxa2xx_ac97_driver = {
  321. .name = "pxa2xx-ac97",
  322. .bus = &platform_bus_type,
  323. .probe = pxa2xx_ac97_probe,
  324. .remove = pxa2xx_ac97_remove,
  325. .suspend = pxa2xx_ac97_suspend,
  326. .resume = pxa2xx_ac97_resume,
  327. };
  328. static int __init pxa2xx_ac97_init(void)
  329. {
  330. return driver_register(&pxa2xx_ac97_driver);
  331. }
  332. static void __exit pxa2xx_ac97_exit(void)
  333. {
  334. driver_unregister(&pxa2xx_ac97_driver);
  335. }
  336. module_init(pxa2xx_ac97_init);
  337. module_exit(pxa2xx_ac97_exit);
  338. MODULE_AUTHOR("Nicolas Pitre");
  339. MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
  340. MODULE_LICENSE("GPL");