kn01.h 3.2 KB

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  1. /*
  2. * Hardware info about DECstation DS2100/3100 systems (otherwise known as
  3. * pmin/pmax or KN01).
  4. *
  5. * This file is subject to the terms and conditions of the GNU General Public
  6. * License. See the file "COPYING" in the main directory of this archive
  7. * for more details.
  8. *
  9. * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
  10. * are by courtesy of Chris Fraser.
  11. * Copyright (C) 2002, 2003 Maciej W. Rozycki
  12. */
  13. #ifndef __ASM_MIPS_DEC_KN01_H
  14. #define __ASM_MIPS_DEC_KN01_H
  15. #include <asm/addrspace.h>
  16. #define KN01_SLOT_BASE KSEG1ADDR(0x10000000)
  17. #define KN01_SLOT_SIZE 0x01000000
  18. /*
  19. * Address ranges for devices.
  20. */
  21. #define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */
  22. #define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */
  23. #define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */
  24. #define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */
  25. #define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */
  26. #define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */
  27. #define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */
  28. #define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */
  29. #define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */
  30. #define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */
  31. #define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */
  32. #define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */
  33. #define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */
  34. #define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */
  35. #define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */
  36. #define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */
  37. #define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */
  38. /*
  39. * Some port addresses...
  40. */
  41. #define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */
  42. #define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */
  43. #define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */
  44. /*
  45. * Frame buffer memory address.
  46. */
  47. #define KN01_VFB_MEM KSEG1ADDR(0x0fc00000)
  48. /*
  49. * CPU interrupt bits.
  50. */
  51. #define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */
  52. #define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */
  53. #define KN01_CPU_INR_RTC 5 /* DS1287 RTC */
  54. #define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */
  55. #define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
  56. #define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */
  57. /*
  58. * System Control & Status Register bits.
  59. */
  60. #define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
  61. #define KN01_CSR_STATUS (1<<14) /* self-test result status output */
  62. #define KN01_CSR_PARDIS (1<<13) /* parity error disable */
  63. #define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
  64. #define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
  65. #define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
  66. #define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
  67. #define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
  68. #define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */
  69. #define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */
  70. #define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
  71. #define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
  72. #endif /* __ASM_MIPS_DEC_KN01_H */